Texas Instruments 74AC11652DWR, 74AC11652DW Datasheet
74AC11652
OCTAL BUS TRANSCEIVER AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS088A - DECEMBER 1989 - REVISED APRIL 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Independent Registers and Enables for A
and B Buses
D
Multiplexed Real-Time and Stored Data
D
Inverting Data Paths
D
Flow-Through Architecture Optimizes PCB
Layout
D
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
500-mA Typical Latch-Up Immunity at
125°C
description
The 74AC11652 consists of bus transceiver
circuits, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data
directly from the data bus or from the internal
storage registers. Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions.
The select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred.
A low input level selects real-time data, and a high input level selects stored data. Figure 1 illustrates the four
fundamental bus-management functions that can be performed with the 74AC11652.
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB and
SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops
by simultaneously enabling OEAB and OEBA
. In this configuration, each output reinforces its input. Thus, when
all other data sources to the two sets of bus lines are at high impedance, each set remains at its last state.
The 74AC11652 is characterized for operation from –40°C to 85°C.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
DW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OEAB
A1
A2
A3
A4
GND
GND
GND
GND
A5
A6
A7
A8
OEBA
CLKAB
SAB
B1
B2
B3
B4
V
CC
V
CC
B5
B6
B7
B8
CLKBA
SBA
74AC11652
OCTAL BUS TRANSCEIVER AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS088A - DECEMBER 1989 - REVISED APRIL 1996
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
OEAB
1
X
L
L
OEAB
1
L
14
L
28
CLKAB
X
16
CLKBA
X
27
SAB
X
15
SBA
L
28
CLKAB
X
16
CLKBA
X
27
SAB
L
15
SBA
X
14
H
28
CLKAB16CLKBA
X
27
SAB
X
15
SBA
X
28
CLKAB16CLKBA27SAB15SBA
X
H
XX
X
X
X
HL L HH
↑
↑
↑↑
OEBA
OEBA
1
H
14
H
OEAB OEBA
114
OEAB OEBA
L
Figure 1. Bus-Management Functions
74AC11652
OCTAL BUS TRANSCEIVER AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS088A - DECEMBER 1989 - REVISED APRIL 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
DATA I/O
†
OEAB OEBA
CLKAB
CLKBA SAB SBA A1 THRU A8 B1 THRU B8
OPERATION OR FUNCTION
L H L L X X Input Input Isolation
L H ↑↑X X Input Input Store A and B data
X H ↑ L X X Input Unspecified
‡
Store A, hold B
H H ↑↑X
‡
X Input Output Store A in both registers
L XL ↑ X X Unspecified
‡
Input Hold A, store B
L L ↑↑XX‡Output Input Store B in both registers
L L X X X L Output Input Real-time B data to A bus
L L X L X H Output Input Stored B data to A bus
H H X X L X Input Output Real-time A data to B bus
H H L X H X Input Output Stored A data to B bus
H L L L H H Output Output
Stored A data to B bus and
stored B data to A bus
†
The data output functions may be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input functions are
always enabled; i.e., data at the bus pins is stored on every low-to-high transition on the clock inputs.
‡
Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.
logic symbol
§
≥1
1
2
A1
2B1
1
4D
6D17
26
OEBA
7
5
5
≥1
EN1 [BA]
14
G7
27
SAB
C4
28
CLKAB
G5
15
SBA
16
CLKBA
EN2 [AB]
1
OEAB
C6
A2
3
B2
25
A3
4
B3
24
A4
5
B4
23
A5
10
B5
20
A6
11
B6
19
A7
12
B7
18
A8
13
B8
17
§
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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