TEXAS INSTRUMENTS 74AC11008 Technical data

74AC11008

QUADRUPLE 2-INPUT POSITIVE-AND GATE

SCAS014C – AUGUST 1987 – REVISED APRIL 1996

D

Flow-Through Architecture Optimizes
PCB Layout

D

Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise

D

EPIC

 (Enhanced-Performance Implanted

CMOS) 1-µm Process

D

500-mA Typical Latch-Up Immunity at
125°C

D

Package Options Include Plastic
Small-Outline (D) and Thin Shrink

D, N, OR PW PACKAGE

(TOP VIEW)

1A
1Y

2Y
GND
GND

3Y

4Y

4B

16

1

15

2

14

3

13

4

12

5

11

6

10

7
8

9

1B
2A
2B
V
V
3A
3B
4A

CC
CC

Small-Outline (PW) Packages, and
Standard Plastic 300-mil DIPs (N)

description

This device contains four independent 2-input AND gates. It performs the Boolean function

Y+A • BorY

+A)

The 74AC11008 is characterized for operation from –40°C to 85°C.

in positive logic.

B

FUNCTION TABLE

(each gate)

INPUTS

A B

H H H

L XL

X L L

OUTPUT

Y

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

†

1

1A

16

1B

15

2A

14

2B

11

3A

10

3B

9

4A

8

4B

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

&

2

1Y

3

2Y

6

3Y

7

4Y

Copyright  1996, Texas Instruments Incorporated

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

74AC11008
QUADRUPLE 2-INPUT POSITIVE-AND GATE

SCAS014C – AUGUST 1987 – REVISED APRIL 1996

logic diagram (positive logic)

1

1A

16

1B

15

2A

14

2B

11

3A

10

3B

9

4A

8

4B

2

1Y

3

2Y

6

3Y

7

4Y

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V

Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through V

Maximum power dissipation at TA = 55°C (in still air) (see Note 2):D package 1.3 W. . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

N package 1.1 W. . . . . . . . . . . . . . . . . . . .

PW package 0.5 W. . . . . . . . . . . . . . . . . . .

†

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER

TEST CONDITIONS

V

MIN

MAX

UNIT

I

mA

74AC11008

QUADRUPLE 2-INPUT POSITIVE-AND GATE

SCAS014C – AUGUST 1987 – REVISED APRIL 1996

recommended operating conditions

MIN NOM MAX UNIT

V

V

V

V
V

I

OH

I

OL

∆t/∆v Input transition rise or fall rate 0 10 ns/V
T

Supply voltage 3 5 5.5 V

CC

VCC = 3 V 2.1

High-level input voltage

IH

Low-level input voltage

IL

Input voltage 0 V

I

Output voltage 0 V

O

High-level output current

Low-level output current

Operating free-air temperature –40 85 °C

A

VCC = 4.5 V
VCC = 5.5 V 3.85
VCC = 3 V 0.9
VCC = 4.5 V
VCC = 5.5 V 1.65

VCC = 3 V –4
VCC = 4.5 V
VCC = 5.5 V –24
VCC = 3 V 12
VCC = 4.5 V
VCC = 5.5 V 24

3.15

1.35

CC
CC

–24

24

V

V

V
V

mA

mA

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

CC

3 V 2.9 2.9

IOH = –50 µA

V

OH

V

OL

I

I

I

CC

C

†

Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.

i

IOH = –4 mA 3 V 2.58 2.48

IOH = –24 mA
IOH = –75 mA

IOL = 50 µA

IOL = 12 mA 3 V 0.36 0.44

= 24

OL

IOL = 75 mA
VI = VCC or GND 5.5 V ±0.1 ±1 µA
VI = VCC or GND, IO = 0 5.5 V 4 40 µA
VI = VCC or GND 5 V 3.5 pF

†

†

4.5 V 4.4 4.4

5.5 V 5.4 5.4

4.5 V 3.94 3.8

5.5 V 4.94 4.8

5.5 V 3.85
3 V 0.1 0.1

4.5 V 0.1 0.1

5.5 V 0.1 0.1

4.5 V 0.36 0.44

5.5 V 0.36 0.44

5.5 V 1.65

TA = 25°C

MIN TYP MAX

V

V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

74AC11008

PARAMETER

MIN

MAX

UNIT

A or B

Y

ns

PARAMETER

MIN

MAX

UNIT

A or B

Y

ns

QUADRUPLE 2-INPUT POSITIVE-AND GATE

SCAS014C – AUGUST 1987 – REVISED APRIL 1996

switching characteristics over recommended operating free-air temperature range,

= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)

V

CC

FROM TO

(INPUT) (OUTPUT)

t

PLH

t

PHL

switching characteristics over recommended operating free-air temperature range,
V

= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

CC

FROM TO

(INPUT) (OUTPUT)

t

PLH

t

PHL

operating characteristics, VCC = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT

C

Power dissipation capacitance per gate CL = 50 pF, f = 1 MHz 29 pF

pd

TA = 25°C

MIN TYP MAX

1.5 6.3 9 1.5 10.2

1.5 5.6 7.8 1.5 8.6

TA = 25°C

MIN TYP MAX

1.5 4.3 6.2 1.5 6.9

1.5 5.6 5.9 1.5 6.5

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

NOTES: A. CL includes probe and jig capacitance.

B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.

500 Ω

Figure 1. Load Circuit and Voltage Waveforms

Input

(see Note B)

Output

t

PLH

50% V

CC

50% V

CC

VOLTAGE WAVEFORMS

50% V

CC

50% V

t

PHL

V

CC

V

V

0 V

OH

OL

CC

4

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Copyright © 2007, Texas Instruments Incorporated

PACKAGE OPTION ADDENDUM

www.ti.com

24-May-2007

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

74AC11008D ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br)

74AC11008DE4 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br)

74AC11008DG4 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br)

74AC11008DR ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br)

74AC11008DRE4 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br)

74AC11008DRG4 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br)

74AC11008N ACTIVE PDIP N 16 25 Pb-Free

74AC11008NE4 ACTIVE PDIP N 16 25 Pb-Free

74AC11008PWLE OBSOLETE TSSOP PW 16 TBD Call TI Call TI

74AC11008PWR ACTIVE TSSOP PW 16 2000 Green (RoHS &

no Sb/Br)

74AC11008PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS &

no Sb/Br)

74AC11008PWRG4 ACTIVE TSSOP PW 16 2000 Green(RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(RoHS)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU N / A for Pkg Type

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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Addendum-Page 1

PACKAGE OPTION ADDENDUM

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

24-May-2007

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

TAPE AND REEL INFORMATION

19-Mar-2008

*All dimensions are nominal

Device Package

74AC11008DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

74AC11008PWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1

Type

Package
Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Mar-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

74AC11008DR SOIC D 16 2500 333.2 345.9 28.6

74AC11008PWR TSSOP PW 16 2000 346.0 346.0 29.0

Pack Materials-Page 2

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

1,20 MAX

14

0,30
0,19

8

4,50
4,30

PINS **

7

0,15
0,05

Seating Plane

8

14

1

A

DIM

0,10

6,60
6,20

M

0,10

0,15 NOM

0°–8°

2016

Gage Plane

24

0,25

0,75
0,50

28

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

4040064/F 01/97

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