Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
500-mA Typical Latch-Up Immunity at
125°C
D
Package Options Include Plastic
Small-Outline (D) and Thin Shrink
D, N, OR PW PACKAGE
(TOP VIEW)
1A
1Y
2Y
GND
GND
3Y
4Y
4B
16
1
15
2
14
3
13
4
12
5
11
6
10
7
8
9
1B
2A
2B
V
V
3A
3B
4A
CC
CC
Small-Outline (PW) Packages, and
Standard Plastic 300-mil DIPs (N)
description
This device contains four independent 2-input AND gates. It performs the Boolean function
Y+A • BorY
+A)
The 74AC11008 is characterized for operation from –40°C to 85°C.
in positive logic.
B
FUNCTION TABLE
(each gate)
INPUTS
AB
HHH
LXL
XLL
OUTPUT
Y
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
†
1
1A
16
1B
15
2A
14
2B
11
3A
10
3B
9
4A
8
4B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
&
2
1Y
3
2Y
6
3Y
7
4Y
Copyright 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
74AC11008
QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCAS014C – AUGUST 1987 – REVISED APRIL 1996
logic diagram (positive logic)
1
1A
16
1B
15
2A
14
2B
11
3A
10
3B
9
4A
8
4B
2
1Y
3
2Y
6
3Y
7
4Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CC
3 V2.92.9
IOH = –50 µA
V
OH
V
OL
I
I
I
CC
C
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
i
IOH = –4 mA3 V2.582.48
IOH = –24 mA
IOH = –75 mA
IOL = 50 µA
IOL = 12 mA3 V0.360.44
= 24
OL
IOL = 75 mA
VI = VCC or GND5.5 V±0.1±1µA
VI = VCC or GND,IO = 05.5 V440µA
VI = VCC or GND5 V3.5pF
†
†
4.5 V4.44.4
5.5 V5.45.4
4.5 V3.943.8
5.5 V4.944.8
5.5 V3.85
3 V0.10.1
4.5 V0.10.1
5.5 V0.10.1
4.5 V0.360.44
5.5 V0.360.44
5.5 V1.65
TA = 25°C
MINTYPMAX
V
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
74AC11008
PARAMETER
MIN
MAX
UNIT
A or B
Y
ns
PARAMETER
MIN
MAX
UNIT
A or B
Y
ns
QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCAS014C – AUGUST 1987 – REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
FROMTO
(INPUT)(OUTPUT)
t
PLH
t
PHL
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
FROMTO
(INPUT)(OUTPUT)
t
PLH
t
PHL
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETERTEST CONDITIONSTYPUNIT
C
Power dissipation capacitance per gateCL = 50 pF,f = 1 MHz29pF
pd
TA = 25°C
MINTYPMAX
1.56.391.510.2
1.55.67.81.58.6
TA = 25°C
MINTYPMAX
1.54.36.21.56.9
1.55.65.91.56.5
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
NOTES: A. CL includes probe and jig capacitance.
B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
500 Ω
Figure 1. Load Circuit and Voltage Waveforms
Input
(see Note B)
Output
t
PLH
50% V
CC
50% V
CC
VOLTAGE WAVEFORMS
50% V
CC
50% V
t
PHL
V
CC
V
V
0 V
OH
OL
CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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