Datasheet CY29FCT818CTSOCT, CY29FCT818CTSOC, CY29FCT818CTQCT, CY29FCT818CTQC, CY29FCT818CTPC Datasheet (Texas Instruments)
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Diagnostic Scan Register
CY29FCT818T
SCCS012 - May 1994 - Revised February 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright © 2000, Texas Instruments Incorporated
Features
• Function,pinoutanddrivecompatiblewithFCT,FLogic
and AM29818
• FCT-C speed at 6.0 ns max. (Com’l),
FCT-A speed at 12.0 ns max. (Mil)
• Reduced V
OH
(typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• Matched rise and fall times
• Fully compatible with TTLinput andoutput logic levels
• Sink current 64 mA (Com’l),
20 mA (Mil)
Source current 32 mA (Com’l),
3 mA (Mil)
• 8-Bit pipeline and shadow register
• ESD > 2000V
Functional Description
The FCT818T contains a high-speed 8-bit general-purpose
data pipeline register and a high-speed 8-bit shadow register.
The general-purpose register can be used in an 8-bit wide
data path fora normalsystem application. The shadow regis-
teris designedforapplications, suchas diagnosticsinsequential circuits, where it is desirable to load known data at a specific locationin the circuit andto read the dataat that location.
The shadow registers can load data from the output of the
FCT818T, and can be used as a right-shift register with
bit-serial input SDI and output SDO, using DCLK. The data
register input is multiplexed toenableloading fromthe shadow
register orfrom thedata inputpins usingPCLK. Notethat data
can be loadedsimultaneously from the shadow registerto the
pipeline register, andfrom the pipeline register to the shadow
register provided set-up and hold time requirements are
satisfied with respect to the two independent clock inputs.
In a typical application, the general-purpose register in the
FCT818T replaces an 8-bit data register in the normal data
path ofa system.The shadowregister isplaced in anauxiliary
bit-serial loop whichis used fordiagnostics. During diagnostic
operation,data isshifted seriallyinto theshadow register,then
transferred to the general purpose register to load a known
value into the data path. To read the contents at that point in
thedata path,the datais transferredfromthe dataregister into
the shadow register, then shifted serially in the auxiliary
diagnostic loop to make it accessible to the diagnostics
controller.This data isthen compared withthe expectedvalue
to diagnose faulty operation of the sequential circuit.
The outputs are designed with a power-off disable feature to
allow for liv e insertion of boards.
Logic Block Diagram Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
OE
DCLK
D
1
D
2
D
3
D
4
D
5
D
0
D
6
D
7
SDI
GND
V
CC
MODE
SDO
Y
0
Y
1
Y
3
Y
4
Y
5
Y
7
Y
6
15
Y
2
Top View
28
4
3
2
1
27
2021 222324
26
19
D5D
4
Y
2
Y
5
25
Y
1
Y
7
D
7
SDI
D
0
NC
NC
DCLK
OE
MODE
Y
0
GND
NC
NC
Y
4
D
2
LCC
Top View
Y
3
V
cc
567891011
D
1
D
3
12
13
14
15
16
17
18
D
6
PCLK
Y
6
SDO
PCLK
DIP, SOIC, QSOP
8-BIT
SHADOW
REGISTER
CLK
D
Q
MUX
8-BIT
PIPELINE
REGISTER
OE
PCLK
MODE
DCLK
SDI
SDO
D
0−D7
P0−P
7
Y0−Y
7
8
8
8
8
S
0−S7
CY29FCT818T
2
Maximum Ratings
[2, 3]
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–65°C to +135°C
Supply Voltage to Ground Potential...............–0.5V to +7.0V
DC Input Voltage............................................–0.5V to +7.0V
DC Output Voltage.........................................–0.5V to +7.0V
DC Output Current (Maximum Sink Current/Pin).......120 mA
Power Dissipation..........................................................0.5W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Function Table
[1]
Inputs Inputs
Shadow
Register
Pipeline
Register OperationMODE SDI DCLK PCLK SDO
L
L
X
X
X
X S
7
S
7
S0←SDI
S
i←Si-1
NA
NA
P
i←Di
Serial Shift; D7–D0 Output Disabled
Load Pipeline Register from Data Input
H
H
H
L
H
X
X
X
X
L
H
SDI
Si←Y
i
Hold
NA
NA
NA
P
i←Si
Load Shadow Register from Y Output
Hold Shadow Register; D
7−D0
Output Enabled
Load Pipeline Register from Shadow Register
Operating Range
Range Range
Ambient
Temperature V
CC
Commercial All –40°C to +85°C 5V ± 5%
Military
[4]
All –55°C to +125°C 5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Typ.
[5]
Max. Unit
V
OH
Output HIGH Voltage VCC=Min., IOH=–32 mA Com’l 2.0 V
VCC=Min., IOH=–15 mA Com’l 2.4 3.3 V
VCC=Min., IOH=–3 mA Mil 2.4 3.3 V
V
OL
Output LOW Voltage VCC=Min., IOL=64 mA Com’l 0.3 0.55 V
VCC=Min., IOL=20 mA Mil 0.3 0.55 V
V
IH
Input HIGH Voltage 2.0 V
V
IL
Input LOW Voltage 0.8 V
V
H
Hysteresis
[6]
All inputs 0.2 V
V
IK
Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 –1.2 V
I
I
Input HIGH Current VCC=Max., VIN=V
CC
5 µA
I
IH
Input HIGH Current VCC=Max., VIN=2.7V ±1 µA
I
IL
Input LOW Current VCC=Max., VIN=0.5V ±1 µA
I
OZH
Off State HIGH-Level Output
Current
VCC=Max., V
OUT
=2.7V 10 µA
I
OZL
Off State LOW-Level
Output Current
VCC=Max., V
OUT
=0.5V –10 µA
I
OS
Output Short Circuit Current
[7]
VCC=Max., V
OUT
=0.0V –60 –120 –225 mA
I
OFF
Power-Off Disable VCC=0V, V
OUT
=4.5V ±1 µA
CY29FCT818T
3
Document #: 38-00275-B
Notes:
1. NA = Not Applicable
2. Unless otherwise noted, these limits are over the operating free-air temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V
CC
or ground.
4. T
A
is the “instant on” case temperature.
5. Typical values are at V
CC
=5.0V, TA=+25˚C ambient.
6. This parameter is specified but not tested.
7. Not more thanone output shouldbe shortedat a time.Duration of short should notexceed one second.The use ofhigh-speed test apparatusand/or sample
and hold techniquesare preferable in order to minimizeinternal chip heatingand more accuratelyreflect operational values.Otherwise prolonged shorting of
a high output may raise the chip temperature wellabovenormal andthereby cause invalidreadings in other parameters tests.In any sequenceof parameter
tests, I
OS
tests should be performed last.
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Typ.
[5]
Max. Unit
Capacitance
[8]
Parameter Description Test Conditions Typ.
[5]
Max. Unit
C
IN
Input Capacitance 5 10 pF
C
OUT
Output Capacitance 9 12 pF
Power Supply Characteristics
Parameter Description Test Conditions Typ.
[5]
Max. Unit
I
CC
Quiescent Power Supply Current VCC=Max., VIN<0.2V, VIN>VCC–0.2V 0.2 1.5 mA
∆I
CC
Quiescent Power Supply Current
(TTL inputs HIGH)
VCC=Max., VIN=3.4V, f1=0, Outputs Open
[8]
0.5 2.0 mA
I
CCD
Dynamic Power Supply Current
[9]
VCC=Max., 50% Duty Cycle, Outputs Open,
One Input Toggling,
OE=GND,
V
IN
<0.2V or VIN>VCC–0.2V
0.25 mA/MHz
I
C
Total Power Supply Current
[10]
VCC=Max., 50% Duty Cycle, Outputs Open,
f
0
=10 MHz, One Bit Toggling at f1=5 MHz,
OE=GND, VIN<0.2V or VIN>VCC–0.2V
5.3 mA
VCC=Max., 50% Duty Cycle, Outputs Open,
f
0
=10 MHz, One Bit Toggling at f1=5 MHz,
OE=GND, VIN=3.4V or VIN=GND
7.3 mA
VCC=Max., 50% Duty Cycle, Outputs Open,
f
0
=10 MHz, Eight Bits and Four Controls
Toggling, f
1
=5 MHz, OE=GND,
V
IN
<0.2V or VIN>VCC–0.2V
17.8
[11]
mA
VCC=Max., 50% Duty Cycle, Outputs Open,
f
0
=10 MHz, Eight Bits and Four Controls
Toggling, f
1
=5 MHz, OE=GND,
V
IN
=3.4V or VIN=GND
30.8
[11]
mA
Notes:
8. Per TTL driven input (V
IN
=3.4V); all other inputs at VCC or GND.
9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
10. I
C
=I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
IC=ICC+∆ICCDHNT+I
CCD(f0
/2 + f1N1)
I
CC
= Quiescent Current with CMOS input levels
∆I
CC
= Power Supply Current for a TTL HIGH input (VIN=3.4V)
D
H
= Duty Cycle for TTL inputs HIGH
N
T
= Number of TTL inputs at D
H
I
CCD
= Dynamic Current caused by an input transition pair (HLH or LHL)
f
0
= Clock frequency for registered devices, otherwise zero
f
1
= Input signal frequency
N
1
= Number of inputs changing at f
1
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
CY29FCT818T
4
Switching Characteristics Over the Operating Range
[12]
Parameter Description
FCT818AT FCT818CT
Unit Fig. No.
[13]
Military Commercial
Min. Max. Min. Max.
t
PD
Propagation Delay
PCLK to Y
MODE to SDO
SDI to SDO
DCLK to SDO
12
18
18
30
6.0
7.2
7.1
7.2
ns
ns
ns
ns
5
6
3
5
t
S
Set-Up Time
D to PCLK
MODE to PCLK
Y to DCLK
MODE to DCLK
SDI to DCLK
DCLK to PCLK
PCLK to DCLK
6
15
5
12
10
15
45
2.0
3.5
2.0
3.5
3.5
3.5
8.5
ns
ns
ns
ns
ns
ns
ns
4
t
H
Hold Time
D to PCLK
MODE to PCLK
Y to DCLK
MODE to DCLK
SDI to DCLK
2
0
5
5
0
1.5
0
1.5
1.5
0
ns
ns
ns
ns
ns
4
t
PLZ
Output Disable Time LOW
OE to Y
DCLK to D
20
45
5.5
5.5
ns
ns
7
5
t
PHZ
Output Disable Time HIGH
OE to Y
DCLK to D
30
90
8.0
8.0
ns
ns
8
5
t
PZL
Output Enable Time LOW
OE to Y
DCLK to D
20
35
8.0
9.0
ns
ns
7
5
t
PZH
Output Enable Time HIGH
OE to Y
DCLK to D
20
30
8.5
9.0
ns
ns
8
5
t
W
Pulse Width
PCLK (HIGH and LOW)
DCLK (HIGH and LOW)
15
25
5.0
5.0
ns
ns
5
5
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
6.0 CY29FCT818CTPC P13/13A 24-Lead (300-Mil) Molded DIP Commercial
CY29FCT818CTQCT Q13 24-Lead (150-Mil) QSOP
CY29FCT818CTSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC
12.0 CY29FCT818ATDMB D14 24-Lead (300-Mil) CerDIP Military
Notes:
12. Minimum limits are specified but not tested on Propagation Delays.
13. See “Parameter Measurement Information” in the General Information section.
CY29FCT818T
5
Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL-STD-1835 D-9 Config.A
28-Square Leadless Chip Carrier L64
MIL-STD-1835 C-4
24-Lead (300-Mil) Molded DIP P13/P13A
CY29FCT818T
6
Package Diagrams (continued)
24-Lead Quarter Size Outline Q13
24-Lead (300-Mil) Molded SOIC
S13
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Copyright 2000, Texas Instruments Incorporated
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