TEXAS INSTRUMENTS UC1823A, 1825A Technical data
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High Speed PWM Controller
FEATURES
Improved versions of the
•
UC3823/UC3825 PWMs
Compatible with Voltage or
•
Current-Mode Topologies
Practical Operation at Switching
•
Frequencies to 1MHz
50ns Propagation Delay to Output
•
High Current Dual Totem Pole
•
Outputs (2A Peak)
Trimmed Oscillator Discharge Current
•
Low 100µA Startup Current
•
• Pulse-by-Pulse Current Limiting
Comparator
• Latched Overcurrent Comparator With
Full Cycle Restart
DESCRIPTION
The UC3823A & B and the UC3825A & B family of PWM control ICs are
improved versions of the standard UC3823 & UC3825 family. Performance
enhancements have been made to several of the circuit blocks. Error ampli
fier gain bandwidth product is 12MHz while input offset voltage is 2mV. Cur
rent limit threshold is guaranteed to a tolerance of 5%. Oscillator discharge
current is specified at 10mA for accurate dead time control. Frequency ac
curacy is improved to 6%. Startup supply current, typically 100µA, is ideal
for off-line applications. The output drivers are redesigned to actively sink
current during UVLO at no expense to the startup current specification. In
addition each output is capable of 2A peak currents during transitions.
Functional improvements have also been implemented in this family. The
UC3825 shutdown comparator is now a high-speed overcurrent comparator
with a threshold of 1.2V. The overcurrent comparator sets a latch that en
sures full discharge of the soft start capacitor before allowing a restart.
While the fault latch is set, the outputs are in the low state. In the event of
continuous faults, the soft start capacitor is fully charged before discharge
to insure that the fault frequency does not exceed the designed soft start
period. The UC3825 Clock pin has become CLK/LEB. This pin combines
the functions of clock output and leading edge blanking adjustment and has
been buffered for easier interfacing.
application
INFO
available
UC1823A,B/1825A,B
UC2823A,B/2825A,B
UC3823A,B/3825A,B
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BLOCK DIAGRAM
(continued)
* Note: 1823A,B Version Toggles Q and Q are always low
SLUS334A - AUGUST 1995 - REVISED NOVEMBER 2000
UDG-95101
DESCRIPTION (cont.)
The UC3825A,B has dual alternating outputs and the
same pin configuration of the UC3825. The UC3823A,B
outputs operate in phase with duty cycles from zero to
less than 100%. The pin configuration of the UC3823A,B
is the same as the UC3823 except pin 11 is now an out
put pin instead of the reference pin to the current limit
comparator. “A” version parts have UVLO thresholds
identical to the original UC3823/25. The “B” versions
have UVLO thresholds of 16 and 10V, intended for ease
of use in off-line applications.
Consult Application Note U-128 for detailed technical
and applications information. Contact the factory for fur
ther packaging and availability information.
Device UVLO Dmax
UC3823A 9.2V/8.4V < 100%
UC3823B 16V/10V < 100%
UC3825A 9.2V/8.4V < 50%
UC3825B 16V/10V < 50%
UC1823A,B/1825A,B
UC2823A,B/2825A,B
UC3823A,B/3825A,B
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VC, VCC) . . . . . . . . . . . . . . . . . . . . . . . . . 22V
Output Current, Source or Sink (Pins OUTA, OUTB)
DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A
Pulse (0.5µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2A
Power Ground (PGND). . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.2V
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Analog Inputs
(INV, NI, RAMP). . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 7V
(ILIM, SS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 6V
Clock Output Current (CLK/LEB) . . . . . . . . . . . . . . . . . . . –5mA
Error Amplifier Output Current (EAOUT) . . . . . . . . . . . . . . 5mA
Soft Start Sink Current (SS) . . . . . . . . . . . . . . . . . . . . . . . 20mA
Oscillator Charging Current (RT) . . . . . . . . . . . . . . . . . . . –5mA
Power Dissipation at TA= 60°C . . . . . . . . . . . . . . . . . . . . . . 1W
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
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Junction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +150°C
Lead Temperature (Soldering, 10 sec.). . . . . . . . . . . . . . 300°C
All currents are positive into, negative out of the specified ter
minal. Consult Packaging Section of Databook for thermal limi
tations and considerations of packages.
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CONNECTION DIAGRAMS
DIL-16, SOIC-16, (Top View)
J or N Package;DW Package
ELECTRICAL CHARACTERISTICS:
the UC1823A,B and UC1825A,B; –40°C to +85°C for the UC2823A,B and UC2825A,B; 0°C to +70°C for the UC3823A,B and
UC3825A,B; RT = 3.65k, CT= 1nF, VCC = 12V, TA=T
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Reference Section
Output Voltage T
Line Regulation 12 < VCC < 20V 2 15 mV
Load Regulation 1mA < I
Total Output Variation Line, Load, Temp 5.03 5.17 V
Temperature Stability T
Output Noise Voltage 10Hz < f < 10kHz (Note 1) 50 µVRMS
Long Term Stability T
Short Circuit Current VREF = 0V 30 60 90 mA
Unless otherwise stated, these specifications apply for TA= –55°C to +125°C for
J.
= 25°C, Io = 1mA 5.05 5.1 5.15 V
J
< 10mA 5 20 mV
O
< TA<T
MIN
= 125°C, 1000 hours (Note 1) 5 25 mV
J
MAX
PLCC-20, LCC-20, (Top View)
Q, L Packages
(Note 1) 0.2 0.4 mV/°C
2
UC1823A,B/1825A,B
UC2823A,B/2825A,B
UC3823A,B/3825A,B
ELECTRICAL CHARACTERISTICS:
Unless otherwise stated, these specifications apply for TA= –55°C to +125°C for
the UC1823A,B and UC1825A,B; –40°C to +85°C for the UC2823A,B and UC2825A,B; 0°C to +70°C for the UC3823A,B and
UC3825A,B; RT = 3.65k, CT= 1nF, VCC = 12V, TA=T
J.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Oscillator Section
Initial Accuracy T
= 25°C (Note 1) 375 400 425 kHz
J
Total Variation Line, Temperature (Note 1) 350 450 kHz
Voltage Stability 12V < VCC < 20V 1 %
Temperature Stability T
MIN
< TA<T
Initial Accuracy RT= 6.6k, CT = 220pF, T
(Note 1) 5 %
MAX
= 25°C (Note 1) 0.9 1 1.1 MHz
A
Total Variation RT = 6.6k, CT = 220pF (Note 1) 0.85 1.15 MHz
Clock Out High 3.7 4 V
Clock Out Low 0 0.2 V
Ramp Peak 2.6 2.8 3 V
Ramp Valley 0.7 1 1.25 V
Ramp Valley to Peak 1.6 1.8 2 V
Oscillator Discharge Current RT = Open, V
= 2V 9 10 11 mA
CT
Error Amplifier Section
Input Offset Voltage 210mV
Input Bias Current 0.6 3 µA
Input Offset Current 0.1 1 µA
Open Loop Gain 1V < V
CMRR 1.5V < V
< 4V 60 95 dB
O
< 5.5V 75 95 dB
CM
PSRR 12V < VCC < 20V 85 110 dB
Output Sink Current V
Output Source Current V
Output High Voltage I
Output Low Voltage I
= 1V 1 2.5 mA
EAOUT
= 4V –0.5 –1.3 mA
EAOUT
= –0.5mA 4.5 4.7 5 V
EAOUT
= 1mA 0 0.5 1 V
EAOUT
Gain Bandwidth Product F = 200kHz 6 12 MHz
Slew Rate (Note 1) 6 9 V/µs
PWM Comparator
RAMP Bias Current V
= 0V –1 –8 µA
RAMP
Minimum Duty Cycle 0%
Maximum Duty Cycle 85 %
Leading Edge Blanking R = 2k, C = 470pF 300 375 450 ns
LEB Resistor V
EAOUT Zero D.C. Threshold V
Delay to Output V
CLK/LEB
RAMP
EAOUT
= 3V 8.5 10 11.5 kohm
= 0V 1.1 1.25 1.4 V
= 2.1V, V
= 0 to 2V Step (Note 1) 50 80 ns
RAMP
Current Limit/Start Sequence/Fault Section
Soft Start Charge Current VSS= 2.5V 8 14 20 µA
Full Soft Start Threshold 4.3 5 V
Restart Discharge Current V
= 2.5V 100 250 350 µA
SS
Restart Threshold 0.3 0.5 V
ILIM Bias Current 0 < V
< 2V 15 µA
ILIM
Current Limit Threshold 0.95 1 1.05 V
3
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