TEXAS INSTRUMENTS TPS77101, 115, 118, 127, 128 Technical data

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TPS77101/115/118/127/128 / 133 / 150 WITH RESET OUTPUT

TPS77201/215/218/227 / 228 / 233/250 WITH POWER GOOD OUTPUT

150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING

SLVS225D – FEBRUAR Y 2000 – REVISED OCT OBER 2000

D Open Drain Power-On Reset With 220-ms

Delay (TPS771xx)

D Open Drain Power-Good (PG) Status

Output (TPS772xx)

D 150-mA Low-Dropout Voltage Regulator
D Available in 1.5-V, 1.8-V, 2.7-V, 2.8-V, 3.3-V,

5.0-V Fixed Output and Adjustable Versions

FB/SENSE

RESET

EN

GND

TPS771xx

DGK Package

(TOP VIEW)

1
2
3
4

8
7
6
5

OUT
OUT
IN
IN

D Dropout Voltage Typically 115 mV

at 150 mA (TPS77133, TPS77233)

D Ultralow 92-µA Quiescent Current (Typ)

TPS772xx

DGK Package

(TOP VIEW)

D 8-Pin MSOP (DGK) Package
D Low Noise (55 µV

) Without External

rms

Filter (Bypass) Capacitor (TPS77118,
TPS77218)

D 2% Tolerance Over Specified Conditions

for Fixed-Output Versions

D Fast Transient Response
D Thermal Shutdown Protection

FB/SENSE

300

1

PG
EN

GND

2
3
4

TPS77x33

DROPOUT VOLTAGE

JUNCTION TEMPERATURE

8
7
6
5

vs

description

The TPS771xx and TPS772xx are low-dropout
regulators with integrated power-on reset and
power good (PG) function respectively. These
devices are capable of supplying 150 mA of output
current with a dropout of 115 mV (TPS77133,
TPS77233). Quiescent current is 92 µA at full load
dropping down to 1 µA when device is disabled.
These devices are optimized to be stable with a
wide range of output capacitors including low ESR
ceramic (10 µF) or low capacitance (1 µF)
tantalum capacitors. These devices have ex­tremely low noise output performance (55 µV

rms

)
without using any added filter capacitors.
TPS771xx and TPS772xx are designed to have
fast transient response for larger load current
changes.

The TPS771xx or TPS772xx is offered in 1.5 V,

1.8-V, 2.7-V, 2.8-V, 3.3-V, and 5.0 V fixed-voltage versions and in an adjustable version (programmable over
the range of 1.5 V to 5.5 V). Output voltage tolerance is 2% over line, load, and temperature ranges. The
TPS771xx and TPS772xx families are available in 8-pin MSOP (DGK) packages.

250

200

150

100

– Dropout Voltage – mV

50

DO

V

0

–50

–40 0 40 80 120 160

TJ – Junction Temperature – °C

IO = 150 mA

IO = 10 mA

OUT
OUT
IN
IN

IO = 0 A

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 115 mV
at an output current of 150 mA for 3.3 volt option) and is directly proportional to the output current. Additionally ,
since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent
of output loading (typically 92 µA over the full range of output current, 0 mA to 150 mA). These two key
specifications yield a significant improvement in operating life for battery-powered systems.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2000, Texas Instruments Incorporated

1

TPS77101/115/118/127/128 / 133 / 150 WITH RESET OUTPUT

125°C

TPS77201/215/218/227 / 228 / 233/250 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING

SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000

description (continued)

The device is enabled when the EN pin is connected to a low-level input voltage. This LDO family also features
a sleep mode; applying a TTL high signal to EN
current to less than 1 µA at T

= 25°C.

J

The TPS771xx features an integrated power-on reset, commonly used as a supply voltage supervisor (SVS)
or reset output voltage. The RESET

output of the TPS771xx initiates a reset in DSP, microcomputer or
microprocessor systems at power up and in the event of an undervoltage condition. An internal comparator in
the TPS771xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated
output voltage. When OUT
a 220 ms delay . RESET

reaches 95% of its regulated voltage, RESET will go to a high-impedance state after

will go to low-impedance state when OUT is pulled below 95% (i.e. over load condition)

of its regulated voltage.
For the TPS772xx, the power good terminal (PG) is an active high output, which can be used to implement a

power-on reset or a low-battery indicator. An internal comparator in the TPS772xx monitors the output voltage
of the regulator to detect an undervoltage condition on the regulated output voltage. When OUT
of its regulated voltage, PG will go to a low-impedance state. PG will go to a high-impedance state when OUT
is above 82% of its regulated voltage.

AVAILABLE OPTIONS

OUTPUT VOLTAGE

T

J

°

–40°C to

NOTE: The TPS77101 and TPS77201 are programmable using an external resistor divider (see application information).

°

The DGK package is available taped and reeled. Add an R suffix to the device type (e.g., TPS77101DGKR).

(V)

TYP

5.0 TPS77150DGK AFV TPS77250DGK AGE

3.3 TPS77133DGK AFU TPS77233DGK AGD

2.8 TPS77128DGK AFS TPS77228DGK AGB

2.7 TPS77127DGK AFR TPS77227DGK AGA

1.8 TPS77118DGK AFP TPS77218DGK AFY

1.5 TPS77115DGK AFO TPS77215DGK AFX

Adjustable

1.5 V to 5.5 V

(enable) shuts down the regulator, reducing the quiescent

falls below 82%

PACKAGED DEVICES

MSOP (DGK)

TPS771xx

SYMBOL

TPS77101DGK AFN TPS77201DGK AFW

TPS772xx

SYMBOL

2

V

I

0.1 µF

5

IN

6

IN

SENSE

3

EN

PG or

RESET

GND

4

OUT
OUT

7
8
1

2

V

PG or RESET

+

10 µF

O

Figure 1. Typical Application Configuration (For Fixed Output Options)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagrams

adjustable version

IN

EN

_

TPS77101/115/118/127/128 / 133 / 150 WITH RESET OUTPUT

TPS77201/215/218/227 / 228 / 233/250 WITH POWER GOOD OUTPUT

150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING

SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000

PG or RESET

V

= 1.1834 V

ref

fixed-voltage version

IN

EN

V

= 1.1834 V

ref

+

+
_

GND

_
+

220 ms Delay

(for TPS771xx Option)

+
_

220 ms Delay

(for TPS771xx Option)

OUT

R1

FB/SENSE

R2

External to the Device

PG or RESET

OUT

SENSE

R1

GND

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

R2

3

TPS77101/115/118/127/128 / 133 / 150 WITH RESET OUTPUT
TPS77201/215/218/227 / 228 / 233/250 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING

SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000

Terminal Functions

TERMINAL

NAME NO.

TPS771XX

FB/SENSE 1 I Feedback input voltage for adjustable device (sense input for fixed options)
RESET 2 O Reset output
EN 3 I Enable input
GND 4 Regulator ground
IN 5, 6 I Input voltage
OUT 7, 8 O Regulated output voltage

TPS772XX

FB/SENSE 1 I Feedback input voltage for adjustable device (sense input for fixed options)
PG 2 O Power good
EN 3 I Enable input
GND 4 Regulator ground
IN 5, 6 I Input voltage
OUT 7, 8 O Regulated output voltage

I/O

DESCRIPTION

TPS771xx RESET timing diagram

V

I

†

V

res

†

V

res

V

O

Threshold

Voltage

RESET
Output

Output

Undefined

†

V

is the minimum input voltage for a valid RESET

res

semiconductor symbology .

‡

VIT – Trip voltage is typically 5% lower than the output voltage (95%VO) V

‡

V

IT+

‡

V

IT–

220 ms
Delay

. The symbol V

t

‡

V

IT+

‡

V

IT–

t

220 ms
Delay

Output
Undefined

t

is not currently listed within EIA or JEDEC standards for

res

to V

IT–

is the hysteresis voltage.

IT+

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS77201/215/218/227 / 228 / 233/250 WITH POWER GOOD OUTPUT

TPS772xx PG timing diagram

V

I

TPS77101/115/118/127/128 / 133 / 150 WITH RESET OUTPUT

150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING

SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000

†

V

res

V

O

Threshold

Voltage

PG

Output

Output

Undefined

†

V

is the minimum input voltage for a valid PG. The symbol V

res

symbology.

‡

VIT – Trip voltage is typically 18% lower than the output voltage (82%VO) V

V

IT+

‡

‡

V

IT–

is not currently listed within EIA or JEDEC standards for semiconductor

res

V

IT+

‡

IT–

to V

is the hysteresis voltage.

IT+

t

‡

V

IT–

t

t

†

V

res

Output
Undefined

absolute maximum ratings over operating junction temperature range (unless otherwise noted)

Input voltage range, V
Voltage range at EN
Maximum RESET

Maximum PG voltage (TPS772xx) 16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak output current Internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage, V
Operating virtual junction temperature range, T
Storage temperature range, T

ESD rating, HBM 2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to network terminal ground.

, (see Note 1) –0.3 V to 13.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

–0.3 V to 16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

voltage (TPS771xx) 16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(OUT, FB) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

J

Ĕ

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TPS77101/115/118/127/128 / 133 / 150 WITH RESET OUTPUT

DGK

TPS77201/215/218/227 / 228 / 233/250 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING

SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000

DISSIPATION RATING TABLE – FREE-AIR TEMPERA TURES

PACKAGE

DGK

AIR FLOW

(CFM)

0 266.2 3.84 376 mW 3.76 mW/°C 207 mW 150 mW
150 255.2 3.92 392 mW 3.92 mW/°C 216 mW 157 mW
250 242.8 4.21 412 mW 4.12 mW/°C 227 mW 165 mW

recommended operating conditions

Input voltage, V
Output voltage range, V
Output current, IO (see Note 2) 0 150 mA
Operating virtual junction temperature, TJ (see Note 2) –40 125

†

To calculate the minimum input voltage for your maximum output current, use the following equation: V

NOTE 2: Continuous current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the

†

I

O

device operate under conditions beyond those specified in this table for extended periods of time.

θ

JA

(°C/W)

θ

JC

(°C/W)

TA < 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

= V

I(min)

O(max)

TA = 85°C

POWER RATING

MIN MAX UNIT

2.7 10 V

1.5 5.5 V

°C

+ V

DO(max load)

.

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS77101/115/118/127/128 / 133 / 150 WITH RESET OUTPUT

Out ut voltage

TPS77201/215/218/227 / 228 / 233/250 WITH POWER GOOD OUTPUT

150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING

SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000

electrical characteristics over recommended operating junction temperature range (–40°C to
125°C), V

Output voltage
(see Notes 3 and 4)

Quiescent current (GND current) (see Notes 3 and 4)

Output voltage line regulation (∆VO/VO) (see Note 5)
Load regulation TJ = 25°C 1 mV
Output noise voltage
Output current Limit VO = 0 V 0.9 1.3 A

Peak output current 2 ms pulse width, 50% duty cycle 400 mA
Thermal shutdown junction temperature 144 °C

Standby current
FB input current Adjustable voltage FB = 1.5 V 1 µA

High level enable input voltage 2 V
Low level enable input voltage 0.7 V
Enable input current –1 1 µA
Power supply ripple rejection (TPS77118, TPS77218) f = 1 KHz, TJ = 25°C 55 dB

NOTES: 3. Minimum input operating voltage is 2.7 V or V

= V

I

O(typ)

current 1 mA.

4. If VO < 1.8 V then V

Line regulation (mV) +ǒ%ńV

+ 1 V, IO = 1 mA, EN = 0 V, CO = 10 µF (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Adjustable voltage

1.5-V Output

1.8-V Output

2.7-V Output

2.8-V Output

3.3-V Output

5.0-V Output

= 10 V, V

I(max)

1.5 V ≤ VO ≤ 5.5 V, TJ = 25°C V

1.5 V ≤ VO ≤ 5.5 V 0.98V
TJ = 25°C, 2.7 V < VIN < 10 V 1.5

2.7 V < VIN < 10 V 1.470 1.530
TJ = 25°C, 2.8 V < VIN < 10 V 1.8

2.8 V < VIN < 10 V 1.764 1.836
TJ = 25°C, 3.7 V < VIN < 10 V 2.7

3.7 V < VIN < 10 V 2.646 2.754
TJ = 25°C, 3.8 V < VIN < 10 V 2.8

3.8 V < VIN < 10 V 2.744 2.856
TJ = 25°C, 4.3 V < VIN < 10 V 3.3

4.3 V < VIN < 10 V 3.234 3.366
TJ = 25°C, 6 V < VIN < 10 V 5.0
6 V < VIN < 10 V 4.900 5.100
TJ = 25°C 92

VO + 1 V < VI ≤ 10 V, TJ = 25°C 0.005 %/V
VO + 1 V < VI ≤ 10 V 0.05 %/V

BW = 300 Hz to 100 kHz, TJ = 25°C,
TPS771 18, TPS77218

I(min)

Ǔ

EN = V
EN = V

O(typ)

= 2.7 V:

ǒ

V

V

O

I,
I

+ 1 V , whichever is greater. Maximum input voltage = 10 V, minimum output

* 2.7 V

I(max)

100

TJ = 25°C 1 µA

Ǔ

1000

O

O

1.02V

55 µVrms

O

125

3 µA

V

V

V

µA

If VO > 2.5 V then V

Line regulation (mV) +ǒ%ńV

5. IO = 1 mA to 150 mA

I(max)

= 10 V, V

= Vo + 1 V:

I(min)

100

ǒ

*

ǒ

V

V

I(max)

O

Ǔ

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VO) 1

Ǔ

Ǔ

1000

7

TPS77101/115/118/127/128 / 133 / 150 WITH RESET OUTPUT

(TPS772xx)

Reset

TPS77201/215/218/227 / 228 / 233/250 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING

SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000

electrical characteristics over recommended operating junction temperature range (–40°C to
125°C), V

PG

Reset
(TPS771xx)

V

DO

NOTE 6: IN voltage equals VO(typ) – 100 mV; 1.5 V, 1.8 V, and 2.7 V dropout voltage limited by input voltage range limitations (i.e., 3.3 V input

= V

I

O(typ)

Minimum input voltage for valid PG I
Trip threshold voltage VO decreasing 79 85 %V
Hysteresis voltage Measured at V
Output low voltage VI = 2.7 V, I
Leakage current V
Minimum input voltage for valid RESET I
Trip threshold voltage VO decreasing 92 98 %V
Hysteresis voltage Measured at V
Output low voltage VI = 2.7 V, I
Leakage current V
RESET time-out delay 220 ms

Dropout voltage (see Note 6) 3.3-V Output

voltage needs to drop to 3.2 V for purpose of this test).

+ 1 V, IO = 1 mA, EN = 0 V, CO = 10 µF (unless otherwise noted) (continued)

PARAMETER TEST CONDITIONS

= 300µA V

2.8-V Output

5.0-V Output

(PG)

O

= 5 V 1 µA

(PG)

(RESET)

IO = 150 mA, TJ = 25°C 150
IO = 150 mA, 265
IO = 150 mA, TJ = 25°C 115
IO = 150 mA 200
IO = 150 mA, TJ = 25°C 75
IO = 150 mA 115

= 300 µA 1.1 V

O

(RESET)

= 5 V 1 µA

(PG)

(PG)

(RESET)

≤ 0.8 V 1.1 V

= 1mA 0.15 0.4 V

= 1 mA 0.15 0.4 V

MIN TYP MAX UNIT

0.5 %V

0.5 %V

O
O

O
O

mV

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

V

O

Z

o

V

DO

Output voltage
Ground current vs Junction temperature 6

Power supply rejection ratio vs Frequency 7
Output spectral noise density vs Frequency 8
Output impedance vs Frequency 9

Dropout voltage
Line transient response 12, 14

Load transient response 13, 15
Output voltage and enable pulse vs Time 16
Equivalent series resistance (ESR) vs Output current 18 – 21

vs Output current 2, 3
vs Junction temperature

vs Input voltage 10
vs Junction temperature

4, 5

11

8

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