Texas TMS320x281 series Reference Manual

Download

Page 1

TMS320x281x DSP

Multichannel Buffered Serial Port (McBSP)

Reference Guide

Literature Number: SPRU061B

May 2003 − Revised November 2004

Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third−party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products & application solutions:

Products Applications

Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive

DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security

Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless

Mailing Address: Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

Page 3

Preface



About This Manual

This guide describes how Multichannel Buffered Serial Port (McBSP) works in the TMS320x281x devices.

Read This First

iii

Page 4

Related Documentation From Texas Instruments

grammed boot-loading software). It also describes other contents of the device on-chip boot ROM and identifies where all of the information is located within that memory.

TMS320x281x, 280x Enhanced Controller Area Network (eCAN) Refer-

ence Guide (literature number SPRU074) describes the eCAN that uses

established protocol to communicate serially with other controllers in electrically noisy environments. With 32 fully configurable mailboxes and time-stamping feature, the eCAN module provides a versatile and robust serial communication interface. The eCAN module implemented in the C28x DSP is compatible with the CAN 2.0B standard (active).

TMS320x281x Event Manager (EV) Reference Guide (literature number

SPRU065) describes the EV modules that provide a broad range of functions and features that are particularly useful in motion control and motor control applications. The EV modules include general-purpose (GP) timers, full-compare/PWM units, capture units, and quadrature-encoder pulse (QEP) circuits.

TMS320x281x External Interface (XINTF) Reference Guide (literature

number SPRU067) describes the external interface (XINTF) of the 28x digital signal processors (DSPs).

TMS320x281x, 280x Peripheral Reference Guide (literature number

SPRU566) describes the peripheral reference guides of the 28x digital signal processors (DSPs).

TMS320x281x, 280x Serial Communication Interface (SCI) Reference

Guide (literature number SPRU051) describes the SCI that is a two-wire

asynchronous serial port, commonly known as a UART. The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format.

TMS320x281x, 280x Serial Peripheral Interface (SPI) Reference Guide (lit-

erature number SPRU059) describes the SPI − a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmed bit−transfer rate. The SPI is used for communications between the DSP controller and external peripherals or another controller.

TMS320x281x System Control and Interrupts Reference Guide (literature

number SPRU078) describes the various interrupts and system control features of the 281x digital signal processors (DSPs).

Page 5

Related Documentation From Texas Instruments

The TMS320C28x Instruction Set Simulator Technical Overview (litera-

ture number SPRU608) describes the simulator, available within the Code Composer Studio for TMS320C2000 IDE, that simulates the instruction set of the C28x core.

TMS320C28x DSP/BIOS Application Programming Interface (API) Refer-

ence Guide (literature number SPRU625) describes development using

DSP/BIOS.

3.3 V DSP for Digital Motor Control Application Report (literature num- ber SPRA550). New generations of motor control digital signal processors (DSPs) lower their supply voltages from 5 V to 3.3 V to offer higher performance at lower cost. Replacing traditional 5-V digital control circuitry by 3.3-V designs introduce no additional system cost and no significant complication in interfacing with TTL and CMOS compatible components, as well as with mixed voltage ICs such as power transistor gate drivers. Just like 5-V based designs, good engineering practice should be exercised to minimize noise and EMI effects by proper component layout and PCB design when 3.3-V DSP, ADC, and digital circuitry are used in a mixed signal environment, with high and low voltage analog and switching signals, such as a motor control system. In addition, software techniques such as Random PWM method can be used by special features of the Texas Instruments (TI) TMS320x24xx DSP controllers to significantly reduce noise effects caused by EMI radiation.

This application report reviews designs of 3.3-V DSP versus 5-V DSP for low HP motor control applications.The application report first describes a scenario of a 3.3-V-only motor controller indicating that for most applications, no significant issue of interfacing between 3.3 V and 5 V exists. Cost-effective 3.3-V − 5-V interfacing techniques are then discussed for the situations where such interfacing is needed. On-chip 3.3-V ADC versus 5-V ADC is also discussed. Sensitivity and noise effects in 3.3-V and 5-V ADC conversions are addressed. Guidelines for component layout and printed circuit board (PCB) design that can reduce system’s noise and EMI effects are summarized in the last section.

Thermo-Electric Cooler Control Using a TMS320F2812 DSP & DRV592

Power Amplifier Application Note (literature number SPRA873).

This application report presents a thermoelectric cooler system consisting of a Texas Instruments TMS320F2812 digital signal processor (DSP) and DRV592 power amplifier. The DSP implements a digital proportional-integral-derivative feedback controller using an integrated

Read This First

Page 6

12-bit analog-to-digital converter to read the thermistor, and direct output of pulse-width-modulated waveforms to the H-bridge DRV592 power amplifier. The system presented provides up to 6.1 watts of heating or cooling to the laser mount, although the DRV592 amplifier is actually capable of delivering up to 15 watts when configured appropriately. The closed-loop TEC system is seen to achieve ±0.0006°C temperature accuracy, depending on the needed operating temperature range, with a step response settling time of 14 to 16 seconds. A complete description of the experimental system, along with software and software operating instructions, are provided.

Running an Application from Internal Flash Memory on the

TMS320F281x DSP Application Report (literature number

SPRA958). Several special requirements exist for running an application from on-chip flash memory on the TMS320F28x DSP. These requirements generally do not manifest themselves during development in RAM since the Code Composer Studio™ debugger can mask problems associated with initialized sections and how they are linked to memory. This application report covers the requirements needed to properly configure application software for execution from on-chip flash memory. Requirements for both DSP/BIOS™ and nonDSP/BIOS projects are presented. Some performance considerations and techniques are also discussed. Example code projects are included that run from on-chip flash on the eZdsp™ F2812 development board (or alternately any F2812, F2811, or F2810 DSP board). Code examples that run from internal RAM are also provided for completeness. These code examples provide a starting point for code development, if desired.

Trademarks

Code Composer Studio and C28x are trademarks of Texas Instruments.

Page 7



1 Overview 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Introduces the multichannel buffered serial port (McBSP).

1.1 Introduction to the McBSP 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1.1 Key Features of the McBSP 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1.2 Block Diagram of the McBSP Module With FIFO 1-4. . . . . . . . . . . . . . . . . . . . . . . . .

1.1.3 McBSP Signals 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Register Summary 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 McBSP Operation 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.1 Data Transfer Process of a McBSP 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.2 Companding (Compressing and Expanding) Data 1-11. . . . . . . . . . . . . . . . . . . . . .

1.3.3 Clocking and Framing Data 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.4 Frame Phases 1-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.5 McBSP Reception 1-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.6 McBSP Transmission 1-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.7 Interrupts and FIFO Events Generated by a McBSP 1-24. . . . . . . . . . . . . . . . . . . .

1.4 Sample Rate Generator of the McBSP 1-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.1 Clock Generation in the Sample Rate Generator 1-28. . . . . . . . . . . . . . . . . . . . . . . .

1.4.2 Frame Sync Generation in the Sample Rate Generator 1-31. . . . . . . . . . . . . . . . . .

1.4.3 Synchronizing Sample Rate Generator Outputs to an External Clock 1-32. . . . . .

1.4.4 Reset and Initialization Procedure for the Sample Rate Generator 1-34. . . . . . . .

1.4.5 Sample Rate Generator Clocking Examples 1-35. . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 McBSP Exception/Error Conditions 1-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5.1 Overrun in the Receiver 1-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5.2 Unexpected Receive Frame-Sync Pulse 1-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5.3 Overwrite in the Transmitter 1-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5.4 Underflow in the Transmitter 1-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5.5 Unexpected Transmit Frame-Sync Pulse 1-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Multichannel Selection Modes 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the process for using multichannel selection.

2.1 Channels, Blocks, and Partitions 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1 Multichannel Selection 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.2 Configuring a Frame for Multichannel Selection 2-2. . . . . . . . . . . . . . . . . . . . . . . . .

2.1.3 Using Two Partitions 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.4 Using Eight Partitions 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vii

Page 8

Contents

2.1.5 Receive Multichannel Selection Mode 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.6 Transmit Multichannel Selection Modes 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.7 Disabling/Enabling Versus Masking/Unmasking 2-9. . . . . . . . . . . . . . . . . . . . . . . . .

2.1.8 Activity on McBSP Pins for Different Values of XMCM 2-10. . . . . . . . . . . . . . . . . . .

2.1.9 Using Interrupts Between Block Transfers 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 A-bis Mode 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 A-bis Mode Receive Operation 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 A-bis Mode Transmit Operation 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 SPI Protocol 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1 Clock Stop Mode 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2 Bits Used to Enable and Configure the Clock Stop Mode 2-16. . . . . . . . . . . . . . . .

2.3.3 Clock Stop Mode Timing Diagrams 2-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.4 Procedure for Configuring a McBSP for SPI Operation 2-19. . . . . . . . . . . . . . . . . .

2.3.5 McBSP as the SPI Master 2-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.6 McBSP as an SPI Slave 2-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Configure the Receiver and Transmitter 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes how to configure the receiver and transmitter.

3.1 Receiver Configuration 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.1 Programming the McBSP Registers for the Desired Receiver Operation 3-2. . . .

3.1.2 Resetting and Enabling the Receiver 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.3 Clock Stop Mode 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.4 Receive Multichannel Selection and A-bis Modes 3-6. . . . . . . . . . . . . . . . . . . . . . . .

3.1.5 Choose 1 or 2 Phases for the Receive Frame 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.6 Set the Receive Companding Mode 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.7 Set the Receive Data Delay 3-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.8 Set the Receive Sign-Extension and Justification Mode 3-12. . . . . . . . . . . . . . . . . .

3.1.9 Set the Receive Interrupt Mode 3-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.10 Set the Receive Frame-Sync Mode 3-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.11 Set the Receive Frame-Sync Polarity 3-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Transmitter Configuration 3-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1 Programming the McBSP Registers for the Desired Transmitter Operation 3-26.

3.2.2 Resetting and Enabling the Transmitter 3-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.3 Set the Transmitter Pins to Operate as McBSP Pins 3-28. . . . . . . . . . . . . . . . . . . .

3.2.4 Enable/Disable the Digital Loopback Mode 3-28. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.5 Enable/Disable the Clock Stop Mode 3-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.6 Enable/Disable Transmit Multichannel Selection 3-30. . . . . . . . . . . . . . . . . . . . . . . .

3.2.7 Enable/Disable the A-bis Mode 3-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.8 Choose 1 or 2 Phases for the Transmit Frame 3-31. . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.9 Set the Transmit Word Length(s) 3-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.10 Set the Transmit Frame Length 3-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.11 Set the Transmit Companding Mode 3-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.12 Set the Transmit Data Delay 3-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.13 Set the Transmit DXENA Mode 3-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii

Page 9

Contents

3.2.14 Set the Transmit Interrupt Mode 3-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.15 Set the Transmit Frame-Sync Mode 3-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.16 Set the Transmit Frame-Sync Polarity 3-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.17 Set the SRG Frame-Sync Period and Pulse Width 3-42. . . . . . . . . . . . . . . . . . . . . .

3.2.18 Set the Transmit Clock Mode 3-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.19 Set the SRG Clock Divide-Down Value 3-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.20 Set the SRG Clock Mode (Choose an Input Clock) 3-47. . . . . . . . . . . . . . . . . . . . . .

4 Emulation and Reset Considerations 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes resetting and initializing the McBSP.

4.1 McBSP Emulation Mode 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.1 Resetting and Initializing a McBSP 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Data Packing Examples 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.1 Data Packing Using Frame Length and Word Length 4-8. . . . . . . . . . . . . . . . . . . . .

4.2.2 Data Packing Using Word Length and the Frame-Sync Ignore Function 4-9. . . .

4.3 GPIO Function 4-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 McBSP FIFO and Interrupts 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the FIFO interface logic.

5.1 McBSP FIFO Overview 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 McBSP Functionality and Limitation Under FIFO Mode 5-3. . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 McBSP FIFO Operation 5-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 McBSP Receive Interrupt Generation 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5 McBSP Transmit Interrupt Generation 5-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5.1 FIFO Data Register Access Constraints 5-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5.2 FIFO Error Flags 5-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5.3 McBSP IDLE Mode 5-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5.4 McBSP Reset Conditions 5-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6 McBSP FIFO Register Descriptions 5-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 McBSP Registers 6-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the McBSP registers and bit descriptions.

6.1 Data Receive and Transmit Registers 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.1 Data Receive Registers (DRR2 and DRR1) 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.2 How Data Travels From the Data Receive (DR) Pin to the DRRs 6-2. . . . . . . . . . .

6.1.3 Data Transmit Registers (DXR2 and DXR1) 6-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.4 How Data Travels From the DXRs to the Data Transmit (DX) Pin 6-3. . . . . . . . . .

6.2 Serial Port Control Registers (SPCR1 and SPCR2) 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 Receive Control Registers (RCR1 and RCR2) 6-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4 Transmit Control Registers (XCR1 and XCR2) 6-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5 Sample Rate Generator Registers (SRGR1 and SRGR2) 6-14. . . . . . . . . . . . . . . . . . . . . . .

6.6 Multichannel Control Registers (MCR1 and MCR2) 6-17. . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.7 Pin Control Register (PCR) 6-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.8 Receive Channel Enable Registers (RCERA − RCERH) 6-24. . . . . . . . . . . . . . . . . . . . . . . .

Contents

Page 10

Contents

6.8.1 RCERs Used in the Receive Multichannel Selection Mode 6-26. . . . . . . . . . . . . . .

6.8.2 RCERs Used in the A-bis Mode 6-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.9 Transmit Channel Enable Registers (XERA − XCERH) 6-29. . . . . . . . . . . . . . . . . . . . . . . . .

6.9.1 XCERs Used in a Transmit Multichannel Selection Mode 6-30. . . . . . . . . . . . . . . .

6.9.2 XCERs Used in the A-bis Mode 6-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.10 Register Bit Summary 6-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 Revision History A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.1 Changes Made in This Revision A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 11

Figures



1−1. Block Diagram With FIFO Interface 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−2. McBSP Data Transfer Paths 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−3. Companding Processes 1-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−4. m-Law Transmit Data Companding Format 1-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−5. A-Law Transmit Data Companding Format 1-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−6. Two Methods by Which the McBSP Can Compand Internal Data 1-13. . . . . . . . . . . . . . . . . . .

1−7. Clock Signal Control Waveform 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−8. 8-Bit Word Size Defined Waveform 1-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−9. One-word Frame Transfer 1-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−10. McBSP Operating at Maximum Packet Frequency 1-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−11. Single-Phase Frame for a McBSP Data Transfer 1-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−12. Dual-Phase Frame for a McBSP Data Transfer 1-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−13. Implementing the AC97 Standard With a Dual-Phase Frame 1-20. . . . . . . . . . . . . . . . . . . . . . .

1−14. Timing of an AC97-Standard Data T ransfer Near Frame Synchronization 1-20. . . . . . . . . . . .

1−15. McBSP Reception Physical Data Path 1-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−16. McBSP Reception Signal Activity 1-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−17. McBSP Transmission Physical Data Path 1-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−18. McBSP Transmission Signal Activity 1-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−19. Sample Rate Generator Clock Selection 1-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−20. Possible Inputs to the Sample Rate Generator and the Polarity Bits 1-29. . . . . . . . . . . . . . . . .

1−21. CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 1 1-33. . . .

1−22. CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 3 1-34. . .

1−23. ST-BUS and MVIP Clocking Example 1-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−24. Single-Rate Clock Example 1-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−25. Double-Rate Clock Example 1-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−26. Overrun in the McBSP Receiver 1-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−27. Overrun Prevented in the McBSP Receiver 1-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−28. Possible Responses to Receive Frame-Sync Pulses 1-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−29. An Unexpected Frame-Sync Pulse During a McBSP Reception 1-43. . . . . . . . . . . . . . . . . . . .

1−30. Proper Positioning of Frame-Sync Pulses 1-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−31. Data in the McBSP Transmitter Overwritten and Thus Not Transmitted 1-45. . . . . . . . . . . . . .

1−32. Underflow During McBSP Transmission 1-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−33. Underflow Prevented in the McBSP Transmitter 1-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−34. Possible Responses to Transmit Frame-Sync Pulses 1-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−35. An Unexpected Frame-Sync Pulse During a McBSP Transmission 1-48. . . . . . . . . . . . . . . . .

1−36. Proper Positioning of Frame-Sync Pulses 1-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

Page 12

Figures

2−1. Alternating Between the Channels of Partition A and the Channels of Partition B 2-4. . . . . .

2−2. Reassigning Channel Blocks Throughout a McBSP Data Transfer 2-5. . . . . . . . . . . . . . . . . . .

2−3. McBSP Data Transfer in the 8-Partition Mode 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−4. Activity on McBSP Pins for the Possible Values of XMCM 2-11. . . . . . . . . . . . . . . . . . . . . . . . .

2−5. A-bis Mode Receive Operation 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−6. A-bis Mode Transmit Operation 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−7. Typical SPI Interface 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−8. SPI Transfer With CLKSTP = 10b (no clock delay), CLKXP = 0, CLKRP = 0 2-18. . . . . . . . .

2−9. SPI Transfer With CLKSTP = 11b (clock delay), CLKXP = 0, CLKRP = 1 2-18. . . . . . . . . . . .

2−10. SPI Transfer With CLKSTP = 10b (no clock delay), CLKXP = 1, CLKRP = 0 2-18. . . . . . . . .

2−11. SPI Transfer With CLKSTP = 11b (clock delay), CLKXP = 1, CLKRP = 1 2-19. . . . . . . . . . . .

2−12. SPI Interface With McBSP as Master 2-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−13. 2-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−1. Unexpected Frame-Sync Pulse With (R/X)FIG = 0 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−2. Unexpected Frame-Sync Pulse With (R/X)FIG = 1 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−3. Companding Processes for Reception and for Transmission 3-10. . . . . . . . . . . . . . . . . . . . . . .

3−4. Range of Programmable Data Delay 3-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−5. 2-Bit Data Delay Used to Skip a Framing Bit 3-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−6. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP

Receiver on a Falling Edge 3-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−7. Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods 3-19. . . . . . . . . . . .

3−8. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP

Receiver on a Falling Edge 3-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−9. Unexpected Frame-Sync Pulse With (R/X)FIG = 0 3-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−10. Unexpected Frame-Sync Pulse With (R/X)FIG = 1 3-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−11. Companding Processes for Reception and for Transmission 3-34. . . . . . . . . . . . . . . . . . . . . . .

3−12. m-Law Transmit Data Companding Format 3-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−13. A-Law Transmit Data Companding Format 3-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−14. Range of Programmable Data Delay 3-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−15. 2-Bit Data Delay Used to Skip a Framing Bit 3-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−16. DX Delay When A-bis Mode is Off 3-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−17. DX Delays When A-bis Mode is On 3-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−18. Data Clocked Externally Using a Rising Edge and Sampled by the

McBSP Receiver on a Falling Edge 3-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−19. Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods 3-43. . . . . . . . . . . .

3−20. Data Clocked Externally Using a Rising Edge and Sampled by the

McBSP Receiver on a Falling Edge 3-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−1. Four 8-Bit Data Words Transferred To/From the McBSP 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−2. One 32-Bit Data Word Transferred To/From the McBSP 4-9. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−3. 8-Bit Data Words Transferred at Maximum Packet Frequency 4-10. . . . . . . . . . . . . . . . . . . . . .

4−4. Configuring the Data Stream of 4−3 as a Continuous 32-Bit Word 4-10. . . . . . . . . . . . . . . . . .

5−1. Receive Interrupt Generation 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−2. Transmit Interrupt Generation 5-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−3. McBSP FIFO Transmit Register (MFFTX) 5-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−4. McBSP FIFO Receive Register (MFFRX) 5-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xii

Page 13

Figures

5−5. McBSP FIFO Control Register (MFFCT) 5-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−6. McBSP FIFO Interrupt Register (MFFINT) 5-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−7. McBSP FIFO Status Register (MFFST) 5-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−1. Data Receive Registers (DRR2 and DRR1) 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−2. Data Transmit Registers (DXR2 and DXR1) 6-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−3. Serial Port Control 2 Register (SPCR2) 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−4. SPCR1 Register 6-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−5. Receive Control 2 Register (RCR2) 6-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−6. RCR1 Register 6-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−7. Transmit Control 2 Register (XCR2) 6-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−8. XCR1 Register 6-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−9. Sample Rate Generator 2 Register (SRGR2) 6-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−10. Sample Rate Generator 1 Register (SRGR1) 6-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−11. Multichannel Control 2 Register (MCR2) 6-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−12. Multichannel Control 1 Register (MCR1) 6-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−13. Pin Control Register (PCR) 6-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−14. Receive Channel Enable Register (RCERA/B) 6-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−15. RCER(A−G)−Receive Channel Enable Registers − A, C, E, G 6-25. . . . . . . . . . . . . . . . . . . . .

6−16. RCER(B−H)−Receive Channel Enable Registers − B,D,F,H 6-25. . . . . . . . . . . . . . . . . . . . . . . .

6−17. Transmit Channel Enable Registers A. C. E. G (XCERA−XCERG) 6-29. . . . . . . . . . . . . . . . . .

6−18. Transmit Channel Enable Registers–B, D, F, H (XCERB−XCERH) 6-30. . . . . . . . . . . . . . . . . .

Contents

xiii

Page 14

Tables



1−1. 28x Implementation Changes 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−2. McBSP Signal Summary 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−3. McBSP Register Summary 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−4. McBSP Register Bits That Determine the Number of Phases, Words, and

1−5. Interrupts and FIFO Events Generated by a McBSP 1-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−6. Sample Rate Generator Clock Options 1-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−7. Effects of DLB and CLKSTP on Clock Modes 1-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−8. Choosing an Input Clock for the Sample Rate Generator With the

1−9. Polarity Options for the Input to the Sample Rate Generator 1-30. . . . . . . . . . . . . . . . . . . . . . .

2−1. Receive Channel Assignment and Control When Eight Receive Partitions Are Used 2-6. . . 2−2. Transmit Channel Assignment and Control When Eight Transmit Partitions Are Used 2-6. .

2−3. Selecting a Transmit Multichannel Selection Mode With the XMCM Bits 2-8. . . . . . . . . . . . . .

2−4. Bits Used to Enable and Configure the Clock Stop Mode 2-16. . . . . . . . . . . . . . . . . . . . . . . . . .

2−5. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme 2-17. . . . . . . . . . . . . . . . . . . . .

2−6. Bit Values Required to Configure the McBSP as an SPI Master 2-21. . . . . . . . . . . . . . . . . . . .

2−7. Bit Values Required to Configure the McBSP as an SPI Slave 2-23. . . . . . . . . . . . . . . . . . . . .

3−1. Reset State of Each McBSP Pin 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−2. Receive Signals Connected to Transmit Signals in Digital Loopback Mode 3-4. . . . . . . . . . . .

3−3. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme 3-5. . . . . . . . . . . . . . . . . . . . . .

3−4. How to Calculate the Length of the Receive Frame 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−5. Example: Use of RJUST Field With 12-Bit Data Value 0xABC 3-13. . . . . . . . . . . . . . . . . . . . . .

3−6. Example: Use of RJUST Field With 20-Bit Data Value 0xABCDE 3-13. . . . . . . . . . . . . . . . . . .

3−7. Select Sources to Provide the Receive Frame-Synchronization Signal and the 3−8. Select Sources to Provide the Receive Clock Signal and the Effect on the

3−9. Reset State of Each McBSP Pin 3-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−10. Receive Signals Connected to Transmit Signals in Digital Loopback Mode 3-28. . . . . . . . . . .

3−11. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme 3-30. . . . . . . . . . . . . . . . . . . . .

3−12. How to Calculate Frame Length 3-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−13. How FSXM and FSGM Select the Source of Transmit Frame-Sync Pulses 3-39. . . . . . . . . . .

3−14. How the CLKXM Bit Selects the Transmit Clock and the Corresponding

4−1. McBSP Emulation Modes Selectable With the FREE and SOFT Bits of SPCR2 4-3. . . . . . .

4−2. Reset State of Each McBSP Pin 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bits Per Frame 1-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SCLKME and CLKSM Bits 1-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Effect on the FSR Pin 3-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CLKR Pin 3-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Status of the CLKX Pin 3-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xiv

Page 15

Tables

5−1. McBSP FIFO Registers 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−2. McBSP Mode Selection 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−3. Receive Interrupt Sources and Signals in NonFIFO Mode and FIFO Mode 5-7. . . . . . . . . . . .

5−4. Transmit Interrupt Sources and Signals in NonFIFO Mode and FIFO Mode 5-9. . . . . . . . . . .

5−5. Receive FIFO Read Order 5-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−6. Transmit FIFO Write Order 5-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−7. McBSP Error Flags 5-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−1. Use of the Receive Channel Enable Registers in theReceive Multichannel

Selection Mode 6-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−2. Use of Receive Channel Enable Registers A and B in the A-bis Mode 6-28. . . . . . . . . . . . . . .

6−3. Use of the Transmit Channel Enable Registers in a Transmit Multichannel

Selection Mode 6-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−4. Use of Transmit Channel Enable Registers A and B in the A-bis Mode 6-33. . . . . . . . . . . . . .

6−5. Register Bit Summary (Base Address 0x00 7800) 6-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−6. FIFO Register Bit Descriptions (Base address 0x00 7800) 6-37. . . . . . . . . . . . . . . . . . . . . . . . .

Contents

Page 16

xvi

Page 17

Chapter 1



The multichannel buffered serial port (McBSP) provides a direct serial interface between a digital signal processor (DSP) and other devices in a system.

This reference guide is applicable for the McBSP found on the TMS320x281x family of processors. This includes all Flash-based, ROM-based, and RAM-based devices within the 281x family.

If you have used a McBSP in other TI DSPs, note that there are differences in this implementation, which are outlined in Table 1−1.

Topic Page

1.1 Introduction to the McBSP 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Register Summary 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 McBSP Operation 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Sample Rate Generator of the McBSP 1-25. . . . . . . . . . . . . . . . . . . . . . . . .

1.5 McBSP Exception/Error Conditions 1-38. . . . . . . . . . . . . . . . . . . . . . . . . . . .

OverviewSPRU061B

1-1

Page 18

Introduction to the McBSP

1.1 Introduction to the McBSP

The McBSP peripheral provides an interface between a 28x device and McBSP-compatible devices such as the VBAP, AIC, Combo Codecs. The external components attached to the McBSP can synchronously transmit/receive 8/16/32-bit serial data.

1.1.1 Key Features of the McBSP

The McBSP provides:

- Full-duplex communication

- Double-buffered transmission and triple-buffered reception, which allow

a continuous data stream

- Independent clocking and framing for reception and for transmission

- 128 channels for transmission and for reception

- Multichannel selection modes that enable you to allow or block

transfers in each of the channels

- DMA replaced with two 16-level, 32-bit FIFOs

- Support for A-bis mode

- Direct interface to industry-standard codecs, analog interface chips

(AICs), and other serially connected A/D and D/A devices

- Support for external generation of clock signals and

frame-synchronization (frame-sync) signals

- A programmable sample rate generator for internal generation and

control of frame-sync signals

- Programmable internal clock and frame generation

- Programmable polarity for frame-synchronization and data clocks

- Support for SPI devices

1-2

Overview

SPRU061B

Page 19

Introduction to the McBSP

Support fractional T1/E1. Direct interface to:

J T1/E1 framers J MVIP switching compatible and ST -BUS compliant devices including:

H MVIP framers H H.100 framers H SCSA framers

J IOM-2 compliant devices J AC97-compliant devices (The necessary multiphase frame capability

is provided.)

J IIS-compliant devices J SPI devices

- A wide selection of data sizes: 8, 12, 16, 20, 24, and 32 bits

Note: A value of the chosen data size is referred to as a serial word or word throughout the McBSP documentation. Elsewhere, word is used to describe a 16-bit value.

- The option of transmitting/receiving 8-bit data with the LSB or MSB first

The McBSP module in C28x devices is adapted from TI’s family of McBSPs. Although it supports most of the McBSP applications, Table 1−1 lists some limitations to this implementation.

Table 1−1. 28x Implementation Changes

Features of TI’s McBSP family

DMA supports for data transfer DMA replaced by two 32 X 16 level

GPIO function on McBSP pins Supported through the GPIO module

Power down-mode using IDLE-EN bit in PCR register

CLKS as external shift clock

Implementation in 28x McBSP Module

FIFOs

available in 28x family. The clock for the McBSP logic is

controlled using bit 12 of the peripheral clock control register (PCLKCR).

CLKS feature is not supported. CLKR/CLKX pin provide this feature.

OverviewSPRU061B

1-3

Page 20

Introduction to the McBSP

1.1.2 Block Diagram of the McBSP Module With FIFO

The McBSP consists of a data-flow path and a control path connected to external devices by seven pins as shown in Figure 1−1.

Figure 1−1. Block Diagram With FIFO Interface

16−bit read in FIFO mode

Peripheral Bus

16−bit write in FIFO mode

15 1500

DRR2_0 DRR1_0

..... .....

DRR2_15 DRR1_15

DRR1

DRR2

16−bit

FIFO mode select

MFFENA

16−bit

DXR2

DXR2_0

.....

DXR2_15

Read/write bus 16−bit

DXR1

DXR1_0

.....

DXR1_15

McBSP module

Receive channel

16−bit

001515

DRR2 − receive register DRR1 − receive register

Transmit channel DXR2 − transmit register DXR1 − transmit register

Multichannel selection

registers

MCR1/2

RCERs XCERs

Clock frame sync and

control registers

SPRC1/2

RCR1/2 XCR1/2

SRGR1/2

PCR

GPIO MUX

CLKX CLKR

FSX FSR

R/W bus 16−bit

MRINT MXINT

Legend:

16−bit Active only in Non_FIFO mode

1-4

Overview

XMIT/receive FIFO

control registers

Interrupt

select

RXFFINT

logic

REVT XEVT

RINT

REVTA

XINT

XEVTA

Interrupts & events REVT XEVT

RINT REVTA XINT XEVTA

SPRU061B

Page 21

Data is communicated to devices interfaced with the McBSP via the data transmit (DX) pin for transmission and the data receive (DR) pin for reception. Control information in the form of clocking and frame synchronization is communicated via the following pins: CLKX (transmit clock), CLKR (receive clock), FSX (transmit frame sync), and FSR (receive frame sync).

DRR2, RBR2, RSR2, DXR2, and XSR2 are not used (written, read, or shifted) if the serial word length is 8 bits, 12 bits, or 16 bits. For larger word lengths, these registers are needed to hold the most significant bits.

The remaining registers are registers for controlling McBSP operation. Details about these registers are available in section 1.2 (page 1-7).

1.1.3 McBSP Signals

Table 1−2 describes the McBSP interface signals. Information on using these signals for general-purpose input/output is in section 4.3 on page 4-11.

Table 1−2. McBSP Signal Summary

Introduction to the McBSP

Signal Name

External Signals External Signals Names

CLKX I/O/Z Input Transmit clock

CLKR I/O/Z

DR I Input Received serial data DX O/Z High-z Transmitted serial data FSR I/O/Z Input Receive frame synchronization FSX I/O/Z Input Transmit frame synchronization

CPU-Interrupt Signals

MRINT Receive interrupt to CPU or FIFO MXINT Transmit interrupt to CPU or FIFO

FIFO Events

REVT Receive synchronization event to FIFO XEVT

†

I = input, O = output, Z = high impedance

Notes: 1) CLKS signal is not supported in this implementation.

Type

Reset

†

Status

Input Receive clock

Description

Transmit synchronization event to FIFO

OverviewSPRU061B

1-5

Page 22

Introduction to the McBSP

Table 1−2. McBSP Signal Summary (Continued)

Signal Name

Type

Reset

†

Status

Description

REVTA Receive synchronization in A-bis mode in the FIFO XEVTA Transmit synchronization in A-bis mode in the FIFO

†

I = input, O = output, Z = high impedance

Notes: 1) CLKS signal is not supported in this implementation.

1-6

Overview

SPRU061B

Page 23

1.2 Register Summary

For each McBSP, the DSP contains the following registers. For the address of each register, see the data sheet for your device.

Table 1−3. McBSP Register Summary

Address

Offset 0x000

xxh

− − − McBSP Receive Buffer Register

16-Bit

Access

Type

R/W

Reset

ValueHex

McBSP Communications Interface Register Description

Data Registers, Receive, Transmit

−

04 05

− − McBSP Receive Shift Register

− − McBSP Transmit Shift Register

DRR2 R 0x0000 McBSP Data Receive Register2

DRR1

DXR2

DXR1 W 0x0000

SPCR2 R/W 0x0000 SPCR1 R/W 0x0000

06 RCR2

R 0x0000

W 0x0000

R/W 0x0000

- Read First if the word size is greater than 16 bit else ignore

DRR2

McBSP Data Receive Register1

- Read second if the word size is greater than 16 bit else read

DRR1 only

McBSP Data Transmit Register2

- Write First if the word size is greater than 16 bit else ignore

DXR2

McBSP Data Transmit Register1

- Write second if the word size is greater than 16 bit else Write

to DXR1 only

McBSP Control Registers

McBSP Serial Port Control Register2 McBSP Serial Port Control Register1

McBSP Receive Control Register2 07 RCR1 08 XCR2 09 XCR1

†

MFFST will read 0x000A if FSX/FSR pins are left unconnected; else, it will assume pin status at reset.

R/W 0x0000 R/W 0x0000 R/W 0x0000

McBSP Receive Control Register1

McBSP Transmit Control Register2

McBSP Transmit Control Register1

Multichannel Buffered Serial Port (McBSP)SPRU061B

1-7

Page 24

Table 1−3. McBSP Register Summary (Continued)

Address

Offset 0x000

xxh

16-Bit

Access

Type

R/W

Reset

ValueHex

Multichannel Control Registers (Continued)

McBSP Communications Interface Register Description

0A SRGR2 0B SRGR1 0C MCR2 0D MCR1 0E RCERA 0F RCERB

10 11 12

XCERA XCERB

PCR1 13 RCERC 14 RCERD 15 XCERC 16 XCERD 17 RCERE 18 RCERF

R/W 0x2000 R/W 0x0001 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000

McBSP Sample Rate Generator Register2 McBSP Sample Rate Generator Register1 McBSP Multi−Channel Register2 McBSP Multi−Channel Register1 McBSP Receive Channel Enable Register Partition A McBSP Receive Channel Enable Register Partition B McBSP Transmit Channel Enable Register Partition A McBSP Transmit Channel Enable Register Partition A McBSP Pin Control Register McBSP Receive Channel Enable Register Partition C McBSP Receive Channel Enable Register Partition D McBSP Transmit Channel Enable Register Partition C McBSP Transmit Channel Enable Register Partition D McBSP Receive Channel Enable Register Partition E

McBSP Receive Channel Enable Register Partition F 19 XCERE 1A XCERF 1B RCERG 1C RCERH 1D XCERG 1E XCERH

†

MFFST will read 0x000A if FSX/FSR pins are left unconnected; else, it will assume pin status at reset.

1-8

Multichannel Buffered Serial Port (McBSP)

R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000

McBSP Transmit Channel Enable Register Partition E

McBSP Transmit Channel Enable Register Partition F

McBSP Receive Channel Enable Register Partition G

McBSP Receive Channel Enable Register Partition H

McBSP Transmit Channel Enable Register Partition G

McBSP Transmit Channel Enable Register Partition H

SPRU061B

Page 25

Table 1−3. McBSP Register Summary (Continued)

Address

Offset 0x000

xxh

16-Bit

Access

Type

R/W

Reset

ValueHex

FIFO Mode Data Registers Applicable Only FIFO Mode

McBSP Communications Interface Register Description

DRR2 R 0x0000 McBSP Data Receive Register2 −Top of receive FIFO

- Read First FIFO pointers will not advance

DRR1

DXR2

DXR1 W

R 0x0000

W 0x0000

0x0000 McBSP Data Transmit Register1−Top of transmit FIFO

McBSP Data Receive Register1−Top of receive FIFO

- Read second for FIFO pointers to advance

McBSP Data Transmit Register2−Top of transmit FIFO

- Write First FIFO pointers will not advance

- Write second for FIFO pointers to advance

FIFO Control Registers

20 MFFTX 21 MFFRX 22 MFFCT 23 MFFINT 24 MFFST

†

MFFST will read 0x000A if FSX/FSR pins are left unconnected; else, it will assume pin status at reset.

R/W 0x2000 R/W R/W R/W R/W

0x201F McBSP FIFO Receive register 0x0000 McBSP FIFO Control register 0x0000 McBSP FIFO Interrupt register

0x000x†McBSP FIFO Status register

McBSP FIFO Transmit register

The registers bits are summarized in Table 6−5.

SPRU061B

Multichannel Buffered Serial Port (McBSP)

1-9

Page 26

McBSP Operation

ÁÁÁ

1.3 McBSP Operation

This section contains the following topics:

Topic See ...

Data transfer process of a McBSP Section 1.3.1 Companding (compressing and expanding) data Section 1.3.2, page 1-11 Clocking and framing data Section 1.3.3, page 1-14 Frame phases Section 1.3.4, page 1-18 McBSP Reception Section 1.3.5, page 1-21 McBSP Transmission Section 1.3.6, page 1-22 Interrupts and FIFO events generated by a McBSP

1.3.1 Data Transfer Process of a McBSP

Figure 1−2 shows a diagram of the McBSP data transfer paths. McBSP receive operation is triple buffered, and transmit operation is double buffered. The use of registers varies depending on whether the defined length of each serial word fits in 16 bits.

Figure 1−2. McBSP Data Transfer Paths

Compand

RSR[1,2] XSR[1,2]

1.3.1.1 Data Transfer Process for Word Length of 8, 12, or 16 Bits

If the word length is 16 bits or smaller, only one 16-bit register is needed at each stage of the data transfer paths. The registers DRR2, RBR2, RSR2, DXR2, and XSR2 are not used (written, read, or shifted).

Receive data arrives on the DR pin and is shifted into receive shift register 1 (RSR1). Once a full word is received, the content of RSR1 is copied to receive buffer register 1 (RBR1), only if RBR1 is not full with previous data. RBR1 is then copied to data receive register 1 (DRR1), unless the previous content of DRR1 has not been read by the CPU. If the companding feature of the McBSP is implemented, the required word length is 8 bits and receive data is expanded into the appropriate format before being passed from RBR1 to DRR1. For more details about reception, see section 1.3.5 on page 1-21.

RBR[1,2] DRR[1,2]

Expand

Compress

DRR[1,2]RBR[1,2] DXR[1,2]

Section 1.3.7, page 1-24

To CPU/FIFO From CPU/FIFO

1-10

Multichannel Buffered Serial Port (McBSP)

SPRU061B

Page 27

Transmit data is written by the CPU to data transmit register 1 (DXR1). If there is no previous data in transmit shift register (XSR1), the value in DXR1 is copied to XSR1; otherwise, DXR1 is copied to XSR1 when the last bit of the previous data is shifted out on the DX pin. If selected, the companding module compresses 16-bit data into the appropriate 8-bit format before passing it to XSR1. After transmit frame synchronization, the transmitter begins shifting bits from XSR1 to the DX pin. For more details about transmission, see section

1.3.6 on page 1-22.

1.3.1.2 Data Transfer Process for Word Length of 20, 24, or 32 Bits

If the word length is larger than 16 bits, two 16-bit registers are needed at each stage of the data transfer paths. The registers DRR2, RBR2, RSR2, DXR2, and XSR2 are needed to hold the most significant bits.

Receive data arrives on the DR pin and is shifted into RSR2 first and then into RSR1. Once the full word is received, the contents of RSR2 and RSR1 are copied to RBR2 and RBR1, respectively, only if RBR1 is not full. Then the contents of RBR2 and RBR1 are copied to DRR2 and DRR1, respectively, unless the previous content of DRR1 has not been read by the CPU. The CPU must read data from DRR2 first and then from DRR1. When DRR1 is read, the next RBR-to-DRR copy occurs. For more details about reception, see section

1.3.5 on page 1-21.

McBSP Operation

For transmission, the CPU must write data to DXR2 first and then to DXR1. When new data arrives in DXR1, if there is no previous data in XSR1, the contents of DXR2 and DXR1 are copied to XSR2 and XSR1, respectively; otherwise, the contents of the DXRs are copied to the XSRs when the last bit of the previous data is shifted out on the DX pin. After transmit frame synchronization, the transmitter begins shifting bits from the XSRs to the DX pin. For more details about transmission, see section 1.3.6 on page 1-22.

1.3.2 Companding (Compressing and Expanding) Data

Companding (COMpressing and exPANDing) hardware allows compression and expansion of data in either µ-law or A-law format. The companding standard employed in the United States and Japan is µ-law. The European companding standard is referred to as A-law . The specifications for µ-law and A-law log PCM are part of the CCITT G.711 recommendation.

A-law and µ-law allow 13 bits and 14 bits of dynamic range, respectively. Any values outside this range are set to the most positive or most negative value. Thus, for companding to work best, the data transferred to and from the McBSP via the CPU must be at least 16 bits wide.

The µ-law and A-law formats both encode data into 8-bit code words. Companded data is always 8 bits wide; the appropriate word length bits

SPRU061B

Multichannel Buffered Serial Port (McBSP)

1-11

Page 28

McBSP Operation

(RWDLEN1, RWDLEN2, XWDLEN1, XWDLEN2) must therefore be set to 0, indicating an 8-bit wide serial data stream. If companding is enabled and either of the frame phases does not have an 8-bit word length, companding continues as if the word length is 8 bits.

Figure 1−3 illustrates the companding processes. When companding is chosen for the transmitter, compression occurs during the process of copying data from DXR1 to XSR1. The transmit data is encoded according to the specified companding law (A-law or µ-law). When companding is chosen for the receiver, expansion occurs during the process of copying data from RBR1 to DRR1. The receive data is decoded to 2s-complement format.

Figure 1−3. Companding Processes

RBR1RSR1

XSR1

Expand

Compress

1.3.2.1 Companding Formats

For reception, the 8-bit compressed data in RBR1 is expanded to left-justified 16-bit data in DRR1. The receive sign-extension and justification mode specified in RJUST is ignored when companding is used.

For transmission using µ-law compression, make sure the 14 data bits are left-justified in DXR1, with the remaining two low-order bits filled with 0s as shown in Figure 1−4.

Figure 1−4. µ-Law Transmit Data Companding Format

µ-law format in DXR1

For transmission using A-law compression, make sure the 13 data bits are left-justified in DXR1, with the remaining three low-order bits filled with 0s as shown in Figure 1−5.

DRR1

DXR1

To CPU

From CPU

1−015−2

00Value

Figure 1−5. A-Law Transmit Data Companding Format

A-law format in DXR1

1-12

Multichannel Buffered Serial Port (McBSP)

15−3 Value

2−0 000

SPRU061B

Page 29

1.3.2.2 Capability to Compand Internal Data

If the McBSP is otherwise unused (the serial port transmit and receive sections are reset), the companding hardware can compand internal data. This can be used to:

- Convert linear to the appropriate µ-law or A-law format.

- Convert µ-law or A-law to the linear format.

- Observe the quantization effects in companding by transmitting linear

data, and compressing and re-expanding this data. This is useful only if both XCOMPAND and RCOMP AND enable the same companding format.

Figure 1−6 shows two methods by which the McBSP can compand internal data. Data paths for these two methods are used to indicate:

- When both the transmit and receive sections of the serial port are reset,

DRR1 and DXR1 are connected internally through the companding logic. Values from DXR1 are compressed, as selected by XCOMPAND, and then expanded, as selected by RCOMP AND. Note that RRDY and XRDY bits are not set. However , data is available in DRR1 within four CPU clocks after being written to DXR1.

McBSP Operation

The advantage of this method is its speed. The disadvantage is that there is no synchronization available to the CPU to control the flow. Note that DRR1 and DXR1 are internally connected if the (X/R)COMP AND bits are set to 10b or 11b (compand using µ-law or A-law).

- The McBSP is enabled in digital loopback mode with companding

appropriately enabled by RCOMPAND and XCOMPAND. Receive and transmit interrupts (RINT when RINTM = 0 and XINT when XINTM = 0) or synchronization events (REVT and XEVT) allow synchronization of the CPU to these conversions. The time for this companding depends on the serial bit rate selected.

Figure 1−6. Two Methods by Which the McBSP Can Compand Internal Data

DRR1

DXR1

SPRU061B

(2) (DLB)

RBR1RSR1

XSR1

Expand

(1)

Compress

Multichannel Buffered Serial Port (McBSP)

To CPU

From CPU

1-13

Page 30

McBSP Operation

1.3.2.3 Reversing Bit Order: Option to Transfer LSB First

Normally, the McBSP transmit or receives all data with the most significant bit (MSB) first. However, certain 8-bit data protocols (that do not use companded data) require the least significant bit (LSB) to be transferred first. If you set XCOMPAND = 01b in XCR2, the bit ordering of 8-bit words is reversed (LSB first) before being sent from the serial port. If you set RCOMPAND = 01b in RCR2, the bit ordering of 8-bit words is reversed during reception. Similar to companding, this feature is enabled only if the appropriate word length bits are set to 0, indicating that 8-bit words are to be transferred serially. If either phase of the frame does not have an 8-bit word length, the McBSP assumes the word length is eight bits, and LSB-first ordering is done.

1.3.3 Clocking and Framing Data

This section explains basic concepts and terminology important for understanding how McBSP data transfers are timed and delimited.

1.3.3.1 Clocking

Data is shifted one bit at a time from the DR pin to the RSR(s) or from the XSR(s) to the DX pin. The time for each bit transfer is controlled by the rising or falling edge of a clock signal.

The receive clock signal (CLKR) controls bit transfers from the DR pin to the RSR(s). The transmit clock signal (CLKX) controls bit transfers from the XSR(s) to the DX pin. CLKR or CLKX can be derived from a pin at the boundary of the McBSP or derived from inside the McBSP. The polarities of CLKR and CLKX are programmable.

In Figure 1−7, the clock signal controls the timing of each bit transfer on the pin.

Figure 1−7. Clock Signal Control Waveform

Internal

CLK(R/X)

Internal

FS(R/X)

D(R/X)

Note:

The McBSP cannot operate at a frequency faster than 1/2 the CPU clock frequency. When driving CLKX or CLKR at the pin, choose an appropriate input clock frequency. When using the internal sample rate generator for CLKX and/or CLKR, choose an appropriate input clock frequency and divide down value (CLKDV).

B0B1B2B3B4B5B6B7A0A1

1-14

Multichannel Buffered Serial Port (McBSP)

SPRU061B

Page 31

1.3.3.2 Serial Words

Bits trav e l ing between a shift register (RSR or XSR) and a data pin (DR or D X) are transferred in a group called a serial word. You define how many bits are in a word.

Bits coming in on the DR pin are held in RSR until RSR holds a full serial word. Only then is the word passed to RBR (and ultimately to the DRR).

During transmission, XSR does not accept new data from DXR until a full serial word has been passed from XSR to the DX pin.

In Figure 1−8, an 8-bit word size was defined (see bits 7 through 0 of word B being transferred).

Figure 1−8. 8-Bit Word Size Defined Waveform

Internal

CLK(R/X)

Internal

FS(R/X)

D(R/X)

McBSP Operation

B0B1B2B3B4B5B6B7A0A1

1.3.3.3 Frames and Frame Synchronization

One or more words are transferred in a group called a frame. You define how many words are in a frame.

All of the words in a frame are sent in a continuous stream. However, there can be pauses between frame transfers. The McBSP uses frame-synchronization (frame-sync) signals to determine when each frame is received/transmitted. When a pulse occurs on a frame-sync signal, the McBSP begins receiving/transmitting a frame of data. When the next pulse occurs, the McBSP receives/transmits the next frame, and so on.

Pulses on the receive frame-sync signal (FSR) initiate frame transfers on DR. Pulses on the transmit frame-sync signal (FSX) initiate frame transfers on DX. FSR or FSX can be derived from a pin at the boundary of the McBSP or derived from inside the McBSP.

In Figure 1−9, a 1-word frame is transferred when a frame-sync pulse occurs.

SPRU061B

Multichannel Buffered Serial Port (McBSP)

1-15

Page 32

McBSP Operation

Figure 1−9. One-word Frame Transfer

Internal

CLK(R/X)

Internal

FS(R/X)

D(R/X)

In McBSP operation, the inactive-to-active transition of the frame-synchronization signal indicates the start of the next frame. For this reason, the frame-sync signal may be high for an arbitrary number of clock cycles. Only after the signal is recognized to have gone inactive, and then active again, does the next frame synchronization occur.

1.3.3.4 Detecting Frame-Sync Pulses, Even in the Reset State

The McBSP can send receive and transmit interrupts to the CPU to indicate specific events in the McBSP. To facilitate detection of frame synchronization, these interrupts can be sent in response to frame-sync pulses. Set the appropriate interrupt mode bits to 10b (for reception, RINTM = 10b; for transmission, XINTM = 10b).

B0B1B2B3B4B5B6B7A0A1

Unlike other serial port interrupt modes, this mode can operate while the associated portion of the serial port is in reset (such as activating RINT when the receiver is in reset). In this case, FSRM/FSXM and FSRP/FSXP still select the appropriate source and polarity of frame synchronization. Thus, even when the serial port is in the reset state, these signals are synchronized to the CPU clock and then sent to the CPU in the form of RINT and XINT at the point at which they feed the receiver and transmitter of the serial port. Consequently, a new frame-synchronization pulse can be detected, and after this occurs the CPU can take the serial port out of reset safely.

1.3.3.5 Ignoring Frame-Sync Pulses

The McBSP can be configured to ignore transmit and/or receive frame-synchronization pulses. To have the receiver or transmitter recognize frame-sync pulses, clear the appropriate frame-sync ignore bit (RFIG = 0 for the receiver, XFIG = 0 for the transmitter). To have the receiver or transmitter ignore frame-sync pulses until the desired frame length or number of words is reached, set the appropriate frame-sync ignore bit (RFIG = 1 for the receiver, XFIG = 1 for the transmitter). For more details on unexpected frame-sync pulses, see one of the following topics:

- Unexpected Receive Frame-Sync Pulse (page 1-40)

- Unexpected Transmit Frame-Sync Pulse (page 1-46)

1-16

Multichannel Buffered Serial Port (McBSP)

SPRU061B

Page 33

You can also use the frame-sync ignore function for data packing (for more details, see section 4.2.2 on page 4-9).

1.3.3.6 Frame Frequency

The frame frequency is determined by the period between frame-synchronization pulses and is defined as shown by Equation 1−1.

Equation 1−1. Frame Frequency of a McBSP

McBSP Operation

Frame Frequency +

Clock Frequency

Number of Clock Cycles Between Frame−Sync Pulses

The frame frequency may be increased by decreasing the time between frame-synchronization pulses (limited only by the number of bits per frame). As the frame transmit frequency increases, the inactivity period between the data packets for adjacent transfers decreases to zero.

1.3.3.7 Maximum Frame Frequency

The minimum number of clock cycles between frame synchronization pulses is equal to the number of bits transferred per frame. The maximum frame frequency is defined as shown by Equation 1−2.

Equation 1−2. Maximum Frame Frequency of a McBSP

Maximum Frame Frequency +

Figure 1−10 shows the McBSP operating at maximum packet frequency. At maximum packet frequency, the data bits in consecutive packets are transmitted contiguously with no inactivity between bits.

Number of Bits Per Frame

Figure 1−10. McBSP Operating at Maximum Packet Frequency

Clock Frequency

CLK(R/X)

FS(R/X)

D(R/X)

SPRU061B

C6C7B0B1B2B3B4B5B6B7A0A1A2

If there is a 1-bit data delay as shown in this figure, the frame-synchronization pulse overlaps the last bit transmitted in the previous frame. Effectively, this permits a continuous stream of data, making frame-synchronization pulses redundant. Theoretically, only an initial frame-synchronization pulse is required to initiate a multipacket transfer.

Multichannel Buffered Serial Port (McBSP)

1-17

Page 34

McBSP Operation

1.3.4 Frame Phases

The McBSP supports operation of the serial port in this fashion by ignoring the successive frame-sync pulses. Data is clocked in to the receiver, or clocked out of the transmitter, during every clock cycle.

Note:

For XDA TDLY = 0 (0-bit data delay), the first bit of data is transmitted asynchronously to the internal transmit clock signal (CLKX). For more details, see Set the Transmit Data Delay on page 3-36.

The McBSP allows you to configure each frame to contain one or two phases. The number of words per frame, and the number of bits per word, can be specified differently for each of the two phases of a frame, allowing greater flexibility in structuring data transfers. For example, a user might define a frame as consisting of one phase containing two words of 16 bits each, followed by a second phase consisting of 10 words of 8 bits each. This configuration permits the user to compose frames for custom applications, or in general, to maximize the efficiency of data transfers.

1.3.4.1 Number of Phases, Words, and Bits Per Frame

Table 1−4 shows which bit fields in the receive control registers (RCR1 and RCR2) and in the transmit control registers (XCR1 and XCR2) determine the number of phases per frame, the number of words per frame, and number of bits per word for each phase, for the receiver and transmitter. The maximum number of words per frame is 128 for a single-phase frame and 256 for a dual-phase frame. The number of bits per word can be 8, 12, 16, 20, 24, or 32 bits.

Table 1−4. McBSP Register Bits That Determine the Number of Phases, Words, and

Bits Per Frame

Words Per Frame

Operation Number of Phases

Reception 1 (RPHASE = 0) RFRLEN1 RWDLEN1 Reception 2 (RPHASE = 1) RFRLEN1 and RFRLEN2 RWDLEN1 for phase 1

Transmission 1 (XPHASE = 0) XFRLEN1 XWDLEN1 Transmission

2 (XPHASE = 1) XFRLEN1 and XFRLEN2 XWDLEN1 for phase 1

Set With ...

Bits Per Word Set With ...

RWDLEN2 for phase 2

XWDLEN2 for phase 2

1-18

Multichannel Buffered Serial Port (McBSP)

SPRU061B

Page 35

1.3.4.2 Single-Phase Frame Example

ÁÁÁ

Figure 1−1 1 shows an example of a single-phase data frame comprising one 8-bit word. Since the transfer is configured for one data bit delay , the data on the DX and DR pins are available one clock cycle after FS(R/X) goes active. The figure makes the following assumptions:

- (R/X)PHASE = 0: Single-phase frame

- (R/X)FRLEN1 = 0b: 1 word per frame

- (R/X)WDLEN1 = 000b: 8-bit word length

- (R/X)FRLEN2 and (R/X)WDLEN2 are ignored

- CLK(X/R)P = 0: Receive data clocked on falling edge; transmit data

clocked on rising edge

- FS(R/X)P = 0: Active-high frame-sync signals

- (R/X)DATDLY = 01b: 1-bit data delay

Figure 1−11.Single-Phase Frame for a McBSP Data Transfer

CLK(R/X)

McBSP Operation

FS(R/X)

D(R/X)

B0B1B2B3B4B5B6B7A0

1.3.4.3 Dual-Phase Frame Example

Figure 1−12 shows an example of a frame where the first phase consists of 2 words of 12 bits each followed by a second phase of three words of 8 bits each. Note that the entire bit stream in the frame is contiguous. There are no gaps either between words or between phases.

Figure 1−12. Dual-Phase Frame for a McBSP Data Transfer

Phase 1 word 1

CLK(R/X)

FS(R/X)

D(R/X)

Phase 1 word 2

1.3.4.4 Implementing the AC97 Standard With a Dual-Phase Frame

Figure 1−13 shows an example of the Audio Codec ‘97 (AC97) standard, which uses the dual-phase frame feature. Notice that words, not individual bits, are shown on the D(R/X) signal. The first phase (P1) consists of a single 16-bit word. The second phase (P2) consists of twelve 20-bit words. The phase configurations are listed after the figure.

Phase 2

word 1

Phase 2

word 2

C5C6C7

Phase 2

word 3

SPRU061B

Multichannel Buffered Serial Port (McBSP)

1-19

Page 36

McBSP Operation

Figure 1−13. Implementing the AC97 Standard With a Dual-Phase Frame

P1W1

FS(R/X)

1-bit data delay

16 bits

20 bits

D(R/X)

PxWy =Phase x Word y

- (R/X)PHASE = 1: Dual-phase frame

- (R/X)FRLEN1 = 0000000b: 1 word in phase 1

- (R/X)WDLEN1 = 010b: 16 bits per word in phase 1

- (R/X)FRLEN2 = 0001011b: 12 words in phase 2

- (R/X)WDLEN2 = 011b: 20 bits per word in phase 2

- CLKRP/CLKXP= 0: Receive data sampled on falling edge of internal

CLKR / transmit data clocked on rising edge of internal CLKX

P2W12P2W11P2W10P2W9P2W8P2W7P2W6P2W5P2W4P2W3P2W2P2W1

- FSRP/FSXP = 0: Active-high frame-sync signal

- (R/X)DATDLY = 01b: Data delay of 1 clock cycle (1-bit data delay)

Figure 1−14 shows the timing of an AC97-standard data transfer near frame synchronization. In this figure, individual bits are shown on D(R/X). Specifically, the figure shows the last two bits of phase 2 of one frame and the first four bits of phase 1 of the next frame. Regardless of the data delay , data transfers can occur without gaps. The first bit of the second frame (P1W1B15) immediately follows the last bit of the first frame (P2W12B0). Because a 1-bit data delay has been chosen, the transition on the frame-sync signal can occur when P2W12B0 is transferred.

Figure 1−14. Timing of an AC97-Standard Data Transfer Near Frame Synchronization

CLKR

FSR

1-bit data delay

P2W12B1

P2W12B0

P1W1B15

PxWyBz = Phase x Word y Bit z

P1W1B14

P1W1B13

P1W1B12

1-20

Multichannel Buffered Serial Port (McBSP)

SPRU061B

Page 37

1.3.5 McBSP Reception

This section explains the fundamental process of reception in the McBSP. For details about how to program the McBSP receiver , see Receiver Configuration on page 3-2.

Figure 1−15 and Figure 1−16 show how reception occurs in the McBSP. Figure 1−15 shows the physical path for the data. Figure 1−16 is a timing diagram showing signal activity for one possible reception scenario. A description of the process follows the figures.

Figure 1−15. McBSP Reception Physical Data Path

McBSP Operation

RSR[1,2]

RSR[1,2]: Receive shift registers 1 and 2 RBR[1,2]: Receive buffer registers 1 and 2

RBR[1,2] DRR[1,2]DRR[1,2]RBR[1,2]

Expand

Justify and bit fill

Figure 1−16. McBSP Reception Signal Activity

CLKR

FSR

RRDY

CLKR: Internal receive clock FSR: Internal receive frame-sync signal

Rx Ready

DR: Data on DR pin RRDY: Status of receiver ready bit (high is 1)

The following process describes how data travels from the DR pin to the CPU:

1) The McBSP waits for a receive frame-sync pulse on internal FSR.

2) When the pulse arrives, the McBSP inserts the appropriate data delay that is selected with the RDATDLY bits of RCR2.

To CPU

DRR[1,2]: Data receive registers 1 and 2

C5C6C7B0B1B2B3B4B5B6B7A0A1

Read from DRR1(b)RBR1 to DRR1 copy(B)Read from DRR1(A)RBR1 to DRR1 copy(A)

SPRU061B

In the preceding timing diagram (Figure 1−16), a 1-bit data delay is selected.

3) The McBSP accepts data bits on the DR pin and shifts them into the receive shift register(s).

If the word length is 16 bits or smaller, only RSR1 is used. If the word length is larger than 16 bits, RSR2 and RSR1 are used, and RSR2 contains the

Multichannel Buffered Serial Port (McBSP)

1-21

Page 38

McBSP Operation

most significant bits. For details on choosing a word length, see Set the Receive Word Length(s).

4) When a full word is received, the McBSP copies the contents of the receive shift register(s) to the receive buffer register(s), provided that RBR1 is not full with previous data.

If the word length is 16 bits or smaller, only RBR1 is used. If the word length is larger than 16 bits, RBR2 and RBR1 are used, and RBR2 contains the most significant bits.

5) The McBSP copies the contents of the receive buffer register(s) into the data receive register(s), provided that DRR1 is not full with previous data. When DRR1 receives new data, the receiver ready bit (RRDY) is set in SPCR1. This indicates that receive data is ready to be read by the CPU.

If the word length is 16 bits or smaller, only DRR1 is used. If the word length is larger than 16 bits, DRR2 and DRR1 are used, and DRR2 contains the most significant bits.

If companding is used during the copy (RCOMPAND = 10b or 11b in RCR2), the 8-bit compressed data in RBR1 is expanded to a left-justified 16-bit value in DRR1. If companding is disabled, the data copied from RBR[1,2] to DRR[1,2] is justified and bit filled according to the RJUST bits.

6) The CPU reads the data from the data receive register(s). When DRR1 is read, RRDY is cleared and the next RBR-to-DRR copy is initiated.

Note:

If both DRRs are needed (word length larger than 16 bits), the CPU must read from DRR2 first and then from DRR1. As soon as DRR1 is read, the next RBR-to-DRR copy is initiated. If DRR2 is not read first, the data in DRR2 is lost.

When activity is not properly timed, errors can occur. See the following topics for more details:

- Overrun in the Receiver (page 1-39)

- Unexpected Receive Frame-Sync Pulse (page 1-40)

1.3.6 McBSP Transmission

This section explains the fundamental process of transmission in the McBSP. For details about how to program the McBSP transmitter, see Transmitter Configuration on page 3-26.

1-22

Multichannel Buffered Serial Port (McBSP)

SPRU061B

Page 39

Figure 1−17 and Figure 1−18 show how transmission occurs in the McBSP.

ÁÁÁ

Figure 1−17 shows the physical path for the data. Figure 1−18 is a timing diagram showing signal activity for one possible transmission scenario. A description of the process follows the figures.

Figure 1−17. McBSP Transmission Physical Data Path

McBSP Operation

XSR[1,2]: Transmit shift registers 1 and 2 DXR[1,2]: Data transmit registers 1 and 2

XSR[1,2]

Compress

Do not modify

Figure 1−18. McBSP Transmission Signal Activity

CLKX

FSX

XRDY

CLKX: Internal transmit clock FSX: Internal transmit frame-sync signal

1) The CPU writes data to the data transmit register(s). When DXR1 is loaded, the transmitter ready bit (XRDY) is cleared in SPCR2 to indicate that the transmitter is not ready for new data.

If the word length is 16 bits or smaller, only DXR1 is used. If the word length is larger than 16 bits, DXR2 and DXR1 are used, and DXR2 contains the most significant bits. For details on choosing a word length, see Set the Transmit Word Length(s) in Chapter 3.

DX: Data on DX pin XRDY: Status of transmitter ready bit (high is 1)

DXR[1,2]

From CPU

C5C6C7B0B1B2B3B4B5B6B7A0A1

Write to DXR1DXR1 to XSR1 copy(C)Write to DXR1(C)DXR1 to XSR1 copy(B)

SPRU061B

Note:

If both DXRs are needed (word length larger than 16 bits), the CPU must load DXR2 first and then load DXR1. As soon as DXR1 is loaded, the contents of both DXRs are copied to the transmit shift registers (XSRs), as described in the next step. If DXR2 is not loaded first, the previous content of DXR2 is passed to the XSR2.

2) When new data arrives in DXR1, the McBSP copies the content of the data transmit register(s) to the transmit shift register(s). In addition, the transmit

Multichannel Buffered Serial Port (McBSP)

1-23

Page 40

McBSP Operation

ready bit (XRDY) is set. This indicates that the transmitter is ready to accept new data from the CPU.

If the word length is 16 bits or smaller, only XSR1 is used. If the word length is larger than 16 bits, XSR2 and XSR1 are used, and XSR2 contains the most significant bits.

If companding is used during the transfer (XCOMPAND = 10b or 11b in XCR2), the McBSP compresses the 16-bit data in DXR1 to 8-bit data in the µ-law or A-law format in XSR1. If companding is disabled, the McBSP passes data from the DXR(s) to the XSR(s) without modification.

3) The McBSP waits for a transmit frame-sync pulse on internal FSX.

4) When the pulse arrives, the McBSP inserts the appropriate data delay that is selected with the XDATDLY bits of XCR2.

In the preceding timing diagram (Figure 1−18), a 1-bit data delay is selected.

5) The McBSP shifts data bits from the transmit shift register(s) to the DX pin.

When activity is not properly timed, errors can occur. See the following topics for more details:

- Overwrite in the Transmitter (page 1-43)

- Underflow in the Transmitter (page 1-44)

- Unexpected Transmit Frame-Sync Pulse (page 1-46)

1.3.7 Interrupts and FIFO Events Generated by a McBSP

The McBSP sends notification of important events to the CPU and FIFO via the internal signals shown in Table 1−5.

Table 1−5. Interrupts and FIFO Events Generated by a McBSP

Internal Signal Description

RINT Receive interrupt

The McBSP can send a receive interrupt request to CPU based upon a selected condition in the receiver of the McBSP (a condition selected by the RINTM bits of SPCR1).

XINT Transmit interrupt

The McBSP can send a transmit interrupt request to CPU based upon a selected condition in the transmitter of the McBSP (a condition selected by the XINTM bits of SPCR2).

1-24

Multichannel Buffered Serial Port (McBSP)

SPRU061B

Page 41

Table 1−5. Interrupts and FIFO Events Generated by a McBSP (Continued)

Internal Signal Description

REVT Receive synchronization event

An REVT signal is sent to the FIFO when data has been received in the data receive registers (DRRs).

XEVT Transmit synchronization event

An XEVT signal is sent to the FIFO when the data transmit registers (DXRs) are ready to accept the next serial word for transmission.

REVTA A-bis mode receive synchronization event

If ABIS = 1 (A-bis mode is enabled) an REVTA signal is sent to the FIFO every 16 cycles.

McBSP Operation

XEVTA

A-bis mode transmit synchronization event If ABIS = 1 (A-bis mode is enabled) an XEVTA signal is sent to the FIFO every 16

cycles.

SPRU061B

Multichannel Buffered Serial Port (McBSP)

1-25

Page 42

Sample Rate Generator of the McBSP

1.4 Sample Rate Generator of the McBSP

Note: General-purpose I/O Selection

Do not use the GPIO function using RIOEN/XIOEN bits 12 and 13 in the PCR register. This feature is not applicable to the 28x McBSP implementation; therefore, these bits are reserved on 28x devices.

The McBSP contains a sample rate generator module that can be programmed to generate internal data-clock (CLKG) and an internal frame-synchronization (FSG) signal. Figure 1−19 is a conceptual block diagram that shows the clock selection options available on the McBSP. The clock selection to the module is selectable using the SCLKME bit (PCR bit 7) and CLKSM bit (SRGR2 bit 13).

Figure 1−19. Sample Rate Generator Clock Selection

CLKX pin

CLKXP

CLKR pin

CLKRP

CLKSM

LSPCLK

CLKS pin tied 0

CLKSP reserved

CLKGD FPER

GSYN

FCSR

CLKSRG

SCLKME

Frame pulse

detection and clock

synchronization

FWID

Frame

pulse

FSG

CLKG

The McBSP contains a sample rate generator that can be used to generate an internal data clock (CLKG) and an internal frame-synchronization signal (FSG). CLKG can be used for bit shifting on the data receive (DR) pin and/or the data transmit (DX) pin. FSG can be used to initiate frame transfers on DR and/or DX.

1-26

The source clock for the sample rate generator (labeled CLKSRG in the diagram) can be supplied by the LSPCLK or by an external pin (CLKS, CLKX, or CLKR). The source is selected with the SCLKME bit of PCR and the CLKSM

Multichannel Buffered Serial Port (McBSP)

SPRU061B

Page 43

Sample Rate Generator of the McBSP

bit of SRGR2. If a pin is used, the polarity of the incoming signal can be inverted with the appropriate polarity bit (CLKSP of SRGR2, CLKXP of PCR, or CLKRP of PCR).

The sample rate generator has a 3-stage clock divider that gives CLKG and FSG programmability. The three stages provide:

- Clock divide down. The source clock is divided according to the CLKGDV

bits of SRGR1 to produce CLKG.

- Frame period divide down. CLKG is divided according to the FPER bits of

SRGR2 to control the period from the start of a frame-sync pulse to the start of the next pulse.

- Frame-sync pulse width countdown. CLKG cycles are counted according

to the FWID bits of SRGR1 to control the width of each frame-sync pulse.

In addition to the 3-stage clock divider, the sample rate generator has a frame-sync pulse detection and clock synchronization module that allows synchronization of the clock divide down with an incoming frame-sync pulse on the FSR pin. This feature is enabled or disabled with the GSYNC bit of SRGR2.

For details on getting the sample rate generator ready for operation, see the reset and initialization procedure on page 1-33.

1.4.1 Clock Generation in the Sample Rate Generator

The sample rate generator can produce a clock signal (CLKG) for use by the receiver, the transmitter, or both. Use of the sample rate generator to drive clocking is controlled by the clock mode bits (CLKRM and CLKXM) in the pin control register (PCR). When a clock mode bit is set to 1 (CLKRM = 1 for reception, CLKXM = 1 for transmission), the corresponding data clock (CLKR for reception, CLKX for transmission) is driven by the internal sample rate generator output clock (CLKG).

Note that the effects of CLKRM = 1 and CLKXM = 1 on the McBSP are partially affected by the use of the digital loopback mode and the clock stop (SPI) mode, respectively, as described in Table 1−6. The digital loopback mode (described in Chapter 3) is selected with the DLB bit of SPCR1. The clock stop mode is selected with the CLKSTP bits of SPCR1.

When using the sample rate generator as a clock source, make sure the sample rate generator is enabled (GRST

= 1).

SPRU061B

Multichannel Buffered Serial Port (McBSP)

1-27

Page 44

Sample Rate Generator of the McBSP

Table 1−6. Effects of DLB and CLKSTP on Clock Modes

Mode Bit Settings Effect

CLKRM = 1 DLB = 0

(Digital loopback mode disabled) DLB = 1

(Digital loopback mode enabled)

CLKXM = 1

CLKSTP = 00b or 01b (Clock stop (SPI) mode disabled)

CLKSTP = 10b or 11b (Clock stop (SPI) mode enabled)

1.4.1.1 Choosing an Input Clock

The sample rate generator must be driven by an input clock signal from one of the four sources selectable with the SCLKME bit of PCR and the CLKSM bit of SRGR2 (see Table 1−7). When CLKSM = 1, the minimum divide down value in CLKGDV bits should be 1. CLKGDV is described in section 1.4.1.3.

Note:

The McBSP cannot operate at a frequency faster than one-half the LSPCLK. Choose an input clock frequency and a CLKDV value such that CLKG is less than or equal to one-half the LSPCLK.

CLKR is an output pin driven by the sample rate generator output clock (CLKG).

CLKR is an output pin driven by internal CLKX. The source for CLKX depends on the CLKXM bit.

CLKX is an output pin driven by the sample rate generator output clock (CLKG).

The McBSP is a master in an SPI system. Internal CLKX drives internal CLKR and the shift clocks of any SPI-compliant slave devices in the system. CLKX is driven by the internal sample rate generator.

Table 1−7. Choosing an Input Clock for the Sample Rate Generator

With the SCLKME and CLKSM Bits

SCLKME CLKSM Input Clock For Sample Rate Generator

0 0 Reserved 0 1 LSPCLK 1 0 Signal on CLKR pin 1

1.4.1.2 Choosing a Polarity for the Input Clock

As shown in Figure 1−20, when the input clock is received from a pin, you can choose the polarity of the input clock. The rising edge of CLKSRG generates CLKG and FSG, but you can determine which edge of the input clock causes a rising edge on CLKSRG. The polarity options and their effects are described in Table 1−8.

1-28

Multichannel Buffered Serial Port (McBSP)

1 Signal on CLKX pin

SPRU061B

Page 45

Sample Rate Generator of the McBSP

Figure 1−20. Possible Inputs to the Sample Rate Generator and the Polarity Bits

CLKX pin

CLKXP

CLKR pin

CLKRP

CLKSM

LSPCLK

Reserved

CLKSRG

To clock dividers

SCLKSME

Table 1−8. Polarity Options for the Input to the Sample Rate Generator

Input Clock Polarity Option Effect

LSPCLK Always positive polarity Rising edge of CPU clock generates transitions on

CLKG and FSG.

Signal on CLKR pin CLKRP = 0 in PCR Falling edge on CLKR pin generates transitions on

CLKG and FSG.

CLKRP = 1 in PCR Rising edge on CLKR pin generates transitions on

CLKG and FSG.

Signal on CLKX pin CLKXP = 0 in PCR Rising edge on CLKX pin generates transitions on

CLKG and FSG.

CLKXP = 1 in PCR Falling edge on CLKX pin generates transitions on

CLKG and FSG.

1.4.1.3 Choosing a Frequency for the Output Clock (CLKG)

The input clock (LSPCLK or external clock) can be divided down by a programmable value to drive CLKG. Regardless of the source to the sample rate generator, the rising edge of CLKSRG (see the sample rate generator diagram on page 1-26) generates CLKG and FSG.

The first divider stage of the sample rate generator creates the output clock from the input clock. This divider stage uses a counter that is preloaded with the divide down value in the CLKGDV bits of SRGR1. The output of this stage is the data clock (CLKG). CLKG has the frequency represented by the following equation.

SPRU061B

Multichannel Buffered Serial Port (McBSP)

1-29

Page 46

Sample Rate Generator of the McBSP

CLKG frequency +

Input clock frequency

(

CLKGDV ) 1

)

Thus, the input clock frequency is divided by a value between 1 and 256. When CLKGDV is odd or equal to 0, the CLKG duty cycle is 50%. When CLKGDV is an even value, 2p, representing an odd divide down, the high-state duration is p+1 cycles and the low-state duration is p cycles.

Note:

The McBSP cannot operate at a frequency faster than one-half the LSPCLK. Choose an input clock frequency and a CLKDV value such that CLKG is less than or equal to one-half the LSPCLK.

1.4.1.4 Keeping CLKG Synchronized to an External Input Clock

When an external signal is selected to drive the sample rate generator (see section 1.4.1.1), the GSYNC bit in SRGR2 and the FSR pin can be used to configure the timing of the output clock (CLKG) relative to the input clock.

GSYNC = 1 ensures that the McBSP and an external device are dividing down the input clock with the same phase relationship. If GSYNC = 1, an inactive-to-active transition on the FSR pin triggers a resynchronization of CLKG and generation of FSG.

For more details about the synchronization, see section 1.4.3 on page 1-31.

1.4.2 Frame Sync Generation in the Sample Rate Generator

The sample rate generator can produce a frame-sync signal (FSG) for use by the receiver, the transmitter, or both.

If you want the receiver to use FSG for frame synchronization, make sure FSRM = 1. (When FSRM = 0, receive frame synchronization is supplied via the FSR pin.)

If you want the transmitter to use FSG for frame synchronization, you must set:

- FSXM = 1 in PCR: This indicates that transmit frame synchronization is

supplied by the McBSP itself rather than from the FSX pin.

- FSGM = 1 in SRGR2: This indicates that when FSXM = 1, transmit frame

synchronization is supplied by the sample rate generator. (When FSGM = 0 and FSXM = 1, the transmitter uses frame-sync pulses generated every time data is transferred from DXR[1,2] to XSR[1,2].)

1-30

Multichannel Buffered Serial Port (McBSP)

SPRU061B

Page 47

Sample Rate Generator of the McBSP

In either case, the sample rate generator must be enabled (GRST = 1) and the frame-sync logic in the sample rate generator must be enabled (FRST = 0).

1.4.2.1 Choosing the Width of the Frame-Sync Pulse on FSG

Each pulse on FSG has a programmable width. You program the FWID bits of SRGR1, and the resulting pulse width is (FWID + 1) CLKG cycles, where CLKG is the output clock of the sample rate generator.

1.4.2.2 Controlling the Period Between the Starting Edges of Frame-Sync Pulses on FSG

You can control the amount of time from the starting edge of one FSG pulse to the starting edge of the next FSG pulse. This period is controlled in one of two ways, depending on the configuration of the sample rate generator:

- If the sample rate generator is using an external input clock and

GSYNC = 1 in SRGR2, FSG pulses in response to an inactive-to-active transition on the FSR pin. Thus, the frame-sync period is controlled by an external device.

- Otherwise, you program the FPER bits of SRGR2, and the resulting

frame-sync period is (FPER + 1) CLKG cycles, where CLKG is the output clock of the sample rate generator.

1.4.2.3 Keeping FSG Synchronized to an External Clock

When an external signal is selected to drive the sample rate generator (see section 1.4.1.1 on page 1-28), the GSYNC bit of SRGR2 and the FSR pin can be used to configure the timing of FSG pulses.

Section 1.4.3 has more details about the synchronization.

1.4.3 Synchronizing Sample Rate Generator Outputs to an External Clock

The sample rate generator can produce a clock signal (CLKG) and a frame-sync signal (FSG) based on an input clock signal that is either the CPU clock signal or a signal at the CLKS, CLKR, or CLKX pin. When an external clock is selec t e d t o drive the sample rate generator, the GSYNC bit of SRGR2 and the FSR pin can be used to control the timing of CLKG and the pulsing of FSG relative to the chosen input clock.

Make GSYNC = 1 when you want the McBSP and an external device to divide down the input clock with the same phase relationship. If GSYNC = 1:

SPRU061B

Multichannel Buffered Serial Port (McBSP)

1-31

Page 48

Sample Rate Generator of the McBSP

An inactive-to-active transition on the FSR pin triggers a

resynchronization of CLKG and a pulsing of FSG.

- CLKG always begins with a high state after synchronization.

- FSR is always detected at the same edge of the input clock signal that

generates CLKG, no matter how long the FSR pulse is.

- The FPER bits of SRGR2 are ignored because the frame-sync period on

FSG is determined by the arrival of the next frame-sync pulse on the FSR pin.

If GSYNC = 0, CLKG runs freely and is not resynchronized, and the frame-sync period on FSG is determined by FPER.

1.4.3.1 Operating the Transmitter Synchronously With the Receiver

When GSYNC = 1, the transmitter can operate synchronously with the receiver, provided that:

- FSX is programmed to be driven by FSG (FSGM = 1 in SRGR2 and

FSXM = 1 in PCR). If the input FSR has appropriate timing so that it can be sampled by the falling edge of CLKG, it can be used, instead, by setting FSXM = 0 and connecting FSR to FSX externally.

- The sample rate generator clock drives the transmit and receive clocking

(CLKRM = CLKXM = 1 in PCR). Therefore, the CLK(R/X) pin should not be driven by any other driving source.

1.4.3.2 Synchronization Examples

Figure 1−21 and Figure 1−22 show the clock and frame-synchronization operation with various polarities of CLKS (the chosen input clock) and FSR. These figures assume FWID = 0 in SRGR1, for an FSG pulse that is 1 CLKG cycle wide. The FPER bits of SRGR2 are not programmed; the period from the start of a frame-sync pulse to the start of the next pulse is determined by the arrival of the next inactive-to-active transition on the FSR pin. Each of the figures shows what happens to CLKG when it is initially synchronized and GSYNC = 1, and when it is not initially synchronized and GSYNC = 1. The second figure has a slower CLKG frequency (it has a larger divide-down value in the CLKGDV bits of SRGR1).

1-32

Multichannel Buffered Serial Port (McBSP)

SPRU061B

Page 49

Sample Rate Generator of the McBSP

Figure 1−21. CLKG Synchronization and FSG Generation When GSYNC = 1

and CLKGDV = 1

CLKS (CLKSP=1)

CLKS (CLKSP=0)

FSR external

(FSRP=0)

FSR external

(FSRP=1)

CLKG

(No need to

resync)

(needs resync)

CLKG

FSG

Figure 1−22. CLKG Synchronization and FSG Generation When

GSYNC = 1 and CLKGDV = 3

CLKS (CLKSP=1)

CLKS (CLKSP=0)

FSR external

(FSRP=0)

FSR external

(FSRP=1)

CLKG

(No need to

resync)

(needs resync)

CLKG

FSG

1.4.4 Reset and Initialization Procedure for the Sample Rate Generator

To reset and initialize the sample rate generator:

1) Place the McBSP/sample rate generator in reset.

SPRU061B

Multichannel Buffered Serial Port (McBSP)

1-33

Page 50

Sample Rate Generator of the McBSP

During a DSP reset, the sample rate generator, the receiver, and the transmitter reset bits (GRST, RRST, and XRST) are automatically forced to 0. Otherwise, during normal operation, the sample rate generator can be reset by making GRST is not used by any portion of the McBSP. Depending on your system you may also want to reset the receiver (RRST transmitter (XRST = 0 in SPCR2).

= 0 in SPCR2, provided that CLKG and/or FSG

= 0 in SPCR1) and reset the

If GRST by 2, and FSG is driven inactive-low. If GRST

= 0 due to a DSP reset, CLKG is driven by the CPU clock divided

= 0 due to program code,

CLKG and FSG are driven low (inactive).

2) Program registers that affect the sample rate generator.

Program the sample rate generator registers (SRGR1 and SRGR2) as required for your application. If necessary, other control registers can be loaded with desired values, provided the respective portion of the McBSP (the receiver or transmitter) is in reset.

After the sample rate generator registers are programmed, wait 2 CLKSRG cycles. This ensures proper synchronization internally.

3) Enable the sample rate generator (take it out of reset).

In SPCR2, make GRST

= 1 to enable the sample rate generator.

After the sample rate generator is enabled, wait 2 CLKG cycles for the sample rate generator logic to stabilize.

On the next rising edge of CLKSRG, CLKG transitions to 1 and starts clocking with a frequency equal to

CLKG frequency +

Input clock frequency

(

CLKGDV ) 1

)

where the input clock is selected with the SCLKME bit of PCR and the CLKSM bit of SRGR2:

1-34

SCLKME CLKSM Input Clock For Sample Rate Generator

0 0 Reserved 0 1 LSPCLK 1 0 Signal on CLKR pin 1

1 Signal on CLKX pin

4) If necessary, enable the receiver and/or the transmitter.

If necessary, remove the receiver and/or transmitter from reset by setting

and/or XRST = 1.

RRST

Multichannel Buffered Serial Port (McBSP)

SPRU061B

Page 51

5) If necessary, enable the frame-sync logic of the sample rate generator.

After the required data acquisition setup is done (DXR[1/2] is loaded with data), set FRST

= 1 in SPCR2 if an internally generated frame-sync pulse is required. FSG is generated with an active-high edge after the programmed number of CLKG clocks (FPER + 1) have elapsed.

1.4.5 Sample Rate Generator Clocking Examples

This section shows three examples of using the sample rate generator to clock data during transmission and reception.

1.4.5.1 Double-Rate ST-Bus Clock

Figure 1−23 shows McBSP configuration to be compatible with the Mitel ST-Bus. Note that this operation is running at maximum frame frequency (described on page 1-17).

Figure 1−23. ST-BUS and MVIP Clocking Example

Sample Rate Generator of the McBSP

4.096 MHz CLKS

FSR external

Internal FSG, FSR,

internal FSX

2.048 MHz CLKG, internal CLKR,

internal CLKS

(first FSR)

DR, DX (first FSR)

Internal CLKG, CLKR,

(subsequent FSR)

DR, DX

(subsequent FSR)

W2B7W1B0W1B1W1B2W1B3W1B4W1B5W1B6W1B7

W2B7W1B1W1B3 W1B2W1B4W1B5W1B6 W1B0W1B7W32B0

WxBy = Word x Bit y

For this McBSP configuration:

- DLB = 0: Digital loopback mode off, CLKSTP = 00b: Clock stop mode off,

and CLKRM/CLKXM = 1: Internal CLKR/CLKX generated internally by sample rate generator

- GSYNC = 1: Synchronize CLKG with external frame-sync signal input on

FSR pin. CLKG is not synchronized until the frame-sync signal is active. FSR is regenerated internally to form a minimum pulse width.

SPRU061B

Multichannel Buffered Serial Port (McBSP)

1-35

Page 52

Sample Rate Generator of the McBSP

SCLKME = 0 and CLKSM = 1: External clock signal at CLKS pin drives

the sample rate generator

- CLKSP = 1: Falling edge of CLKS generates CLKG and thus internal

CLK(R/X)

- CLKGDV = 1: Frequency of receive clock (shown as CLKR) is half CLKS

frequency

- FSRP/FSXP = 1: Active-low frame-sync pulse

- RFRLEN1/XFRLEN1 = 11111b: 32 words per frame

- RWDLEN1/XWDLEN1 = 0: 8 bits per word

- RPHASE/XPHASE = 0: Single-phase frame and thus (R/X)FRLEN2 and

(R/X)WDLEN2 are ignored

- RDATDLY/XDATDLY = 0: No data delay

1.4.5.2 Single-Rate ST-Bus Clock

The example in Figure 1−24 is the same as the double-rate ST-bus clock example in section 1.4.5.1 except that:

- CLKGDV = 0: CLKS drives internal CLK(R/X) without any divide down

(single-rate clock).

- CLKSP = 0: Rising edge of CLKS generates CLKG and internal CLK(R/X)

Figure 1−24. Single-Rate Clock Example

CLKS

FSR external

Internal FSG, FSR,

internal FSX

Internal CLKG, CLKR,

internal CLKX

(first FSR)

DR, DX (first FSR)

Internal CLKG, CLKR,

(subsequent FSR)

DR, DX

(subsequent FSR)

The rising edge of CLKS is used to detect the external FSR pulse, which resynchronizes the internal McBSP clocks and generates a frame-sync pulse

W2B7W1B0W1B1W1B2W1B3W1B4W1B5W1B6W1B7

W2B7W1B1W1B3 W1B2W1B4W1B5W1B6 W1B0W1B7W32B0

WxBy = Word x Bit y

1-36

Multichannel Buffered Serial Port (McBSP)

SPRU061B

Page 53

for internal use. The internal frame-sync pulse is generated so that it is wide enough to be detected on the falling edge of internal clocks.

1.4.5.3 Other Double-Rate Clock

The example in Figure 1−25 is the same as the double-rate ST-bus clock example in section 1.4.5.1 except that:

- CLKSP = 0: Rising edge of CLKS generates CLKG and thus CLK(R/X)

- CLKGDV = 1: Frequency of CLKG (and thus internal CLKR and internal

CLKX) is half CLKS frequency

- FSRM/FSXM = 0: Frame synchronization is externally generated. The

frame-sync pulse is wide enough to be detected.

- GSYNC = 0: CLKS drives CLKG. CLKG runs freely; it is not

resynchronized by a pulse on the FSR pin.

- FSRP/FSXP = 0: Active-high input frame-sync signal

- RDATDLY/XDATDLY = 1: Data delay of one bit

Sample Rate Generator of the McBSP

Figure 1−25. Double-Rate Clock Example

CLKS

Internal FS(R/X)

Internal CLK(R/X)

D(R/X)

W2B7W1B0W1B1W1B2W1B3W1B4W1B5W1B6W1B7W32B0

WxBy = Word x Bit y

SPRU061B

Multichannel Buffered Serial Port (McBSP)

1-37

Page 54

McBSP Exception/Error Conditions

1.5 McBSP Exception/Error Conditions

There are five serial port events that may constitute a system error:

- Receiver Overrun (RFULL = 1). This occurs when DRR1 has not been

read since the last RBR-to-DRR copy. Consequently, the receiver does not copy a new word from the RBR(s) to the DRR(s), and the RSR(s) are now full with another new word shifted in from DR. Therefore, RFULL = 1 indicates an error condition wherein any new data that may arrive at this time on DR will replace the contents of the RSR(s), and thus, the previous word is lost. The RSR(s) continue to be overwritten as long as new data arrives on DR and DRR1 is not read. For more details about overrun in the receiver, see page 1-39.

- Unexpected Receive Frame-Sync Pulse (RSYNCERR = 1). This

occurs during reception when RFIG = 0 and an unexpected frame-sync pulse occurs. An unexpected frame-sync pulse is one that begins the next frame transfer before all the bits of the current frame have been received. Such a pulse causes data reception to abort and restart. If new data has been copied into the RBR(s) from the RSR(s) since the last RBR-to-DRR copy, this new data in the RBR(s) is lost. This is because no RBR-to-DRR copy occurs; the reception has been restarted. For more details about receive frame-sync errors, see page 1-40.

1-38

- Transmitter Data Overwrite. This occurs when the CPU overwrites data

in the DXR(s) before the data is copied to the XSR(s). The overwritten data never reaches the DX pin. For more details about overwrite in the transmitter, see page 1-43.

- Transmitter Underflow (XEMPTY = 0). If a new frame-sync signal

arrives before new data is loaded into DXR1, the previous data in the DXR(s) is sent again. This will continue for every new frame-sync pulse that arrives until DXR1 is loaded with new data. For more details about underflow in the transmitter, see page 1-44.

- Unexpected Transmit Frame-Synch Pulse (XSYNCERR = 1). This

occurs during transmission when XFIG = 0 and an unexpected frame-sync pulse occurs. An unexpected frame-sync pulse is one that begins the next frame transfer before all the bits of the current frame have been transferred. Such a pulse causes the current data transmission to abort and restart. If new data has been written to the DXR(s) since the last DXR-to-XSR copy, the current value in the XSR(s) is lost. For more details about transmit frame-sync errors, see page 1-46.

Multichannel Buffered Serial Port (McBSP)

SPRU061B

Page 55

1.5.1 Overrun in the Receiver

RFULL = 1 in SPCR1 indicates that the receiver has experienced overrun and is in an error condition. RFULL is set when all of the following conditions are met:

1) DRR1 has not been read since the last RBR-to-DRR copy (RRDY = 1).

2) RBR1 is full and an RBR-to-DRR copy has not occurred.

3) RSR1 is full and an RSR1-to-RBR copy has not occurred. As described in the section on McBSP reception (page 1-21), data arriving on

DR is continuously shifted into RSR1 (for word length of 16 bits or smaller) or RSR2 and RSR1 (for word length larger than 16 bits). Once a complete word is shifted into the RSR(s), an RSR-to-RBR copy can occur only if the previous data in RBR1 has been copied to DRR1. The RRDY bit is set when new data arrives in DRR1 and is cleared when that data is read from DRR1. Until RRDY = 0, the next RBR-to-DRR copy will not take place, and the data is held in the RSR(s). New data arriving on the DR pin is shifted into RSR(s), and the previous content of the RSR(s) is lost.

McBSP Exception/Error Conditions

Y ou can prevent the loss of data if DRR1 is read no later than 2.5 cycles before the end of the third word is shifted into the RSR1.

Important: If both DRRs are needed (word length larger than 16 bits), the CPU must read from DRR2 first and then from DRR1. As soon as DRR1 is read, the next RBR-to-DRR copy is initiated. If DRR2 is not read first, the data in DRR2 is lost.

Note that after the receiver starts running from reset, a minimum of three words must be received before RFULL is set. Either of the following events clears the RFULL bit and allows subsequent transfers to be read properly:

- The CPU reads DRR1.

- The receiver is reset individually (RRST = 0) or as part of a DSP reset.

Another frame-sync pulse is required to restart the receiver.

1.5.1.1 Example of the Overrun Condition

Figure 1−26 shows the receive overrun condition. Because serial word A is not read from DRR1 before serial word B arrives in RBR1, B is not transferred to DRR1 yet. Another new word (C) arrives and RSR1 is full with this data. DRR1 is finally read, but not earlier than 2.5 cycles before the end of word C. Therefore, new data (D) overwrites word C in RSR1. If DRR1 is not read in time, the next word can overwrite D.

SPRU061B

Multichannel Buffered Serial Port (McBSP)

1-39

Page 56

McBSP Exception/Error Conditions

Figure 1−26. Overrun in the McBSP Receiver

CLKR

FSR

RRDY

RFULL

RBR1 to DRR1 copy(A)

No RBR1 to DRR1 copy(B)No read from DRR1(A)

1.5.1.2 Example of Preventing the Overrun Condition

Figure 1−27 shows the case where RFULL is set, but the overrun condition is prevented by a read from DRR1 at least 2.5 cycles before the next serial word (C) is completely shifted into RSR1. This ensures that an RBR1-to-DRR1 copy of word B occurs before receiver attempts to transfer word C from RSR1 to RBR1.

Figure 1−27. Overrun Prevented in the McBSP Receiver

CLKR

FSR

RRDY

RFULL

RBR1 to DRR1 copy(A)

No RBR1 to DRR1 copy(B)No read from DRR1(A)

D7C0C1C2C3C4C5C6C7B0B1B2B3B4B5B6B7A0A1

No RSR1 to RBR1 copy(C)

No read from DRR1(A)

C0C1C2C3C4C5C6C7B0B1B2B3B4B5B6B7A0A1

RBR1 to DRR1(B)

Read from DRR1(A)

1.5.2 Unexpected Receive Frame-Sync Pulse

Section 1.5.2.1 shows how the McBSP responds to any receive frame-sync pulses, including an unexpected pulse. Sections 1.5.2.2 and 1.5.2.3 show an examples of a frame-sync error and an example of how to prevent such an error, respectively.

1.5.2.1 Possible Responses to Receive Frame-Sync Pulses

Figure 1−28 shows the decision tree that the receiver uses to handle all incoming frame-sync pulses. The figure assumes that the receiver has been

= 1 in SPCR1). Case 3 in the figure is the case in which an error

1-40

started (RRST occurs.

Multichannel Buffered Serial Port (McBSP)

SPRU061B

Page 57

McBSP Exception/Error Conditions

Figure 1−28. Possible Responses to Receive Frame-Sync Pulses

Receive frame-sync

pulse occurs

Unexpected

frame-sync

pulse

Yes

RFIG=1

Yes

Case 1:

With Frame Ignore

Ignore frame pulse

Receiver continues

running

Any one of three cases can occur:

Case 2:

Normal Reception

Start receiving data

Case 3:

Without Frame Ignore

Abort reception

SET RSYNCERR

Start next reception

immediately

Previous word is lost

SPRU061B

- Case 1: Unexpected internal FSR pulses with RFIG = 1 in RCR2. Receive

frame-sync pulses are ignored, and the reception continues.

- Case 2: Normal serial port reception. Reception continues normally

because the frame-sync pulse is not unexpected. There are three possible reasons why a receive operation might not be in progress when the pulse occurs:

J The FSR pulse is the first after the receiver is enabled (RRST = 1 in

SPCR1).

J The FSR pulse is the first after DRR[1,2] is read, clearing a receiver full

(RFULL = 1 in SPCR1) condition.

Multichannel Buffered Serial Port (McBSP)

1-41

Page 58

McBSP Exception/Error Conditions

- Case 3: Unexpected receive frame synchronization with RFIG = 0

(frame-sync pulses not ignored). Unexpected frame-sync pulses can originate from an external source or from the internal sample rate generator.

If a frame-sync pulse starts the transfer of a new frame before the current frame is fully received, this pulse is treated as an unexpected frame-sync pulse, and the receiver sets the receive frame-sync error bit (RSYNCERR) in SPCR1. RSYNCERR write of 0 to this bit.

If you want the McBSP to notify the CPU of receive frame-sync errors, you can set a special receive interrupt mode with the RINTM bits of SPCR1. When RINTM = 1 1b, the McBSP sends a receive interrupt (RINT) request to the CPU each time that RSYNCERR is set.

The serial port is in the interpacket intervals. The programmed data delay for reception (programmed with the RDATDLY bits in RCR2) may start during these interpacket intervals for the first bit of the next word to be received. Thus, at maximum frame frequency, frame synchronization can still be received 0 to 2 clock cycles before the first bit of the synchronized frame.

can be cleared only by a receiver reset or by a

1.5.2.2 Example of an Unexpected Receive Frame-Sync Pulse

Figure 1−29 shows an unexpected receive frame-sync pulse during normal operation of the serial port, with time intervals between data packets. When the unexpected frame-sync pulse occurs, the RSYNCERR bit is set, the reception of data B is aborted, and the reception of data C begins. In addition, if RINTM = 11b, the McBSP sends a receive interrupt (RINT) request to the CPU.

Figure 1−29. An Unexpected Frame-Sync Pulse During a McBSP Reception

CLKR

FSR

RRDY

RSYNCERR

1-42

Multichannel Buffered Serial Port (McBSP)

Unexpected frame synchronization

C0C1C2C3C4C5C6C7B4B5B6B7A0A1

RBR1 to DRR1(B)

Read from DRR1(C)RBR1 to DRR1 copy(C)Read from DRR1(A)RBR1 to DRR1 copy(A)

SPRU061B

Page 59

1.5.2.3 Preventing Unexpected Receive Frame-Sync Pulses

Each frame transfer can be delayed by 0, 1, or 2 CLKR cycles, depending on the value in the RDATDLY bits of RCR2. For each possible data delay, Figure 1−30 shows when a new frame-sync pulse on FSR can safely occur relative to the last bit of the current frame.

Figure 1−30. Proper Positioning of Frame-Sync Pulses

For 2-bit delay: Next frame-sync pulse here or later is OK.

For 1-bit delay: Next frame-sync pulse here or later is OK.

McBSP Exception/Error Conditions

For 0-bit delay: Next frame-sync pulse here or later is OK.

CLKR/CLKX

FSR/FSX

DR/DX

1.5.3 Overwrite in the Transmitter

As described in the section on McBSP transmission (page 1-22), after the CPU writes data to the DXR(s), the transmitter must then copy that data to the XSR(s) and then shift each bit from the XSR(s) to the DX pin. If new data is written to the DXR(s) before the previous data is copied to the XSR(s), the previous data in the DXR(s) is overwritten and thus lost.

Last bit of current frame

Earliest possible time to begin transfer of next frame

SPRU061B

Multichannel Buffered Serial Port (McBSP)

1-43

Page 60

McBSP Exception/Error Conditions

1.5.3.1 Example of the Overwrite Condition

Figure 1−31 shows what happens if the data in DXR1 is overwritten before being transmitted. Initially, DXR1 is loaded with data C. A subsequent write to DXR1 overwrites C with D before C is copied to XSR1. Thus, C is never transmitted on DX.

Figure 1−31. Data in the McBSP Transmitter Overwritten and Thus Not Transmitted

CLKX

FSX

XRDY

1.5.3.2 Preventing Overwrites

You can prevent CPU overwrites by making the CPU:

- Poll for XRDY = 1 in SPCR2 before writing to the DXR(s). XRDY is set

when data is copied from DXR1 to XSR1 and is cleared when new data is written to DXR1.

- Wait for a transmit interrupt (XINT) before writing to the DXR(s). When

XINTM = 00b in SPCR2, the transmitter sends XINT to the CPU each time XRDY is set.

1.5.4 Underflow in the Transmitter

The McBSP indicates a transmitter empty (or underflow) condition by clearing the XEMPTY (XEMPTY = 0):

- DXR1 has not been loaded since the last DXR-to-XSR copy, and all bits

of the data word in the XSR(s) have been shifted out on the DX pin.

bit in SPCR2. Either of the following events activates XEMPTY

Write to DXR1(D)

D5D6D7B0B1B2B3B4B5B6B7A0A1

Write to DXR1(E)DXR1 to XSR1 copy(D)Write to DXR1(C)

1-44

- The transmitter is reset (by forcing XRST = 0 in SPCR2, or by a DSP reset)

and is then restarted.

In the underflow condition, the transmitter continues to transmit the old data that is in t h e DXR(s) for every new transmit frame-sync signal until a new value is loaded into DXR1 by the CPU.

Multichannel Buffered Serial Port (McBSP)

SPRU061B

Page 61

McBSP Exception/Error Conditions

Note:

If both DXRs are needed (word length larger than 16 bits), the CPU must load DXR2 first and then load DXR1. As soon as DXR1 is loaded, the contents of both DXRs are copied to the transmit shift registers (XSRs). If DXR2 is not loaded first, the previous content of DXR2 is passed to the XSR2.

XEMPTY is deactivated (XEMPTY = 1) when a new word in DXR1 is transferred to XSR1. If FSXM = 1 in PCR and FSGM = 0 in SRGR2, the transmitter generates a single internal FSX pulse in response to a DXR-to-XSR copy. Otherwise, the transmitter waits for the next frame-sync pulse before sending out the next frame on DX.

When the transmitter is taken out of reset (XRST ready (XRDY = 1 in SPCR2) and transmitter empty (XEMPTY DXR1 is loaded by the CPU before internal FSX goes active high, a valid DXR-to-XSR transfer occurs. This allows for the first word of the first frame to be valid even before the transmit frame-sync pulse is generated or detected. Alternatively , i f a transmit frame-sync pulse is detected before DXR1 is loaded, zeros will be output on DX.

1.5.4.1 Example of the Underflow Condition

Figure 1−32 shows an underflow condition. After B is transmitted, DXR1 is not reloaded before the subsequent frame-sync pulse. Thus, B is again transmitted on DX.

Figure 1−32. Underflow During McBSP Transmission

CLKX

FSX

XRDY

XEMPTY

= 1), it is in a transmitter

= 0) state. If

B5B6B7B0B1B2B3B4B5B6B7A0A1

Write to DXR1(C)DXR1 to XSR1 copy(B)

1.5.4.2 Example of Preventing the Underflow Condition

Figure 1−33 shows the case of writing to DXR1 just before an underflow condition would otherwise occur. After B is transmitted, C is written to DXR1 before the next frame-sync pulse. As a result, there is no underflow; B is not transmitted twice.

SPRU061B

Multichannel Buffered Serial Port (McBSP)

1-45

Page 62

McBSP Exception/Error Conditions

Figure 1−33. Underflow Prevented in the McBSP Transmitter

CLKX

FSX

XRDY

XEMPTY

1.5.5 Unexpected Transmit Frame-Sync Pulse

Section 1.5.5.1 shows how the McBSP responds to any transmit frame-sync pulses, including an unexpected pulse. Sections 1.5.5.2 and 1.5.5.3 show an examples of a frame-sync error and an example of how to prevent such an error, respectively.

1.5.5.1 Possible Responses to Transmit Frame-Sync Pulses

Figure 1−34 shows the decision tree that the transmitter uses to handle all incoming frame-sync pulses. The figure assumes that the transmitter has been started (XRST an error occurs.

= 1 in SPCR2). Case 3 in the figure is the case in which

C5C6C7B0B1B2B3B4B5B6B7A0A1

DXR1 to XSR1 copy(C)Write to DXR1(C)DXR1 to XSR1 copy

1-46

Multichannel Buffered Serial Port (McBSP)

SPRU061B

Page 63

McBSP Exception/Error Conditions

Figure 1−34. Possible Responses to Transmit Frame-Sync Pulses

Transmit frame-sync

pulse occurs

Unexpected

frame-sync

pulse

Yes

XFIG=1

Yes

Case 1:

With Frame Ignore

Ignore frame pulse

Transmit stays

running

Normal Transmission

Without Frame Ignore

Case 2:

Start new transmit

Case 3:

Abort transfer.

Set XSYNCERR.

Restart current

transfer

Any one of three cases can occur:

- Case 1: Unexpected internal FSX pulses with XFIG = 1 i n XCR2. Transmit

frame-sync pulses are ignored, and the transmission continues.

SPRU061B

- Case 2: Normal serial port transmission. Transmission continues

normally because the frame-sync pulse is not unexpected. There are two possible reasons why a transmit operations might not be in progress when the pulse occurs:

This FSX pulse is the first after the transmitter is enabled (XRST

= 1).

The serial port is in the interpacket intervals. The programmed data delay for transmission (programmed with the XDATDLY bits of XCR2) may start during these interpacket intervals before the first bit of the previous word is transmitted. Thus, at maximum packet frequency , frame synchronization can still be received 0 to 2 clock cycles before the first bit of the synchronized frame.

Multichannel Buffered Serial Port (McBSP)

1-47

Page 64

McBSP Exception/Error Conditions

Case 3: Unexpected transmit frame synchronization with XFIG = 0

(frame-sync pulses not ignored). Unexpected frame-sync pulses can originate from an external source or from the internal sample rate generator.

If a frame-sync pulse starts the transfer of a new frame before the current frame is fully transmitted, this pulse is treated as an unexpected frame-sync pulse, and the transmitter sets the transmit frame-sync error bit (XSYNCERR) in SPCR2. XSYNCERR transmitter reset or by a write of 0 to this bit.

If you want the McBSP to notify the CPU of frame-sync errors, you can set a special transmit interrupt mode with the XINTM bits of SPCR2. When XINTM = 11b, the McBSP sends a transmit interrupt (XINT) request to the CPU each time that XSYNCERR is set.

1.5.5.2 Example of an Unexpected Transmit Frame-Sync Pulse

Figure 1−35 shows an unexpected transmit frame-sync pulse during normal operation of the serial port, with intervals between the data packets. When the unexpected frame-sync pulse occurs, the XSYNCERR bit is set and because no new data has been passed to XSR1 yet, the transmission of data B is restarted. In addition, if XINTM = 11b, the McBSP sends a transmit interrupt (XINT) request to the CPU.

can be cleared only by a

Figure 1−35. An Unexpected Frame-Sync Pulse During a McBSP Transmission

CLKX

FSX

XRDY

XSYNCERR

1.5.5.3 Preventing Unexpected Transmit Frame-Sync Pulses

Each frame transfer can be delayed by 0, 1, or 2 CLKX cycles, depending on the value in the XDATDLY bits of XCR2. For each possible data delay, Figure 1−36 shows when a new frame-sync pulse on FSX can safely occur relative to the last bit of the current frame.

1-48

Multichannel Buffered Serial Port (McBSP)

Unexpected frame synchronization

B0B1B2B3B4B5B6B7B4B5B6B7A0A1

Write to DXR1(D)DXR1 to XSR1 (C)Write to DXR1(C)DXR1 to XSR1 copy(B)

SPRU061B

Page 65

Figure 1−36. Proper Positioning of Frame-Sync Pulses

For 2-bit delay: Next frame-sync pulse here or later is OK.

For 1-bit delay: Next frame-sync pulse here or later is OK.

CLKR/CLKX

FSR/FSX

DR/DX

McBSP Exception/Error Conditions

For 0-bit delay: Next frame-sync pulse here or later is OK.

Last bit of current frame

Earliest possible time to begin transfer of next frame

SPRU061B

Multichannel Buffered Serial Port (McBSP)

1-49

Page 66

1-50

Multichannel Buffered Serial Port (McBSP)

SPRU061B

Page 67

Chapter 2



This chapter explains how to assign blocks to partitions for multichannel selection.

Topic Page

2.1 Channels, Blocks, and Partitions 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 A-bis Mode 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 SPI Protocol 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-1

Page 68

Channels, Blocks, and Partitions

2.1 Channels, Blocks, and Partitions

A McBSP channel is a time slot for shifting in/out the bits of one serial word. Each McBSP supports up to 128 channels for reception and 128 channels for transmission.

In the receiver and in the transmitter, the 128 available channels are divided into eight blocks that each contain 16 contiguous channels:

Block 0: Channels 0–15 Block 1: Channels 16–31 Block 2: Channels 32–47 Block 3: Channels 48–63

The blocks are assigned to partitions according to the selected partition mode. In the 2-partition mode, you assign one even-numbered block (0, 2, 4, or 6) to partition A and one odd-numbered block (1, 3, 5, or 7) to partition B. In the 8-partition mode, blocks 0 through 7 are automatically assigned to partitions, A through H, respectively.

The number of partitions for reception and the number of partitions for transmission are independent. For example, it is possible to use 2 receive partitions (A and B) and 8 transmit partitions (A–H).

2.1.1 Multichannel Selection

When a McBSP uses a time-division multiplexed (TDM) data stream while communicating with other McBSPs or serial devices, the McBSP may need to receive and/or transmit on only a few channels. To save memory and bus bandwidth, you can use a multichannel selection mode to prevent data flow in some of the channels.

Each channel partition has a dedicated channel-enable register. If the appropriate multichannel selection mode is on, each bit in the register controls whether data flow is allowed or prevented in one of the channels that is assigned to that partition.

Block 4: Channels 64–79 Block 5: Channels 80–95 Block 6: Channels 96–111 Block 7: Channels 112–127

The McBSP has one receive multichannel selection mode (described in section 2.1.5) and three transmit multichannel selection modes (described in section 2.1.6).

2.1.2 Configuring a Frame for Multichannel Selection

Before you enable a multichannel selection mode, make sure you properly configure the data frame:

- Select a single-phase frame (RPHASE/XPHASE = 0). Each frame

represents a TDM data stream.

2-2

Multichannel Selection Modes

SPRU061B

Page 69

Set a frame length (in RFRLEN1/XFRLEN1) that includes the

highest-numbered channel that will be used. For example, if you plan to use channels 0, 15, and 39 for reception, the receive frame length must be at least 40 (RFRLEN1 = 39). If XFRLEN1 = 39 in this case, the receiver creates 40 time slots per frame but only receives data during time slots 0, 15, and 39 of each frame.

2.1.3 Using Two Partitions

For multichannel selection operation in the receiver and/or the transmitter, you can use two partitions or eight partitions. If you choose the 2-partition mode (RMCME = 0 for reception, XMCME = 0 for transmission), McBSP channels are activated using an alternating scheme. In response to a frame-sync pulse, the receiver or transmitter begins with the channels in partition A and then alternates between partitions B and A until the complete frame has been transferred. When the next frame-sync pulse occurs, the next frame is transferred, beginning with the channels in partition A.

2.1.3.1 Assigning Blocks to Partitions A and B

For reception, any two of the eight receive-channel blocks can be assigned to receive partitions A and B, which means up to 32 receive channels can be enabled at any given point in time. Similarly, any two of the eight transmit-channel blocks (up 32 enabled transmit channels) can be assigned to transmit partitions A and B.

Channels, Blocks, and Partitions

For reception:

- Assign an even-numbered channel block (0, 2, 4, or 6) to receive partition

A by writing to the RPABLK bits. In the receive multichannel selection mode (described in section 2.1.5), the channels in this partition are controlled by receive channel enable register A (RCERA).

- Assign an odd-numbered block (1, 3, 5, or 7) to receive partition B with the

RPBBLK bits. In the receive multichannel selection mode, the channels in this partition are controlled by receive channel enable register B (RCERB).

For transmission:

- Assign an even-numbered channel block (0, 2, 4, or 6) to transmit partition

A by writing to the XPABLK bits. In one of the transmit multichannel selection modes (described in section 2.1.6), the channels in this partition are controlled by transmit channel enable register A (XCERA).

- Assign an odd-numbered block (1, 3, 5, or 7) to transmit partition B with

the XPBBLK bits. In one of the transmit multichannel selection modes, the

Multichannel Selection ModesSPRU061B

2-3

Page 70

Channels, Blocks, and Partitions

channels in this partition are controlled by transmit channel enable register B (XCERB).

Figure 2−1 shows an example of alternating between the channels of partition A and the channels of partition B. Channels 0–15 have been assigned to partition A, and channels 16–31 have been assigned to partition B. In response to a frame-sync pulse, the McBSP begins a frame transfer with partition A and then alternates between partitions B and A until the complete frame is transferred.

Figure 2−1. Alternating Between the Channels of Partition A and the

Channels of Partition B

2-partition mode. Example with fixed block assignments

Partition

Block

Channels

FS(R/X)

ABABABABA 010101010

As explained next, you can dynamically change which blocks of channels are assigned to the partitions.

2.1.3.2 Reassigning Blocks During Reception/Transmission

If you want to use more than 32 channels, you can change which channel blocks are assigned to partitions A and B during the course of a data transfer. However, these changes must be carefully timed. While a partition is being transferred, its the associated block assignment bits cannot be modified, and its associated channel enable register cannot be modified. For example, if block 3 is being transferred and block 3 is assigned to partition A, you cannot modify (R/X)PABLK to assign different channels to partition A, and you cannot modify (R/X)CERA to change the channel configuration for partition A. Several features of the McBSP help you time the reassignment:

- The block of channels currently involved in reception/transmission (the

current block) is reflected in the RCBLK/XCBLK bits. Your program can poll these bits to determine which partition is active. When a partition is not active, it is safe to change its block assignment and channel configuration.

0−1516−310−1516−310−1516−310−1516−310−15

2-4

- At the end of every block (at the boundary of two partitions), an interrupt

can be sent to the CPU. In response to the interrupt, the CPU can then check the RCBLK/XCBLK bits and update the inactive partition.

Figure 2−2 shows an example of reassigning channels throughout a data transfer. In response to a frame-sync pulse, the McBSP alternates between

Multichannel Selection Modes

SPRU061B

Page 71

Channels, Blocks, and Partitions

partitions A and B. Whenever partition B is active, the CPU changes the block assignment for partition A. Whenever, partition A is active, the CPU changes the block assignment for partition B.

Figure 2−2. Reassigning Channel Blocks Throughout a McBSP Data Transfer

2-partition mode. Example with changing block assignments

Partition

Block

Channels

FS(R/X)

ABABABABA 012345670

Block 2 assigned

to partition A

Block 3 assigned

to partition B

2.1.4 Using Eight Partitions

For multichannel selection operation in the receiver and/or the transmitter, you can use eight partitions or two partitions. If you choose the 8-partition mode (RMCME = 1 for reception, XMCME = 1 for transmission), McBSP channels are activated in the following order: A, B, C, D, E, F, G, H. In response to a frame-sync pulse, the receiver or transmitter begins with the channels in partition A and then continues with the other partitions in order until the complete frame has been transferred. When the next frame-sync pulse occurs, the next frame is transferred, beginning with the channels in partition A.

Block 4 assigned

to partition A

Block 5 assigned

to partition B

Block 6 assigned

to partition A

Block 7 assigned

to partition B

0−15112−12796−11180−9564−7948−6332−4716−310−15

Block 0 assigned

to partition A

Block 1 assigned

to partition B

In the 8-partition mode, the (R/X)PABLK and (R/X)PBBLK bits are ignored a nd the 16-channel blocks are assigned to the partitions as shown in Table 2−1 and Table 2−2. These assignments cannot be changed. The tables also show the registers used to control the channels in the partitions.

Multichannel Selection ModesSPRU061B

2-5

Page 72

Channels, Blocks, and Partitions

Table 2−1. Receive Channel Assignment and Control When Eight Receive

Partitions Are Used

Receive

Partition

A Block 0: channels 0 through 15 RCERA B Block 1: channels 16 through 31 RCERB C Block 2: channels 32 through 47 RCERC D Block 3: channels 48 through 63 RCERD E Block 4: channels 64 through 79 RCERE F Block 5: channels 80 through 95 RCERF

G Block 6: channels 96 through 111 RCERG

Assigned Block of Receive Channels

Block 7: channels 112 through 127 RCERH

Table 2−2. Transmit Channel Assignment and Control When Eight Transmit

Partitions Are Used

Transmit Partition

A Block 0: channels 0 through 15 XCERA B Block 1: channels 16 through 31 XCERB

Assigned Block of Transmit Channels

2-6

C Block 2: channels 32 through 47 XCERC D Block 3: channels 48 through 63 XCERD E Block 4: channels 64 through 79 XCERE F Block 5: channels 80 through 95 XCERF

G Block 6: channels 96 through 111 XCERG

Multichannel Selection Modes

Block 7: channels 112 through 127 XCERH

SPRU061B

Page 73

Figure 2−3 shows an example of the McBSP using the 8-partition mode. In response to a frame-sync pulse, the McBSP begins a frame transfer with partition A and then activates B, C, D, E, F, G, and H to complete a 128-word frame.

Figure 2−3. McBSP Data Transfer in the 8-Partition Mode

8-partition mode

Channels, Blocks, and Partitions

Partition

Block

Channels

FS(R/X)

ABCDEFGHA 012345670

2.1.5 Receive Multichannel Selection Mode

The RMCM bit of MCR1 determines whether all channels or only selected channels are enabled for reception. When RMCM = 0, all 128 receive channels are enabled and cannot be disabled. When RMCM = 1, the receive multichannel selection mode is enabled. In this mode:

- Channels can be individually enabled or disabled. The only channels

enabled are those selected in the appropriate receive channel enable registers (RCERs). The way channels are assigned to the RCERs depends on the number of receive channel partitions (2 or 8), as defined by the RMCME bit of MCR1.

- If a receive channel is disabled, any bits received in that channel are

passed only a s f a r a s the receive bu f fer register(s) (RBR(s)). The receiver does not copy the content of the RBR(s) to the DRR(s), and as a result, does not set the receiver ready bit (RRDY). Therefore, no receive FIFO event (REVT) is generated, and if the receiver interrupt mode depends on RRDY (RINTM = 00b), no interrupt is generated.

0−15112−12796−11180−9564−7948−6332−4716−310−15

As an example of how the McBSP behaves in the receive multichannel selection mode, suppose you enable only channels 0, 15, and 39 and that the frame length is 40. The McBSP:

1) Accepts bits shifted in from the DR pin in channel 0

2) Ignores bits received in channels 1–14

3) Accepts bits shifted in from the DR pin in channel 15

4) Ignores bits received in channels 16–38

5) Accepts bits shifted in from the DR pin in channel 39

Multichannel Selection ModesSPRU061B

2-7

Page 74

Channels, Blocks, and Partitions

2.1.6 Transmit Multichannel Selection Modes

The XMCM bits of XCR2 determine whether all channels or only selected channels are enabled and unmasked for transmission. More details on enabling and masking are in section 2.1.7. The McBSP has three transmit multichannel selection modes (XMCM = 01b, XMCM = 10b, and XMCM = 11b), which are described in the following table:

Table 2−3. Selecting a Transmit Multichannel Selection Mode With the XMCM Bits

XMCM Transmit Multichannel Selection Mode

00b No transmit multichannel selection mode is on. All channels are

enabled and unmasked. No channels can be disabled or masked.

01b All channels are disabled unless they are selected in the

appropriate transmit channel enable registers (XCERs) If enabled, a channel in this mode is also unmasked.

The XMCME bit of MCR2 determines whether 32 channels or 128 channels are selectable in XCERs.

10b All channels are enabled, but they are masked unless they are

selected in the appropriate transmit channel enable registers (XCERs).

The XMCME bit of MCR2 determines whether 32 channels or 128 channels are selectable in XCERs.

2-8

11b

Multichannel Selection Modes

This mode is used for symmetric transmission and reception. All channels are disabled for transmission unless they are enabled

for reception in the appropriate receive channel enable registers (RCERs). Once enabled, they are masked unless they are also selected in the appropriate transmit channel enable registers (XCERs).

The XMCME bit of MCR2 determines whether 32 channels or 128 channels are selectable in RCERs and XCERs.

SPRU061B

Page 75

As an example of how the McBSP behaves in a transmit multichannel selection mode, suppose that XMCM = 01b (all channels disabled unless individually enabled) and that you have enabled only channels 0, 15, and 39. Suppose also that the frame length is 40. The McBSP …

1) Shifts data to the DX pin in channel 0

2) Places the DX pin in the high impedance state in channels 1–14

3) Shifts data to the DX pin in channel 15

4) Places the DX pin in the high impedance state in channels 16–38

5) Shifts data to the DX pin in channel 39

2.1.7 Disabling/Enabling Versus Masking/Unmasking

For transmission, a channel can be:

- Enabled and unmasked (transmission can begin and can be completed)

- Enabled but masked (transmission can begin but cannot be completed)

- Disabled (transmission cannot occur)

The following definitions explain the channel control options:

Channels, Blocks, and Partitions

Enabled channel A channel that can begin transmission by passing

data from the data transmit register(s) (DXR(s)) to the transmit shift registers (XSR(s)).

Masked channel A channel that cannot complete transmission. The

DX pin is held in the high impedance state; data cannot be shifted out on the DX pin.

In systems where symmetric transmit and receive provides software benefits, this feature allows transmit channels to be disabled on a shared serial bus. A similar feature is not needed for reception because multiple receptions cannot cause serial bus contention.

Disabled channel A channel that is not enabled. A disabled channel is

also masked. Because no DXR-to-XSR copy occurs, the XRDY bit

of SPCR2 is not set. Therefore, no transmit FIFO event (XEVT) is generated, and if the transmit interrupt mode depends on XRDY (XINTM = 00b in SPCR2), no interrupt is generated.

The XEMPTY

bit of SPCR2 is not affected.

Unmasked channel A channel that is not masked. Data in the XSR(s) is

shifted out on the DX pin.

Multichannel Selection ModesSPRU061B

2-9

Page 76

Channels, Blocks, and Partitions

2.1.8 Activity on McBSP Pins for Different Values of XMCM

Figure 2−4 shows the activity on the McBSP pins for the various XMCM values. In all cases, the transmit frame is configured as follows:

- XPHASE = 0: Single-phase frame (required for multichannel selection

modes)

- XFRLEN1 = 0000011b: 4 words per frame

- XWDLEN1 = 000b: 8 bits per word

- XMCME = 0: 2-partition mode (only partitions A and B used)

In the case where XMCM = 11b, transmission and reception are symmetric, which means the corresponding bits for the receiver (RPHASE, RFRLEN1, RWDLEN1, and RMCME) must have the same values as XPHASE, XFRLEN1, and XWDLEN1, respectively.

In the figure, the arrows showing where the various events occur are only sample indications. Wherever possible, there is a time window in which these events can occur.

Figure 2−4. Activity on McBSP Pins for the Possible Values of XMCM

2-10

Multichannel Selection Modes

SPRU061B

Page 77

(a) XMCM = 00b: All channels enabled and unmasked

Internal FSX

Channels, Blocks, and Partitions

XRDY

Write to DXR1(W1)

DXR1 to XSR1 copy(W0)

DXR1 to XSR1 copy(W1)

(b) XMCM = 01b, XPABLK= 00b, XCERA = 1010b: Only channels 1 and 3 enabled and unmasked

Internal FSX

XRDY

DXR1 to XSR1 copy(W1)

Internal FSX

XRDY

Write to DXR1(W1)

DXR1 to XSR1 copy(W0)

DXR1 to XSR1 copy(W1)

DXR1 to XSR1 copy(W2)

Write to DXR1(W2)

DXR1 to XSR1 copy(W2)

Write to DXR1(W2)

Write to DXR1(W3)

DXR1 to XSR1 copy(W3)

DXR1 to XSR1 copy(W3)Write to DXR1(W3)

Write to DXR1(W3)

DXR1 to XSR1 copy(W3)

W3W2W1W0

(d) XMCM = 11b, RPABLK = 00b, XPABLK = X, RCERA = 1010b, XCERA = 1000b: Receive channels: 1 and 3 enabled; transmit channels: 1 and 3 enabled, but only 3 unmasked

Internal FS(R/X)

RRDY

Read from DRR1(W3)

RBR1 to DRR1 copy (W3)

XRDY

DXR1 to XSR1 copy (W1)

Read from DRR1(W1)

RBR1 to DRR1 copy (W1)

RBR1 to DRR1 (W3)

DXR1 to XSR1 copy (W3)Write to DXR1(W3)

Multichannel Selection ModesSPRU061B

2-11

Page 78

Channels, Blocks, and Partitions

2.1.9 Using Interrupts Between Block Transfers

When a multichannel selection mode is used, an interrupt request can be sent to the CPU at the end of every 16-channel block (at the boundary between partitions and at the end of the frame). In the receive multichannel selection mode, a receive interrupt (RINT) request is generated at the end of each block transfer if RINTM = 01b. In any of the transmit multichannel selection modes, a transmit interrupt (XINT) request is generated at the end of each block transfer if XINTM = 01b. When RINTM/XINTM = 1b, no interrupt is generated unless a multichannel selection mode is on.

This type of interrupt is especially helpful if you are using the 2-partition mode and you want to know when you can assign a different block of channels to partition A or B.

2-12

Multichannel Selection Modes

SPRU061B

Page 79

2.2 A-bis Mode

A-bis Mode

In the A-bis mode (ABIS = 1 in SPCR1), the McBSP can receive and transmit up to 1024 bits on a PCM link. The receive section can extract all 1024 bits from a 1024-bit PCM frame according to a given bit-enable pattern, and generate an interrupt to the CPU when 16 enabled bits have been compacted into a word in DRR1, or when a receive frame is complete. In addition, the transmit section can expand up to 1024 bits into a 1024-bit PCM frame at a specific position, according to a given bit-enable pattern, and generate an interrupt when 16 enabled bits have been transmitted or a transmit frame is complete.

The bit-enable patterns are specified with channel enable registers A and B (RCERA and RCERB for reception, XCERA and XCERB for transmission). These registers have a different function than in the multichannel selection modes (described in section 2.1). Instead of indicating which channels will be enabled, these registers indicate which bits in the data stream will be enabled. A 1 in a given position in the (R/X)CER(A/B) register enables a corresponding bit in the receive/transmit data stream.

The A-bis mode requires a word length of 16 bits (for reception: RWDLEN1 = 010b in RCR1, for transmission: XWDLEN1 = 010b in XCR1). Otherwise, operation in the A-bis mode is undetermined.

2.2.1 A-bis Mode Receive Operation

In the A-bis mode, bits that are not enabled in the RCERA and RCERB registers are ignored and are not compacted in the receiver. Bits that are enabled are received and compacted. When 16 enabled bits have been received, the received word is copied from RSR1 to DRR1 and the McBSP generates an interrupt to the CPU. RCERA and RCERB alternate specifying the receive masking pattern for each of the 16 receive clocks. Figure 2−5 shows an example bit sequence for the receiver (in the figure, − indicates that the bit on the DR pin is ignored and thus is not passed to DRR1).

Figure 2−5. A-bis Mode Receive Operation

RCERA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RCERB 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 DR pin 1 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 DRR1 − 0 − 1 − 1 − 1 − 0 − 1 0 − − 1 − − 1 − − 1 1 0 − − 0 − − 0 1 1 75E3h

Note: − indicates that the bit on the DR pin is ignored and thus is not passed to DRR1.

Multichannel Selection ModesSPRU061B

2-13

Page 80

A-bis Mode

2.2.2 A-bis Mode Transmit Operation

In the A-bis mode, only bits that are enabled in the XCERA and XCERB registers are transmitted out from the DX pin. Bits that are not enabled are not transmitted, and the DX pin is in the high-impedance state during that clock cycle. XCERA and XCERB alternate specifying the bit-enable pattern for each 16 clock cycles. When 16 enabled have been shifted out, the McBSP generates an interrupt to the CPU. Figure 2−6 shows an example bit sequence for the transmitter (in the figure, z indicates the high-impedance state).

Figure 2−6. A-bis Mode Transmit Operation

XCERA 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 XCERB 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 DXR1 1 0 1 1 0 1 0 1 0 0 0 1 1 1 1 1 1 0 1 1 0 1 1 0 1 1 0 0 0 0 0 0 DX pin z 0 1 1 0 1 z z z 0 0 z z 1 1 1 z z 1 1 z z z 0 1 z z z 0 0 z z

Note: z indicates the high-impedance state.

2-14

Multichannel Selection Modes

SPRU061B

Page 81

2.3 SPI Protocol

The SPI protocol is a master-slave configuration with one master device and one or more slave devices. The interface consists of the following four signals:

- Serial data input (also referred to as Master In − Slave Out, or MISO)

- Serial data output (also referred to as Master Out − Slave In, or MOSI)

- Shift-clock (also referred to as SCK)

- Slave-enable signal (also referred to as SS)

A typical SPI interface with a single slave device is shown in Figure 2−7.

Figure 2−7. Typical SPI Interface

SPI Protocol

SPI-compliant

master

SCK

MOSI

MISO

SPI-compliant

slave

SCK

MOSI

MISO

The master device controls the flow of communication by providing shift-clock and slave-enable signals. The slave-enable signal is an optional active-low signal that enables the serial data input and output of the slave device (device not sending out the clock).

In the absence of a dedicated slave-enable signal, communication between the master and slave is determined by the presence or absence of an active shift-clock. In such a configuration, the slave device must remain enabled at all times, and multiple slaves cannot be used.

2.3.1 Clock Stop Mode

The clock stop mode of the McBSP provides compatibility with the SPI protocol. When the McBSP is configured in clock stop mode, the transmitter and receiver are internally synchronized, so that the McBSP functions as an SPI master or slave device. The transmit clock signal (CLKX) corresponds to the serial clock signal (SCK) of the SPI protocol, while the transmit frame-synchronization signal (FSX) is used as the slave-enable signal (SS

Multichannel Selection ModesSPRU061B

2-15

Page 82

SPI Protocol

The receive clock signal (CLKR) and receive frame-synchronization signal (FSR) are not used in the clock stop mode because these signals are internally connected to their transmit counterparts, CLKX and FSX.

2.3.2 Bits Used to Enable and Configure the Clock Stop Mode

The bits required to configure the McBSP as an SPI device are introduced in Table 2−4. Table 2−5 shows how the various combinations of the CLKSTP bit and the polarity bits CLKXP and CLKRP create four possible clock stop mode configurations. The timing diagrams in section 2.3.3 show the effects of CLKSTP, CLKXP, and CLKRP.

Table 2−4. Bits Used to Enable and Configure the Clock Stop Mode

Bit Field Description

CLKSTP bits of SPCR1 Use these bits to enable the clock stop mode and to select one of two

timing variations. (See also Table 2−5.)

CLKXP bit of PCR This bit determines the polarity of the CLKX signal. (See also

Table 2−5.)

CLKRP bit of PCR This bit determines the polarity of the CLKR signal. (See also

Table 2−5.)

CLKXM bit of PCR This bit determines whether CLKX is an input signal (McBSP as slave)

or an output signal (McBSP as master). XPHASE bit of XCR2 You must use a single-phase transmit frame (XPHASE = 0). RPHASE bit of RCR2 You must use a single-phase receive frame (RPHASE = 0). XFRLEN1 bits of XCR1 You must use a transmit frame length of 1 serial word (XFRLEN1 = 0). RFRLEN1 bits of RCR1 You must use a receive frame length of 1 serial word (RFRLEN1 = 0). XWDLEN1 bits of XCR1 The XWDLEN1 bits determine the transmit packet length. XWDLEN1

must be equal to RWDLEN1 because in the clock stop mode, the

McBSP transmit and receive circuits are synchronized to a single clock. RWDLEN1 bits of RCR1

The RWDLEN1 bits determine the receive packet length. RWDLEN1

must be equal to XWDLEN1 because in the clock stop mode, the

McBSP transmit and receive circuits are synchronized to a single clock.

2-16

Multichannel Selection Modes

SPRU061B

Page 83

Table 2−5. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme

Bit Settings Clock Scheme

SPI Protocol

CLKSTP = 00b or 01b CLKXP = 0 or 1 CLKRP = 0 or 1

CLKSTP = 10b CLKXP = 0 CLKRP = 0

CLKSTP = 11b CLKXP = 0 CLKRP = 1

CLKSTP = 10b CLKXP = 1 CLKRP = 0

CLKSTP = 11b CLKXP = 1 CLKRP = 1

Clock stop mode disabled. Clock enabled for non-SPI mode.

Low inactive state without delay: The McBSP transmits data on the rising edge of CLKX and receives data on the falling edge of CLKR.

Low inactive state with delay: The McBSP transmits data one-half cycle ahead of the rising edge of CLKX and receives data on the rising edge of CLKR.

High inactive state without delay: The McBSP transmits data on the falling edge of CLKX and receives data on the rising edge of CLKR.

High inactive state with delay: The McBSP transmits data one-half cycle ahead of the falling edge of CLKX and receives data on the falling edge of CLKR.

2.3.3 Clock Stop Mode Timing Diagrams

The timing diagrams for the four possible clock stop mode configurations are shown here. Notice that the frame-synchronization signal used in clock stop mode is active throughout the entire transmission as a slave-enable signal. Although the timing diagrams show 8-bit transfers, the packet length can be set to 8, 12, 16, 20, 24, or 32 bits per packet. The receive packet length is selected with the RWDLEN1 bits of RCR1, and the transmit packet length is selected with the XWDLEN1 bits of XCR1. For clock stop mode, the values of RWDLEN1 and XWDLEN1 must be the same because the McBSP transmit and receive circuits are synchronized to a single clock.

Note:

Even if multiple words are consecutively transferred, the CLKX signal is always stopped and the FSX signal returns to the inactive state after a packet transfer. When consecutive packet transfers are performed, this leads to a minimum idle time of two bit-periods between each packet transfer.

Multichannel Selection ModesSPRU061B

2-17

Page 84

SPI Protocol

БББББББББББББББББББББББ

Figure 2−8. SPI Transfer With CLKSTP = 10b (no clock delay), CLKXP = 0, CLKRP = 0

CLKX/SCK

DX or DR/MOSI

(from master)

DX or DR/MISO

(from slave)

B3B4B5B6B7

B3 B0B5B6

B1B2

FSX/SS

Notes: 1) If the McBSP is the SPI master (CLKXM = 1), MOSI = DX. If the McBSP is the SPI

slave (CLKXM = 0), MOSI = DR.

2) If the McBSP is the SPI master (CLKXM = 1), MISO = DR. If the McBSP is the SPI slave (CLKXM = 0), MISO = DX.

Figure 2−9. SPI Transfer With CLKSTP = 11b (clock delay), CLKXP = 0, CLKRP = 1

CLKX/SCK

DX or DR/MOSI

(from master)

DX or DR/MISO

(from slave)

FSX/SS

B3B4B5B6B7

Notes: 1) If the McBSP is the SPI master (CLKXM = 1), MOSI = DX. If the McBSP is the SPI

slave (CLKXM = 0), MOSI = DR.

2) If the McBSP is the SPI master (CLKXM = 1), MISO = DR. If the McBSP is the SPI slave (CLKXM = 0), MISO = DX.

B3 B0B5B6

B1B2

Figure 2−10. SPI Transfer With CLKSTP = 10b (no clock delay), CLKXP = 1, CLKRP = 0

CLKX/SCK

DX or DR/MOSI

(from master)

DX or DR/MISO

(from slave)

FSX/SS

2-18

Multichannel Selection Modes

B6B7

Notes: 1) If the McBSP is the SPI master (CLKXM = 1), MOSI = DX. If the McBSP is the SPI

slave (CLKXM = 0), MOSI = DR.

2) If the McBSP is the SPI master (CLKXM = 1), MISO = DR. If the McBSP is the SPI slave (CLKXM = 0), MISO = DX.

B4B5B6

B1B2B4

SPRU061B

Page 85

SPI Protocol

Figure 2−11.SPI Transfer With CLKSTP = 11b (clock delay), CLKXP = 1, CLKRP = 1

CLKX/SCK

DX or DR/MOSI

(from master)

DX or DR/MISO

(from slave)

FSX/SS

Notes: 1) If the McBSP is the SPI master (CLKXM = 1), MOSI=DX. If the McBSP is the SPI

slave (CLKXM = 0), MOSI = DR.

2) If the McBSP is the SPI master (CLKXM = 1), MISO=DR. If the McBSP is the SPI slave (CLKXM = 0), MISO = DX.

B5B6

B3B4

2.3.4 Procedure for Configuring a McBSP for SPI Operation

To configure the McBSP for SPI master or slave operation:

1) Place the transmitter and receiver in reset. Clear the transmitter reset bit (XRST

transmitter. Clear the receiver reset bit (RRST = 0) in SPCR1, to reset the receiver.

2) Place the sample rate generator in reset. Clear the sample rate generator reset bit (GRST

the sample rate generator.

= 0) in SPCR2, to reset the

B0B1B2

B1B2B4

= 0) in SPCR2, to reset

3) Program registers that affect SPI operation. Program the appropriate McBSP registers to configure the McBSP for

proper operation as an SPI master or an SPI slave. For a list of important bits settings, see one of the following topics:

- McBSP as the SPI Master (page 2-20)

- McBSP as an SPI Slave (page 2-22)

4) Enable the sample rate generator. To release the sample rate generator from reset, set the sample rate

generator reset bit (GRST

= 1) in SPCR2.

Make sure that during the write to SPCR2, you only modify GRST Otherwise, you will modify the McBSP configuration you selected in the previous step.

5) Enable the transmitter and receiver.

Multichannel Selection ModesSPRU061B

2-19

Page 86

SPI Protocol

After the sample rate generator is released from reset, wait two sample rate generator clock periods for the McBSP logic to stabilize.

If the CPU services the McBSP transmit and receive buffers, then you can immediately enable the transmitter (XRST receiver (RRST

= 1 in SPCR1).

= 1 in SPCR2) and enable the

The FIFO has to be configured first if it must write into the McBSP transmit buffer or read from the McBSP receive buffer. After the FIFO has been configured, make XRST = 1 and RRST

= 1.

Note: In either case, make sure you only change XRST you write to SPCR2 and SPCR1. Otherwise, you will modify the bit settings you selected earlier in this procedure.

After the transmitter and receiver are released from reset, wait two sample rate generator clock periods for the McBSP logic to stabilize.

6) If necessary, enable the frame-sync logic of the sample rate generator. After the required data acquisition setup is done (DXR[1/2] is loaded with

data), set FRST

= 1 if an internally generated frame-sync pulse is required

(that is, if the McBSP is the SPI master).

2.3.5 McBSP as the SPI Master

An SPI interface with the McBSP used as the master is shown in Figure 2−12. When the McBSP is configured as a master, the transmit output signal (DX) is used as the MOSI signal of the SPI protocol, and the receive input signal (DR) is used as the MISO signal.

Figure 2−12. SPI Interface With McBSP as Master

McBSP-master

and RRST when

SPI-compliant

slave

2-20

Multichannel Selection Modes

CLKX

FSX

SCK

MOSI

MISO

SPRU061B

Page 87

SPI Protocol

The register bit values required to configure the McBSP as a master are listed in the following table. After the table are more details about the configuration requirements.

Table 2−6. Bit Values Required to Configure the McBSP as an SPI Master

Required Bit Setting Description

CLKSTP = 10b or 11b The clock stop mode (without or with a clock delay) is selected. CLKXP = 0 or 1 The polarity of CLKX as seen on the CLKX pin is positive (CLKXP = 0) or

negative (CLKXP = 1).

CLKRP = 0 or 1 The polarity of CLKR as seen on the CLKR pin is positive (CLKRP = 0) or

negative (CLKRP = 1).

CLKXM = 1 The CLKX pin is an output pin driven by the internal sample rate generator.

Because CLKSTP is equal to 10b or 11b, CLKR is driven internally by CLKX.

SCLKME = 0 CLKSM = 1

CLKGDV is a value from 0 to 255

FSXM = 1 The FSX pin is an output pin driven according to the FSGM bit. FSGM = 0 The transmitter drives a frame-sync pulse on the FSX pin every time data is

FSXP = 1 The FSX pin is active low. XDATDLY = 01b

RDATDLY = 01b

The clock generated by the sample rate generator (CLKG) is derived from the CPU clock.

CLKGDV defines the divide down value for CLKG.

transferred from DXR1 to XSR1.

This setting provides the correct setup time on the FSX signal.

When the McBSP functions as the SPI master, it controls the transmission of data by producing the serial clock signal. The clock signal on the CLKX pin is enabled only during packet transfers. When packets are not being transferred, the CLKX pin remains high or low depending on the polarity used.

For SPI master operation, the CLKX pin must be configured as an output. The sample rate generator is then used to derive the CLKX signal from the CPU clock. The clock stop mode internally connects the CLKX pin to the CLKR signal so that no external signal connection is required on the CLKR pin, and both the transmit and receive circuits are clocked by the master clock (CLKX).

The data delay parameters of the McBSP (XDA TDLY and RDA TDLY) must be set to 1 for proper SPI master operation. A data delay value of 0 or 2 is undefined in the clock stop mode.

The McBSP can also provide a slave-enable signal (SS

) on the FSX pin. If a

slave-enable signal is required, the FSX pin must be configured as an output,

Multichannel Selection ModesSPRU061B

2-21

Page 88

SPI Protocol

and the transmitter must be configured so that a frame-sync pulse is generated automatically each time a packet is transmitted (FSGM = 0). The polarity of the FSX pin is programmable high or low; however, in most cases the pin should be configured active-low.

When the McBSP is configured as described for SPI-master operation, the bit fields for frame-sync pulse width (FWID) and frame-sync period (FPER) are overridden, and custom frame-sync waveforms are not allowed. To see the resulting waveform produced on the FSX pin, see the timing diagrams in section 2.3.3. The signal becomes active before the first bit of a packet transfer, and remains active until the last bit of the packet is transferred. After the packet transfer is complete, the FSX signal returns to the inactive state.

2.3.6 McBSP as an SPI Slave

An SPI interface with the McBSP used as a slave is shown in Figure 2−13. When the McBSP is configured as a slave, DX is used as the MISO signal, and DR is used as the MOSI signal.

Figure 2−13. SPI With McBSP Configured as Slave

McBSP-slave

CLKX

FSX

SPI-compliant

master

SCK

MISO

MOSI

The register bit values required to configure the McBSP as a slave are listed in the following table. After the table are more details about the configuration requirements.

2-22

Multichannel Selection Modes

SPRU061B

Page 89

SPI Protocol

Table 2−7. Bit Values Required to Configure the McBSP as an SPI Slave

Required Bit Setting Description

CLKSTP = 10b or 11b The clock stop mode (without or with a clock delay) is selected. CLKXP = 0 or 1 The polarity of CLKX as seen on the CLKX pin is positive (CLKXP = 0) or

negative (CLKXP = 1).

CLKRP = 0 or 1 The polarity of CLKR as seen on the CLKR pin is positive (CLKRP = 0) or

negative (CLKRP = 1).

CLKXM = 0 The CLKX pin is an input pin, so that it can be driven by the SPI master.

Because CLKSTP = 10b or 11b, CLKR is driven internally by CLKX.

SCLKME = 0 CLKSM = 1

CLKGDV = 1 The sample rate generator divides the CPU clock by 2 before generating

FSXM = 0 The FSX pin is an input pin, so that it can be driven by the SPI master. FSXP = 1 The FSX pin is active low. XDATDLY = 00b

RDATDLY = 00b

The clock generated by the sample rate generator (CLKG) is derived from the CPU clock. (The sample rate generator is used to synchronize the McBSP logic with the externally-generated master clock.)

CLKG.

These bits must be 0s for SPI slave operation.

When the McBSP is used as an SPI slave, the master clock and slave-enable signals are generated externally by a master device. Accordingly, the CLKX and FSX pins must be configured as inputs. The CLKX pin is internally connected to the CLKR signal, so that both the transmit and receive circuits of the McBSP are clocked by the external master clock. The FSX pin is also internally connected to the FSR signal, and no external signal connections are required on the CLKR and FSR pins.

Although the CLKX signal is generated externally by the master and is asynchronous to the McBSP, the sample rate generator of the McBSP must be enabled for proper SPI slave operation. The sample rate generator should be programmed to its maximum rate of half the CPU clock rate. The internal sample rate clock is then used to synchronize the McBSP logic to the external master clock and slave-enable signals.

The McBSP requires an active edge of the slave-enable signal on the FSX input for each transfer. This means that the master device must assert the slave-enable signal at the beginning of each transfer, and deassert the signal after the completion of each packet transfer; the slave-enable signal cannot remain active between transfers.

Multichannel Selection ModesSPRU061B

2-23

Page 90

SPI Protocol

The data delay parameters of the McBSP must be set to 0 for proper SPI slave operation. A value of 1 or 2 is undefined in the clock stop mode.

2-24

Multichannel Selection Modes

SPRU061B

Page 91

Chapter 3



This chapter explains how to configure the receiver/transmitter and program the registers.

Topic Page

3.1 Receiver Configuration 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Transmitter Configuration 3-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Configure the Receiver and TransmitterSPRU061B

3-1

Page 92

Receiver Configuration

3.1 Receiver Configuration

To configure the McBSP receiver, perform the following procedure:

1) Place the McBSP receiver in reset (see section 3.1.2).

2) Program the McBSP registers for the desired receiver operation (see section 3.1.1).

3) Take the receiver out of reset (see section 3.1.2).

3.1.1 Programming the McBSP Registers for the Desired Receiver Operation

The following is a list of important tasks to be performed when you are configuring the McBSP receiver. Each task corresponds to one or more McBSP register bit fields. Note that in the list, SRG is an abbreviation for sample rate generator.

- Global behavior: J Set the receiver pins to operate as McBSP pins

J Enable/disable the digital loopback mode J Enable/disable the clock stop mode J Enable/disable the receive multichannel selection mode J Enable/disable the A-bis mode

- Data behavior: J Choose 1 or 2 phases for the receive frame

J Set the receive word length(s) J Set the receive frame length J Enable/disable the receive frame-sync ignore function J Set the receive companding mode J Set the receive data delay J Set the receive sign-extension and justification mode J Set the receive interrupt mode

- Frame-sync behavior: J Set the receive frame-sync mode

J Set the receive frame-sync polarity J Set the SRG frame-sync period and pulse width

- Clock behavior: J Set the receive clock mode

J Set the receive clock polarity J Set the SRG clock divide-down value J Set the SRG clock synchronization mode J Set the SRG clock mode (choose an input clock) J Set the SRG input clock polarity

3-2

Configure the Receiver and Transmitter

SPRU061B

Page 93

3.1.2 Resetting and Enabling the Receiver

The first step of the receiver configuration procedure is to reset the receiver, and the last step is to enable the receiver (to take it out of reset).

The serial port can be reset in the following two ways:

Receiver Configuration

1) A DSP reset (RESET

signal driven low) places the receiver, transmitter, and sample rate generator in reset. When the device reset is removed (RESET

signal released), GRST = FRST = RRST = XRST = 0, keeping

the entire serial port in the reset state.

2) The serial port transmitter and receiver can be reset directly using the RRST and XRST bits in the serial port control registers. The sample rate generator can be reset directly using the GRST bit in SPCR2.

To get this result ... Use this bit ...

Enable the receiver RRST (bit 0 of the SPCR1 register) set to 1 Disable the receiver (the reset

state) Reset the sample-rate generator GRST (bit 6 of the SPCR2 register) set to 0 Enable the sample-rate generator GRST set to 1 Reset the frame-sync logic FRST (bit 7 of the SPCR2 register) = 0 Enable the frame-sync logic

RRST set to 0

FRST = 1

For details on the Serial Port Control Register 1 (SPCR1) and SPCR2 see Figure 6−3 (page 6-4) and Figure 6−4 (page 6-6). Table 3−1 shows the state of McBSP pins when the serial port is reset due to a DSP reset and a direct receiver/transmitter reset.

Configure the Receiver and TransmitterSPRU061B

3-3

Page 94

Receiver Configuration

Table 3−1. Reset State of Each McBSP Pin

Possible

DR I Input Input

CLKR I/O/Z Input Known state

FSR I/O/Z Input Known state if Input; FSRP inactive state if output

DX O/Z High impedance High impedance

CLKX I/O/Z Input Known state if Input; CLKX running if output

FSX

Note: In Possible State(s) column, I = Input, O = Output, Z = High impedance

State(s)

I/O/Z Input Known state if Input; FSXP inactive state if output

State Forced By

DSP Reset

State Forced By Receiver/Transmitter Reset

Receiver Reset (RRST = 0 and GRST = 1)

if Input; CLKR running if output

Transmitter Reset (XRST = 0 and GRST = 1)

For more details about McBSP reset conditions and effects, see Resetting and Initializing a McBSP on page 4-3.

To get this result… Set this bit...

Set the receiver pins to operate as McBSP pins in the reset state.

RIOEN (bit 12 of the PCR register) set to 0

0 is the only possible setting for this bit. 1 is a reserved function and must not

be used. Disable the digital-loopback mode DLB (bit 15 of the SPCR1 register) Enable the digital-loopback mode DLB (bit 15 of the SPCR1 register)

In the digital loopback mode, the receive signals are connected internally through multiplexers to the corresponding transmit signals, as shown in Table 3−2. This mode allows testing of serial port code with a single DSP device; the McBSP receives the data it transmits.

Table 3−2. Receive Signals Connected to Transmit Signals in Digital Loopback Mode

Is fed internally by this

transmit signal …

CLKX (transmit clock)

SPRU061B

3-4

This receive signal …

DR (receive data) DX (transmit data) FSR (receive frame synchronization) FSX (transmit frame synchronization) CLKR (receive clock)

Configure the Receiver and Transmitter

Page 95

3.1.3 Clock Stop Mode

The CLKSTP bits in the serial port control registers determine whether the clock stop mode is on.

The clock stop mode supports the SPI master-slave protocol. If you will not be using the SPI protocol, you can clear the CLKSTP bits (12:11 in SPCR1) to disable the clock stop mode.

In the clock stop mode, the clock stops at the end of each data transfer. At the beginning of each data transfer, the clock starts immediately (CLKSTP = 10b) or after a half-cycle delay (CLKSTP = 11b). The CLKXP bit determines whether the starting edge of the clock on the CLKX pin is rising or falling. The CLKRP bit determines whether receive data is sampled on the rising or falling edge of the clock shown on the CLKR pin.

Table 3−3 summarizes the impact of CLKSTP, CLKXP, and CLKRP on serial port operation. Note that in the clock stop mode, the receive clock is tied internally to the transmit clock, and the receive frame-sync signal is tied internally to the transmit frame-sync signal.

Receiver Configuration

Table 3−3. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme

Bit Settings Clock Scheme

CLKSTP = 00b or 01b CLKXP = 0 or 1 CLKRP = 0 or 1

CLKSTP = 10b CLKXP = 0 CLKRP = 0

CLKSTP = 11b CLKXP = 0 CLKRP = 1

CLKSTP = 10b CLKXP = 1 CLKRP = 0

CLKSTP = 11b CLKXP = 1 CLKRP = 1

Clock stop mode disabled. Clock enabled for non-SPI mode.

Low inactive state without delay: The McBSP transmits data on the rising edge of CLKX and receives data on the falling edge of CLKR.

Low inactive state with delay: The McBSP transmits data one-half cycle ahead of the rising edge of CLKX and receives data on the rising edge of CLKR.

High inactive state without delay: The McBSP transmits data on the falling edge of CLKX and receives data on the rising edge of CLKR.

High inactive state with delay: The McBSP transmits data one-half cycle ahead of the falling edge of CLKX and receives data on the falling edge of CLKR.

Configure the Receiver and TransmitterSPRU061B

3-5

Page 96

Receiver Configuration

3.1.4 Receive Multichannel Selection and A-bis Modes

The RMCM bit determines whether the receive multichannel selection mode is on. For more details on this mode, see Receive Multichannel Selection Mode on page 2-7. For more details on the multichannel control registers, see Section 6.6 (page 6-17).

For more details on A-bis mode, see page 2-13. If A-bis mode is enabled, individual bits can be enabled or disabled during reception and transmission. For transmission, the bits are controlled by transmit channel enable registers A and B (XCERA and XCERB). For reception, the bits are controlled by receive channel enable registers A and B (RCERA and RCERB).

To get this result… Use this bit …

Enable multichannel selection mode RMCM bit in MCR1 to 1 (individual

channels can be enabled or disabled

with this setting) Disable multichannel selection mode Set RMCM to 0 so that all 128 channels

are enabled Enable A-bis mode ABIS bit (number 6 in SPCR1) set to 1 Disable A-bis mode

3.1.5 Choose 1 or 2 Phases for the Receive Frame

The RPHASE bit in the Receive Control Register 2 (RCR2) determines whether the receive data frame has one or two phases. See Section 6.3 for details of RCR1 and RCR2.

To get this result … Use this bit…

Set receive frame to single phase RPHASE bit in Receive FRCR2 set to 0 Set receive frame to dual-phase frame RPHASE bit in RCR2 set to 1

3.1.5.1 Set the Receive Word Length(s)

The RWDLEN1 and RWDLEN2 bit fields determine how many bits are in each serial word in phase 1 and in phase 2, respectively, of the receive data frame.

ABIS set to 0

3-6

Configure the Receiver and Transmitter

SPRU061B

Page 97

Receiver Configuration

To get this result …

Specify the length of every serial word in phase 1 of the receive frame

Use this bit…

Set RWDLEN1 (bits 7:5 of RCR1) to one of the following:

000 8 bits 001 12 bits 010 16 bits 011 20 bits 100 24 bits 101 32 bits 11x Reserved

Each frame can have one or two phases, depending on the value that you load into the RPHASE bit. If a single-phase frame is selected, RWDLEN1 selects the length for every serial word received in the frame. If a dual-phase frame is selected, RWDLEN1 determines the length of the serial words in phase 1 of the frame, and RWDLEN2 determines the word length in phase 2 of the frame with the same bit settings. For details on the receive control registers, see Section 6.3 (page 6-8).

3.1.5.2 Set the Receive Frame Length

The RFRLEN1 and RFRLEN2 bit fields determine how many serial words are in phase 1 and in phase 2, respectively, of the receive data frame.

To get this result … Use this bit…

Set receive frame length Set RFRLEN1 (bits 14:8 of RCR1) to

The receive frame length is the number of serial words in the receive frame. Each frame can have one or two phases, depending on value that you load into the RPHASE bit.

one of the following: 000 0000 1 word in phase 1 000 0001 2 words in phase 1 .

. .

111 1111 128 words in phase 1

Configure the Receiver and TransmitterSPRU061B

3-7

Page 98

Receiver Configuration

If a single-phase frame is selected (RPHASE = 0), the frame length is equal to the length of phase 1. If a dual-phase frame is selected (RPHASE = 1), the frame length is the length of phase 1 plus the length of phase 2:

The 7-bit RFRLEN fields allow up to 128 words per phase. See Table 3−4 for a summary of how to calculate the frame length. This length corresponds to the number of words or logical time slots or channels per frame-synchronization pulse.

Note: Program the RFRLEN fields with [w minus 1], where w represents the number of words per phase. For the example, if you want a phase length of 128 words in phase 1, load 127 into RFRLEN1.

Table 3−4. How to Calculate the Length of the Receive Frame

RPHASE RFRLEN1 RFRLEN2 Frame Length

0 0 ≤ RFRLEN1 ≤ 127 Don’t care (RFRLEN1 + 1) words 1 0 ≤ RFRLEN1 ≤ 127 0 ≤ RFRLEN2 ≤ 127 (RFRLEN1 + 1) + (RFRLEN2 + 1) words

3.1.5.3 Enable/Disable the Receive Frame-Sync Ignore Function

The RFIG bit controls the receive frame-sync ignore function.

If there is an unexpected receive frame-sync pulse …

Restart the frame transfer Set RFIG (bit 2 in RCR2) to 0 Ignore the unexpected pulses Set RFIG to 1

Use this bit…

If a frame-synchronization (frame-sync) pulse starts the transfer of a new frame before the current frame is fully received, this pulse is treated as an unexpected frame-sync pulse.

When RFIG = 1, reception continues, ignoring the unexpected frame-sync pulses.

When RFIG = 0, an unexpected FSR pulse causes the McBSP to discard the contents of RSR[1,2] in favor of the new incoming data. Therefore, if RFIG = 0 and an unexpected frame-sync pulse occurs, the serial port:

1) Aborts the current data transfer

2) Sets RSYNCERR in SPCR1 to 1

3) Begins the transfer of a new data word For more details about the frame-sync error condition, see Unexpected

Receive Frame-Sync Pulse on page 1-40.

3-8

Configure the Receiver and Transmitter

SPRU061B

Page 99

3.1.5.4 Examples Showing the Effects of RFIG

Figure 3−1 shows an example in which word B is interrupted by an unexpected frame-sync pulse when (R/X)FIG = 0. In the case of reception, the reception of B is aborted (B is lost), and a new data word (C in this example) is received after the appropriate data delay. This condition is a receive synchronization error, and thus sets the RSYNCERR bit.

Figure 3−1. Unexpected Frame-Sync Pulse With (R/X)FIG = 0

CLK(R/X)

FS(R/X)

(R/X)SYNCERR

In contrast with Figure 3−1, Figure 3−2 shows McBSP operation when unexpected frame-sync signals are ignored (when (R/X)FIG = 1). Here, the transfer of word B is not affected by an unexpected pulse.

Frame sync aborts current transfer

New data received

Current data re-transmitted

B2B3B4B5B7 B6B6B7A0 B1

Receiver Configuration

D6D7C0C1C2C3C4C5C6C7B6B7A0

C6C7B0

Figure 3−2. Unexpected Frame-Sync Pulse With (R/X)FIG = 1

CLK(R/X)

FS(R/X)

D(R/X)

(R/X)SYNCERR

Frame synchronization ignored

3.1.6 Set the Receive Companding Mode

The µ-law and A-law formats both encode data into 8-bit code words. Companded data is always 8 bits wide; the appropriate word length bits

C4C5C6C7B0B1B2B3B4B5B6B7A0

Configure the Receiver and TransmitterSPRU061B

3-9

Page 100

Receiver Configuration

Figure 3−3 illustrates the companding processes. When companding is chosen for the transmitter, compression occurs during the process of copying data from DXR1 to XSR1. The transmit data is encoded according to the specified companding law (A-law or µ-law). When companding is chosen for the receiver, expansion occurs during the process of copying data from RBR1 to DRR1. The receive data is decoded to 2s-complement format.

Figure 3−3. Companding Processes for Reception and for Transmission

RBR1RSR1

Expand

DRR1

To CPU or FIFO

XSR1

Compress

DXR1

From CPU or FIFO

For reception, the 8-bit compressed data in RBR1 is expanded to left-justified 16-bit data in DRR1. Note that the RJUST bit of SPCR1 is ignored when companding is used.

If the McBSP is otherwise unused (the serial port transmit and receive sections are reset), the companding hardware can compand internal data. See Capability to Compand Internal Data on page 1-13.

Normally, the McBSP transmit or receives all data with the most significant bit (MSB) first. However, certain 8-bit data protocols (that do not use companded data) require the least significant bit (LSB) to be transferred first. If you set RCOMPAND = 01b in RCR2, the bit ordering of 8-bit words is reversed during reception. Similar to companding, this feature is enabled only if the appropriate word length bits are set to 0, indicating that 8-bit words are to be transferred serially. If either phase of the frame does not have an 8-bit word length, the McBSP assumes the word length is eight bits, and LSB-first ordering is done.

The RCOMPAND bits determine whether companding or another data transfer option is chosen for McBSP reception. Modes other than 00b are enabled only when the appropriate RWDLEN is 000b, indicating 8-bit data.

To get this result … Use this bit…

3-10

Receive companding mode Set RCOMPAND (bits 4:3 in RCR2) to

Configure the Receiver and Transmitter

one of the following

00 No companding, any size data,

MSB received first

SPRU061B