TERIDIAN Semiconductor 78Q2120C Technical data

78Q2120C

10/100BASE-TX

Transceiver

DESCRIPTION

The 78Q2120C is a 10BASE-T/100BASE-TX Fast Ethernet transceiver. It includes integrated MII, ENDECs, scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation function. The transmitter includes an on-chip pulse-shaper and a low-power line driver. The receiver has an adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery. The transceiver interfaces to Category-5 unshielded twisted pair (Cat5 UTP) cabling for 100BASE-TX/10BASE-T and Category-3 unshielded twisted pair for 10BASE-T. Connection to the line media is via 1:1 isolation transformers. No external filter is required. Interface to the MAC is accomplished through an IEEE-802.3 compliant Media Independent Interface (MII). The product is fabricated in an advanced CMOS process for high performance and low power operation.

DATA SHEET

January 2009

FEATURES

• 10BASE-T/100BASE-TX IEEE-802.3 compliant

TX and RX functions requiring a dual 1:1 isolation transformer interface to the line

• Integrated MII, 10BASE-T/100BASE-TX ENDEC,

100BASE-TX scrambler/descrambler, and fullfeatured auto-negotiation function

• Full duplex operation capable

• PCS Bypass supports 5-bit symbol interface

• Register-programmable transmit amplitude

• Dual speed digital clock recovery

• Automatic polarity correction during auto-

negotiation and 10BASE-T signal reception

• Power-saving and power-down modes

including transmitter disable

• LED indicators: LINK, TX, RX, COL, 100, 10,

FDX

RX_CLK

TX_CLK

RXD[3:0]

TXD[3:0]

• User programmable Interrupt pin

• 64-Pin TQFP (JEDEC LQFP) package

• Single 3.3 V ± 0.3V Supply

BLOCK DIAGRAM

4B/5B Encoder,

100M

Scrambler,

Parallel/Serial

MII

Registers

Interface

Logic

10M

Manchester Encoder

Parallel/Serial,

Manchester Dec oder,

Parallel/Serial

Serial/Parallel

Descrambler,

5B/4B Decoder

GND

VCC

GND

VCC

NRZ/NRZI

MLT3 Encoder

TX CLK GEN

Carrier Sense,

Collision Detect

CLK

Recovery

Clock Reference

25MHz

CKIN

25MHz

Pulse Shaper

and Filter

MDI

uto

Negotiation

10M 100M

daptive EQ,

Baseline Wander Correct,

Baseline Wander Correct, MLT3 Decode, NRZI/NRZ

MLT3 Decode, NRZI/NRZ

LEDs

LEDL LEDBTX LEDTX LEDCOL LEDBT LEDFX LEDRX

TXOP/N

RXIP/N

FUNCTIONAL DESCRIPTION

GENERAL

Power Management

The 78Q2120C has three power saving modes:

• Chip Power-Down

• Receive Power Management

• Transmit High Impedance Mode

Chip power-down is activated by setting the PWRDN bit in MII register MR0.11 or pulling high the PWRDN pin. When the chip is in the power-down mode, all on-chip circuitry is shut off, and the device consumes minimum power. While in the powerdown state, the 78Q2120C still responds to management transactions.

Receive power management (RXCC mode) is activated by setting the RXCC bit in MII register MR16.0. In this mode of operation, the adaptive equalizer, the clock recovery phase lock loop (PLL), and all other receive circuitry will be powered down when no valid MLT-3 signal is present at the UTP receive line interface. As soon as a valid signal is detected, all circuits will automatically be powered up to resume normal operation. During this mode of operation, RX_CLK will be inactive when there is no data being received. Note that the RXCC mode is not supported during 10BASE-T operation.

Transmit high impedance mode is activated by setting the TXHIM bit in MII register MR16.12. In this mode of operation, the transmit UTP drivers are in a high impedance state and TX_CLK is tri-stated. A weak internal pull-up is enabled on TX_CLK. The receive circuitry remains fully operational. The default state of MR16.12 is a logic low for disabling the transmit high impedance mode. The transmitter is fully functional when MR16.12 is cleared.

78Q2120C

10/100BASE-TX

Transceiver

mode of operation, a 25MHz crystal should be connected between the XTLP and XTLN pins. Alternatively, an external 25MHz clock signal can be connected to the CKIN pin. The chip senses activity on the CKIN pin, and will automatically configure itself to use the external clock. In this mode of operation, a crystal is not required and the XTLP and XTLN pins should be left floating or connected together.

Transmit Clock Generation

The transmitter uses an on-chip frequency synthesizer to generate the transmit clock. In 100BASE-TX operation, the synthesizer multiplies the reference clock by 5 to obtain the internal 125MHz serial transmit clock. In 10BASE-T mode, it generates an internal 20MHz transmit clock by multiplying the 25MHz reference clock by 4/5. The synthesizer references either the local 25 MHz crystal oscillator, or the externally applied clock, depending on the selected mode of operation.

Receive Signal Qualification

The integrated signal qualifier has separate squelch and unsquelch thresholds. It also includes a built-in timer to ensure fast and accurate signal detection and line noise rejection. Upon detection of two or more valid 10BASE-T or 100BASE-TX pulses on the line receive port, signal detect is indicated. The signal detect threshold is then lowered by about 40%. All adaptive circuits are released from their initial states and allowed to lock onto the incoming data. In 100BASE-TX operation, signal detect is de-asserted when no signal is presented for a period of about

1.2us. In 10BASE-T operation, signal detect is deasserted whenever no Manchester data is received. In either case, the signal detect threshold will return to the squelched level whenever the signal detect indication is de-asserted. Signal detect is also used to control the operation of the clock/data recovery circuit to assure fast acquisition.

Analog Biasing and Supply Regulation

The 78Q2120C requires no external component to generate on-chip bias voltages and currents. High accuracy is maintained through a closed-loop trimmed biasing network.

On-chip digital logic runs off an internal voltage regulator. Hence only a single Vcc supply is required to power-up the device. The on-chip regulator is not affected by the power-down mode.

Clock Selection

The 78Q2120C will use the on-chip crystal oscillator as the clock source if the CKIN pin is tied low. In this

Receive Clock Recovery

In 100BASE-TX mode, the 125MHz receive clock is extracted using a digital DLL-based loop. When no receive signal is present, the CDR is directed to lock onto the 125MHz transmit serial clock. When signal detect is asserted, the CDR will use the received MLT3 signal as the clock reference. The recovered clock is used to re-time the data signal and for conversion of the data to NRZ format.

In 10BASE-T mode, the 10MHz receive clock is recovered digitally from the Manchester data using a DLL locked to the reference clock. When Manchester-coded preambles are detected, the

CDR immediately re-aligns the phase of the clock to synchronize with the incoming data. Hence clock acquisition is fast and immediate.

100BASE-TX OPERATION

100BASE-TX Transmit

The 78Q2120C contains all of the necessary circuitry to convert the transmit MII signaling from a MAC to an IEEE-802.3 compliant data-stream driving Cat-5 UTP cabling. The internal PCS interface maps 4 bit nibbles from the MII to 5 bit code groups as defined in Table 24-1 of IEEE-802.3. These 5 bit code groups are then scrambled and converted to a serial stream before being sent to the MLT-3 pulse shaping circuitry and line driver. The pulse-shaper uses current modulation to produce the desired output waveform. Controlled rise/fall time in the MLT-3 signal is achieved using an accurately controlled voltage ramp generator. The line driver requires an external 1:1 isolation transformer to interface with the line media. The center-tap of the primary side of the transformer must be connected to the Vcc supply.

100BASE-TX Receive

The 78Q2120C receives a 125MBaud MLT-3 signal through a 1:1 transformer. The signal then goes through a combination of adaptive offset adjustment (baseline wander correction) and adaptive equalization. The effect of these circuits is to sense the amount of dispersion and attenuation caused by the cable and transformer, and restore the received pulses to logic levels. The amount of gain and equalization applied to the pulses varies with the detected attenuation and dispersion and, therefore, with the length of the cable. The 78Q2120C can compensate for cable loss of up to 10dB at 16 MHz. This loss is represented as test-chan 5 in Annex A of the ANSI X3.263:199X specification. The equalized MLT-3 data signal is bi-directionally sliced and the resulting NRZI bit-stream is presented to the CDR where it is re-timed and decoded to NRZ format. The re-timed serial data passes through a serial to parallel converter, then is descrambled and aligned into 5 bit code groups. The receive PCS interface maps these code groups to 4 bit data for the MII as outlined in Table 24-1 in Clause 24 of IEEE-802.3.

PCS Bypass Mode (Auto-negotiate must be off)

The PCS Bypass mode is entered by pulling PCSBP high or by setting register bit MR 16.1. In this mode the 78Q2120C accepts scrambled 5 bit code words at the TX_ER and TXD[3:0] pins, TX_ER being the

78Q2120C

10/100BASE-TX

Transceiver

MSB of the data input. The 5 bit code groups are converted to MLT-3 signal for transmission.

The received MLT-3 signal is converted to 5 bit NRZ code groups and output from the RX_ER and RXD[3:0] pins, RX_ER being the MSB of the data output. The RX_DV and TX_EN pins are unused in PCS Bypass mode.

10BASE-T OPERATION

10BASE-T Transmit

The 78Q2120C takes 4-bit parallel NRZ data via the MII interface and passes it through a parallel to serial converter. The data is then passed through a Manchester encoder, pre-emphasis pulse-shaper, media filter, and finally to the twisted-pair line driver. The pulse-shaper and filter ensure the output waveforms meet the voltage template and spectral content requirements detailed in Clause 14 of IEEE-

802.3. Interface to the twisted-pair media is through a center-tapped 1:1 transformer. No external filtering is required. During auto-negotiation and 10BASE-T idle periods, link pulses are transmitted.

The 78Q2120C employs an onboard timer to prevent the MAC from capturing a network through excessively long transmissions. When this timer expires, the chip enters the jabber state and transmission is halted. The jabber state is exited after the MII goes idle for 500±250ms.

10BASE-T Receive

The 78Q2120C receives Manchester-encoded 10BASE-T data through the twisted pair inputs and re-establishes logic levels through a slicer with a smart squelch function. The slicer automatically adjusts its level after detection of valid data with the appropriate levels. Data is passed on to the CDR where the clock is recovered, and the data is retimed and decoded. From there, data enters the serial-to-parallel converter for transmission to the MAC via the Media Independent Interface. Interface to the twisted-pair media is through an external 1:1 transformer. Polarity information is detected and corrected within internal circuitry.

Polarity Correction

The 78Q2120C is capable of either automatic or manual polarity reversal for 10BASE-T and auto-negotiation functions. Register bits MR16.5 and MR16.4 control this feature. The default is automatic mode where MR16.5

is low and MR16.4 indicates if the detection circuitry has inverted the input signal. To enter manual mode, MR16.5 should be set high and MR16.4 will then control the signal polarity.

SQE TEST

The 78Q2120C supports the Signal Quality Error (SQE) function detailed in IEEE-802.3. At an interval of 1µs after each negative transition of the TXEN pin in 10BASE-T mode, the COL pin will go high for a period of 1µs. SQE is not signaled during transmission after collision is detected. SQE is automatically disabled when repeater mode is enabled. This function can be disabled through register bit MR16.11.

Natural Loopback

When enabled, whenever the 78Q2120C is transmitting and not receiving on the twisted pair media (10BASE-T Half Duplex mode), data on the TXD[3:0] pins is looped back onto the RXD[3:0] pins. During a collision, data from the RXI pins is routed to the RXD[3:0] pins. The natural loopback function is enabled through register bit MR16.10.

78Q2120C

10/100BASE-TX

Transceiver

will look for either 10BASE-T idle, 100BASE-TX idle, or fast link pulses from its link partner. If either idle pattern is detected, the 78Q2120C configures itself in half-duplex mode at the appropriate speed. If it detects fast link pulses, it decodes and analyzes the link code transmitted by the link partner. When three identical link code words are received (ignoring the acknowledge bit) the link code word is stored in register MR5. Upon receiving three more identical link code words, with the acknowledge bit set, the 78Q2120C configures itself to the highest priority technology common to the two link partners. The technology priorities are, in descending order:

100BASE-TX, Full Duplex 100BASE-TX, Half Duplex 10BASE-T, Full Duplex 10BASE-T, Half Duplex

Once auto-negotiation is complete, register bits MR18.11:10 will reflect the actual speed and duplex that was chosen.

Repeater Mode

When the RPTR pin is high or register bit MR16.15 is set, the 78Q2120C is placed in repeater mode. In this mode, full duplex operation is prohibited, CRS responds only to receive activity and, in 10BASE-T mode, the SQE test function is disabled.

AUTO-NEGOTIATION

The 78Q2120C supports the auto-negotiation functions of Clause 28 of IEEE-802.3 for 10/100 Mbps operation over copper wiring. This function can be enabled via a pin selection or register settings. If the ANEGA pin is tied high, the autonegotiation function defaults to ON and bit MR0.12 (ANEGEN) is high after reset. Software can disable the auto-negotiation function by writing to bit MR0.12. If the ANEGA pin is tied low, the function defaults to OFF and bit MR0.12 is set low after reset and cannot be written to.

The contents of register MR4 are sent to the 78Q2120C’s link partner during auto-negotiation using fast link pulse coding. Bits MR4.8:5 reflect the state of the TECH[2:0] pins after reset. If TECH[2:0] = ‘111’, then all 4 bits are high. If TECH[2:0] = ‘001’, then only bit 5 is high. After reset, software can change any of these bits from a ‘1’ to a ‘0’; but not from a ‘0’ to a ‘1’. Therefore, a technology permitted by the setting of the TECH pins can be disabled, but cannot be enabled through register selection.

With auto-negotiation enabled, the 78Q2120C will start sending fast link pulses at power on, loss of link or upon a command to restart. At the same time, it

If auto-negotiation fails to establish a link for any reason, register bit MR18.12 will reflect this and auto negotiation will restart from the beginning. Writing a ‘1’ to bit MR0.9(RANEG) will also cause autonegotiation to restart.

MEDIA INDEPENDENT INTERFACE

MII Transmit and Receive Operation

The MII interface on the 78Q2120C provides independent transmit and receive paths for both 10Mb/s and 100Mb/s data rates as described in Clause 22 of the IEEE-802.3 standard.

The transmit clock, TX_CLK, provides the timing reference for the transfer of TX_EN, TXD[3:0], and TX_ER signals from the MAC to the 78Q2120C. TXD[3:0] is captured on the rising edge of TX_CLK when TX_EN is asserted. TX_ER is also captured on the rising edge of TX_CLK and is asserted by the MAC to request that an error code group is to be transmitted. The assertion of TX_ER is ignored when the 78Q2120C is operating in 10BASE-T mode.

The receive clock, RX_CLK, provides the timing reference to transfer RX_DV, RXD[3:0], and RX_ER signals from the 78Q2120C to the MAC. RX_DV transitions synchronously with respect to RX_CLK and is asserted when the 78Q2120C is presenting valid data on RXD[3:0]. RX_ER is asserted and is synchronous to RX_CLK when a code group violation has been detected in the current receive packet.

Station Management Interface

The station management interface consists of circuitry which implements the serial protocol as described in Clause 22.2.4.5 of IEEE-802.3. A 16bit shift register receives serial data applied to the MDIO pin at the rising-edge of the MDC clock signal. Once the preamble is received, the station management control logic looks for the start-offrame sequence and a read or write op-code, followed by the PHYAD and REGAD fields. For a read operation, the MDIO port becomes enabled as an output and the register data is loaded into a shift register for transmission. The 78Q2120C can work with a one bit preamble rather than the 32 bits prescribed by IEEE-802.3. This allows for faster programming of the registers. If a register does not exist at an address indicated by the REGAD field or if the PHYAD field does not match the 78Q2120C PHYAD indicated by the PHYAD pins, a read of the MDIO port will return all ones. For a write operation, the data is shifted in and loaded into the appropriate register after the sixteenth data bit has been received.

When the PHYAD field is all zeros, the Station Management Entity (STA) is requesting a broadcast data transaction. All PHYs sharing the same Management Interface must respond to this broadcast request. The 78Q2120C will respond to the broadcast data transaction.

ADDITIONAL FEATURES

LED Indicators

78Q2120C

10/100BASE-TX

Transceiver

78Q2120C. There is an LED pin that indicates the link is up (LEDL), others that indicate the 78Q2120C is either transmitting (LEDTX) or receiving (LEDRX), one that signals a collision event (LEDCOL), two more that reflect the data rate (LEDBTX and LEDBT), and one that reflects full duplex mode of operation (LEDFDX).

Interrupt Pin

The 78Q2120C has an Interrupt pin (INTR) that is asserted whenever any of the eight interrupt bits of MR17.7:0 are set. These interrupt bits can be disabled via the MR17.15:8 Interrupt Enable bits. The Interrupt Polarity bit, MR16.14, controls the active level of the INTR pin. When the INTR pin is not asserted, this pin is held in a high impedance state. An external pull-up or pull-down resistor may be required for use with the INTR pin.

APPLICATIONS REQUIREMENTS

RXIP/N Termination Connection

The input circuitry of the TERIDIAN 78Q2120C has changed for continuing performance improvements. Device revision C09 requires that the RXIP/N termination resistors and transformer center tap connections be directly connected to VCC for proper receiver operation. Refer to Figure 1: Typical Applications Circuit for the schematic showing the required RXIP/N termination resistors and transformer center tap connections to VCC for revision 78Q2120C.

There are seven LED pins that can be used to indicate various states of operation of the

78Q2120C

10/100BASE-TX

Transceiver

PIN DESCRIPTION

LEGEND

TYPE DESCRIPTION TYPE DESCRIPTION

A Analog Pin CI TTL-level Input (5V compatible)

CIU TTL-level Input w/ Pull-up (5V compatible) CIO TTL-compatible Bi-directional Pin (5V compatible)

CID TTL-level Input w/ Pull-down

(5V compatible)

CIS TTL-level Input w/ Schmitt Trigger

(5V compatible)

CO CMOS Output S Supply

MII (MEDIA INDEPENDENT INTERFACE)

NAME PIN TYPE DESCRIPTION

TX_CLK

TX_EN

TXD[3:0]

TX_ER

CRS

COL

RX_CLK

RX_DV

RXD[3:0]

27 COZ

28 CI

32-29 CI

26 CI

34 COZ

33 COZ

24 COZ

23 COZ

19-22 COZ

TRANSMIT CLOCK: TX_CLK is a continuous clock, which provides a timing reference for the TX_EN, TX_ER and TXD[3:0] signals from the MAC. The clock frequency is 25MHz in 100BASE-TX mode and 2.5MHz in 10BASE-T mode. This pin is tristated in the isolate mode and the TXHIM mode.

TRANSMIT ENABLE: TX_EN is asserted by the MAC to indicate that valid data for transmission is present on the TXD[3:0] pins.

TRANSMIT DATA: TXD[3:0] receives data from the MAC for transmission on a nibble basis. This data is captured on the rising edge of TX_CLK when TX_EN is high.

TRANSMIT ERROR: TX_ER is asserted high by the MAC to request that an error code-group be transmitted when TX_EN is high. In PCS bypass mode this pin becomes the MSB of the transmit 5-bit code group.

CARRIER SENSE: When the 78Q2120C is not in repeater mode, CRS is high whenever a non-idle condition exists on either the transmitter or the receiver. In repeater mode, CRS is only active when a non-idle condition exists on the receiver. This pin is tristated in the isolate mode.

COLLISION: COL is asserted high when a collision has been detected on the media. In 10BASE-T mode, COL is also used for the SQE test function. This pin is tristated in the isolate mode. During half duplex operation, the rising edge of COL will occasionally occur upon the rising edge of TX_CLK.

RECEIVE CLOCK: RX_CLK is a continuous clock, which provides a timing reference to the MAC for the RX_DV, RX_ER and RXD[3:0] signals. The clock frequency is 25MHz in 100BASE-TX mode, and 2.5MHz in 10BASE-T mode. To reduce power consumption in 100BASE-TX mode, the 78Q2120C provides an optional mode, enabled through MR16.0, in which RX_CLK is held inactive (low) when no receive data is detected. This pin is tristated in the isolate mode.

RECEIVE DATA VALID: RX_DV is asserted high to indicate that valid data is present on the RXD[3:0] pins. In 100BASE-TX mode, it transitions high with the first nibble of the preamble and is pulled low when the last data nibble has been received. In 10BASE-T mode, it transitions high when the start-of-frame delimiter (SFD) is detected. This pin is tristated in the isolate mode.

RECEIVE DATA: Received data is provided to the MAC via RXD[3:0]. These pins are tristated in the isolate mode.

COZ Tristate-able CMOS output

G Ground

MII (continued)

NAME PIN TYPE DESCRIPTION

RX_ER

MDC 18 CIS

MDIO 17 CIO

PHY ADDRESS

NAME PIN TYPE DESCRIPTION

PHYAD[4:0] 12-16 CI

25 COZ

RECEIVE ERROR: RX_ER is asserted high when an error is detected during a frame reception. In PCS bypass mode, this pin becomes the MSB of the receive 5-bit code group. This pin is tristated in the isolate mode.

MANAGEMENT DATA CLOCK: MDC is the clock used for transferring data via the MDIO pin.

MANAGEMENT DATA INPUT/OUTPUT: MDIO is a bi-directional port used to access management registers within the 78Q2120C. This pin requires an external pull-up resistor as specified in IEEE-802.3.

PHY ADDRESS: Allows 31 configurable PHY addresses. The 78Q2120C always responds to broadcast data transactions via the MII interface when the PHYAD bits are all zero, independent of the logic levels of the PHYAD pins.

78Q2120C

10/100BASE-TX

Transceiver

PMA (PHYSICAL MEDIA ATTACHMENT) INTERFACE

NAME PIN TYPE DESCRIPTION

PCSBP 64 CID

CONTROL AND STATUS

NAME PIN TYPE DESCRIPTION

RST

PWRDN 7 CID

6 CIU

PCS BYPASS: When high, the 100BASE-TX PCS is bypassed, as well as the scrambler and descrambler functions. Scrambled 5-bit code groups for transmission are applied to the TX_ER, TXD[3:0] pins and received on the RX_ER, RXD[3:0] pins. The RX_DV and TX_EN signals are not valid in this mode. PCS bypass mode is only valid when 100BASE-TX is enabled and auto-negotiation is disabled. This mode can also be entered by setting MR16.1.

ACTIVE-LOW RESET: When pulled low, the pin resets the chip. The reset pulse must be long enough to guarantee stabilization of the supply voltage and startup of the oscillator. Refer to the Electrical Specifications for the reset pulse requirements. There are 2 other ways to reset the chip:

i) through the internal power-on-reset (activated when the chip is

being powered up)

ii) through the MII register bit (MR0.15)

POWER-DOWN: The 78Q2120C may be placed in a low power consumption state by setting this signal to logic high. While in the power-down state, the 78Q2120C still responds to management transactions. This power-down state can also be activated using the PWRDN bit in the MII register (MR0.11).

CONTROL AND STATUS (CONTINUED)

NAME PIN TYPE DESCRIPTION

ISO 2 CI

ISODEF 1 CI

ANEGA 47 CI

TECH[2:0] 44-46 CI

ISOLATE: When set to logic one, the 78Q2120C will present a high impedance on its MII output pins. This allows for multiple chips to be attached to the same MII interface. When the 78Q2120C is isolated, it still responds to management transactions. This high impedance state can also be achieved using the ISO bit in the MII register (MR0.10).

ISOLATE DEFAULT: This pin determines the power-up/reset default of the ISO bit (MR0.10). If it is connected to VCC, the ISO bit will have a default value of ‘1’. Otherwise, the bit defaults to ‘0’. When this signal is tied to VCC, it allows multiple chips to be connected to the same MII interface.

AUTO-NEGOTIATION ABILITY: Connect to logic high to enable the autonegotiation function. When connected to logic low, the auto-negotiation logic is disabled and manual technology selection is done through TECH[2:0] pins. This pin is reflected as the ANEGA bit in MR1.3.

TECHNOLOGY ABILITY/SELECT: TECH[2:0] sets the technology ability of the chip which is reflected in MR0.13,8, MR1.14:11 and MR4.12:5.

78Q2120C

10/100BASE-TX

Transceiver

TECH[2:0] Technology Ability

111 Both 10BASE-T and 100BASE-TX, and Both half and full duplex 000 None 001 10BASE-T, half duplex 010 100BASE-TX, half duplex

011 Both 10BASE-T and 100BASE-TX, half duplex only 100 None 101 10BASE-T Both half and full duplex

110 100BASE-TX Both half and full duplex

RPTR 50 CID

MDI (MEDIA DEPENDENT INTERFACE)

NAME PIN TYPE DESCRIPTION

TXOP/N 61,62 A

RXIP/N 52,51 A

REPEATER MODE: When pulled high, this pin puts the chip into repeater mode. In this mode, full duplex is prohibited, CRS responds to receive activity only. In 10BASE-T mode, the SQE test function is disabled. This mode can also be enabled by setting bit MR16.15

TRANSMIT OUTPUT POSITIVE/NEGATIVE: Transmitter differential outputs for both 10BASE-T and 100BASE-TX operation.

RECEIVE INPUT POSITIVE/NEGATIVE: Receiver differential inputs for both 10BASE-T and 100BASE-TX operation.

78Q2120C

10/100BASE-TX

Transceiver

LED INDICATORS

The LED pins use standard logic drivers. They output a logic low when the LED is meant to be on and a logic high when it is meant to be off. The LED should be connected in series with a resistor between the output pin and the power supply.

NAME PIN TYPE DESCRIPTION

LEDL LEDTX LEDRX LEDCOL

LEDBTX

LEDBT

LEDFDX

40 CO LED LINK: ON for link up.

39 CO LED TRANSMIT: ON when there is a transmission (normally OFF).

38 CO LED RECEIVE: ON when there is a reception (normally OFF).

37 CO

36 CO

48 CO

49 CO

LED COLLISION: In half duplex mode, this is a collision indicator and turns ON when a collision occurs. In full duplex mode, this LED is held OFF.

LED 100BASE-TX: ON for 100BASE-TX connection and OFF for other connections. LEDBTX is OFF during auto-negotiation.

LED 10BASE-T: ON for 10BASE-T connection and OFF for other connections. LEDBT is OFF during auto-negotiation.

LED FULL DUPLEX: ON when in full duplex mode and OFF when in half duplex mode.

OSCILLATOR/CLOCK

NAME PIN TYPE DESCRIPTION

CKIN 4 CIS

XTLP/N 59,58 A

MISCELLANEOUS PIN

NAME PIN TYPE DESCRIPTION

INTR 35 COZ

NC 54,56 -- No Connect. Do not connect to ground or supply.

POWER SUPPLY AND GROUND

NAME PIN TYPE DESCRIPTION

VCC

GND

8,11,41,

43,57,63

3,5,9,10,

42,53,55,60

CLOCK INPUT: Connects to a 25 MHz TTL compatible clock source. This pin should be held low when XTLP and XTLN are being used as the 25 MHz clock source.

CRYSTAL PINS: Should be connected to a 25 MHz crystal. When CKIN is being used as the 25 MHz clock source, these pins should be left floating or connected together.

INTERRUPT PIN: This pin is used to signal an interrupt to the media access controller. The pin is held in the high impedance state when an interrupt is not indicated. The pin will be forced high or low to signal an interrupt depending upon the value of the INPOL bit (MR16.14). The events which trigger an interrupt can be programmed via the Interrupt Control Register located at address MR17.

S 3.3V SUPPLY

G GROUND

78Q2120C

10/100BASE-TX

Transceiver

The 78Q2120C implements 11 16-bit registers, which are accessible via the MDIO and MDC pins. The supported registers are shown below in the following table. Attempts to read unsupported registers will be ignored and the MDIO pin will not be enabled as an output, as per the IEEE 802.3 specification. All of the registers except those which are unique to the 78Q2120C, will respond to the broadcast PHYAD value of ‘00000’. The registers specific to the 78Q2120C occupy address space MR16-22.

ADDRESS SYMBOL NAME DEFAULT (HEX)

0 MR0 Control (3100) 1 MR1 Status (7809) 2 MR2 PHY Identifier 1 000E 3 MR3 PHY Identifier 2 70C9 4 MR4 Auto-Negotiation Advertisement (01E1) 5 MR5 Auto-Negotiation Link Partner Ability 0000 6 MR6 Auto-Negotiation Expansion 0000 7 MR7 Not Implemented 0000

8-14 MR8-14 Reserved 0000

15 MR15 Not Implemented 0000 16 MR16 Vendor Specific (0140) 17 MR17 Interrupt Control/Status Register 0000 18 MR18 Diagnostic Register 0000 19 MR19 Transceiver Control 4XXX

20-22 MR20-MR22 Reserved 0000

Legend:

TYPE DESCRIPTION TYPE DESCRIPTION

R Readable by management. W Writeable by management.

SC Writeable by management. Self

Clearing.

0/1 Default value upon power up or

reset.

RC Readable by management.

Cleared upon a read operation.

(0/1) Default value dependent on pin

settings. The value in bracket indicates typical case.

MR0: Control Register

BIT SYMBOL TYPE DEFAULT DESCRIPTION

0.15 RESET R/SC 0

0.14 LOOPBK R/W 0

0.13 SPEEDSL R/W (1)

0.12 ANEGEN R/W (1)

0.11 PWRDN R/W 0

0.10 ISO R/W (0)

0.9 RANEG R/SC 0

Reset: Setting this bit to ‘1’ resets the device and sets all registers to their default states. This bit is self-clearing.

Loopback: When this bit is set to ‘1’, no transmission of data on the network medium occurs and any receive data on the network medium is ignored. The loopback signal path will encompass most of the digital circuitry.

Speed Selection: This bit determines the speed of operation of the 78Q2120C. Setting this bit to ‘1’ indicates 100Base-TX operation and a ‘0’ indicates 10Base-T mode. This bit will default to a ‘1’ upon reset. If the TECH[2:0] pins are all logic zero and auto-negotiation is not enabled, this bit will be writeable. If auto-negotiation is not enabled and the TECH[2:0] pins are set to indicate that only 10Base-T is supported, this bit will be forced to logic zero and will not be writeable. If auto-negotiation is not enabled and the TECH[2:0] pins are set to indicate that only 100Base-TX is supported, this bit will be forced to logic one and will not be writeable. When auto-negotiation is enabled, this bit will not be writeable and will have no effect on the 78Q2120C. If the TECH[2:0] pins are brought to zero from another value, this bit will retain its original value until it is overwritten.

Auto-Negotiation Enable: Setting this bit to ‘1’ enables the autonegotiation process. This bit can only be set if the ANEGA pin is a logic one and will default to ‘1’ upon reset. If this bit is cleared to ‘0’, manual speed and duplex mode selection is accomplished through bits 0.13 (SPEEDSL) and 0.8 (DUPLEX) of the Control Register or the TECH[2:0] pins according to the table shown in the section describing the TECH[2:0] pins. If the ANEGA pin is brought from ‘0’ to ‘1’ and reset is not asserted, this bit will remain at ‘0’ until a ‘1’ is written.

Power-Down: The device may be placed in a low power consumption state by setting this bit to ‘1’. While in the power-down state, the device will still respond to management transactions. Setting the PWRDN pin high also activates the power-down state.

Isolate: When set to ‘1’, the device presents a high-impedance on its MII output pins. This allows for multiple PHY’s to be attached to the same MII interface. When the device is isolated, it still responds to management transactions. The default value of this bit depends on the ISODEF pin. When ISODEF pin is tied high, the ISO bit defaults to high. Otherwise, it defaults to low. The Isolate mode can also be activated using the ISO pin.

Restart Auto-Negotiation: Normally, the Auto-Negotiation process is started at power up. The process can be restarted by setting this bit to ‘1’. This bit is self-clearing.

78Q2120C

10/100BASE-TX

Transceiver

+ 24 hidden pages

TERIDIAN Semiconductor 78Q2120C Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual