TERIDIAN Semiconductor 73S8023C Technical data

73S8023C

Smart Card Interface

Simplifying System Integration™

DESCRIPTION

The Teridian 73S8023C is a low-power, high efficiency, single smart card interface IC suitable for 3V and 5V cards. It provides full electrical compliance with ISO7816-3 and EMV 4.0 (EMV2000) specifications.

Hardware support for any type of synchronous cards (memory cards) is provided.

Interfacing with the system controller is done through the control bus; composed of digital input s to control the interface, and one interrupt output to inform the system controller of the card presence and faul ts. Data exchange with the card is managed from the system controller using the I/O line (and eventually the auxi l iary I/O lines).

A chip select input allows multiple 73S8023C ICs to share the same control bus. When chip select is set low, the host microcontroller inputs are latch ed and outputs are taken to a high impedance state.

The card clock signal can be generated by an on-chip oscillator using an external crystal or by connecting an external clock signal.

The 73S8023C device incorporat es an ISO-7816-3 activation/deactivation sequencer that controls the card signals. Emergency card deactivatio n i s i nitiated upon card extraction or upon any fault generated by the protection circuitry.

The 73S8023C requires only a single 2.7 V to 3.6 V power supply, and features a high-efficiency embedded DC-DC converter. This architecture, plus a Power Down digital input that allow placing the IC in a very low-power mode making the 73S8023C particularly sui table for low-power applications (cell-phones, PDAs, payphones, hand-held POS terminals…).

ADVANTAGES

• Supports both synchronous and asynchronous smart cards

• Replacement for TDA8002, with up to 60 0 mW in power savings (@ EMV ICCmax condition) !

• The inductor-based DC-DC converter provides higher current and efficiency

 Ideal for battery-powered applications  Suitable for high current cards and SAM s: (100 mA

max)

 Single 2.7 V to 3.6 V power supply allows removal

of 5 V from the system

• Power down mode: 2 µA typical

• Package: Small Format (5x5mm) 32-QFN

DATA SHEET

April 2009

FEATURES

• Card Interface:

 Complies with ISO-7816-3, EMV 4.0  A DC-DC Converter provides 3V / 5V to the card

from an external power supply input

 High-efficiency converter: > 80% @ V

=5 V and I

= 65 mA

 Up to 100 mA supplied to the card  ISO-7816-3 Activation / Deactivation sequencer

with emergency automated deactivation

 Protection includes 2 voltage supervisors which

detect voltage drops on card V

power supply

 The V

voltage supervisor threshold value can be

externally adjusted

 True over-current detection (150 mA max.)  2 card detection inputs, 1 for either possible switch

configuration

 Full support of synchronous cards

• System Controller Interface:  3 Digital inputs control the card ac tivation /

deactivation, card reset and card voltage

 3 Digital inputs control the card clock (division rate

and card clock source selection)

 1 Digital output, interrupt to the system controller,

allows the system controller to monitor the card presence and faults

 1 Power down digital input (places the 73S8023C

in a very low-power mode (card deactivated)

 1 Chip select digital input for parall el operation of

several 73S8023C ICs.

 1 External clock input (STROBE), used for

synchronous operation

 1 Digital output clock, buffered version of signal on

XTALIN

 Crystal oscillator or host clock (XTALIN), up to

27 MHz

• Power Supply: V

2.7 V to 3.6 V

• 6 kV ESD Protection on the card interface

APPLICATIONS

• Point of Sales and Transaction Terminals

• Payphones

• Set-Top-Boxes, DVD / HDD Recorders

• Payment card interfaces in portable devices (PDAs,

mobile phones…)

=3.3 V,

and on V

73S8023C Data Sheet DS_8023C_019

ICC I/O BUFFERS

VDD VOLTAGE SUPERVISOR

VOLTAGE REFERENCE

XTAL

OSC

CLOCK

GENERATION

DIGITAL

CIRCUITRY

FAULT LOGIC

FAULT

Int_Clk

VDD VDD

VCC

RST

CLK

PRES

XTALIN

XTALOUT

CLKDIV1

CLKDIV2

GND

TEMP FAULT

ISO-7816-3

SEQUENCER

R-C

OSC.

DC-DC

CONVERTER

ICC RESET

BUFFER

ICC CLOCK

BUFFER

OVER TEMP

PWRDN

I/O

AUX1

AUX2

IOUC

AUX1UC

AUX2UC

VDDF_ADJ

RSTIN

CMDVCC

5V/3V

OFF

GND

LIN

GND

ICC FAULT

CLKOUT

CLKSEL

STROBE

FUNCTIONAL DIAGRAM

Figure 1: 73S8023C Block Diagram

2 Rev. 1.5

DS_8023C_019 73S8023C Data Sheet

Table of Contents

1 Pin Description .................................................................................................................................... 5

1.1

Card I nterface ............................................................................................................................... 5

Miscellaneous Inputs and Outputs ................................................................................................ 5

1.2

Power S upply and Ground ............................................................................................................ 5

1.3

Microc ontroller Interface ............................................................................................................... 6

1.4

System Controller Interface ............................................................................................................... 7

Oscillator .............................................................................................................................................. 8

DC-DC Converter – Card Power Supply .......................................................................................... 8

Voltage Supervision ........................................................................................................................... 9

Power Down ....................................................................................................................................... 10

Over-Temperature Monitor ............................................................................................................... 10

Activation and Deactivation ............................................................................................................. 11

8.1

Activation Sequence (Synchronous Mode) ................................................................................ 11

Deactiv ati on Sequen ce (Synchr ono us Mode) ............................................................................ 11

8.2

Activation Sequence (Asynchronous Mode) ............................................................................... 12

8.3

Deactiv ati on Sequen ce (Async hronou s Mode ) .......................................................................... 14

8.4

OFF and Fault Detection .................................................................................................................. 14

I/O Circuitry and Timing ................................................................................................................... 15

Typical Application Schematic ........................................................................................................ 17

Electrical Specification ..................................................................................................................... 18

12.1

Absolute Maximum Ratings ........................................................................................................ 18

Recommended Operating Conditions ......................................................................................... 18

12.2

Package Thermal Parameters .................................................................................................... 18

12.3

Card Interface Characteristics .................................................................................................... 19

12.4

Digital Signals ............................................................................................................................. 22

12.5

DC Characteristics ...................................................................................................................... 23

12.6

Voltage / Temperature Fault Detection Circuits .......................................................................... 23

12.7

Mechanical Drawing (32-QFN) ......................................................................................................... 24

Package Pin Designation (32-QFN) ................................................................................................. 25

Ordering Information ........................................................................................................................ 26

Related Documentation .................................................................................................................... 26

Contact Information .......................................................................................................................... 26

17 Revision History

........................................................................................................................................ 27

Rev. 1.5 3

73S8023C Data Sheet DS_8023C_019

Figures

Figure 1: 73S8023C Block Diagram ............................................................................................................. 2

Figure 2: Power Down Mode Operation: CS = high Figure 3: Activation Sequence – Synchronous Mod e Figure 4: Synchronous Deactivation Operation – CKSEL = High Figure 5: Asynchronous Activation Sequence – RS T IN Low When CMDVCC Goes Low Figure 6: Asynchronous Activation Sequence – Timing Diagram #2 Figure 7: Asynchronous Deactivation Sequence Figure 8: Timing Diagram – Management of the Interrupt Line OFF Figure 9: I/O and I/OUC State Diagram Figure 10: I/O – I/OUC Delays Timing Diagram Figure 11: 73S8023C – Typical Application Schematic Figure 12: DC – DC Converter efficiency (V Figure 13: DC – DC Converter Efficienc y (V Figure 14: 32-QFN Mechanical Drawing Figure 15: 32-QFN 73S8023C Pin Out

= 5 V) ................................................................................ 20

= 3 V) ................................................................................ 20

Table

Table 1: Choice of VCC Pin Capacitor .......................................................................................................... 8

.................................................................................... 10

................................................................................. 11

............................................................... 12

......................... 13

......................................................... 13

........................................................................................ 14

.......................................................... 15

...................................................................................................... 16

.......................................................................................... 16

.............................................................................. 17

..................................................................................................... 24

....................................................................................................... 25

4 Rev. 1.5

DS_8023C_019 73S8023C Data Sheet

CC.

1 Pin Description

1.1 Card Interface

Name Pin Description

I/O 9 Card I/O: Data signal to/from card. Includes a pull-up resistor to V AUX1 11 AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to V AUX2 10 AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to V

RST 14 Card reset: Provides reset (RST) signal to card. CLK 13

Card clock: Provides clock (CLK) signal to card. The r ate of this clock is determined by crystal oscillator frequency and CLKDIV selections.

PRES 7

Card Presence switch: Active high indicates card is present. Includes a pull-down current source.

PRES

Card Presence switch: Active low indicates card is present. Includes a pull-up current source.

VCC 15

Card power supply: Logically controlled by sequ encer, output of DC-DC converter. Requires an external filter capacitor to the card GND.

GND 12 Card ground.

1.2 Miscellaneous Inputs and Outputs

Name Pin Description

XTALIN 23

XTALOUT 24

VDDF_ADJ 17

NC 4 Non-connected pin. Must be left open.

Crystal oscillator input: can either be conne ct ed to crystal or driven as a source for the card clock.

Crystal oscillator output: connected to cry st al. Left open if XTALIN is being used as external clock input.

fault threshold adjustment input: this pin can be used to adjust V

value (that controls deactivation of the card ). M ust be left open if unused.

DDF

CC.

1.3 Power Supply and Ground

Name Pin Description

VDD 3, 20

GND 1 DC-DC converter ground. GND 21 Digital ground. LIN 2

Rev. 1.5 5

System controller interface supply voltage: Supply voltage for internal power supply and DC-DC converter power supply source.

External inductor. Connect external inductor from pin 2 to V

. Keep the

inductor close to pin 2.

73S8023C Data Sheet DS_8023C_019

0 0 XTALIN/8

0 1 XTALIN/4

1 1 XTALIN/2

1 0 XTALIN

DD.

1.4 Microcontroller Interface

Name Pin Description

CMDVCC 18

Command V converter to ramp the V

(negative assertion): Logic low on this pin causes the DC-DC

supply to the card and initiates a card activati on

sequence.

5V/#V

5 volt / 3 volt card selection: Logic one selects 5 volts for V

and card

interface, logic low selects 3 volt operation. When the part is to be used with a single card voltage, this pin should be tied to either GND or V

. However,

it includes a high impedance pull-up resistor to default this pin high (selection of 5V card) when unconnected

PWRDN 5

Power Down control input: Active High. When Power Down (PD) mode is activated, all internal analog functions are disabl ed to place the 73S8023C in its lowest power consumption mode. The PD mode is allowed only out of a card session (PWRDN high is ignored when CMDVCC = 0). Must be tied to ground when power down function is not used.

CLKDIV1 CLKDIV2

29 30

Sets the divide ratio from the XTALIN oscillator (or external clock input) to the card clock. These pins include pull-down resisto rs.

CLKDIV1 CLKDIV2 Clock Rate

OFF 22

Interrupt signal to the processor: Active Low. Multi-function indicating fault conditions and card presence. Open drain output configuration; it includes an

internal 20 kΩ pull-up to V RSTIN 19 Reset Input: This signal controls the RST signal to the card. I/OUC 26

AUX1UC 27

AUX2UC 28

CS 8

System controller data I/O to/from the card. Includes internal pull-up resistor

to V

DD.

System controller auxiliary data I/O to/ from the card. Includes internal pull-up

resistor to V

DD.

System controller auxiliary data I/O to/from the card. Includes internal pull-up

resistor to V

When CS = 1, the control and signal pins are configured normally. When CS

is set low, signals CMDVCC, RSTIN, PWRDN, 5V/#V, CLKDIV1, CLKDIV2,

CLKSEL are latched. I/OUC, AUX1UC, and AUX2UC are set to high

impedance pull-up mode and won’t pass data to or from the smart card. OFF

output is tri-stated. CLKSEL 16

Selects CLK and RST operational mode. When CLKSEL is low (default), the

circuit is configured for asynchronous card ope ration and the sequencer

manages the control of CLK and RST. When CLKSEL is high, the signal

CLK is a buffered copy of STROBE and the signal R S T i s directly controlled

by RSTIN. STROBE 25 When CLKSEL = 1, the signal CLK is controlled directly by STROBE. CLKOUT 32 CLKOUT is the buffered version of the signal on pi n XTALIN.

6 Rev. 1.5

DS_8023C_019 73S8023C Data Sheet

2 System Controller Interface

• The CS (chip select) input allows multiple devices to operate in parallel. When CS is high, the system interface signals operate as described. When CS is taken low, the system interface signals are latched internally. The pins I/OUC, AUX1UC, an d AUX2UC are weakly pulled up and the OFF signal is put into a high impedance state.

• The CLKSEL signal selects between synchronous and asynchronous operation. When CLKSE L i s low, asynchronous operation is selected. When CLKSEL is high, synchronous operation i s selected.

• Digital inputs allow direct control of the card interface from the host as follows:

 Pin CMDVCC: When set low, starts an activation sequence if a card is present.  Pin 5V/#V: Defines the card voltage.

• The card I/O and Reset signals have their corresponding controller I/Os to be connected directly to the host:

 Pin RSTIN: controls the card RST signal. When enabled by the sequencer, RST is equal to

RSTIN for both synchronous and asynchronous m odes.

 Pin I/OUC: data transfer to card I/O contact.  Pins AUX1UC and AUX2UC (auxiliary I/O l i nes as sociated to the auxiliary I/Os which are

connected to the C4 and C8 card connector contact s).

• Two digital inputs control the card clock frequency division rate: CLKDIV1 and CLKDIV2 define the card clock frequency from the input clock f requency (crystal or external clock). The division rate is defined as follows:

CLKDIV2 CLKDIV1 CLK

0 0 0 1 XTAL

1 0 ¼ XTAL 1 1 ½ XTAL

When the division rate is equal to 1 (CLKDIV2 =0 and CLKDIV 1 = 1), the duty-cycle of the card clock depends on the duty-cycle and wavefor m of the signal applied on the pin XTALIN. When other division rates are used, the 73S8023C circuitry guarantees a duty-cycle in the range 45% to 55%, conforming to ISO-7816-3 and E M V 4.1 specifications.

• Interrupt output to the host: As long as the card is not activated, the OFF pin informs the host about the card presence only (low = no card in the reader). When CMDVCC is set low (Card activation sequence requested from the host), a low level on OFF means a fault has been detected (e.g. card removedl during a card session, or voltage fault, or thermal / over-current fault) that automatically initiates a deactivation sequence.

• Power Down: The PWRDN pin is a digital input that allows the host controller to put the 73S8023C in its Power Down state. This pin can only be activated outside of a card session.

• The CLKOUT signal is a buffered output of the signal applied to the XTALIN pin whether it is an external clock source or it is configured as a cry st al oscillator. CLKOUT can be used when using multiple 73S8023C devices to share a single clock signal.

• The STROBE input directly drives the smart card CLK signal when operating in synchronous mode. STROBE is ignored in asynchronous mode.

⅛ XTAL

Rev. 1.5 7

73S8023C Data Sheet DS_8023C_019

Specification

3 Oscillator

The 73S8023C device has an on-chip oscillator that can generate the smart card clock using an ext ernal crystal (connected between the pins XTALIN and X TALOUT) to set the oscillator frequency. When the card clock signal is available from another source, i t can be connected to the pin XTALIN, and t he pi n XTALOUT should be left unconnected. Signal CLKOUT is the buffered version of the signal on XTALIN.

4 DC-DC Converter – Card Power Supply

An internal DC-DC converter provides the card powe r supply. This converter is able to provide either 3 V or 5 V card voltage from the power supply applied on the V controls the converter. Card voltage selection is carried out by the digital input 5V/#V.

The circuit is an inductive step-up converter/regulator. The external components required are 2 filter capacitors on the power-supply input V output filter capacitor on the card power supply V step-up operation when V and the input supply V

= 3.6 V, VCC =3 V) the circuit operates as a linear regulator.

is below a set point of 5.0 or 3.0 volts minus a comparator hysteresis voltage

is less than the set point for VCC. When VDD is greater than the set point for VCC

(next to the LIN pin, 100 nF + 10 µF), an inductor, and an

. The circuit performs regulation by activat ing the

Depending on the inductor values, the voltage converter can provide current on V The circuit provides over-current protect i on and l im i ts I sensed, the circuit initiates a deactivation sequence from the control logic and reports back t o the host controller a fault on the interrupt output OFF.

Choice of the inductor

The nominal inductor value is 10 µH, rated for 400 mA. The inductor is connected between LIN (pin 2) and the V (I

CC_MAX

supply voltage. The inductor value can be opt i m ized to meet a particular configuration

). The inductor should be located on the PCB as close a s possible to the LIN pin of the IC.

Choice of the V

capacitor

Depending on the applications, the requirements in terms of both the V transient currents that the interface must provide t o the card are different. shows the recommended capacitors for each V

power supply configuration and applicabl e specification.

Table 1: Choice of VCC Pin Capacitor

pin. The digital ISO-7816-3 sequencer

as high as 100 mA.

to 150 mA. When an over-current condition is

minimum voltage and the

Table 1

Specification Requirement Application

Min V

Allowed During

Transient Current

EMV 4.1 4.6 V 30 nAs ISO-7816-3 4.5 V 20 nAs NDS 4.65 V 40 nAs

Voltage

Max Transient

Current Charge

Capacitor

Type

X5R/X7R w/

ESR < 100 mΩ

Capacitor

Value

3.3 µF 1 µF

3.3 µF

8 Rev. 1.5

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