TERIDIAN Semiconductor 73S8009CN Technical data

73S8009CN

Combo ISO-

7816 and USB Universal

Smart Card Interface IC

Simplifying System In tegration™

DS_8009C_026 August 2009

DESCRIPTION

The Teridian 73S8009CN is the world’s first
single-chip smart car d electri cal interface circuit t hat
supports al l types of smart cards: 5V, 3V and 1 .8V,
including traditional ISO-7816-3 asynchronous and
synchronous type 1 and type 2, as well as USB,
ISO-7816-12 card s.

The 73S8009CN is ideally suited for applications
such as desktop com puters, laptops and gen er al
pu r pose sm ar t card r eaders that r equire low power
operat ion fr om a single 2.7V to 6.5V power supply
voltage sou r ce. A powe r down mode (“OFF” mode)
is available and exhibi ts a 10nA typ i cal cu r r ent
consumption.

The circuit provides control, conversion and regulation
of power for the smart card. In addition, the circuit
provides a 3.3V-regul ated volt age that is u sed as an
internal dig i tal supply voltage to t he host int er face . It is
also made available to supply power to so me external
circuitry (a host cont r ol ler for instance).

For asynchronous and synch r onous sm ar t card
operat ion, the sign als for RST, C LK, I/O and auxiliary
signals AUX1 an d AUX2 ar e directly controlled from
the host pr ocessor and are level-shifted by the circuit
to the selected V
the host processor is responsible for handling the
sig nal timing for smart card activation and de­activation und er norm al conditions.

The power management circuitry allows operation
from a sing l e power suppl y source V

is converted using an inductive, step-up power

V

PC

converter t o the intermedi ate voltag e, V
by linear volt age regul ators and swit ches i nternal to
the IC to create the voltages V

. VDD is used by the 73S8009CN an d i s also

V

CC

made available for the companion host processor
circuit or for other external circuits.

The 73S8009CN features an ON/OFF pin suitable to
connect to a “push-on/push-off” main system switch.
When the 73S8009CN is “OFF,” the typical current
drawn from VPC is 10nA. For appli cations that do
not implement any ON/OFF system switch, the
ON/ OFF input pin ca n be driven from a digital output
of the host processor.

value. For more design flexibilit y,

CC

(2.7V to 6.5V).

PC

. VP is used

P

and as r equi r ed,

DD

FEATURES

• Smart Card Interface:

 Smart card voltage V

o Selectable: 1.8V, 3V or 5V
o Gener ated by an in ternal voltage regulator
o Provid es up to 65m A to 3V and 5V cards

and up to 40m A to 1.8V ca r ds

 ISO-7816-3 ca r d emer gency deact i vation
 Volt age supervisor detects vol tage drop on

VCC (card supply)

 True card over-current detection 150mA max.
 1 input for a card presence detection switch
 Auxiliary I/O lines for synchronous and

ISO-7816-1 2 USB card support

 Proper isolation of smar t card sign al s

depending on smart card type

 Card CLK clock frequency up to 20MHz
 6kV ESD and short circuit protection on the

card inter face

• System Controller Interface:

 Digital logic level: 3 .3V
 5 si gnal images of the car d signals (RSTIN,

CLKIN, I/OUC, AUX1UC and AUX2UC)

 1 control signal to switch between

synchronous / asynchronous and
ISO-7816-12 USB smart card modes

 2 inputs activate and select t he card voltag e

(CMDVCC% and CMDVCC#)

 2 ou tputs, interr upt t o the syst em controller

(OFF and RDY), to inform the system
controller of the card presence / faults and
status of t he inter face

 1 Chip Select input
 2 handshaking signals (OFF_REQ,

OFF_ACK) for proper shutdown sequencing
of all smart card signals

• ON/OFF Input for a Main System Switch

• DC-DC Step-up Converter:

 Gener ates an inter mediary voltage VP
 Requires a sing le 10µH In duct or ( r ated for

400mA maximum peak current)

• VDD power supply output available to power up
external circuitry: 3.3V ±0.3V, 4 0 mA

• Indust r i al temp er ature range ( -40 °C to +85 °C)

• Small form at QFN32 package: 5x5mm

• RoHS compliant (6/6) lead-free package

DATA SH EET

:

CC

Rev. 1.4 © 20 09 Teridian Semicondu ctor Corpor ation 1

73S 8009CN Data Sh eet DS_8009CN_026

V

PC

V

DD

DP

V

CC

L

IN

RDY

CMDVCC#
CMDVCC%

Delay/

Debounce

Circuit

3.3V Regulator

CS

V

CC

Regulator

Linear/

DC - DC

Converter

V1.8ThREF

V3.0ThREF

V5.0ThREF

Analog

Mux

V

P

ON

OFF

V

P

SHUTDOWN

DM

+

-

10µF

0.47µF

4.7µF

10uH

I/O

RST

CLK

AUX1

AUX2

I/OUC
RSTIN
CLKIN

AUX1UC

AUX2UC

PRES

SC/USB

GND

GND

GND

OFF

Card

I/O

Buffer

and

Signal

Logic

0.1µF

0.1µF

ON/OFF

OFF_REQ

OFF_ACK

Debounce
and Latch

100K

Card

Supply

and

Control

Logic

0.1µF

Vcc Status

TEST1
TEST2

To Internal

Digital Logic

24K

FUNCTIONAL DIAGRAM

Figure 1: 73S8009C N Block Diagram

2 Rev. 1.4

DS_8009CN_026 73S8009CN Data Sheet

Table of Contents

1 Pinout ............................................................................................................................................. 5

2 Electrical Specifications ................................................................................................................ 9

2.1 Ab solute Maximum Rati ngs ..................................................................................................... 9

2.2 Recommended Oper ating Conditions ...................................................................................... 9

2.3 Smart Card Int er face Requ i r emen ts ...................................................................................... 10

2.4 Digital Signals Characteristics ............................................................................................... 12

2.5 DC Characteristics ................................................................................................................ 13

2.6 Volt age / Tem perature Fault Detection Circuit s ...................................................................... 13

2.7 Therm al Characteri stics ........................................................................................................ 13

3 Applications Information ............................................................................................................. 13

3.1 Example 73S8009CN Schematics ......................................................................................... 13

3.2 Power Supply and Converter ................................................................................................. 16

3.3 Interface Function - ON/OFF Modes ...................................................................................... 16

3.4 System Controller Interface ................................................................................................... 18

3.5 Card Power Suppl y and V ol tage Supervision......................................................................... 18

3.6 Activation and D e-activation Sequence ................................................................................. 19

3.7 OFF and F ault D etection ....................................................................................................... 20

3.8 Chip Selection ....................................................................................................................... 21

3.9 I/O Circuitry and Timing......................................................................................................... 22

4 Equivalent Circuits ...................................................................................................................... 24

5 Mechanical Drawing .................................................................................................................... 28

6 Ordering Information ................................................................................................................... 29

7 Related Documentation ............................................................................................................... 29

8 Contact Information ..................................................................................................................... 29

Rev. 1.4 3

73S 8009CN Data Sh eet DS_8009CN_026

Figures

Figure 1: 73S8009CN Block Diag r am ...................................................................................................... 2

Figure 2: 73S8009CN 32-Pin QFN Pinout
Figure 3: Typical 73S8009CN Application Schematic with a Main System Switch
Figure 4: Typical 73S8009CN Application Schematic without a Main System Switch
Figure 5: Activation Sequence
Figure 6: D eactivation Sequence
Figure 7: OFF Activity
Figure 8: CS Timing Definitions
Figure 9: I/O and I/OUC State Diagram
Figure 10: I/O – I/OUC Delays - Timing Diag ram
Figure 11: On_Off Pin
Figure 12: Open Drai n typ e – OFF and RDY
Figure 13: Po w e r Input/Outp ut Cir cuit, VDD, LIN, VPC, VCC, VP
Figure 14: USB – DM, DP Pins
Figure 15: Smart Card CLK Driver Circuit
Figure 16: Smart Card RS T Driver Circuit
Figure 17: Smart C ar d IO , AUX1, and AUX2 Interface Circuit
Figure 18: Smart Card IOUC, AUX1UC and AUX2UC Interface Circuit
Figure 19: General Input Circuit
Figur e 20: OF F _REQ Inte r face Cir cui t
Figur e 21: 32-Pin QFN Package Dimensions

Tables

Table 1: 73S8009CN Pin Definitions ........................................................................................................ 5

Table 2: Absolu te Maximum Device R atings
Table 3: Recommended Operating Conditions
Table 4: DC S mart Card Inter face Requirements
Table 5: Digital Signals Characteristics
Table 6: DC Characteristics
Table 7: Voltage / Temperature Fault D etection Circuits
Table 8: Thermal Char acte r i stics
Table 9: Order Num bers and Packaging Marks

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4 Rev. 1.4

DS_8009CN_026 73S8009CN Data Sheet

6

7

8

9

5

4

3

2

1

17

18

19

20

24

23

22

21

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

LIN

VPC

RDY

PRES

I/O

ON/OFF

DM

GND

VDD

RSTIN

OFF_ACK

AUX2

AUX1

GND

CLK

RST

VCC

VP

TERIDIAN

73S8009CN

TEST1

CLKIN

DP

AUX2UC

AUX1UC

I/OUC

CS

SC/USB

CMDVCC5

CMDVCC3

OFF_REQ

TEST2

GND

OFF

1 Pinout

The 73S8009CN is supplied as a 32-pi n QF N pa ckage.

Figure 2: 73S8 00 9C N 32-Pin QFN Pinout

Table 1 describes the pin functions for the device.

Table 1: 73S8009CN Pin Definitions

Pin
Name

Pin
Number

Type

Equivalent

Circuit

Description

Card Interface

I/O 22 IO Figure 17 Card I/O: Data signal to/from smart card. Includes

an 11kΩ pull-up resistor to V

CC

Will be tri-stated when SC/USB is set low.

AUX1 21 IO Figure 17 AUX1: Au xil iary data signal to/from smart card for

AUX2 20 IO Figure 17 AUX2: Auxiliary data signal to/from smart card for

synchronous smar t card operat ion. Smart card USB
DP signal for I S0-7816-12 U SB smart card operati on.
Includes an 11kΩ pull-up resistor to V

CC

for

synchronous / asynchronous operation only.

synchronous smar t card operat ion. Smart card USB

RST 18 O Figure 16 Card reset: provides reset (RS T) sign al to card. RST

DM signal for IS0-7816-12 US B smart card
operation. Includes an 11kΩ pull-up resistor to V
for synchronous / asynchronous oper ation only.

is the pass through signal on RSTIN. Internal con trol
logic will hold RST low when card is n ot act ivated or
VCC is too low. Will be tri-stated wh en SC/USB is
set low.

Rev. 1.4 5

CC

73S 8009CN Data Sh eet DS_8009CN_026

32

O

Figure 12

1

IO

Figure 18

2

IO

Figure 18

3

IO

Figure 18

Pin
Name

Pin
Number

Type

Equivalent

Circuit

Description

CLK 16 O Figure 15 Card clock: provides clock signal (C LK) to card. CLK

is the pass through of the signal on pi n CLKIN .
Internal con trol logic will hold CLK low when card is
not activated or VCC is too low. Will be tri-stated
when SC/USB is set low.

PRES 14 I Figure 19 S mart card Prese nce switch: Active high indi cates

card is present .
Smart card act i vation will not be permitted unless

PRES is active.

VCC 19 PSO Figure 13 Card power supply – logically control led by

sequence r , outp ut of LDO regulator. Requir es an
external 0.47uF low ES R filter ca pacitor to G N D.

GND 17 GND – Card ground.

Host Pro cesso r Interface

CS 12 I Figure 19 Chip Select. When CS = 1, the control and signal

pins are configured normally. When C S is set l ow,
CMDVCC%, RSTIN, and CMDVCC# are latched.
I/OUC, AUX1UC, and AUX2UC are set to
high-impedance pull-up mo de and do not pa ss data
to or fr om the smart card . Signals RDY and OFF are
disa bled to prevent a low outpu t and the internal
pull-up resistor s are disconnect ed. Shoul d be tied to
VDD when a single 73S8009CN is used.

OFF

Interrupt signal to th e processor. Active Low -
Multi-function indicating fault conditions and card
presence. Open drain output configuration – It
includes an internal 20kΩ pull-up to V

Pull-up i s

DD.

disabled in Power down state and CS = 0 modes.

I/OUC

AUX1UC

System controll er data I/O to/ from the card. Includes
an 11kΩ pull-up resistor to V

DD.

System controll er auxiliary data I/ O to/ from the card
for synchronous / asynchronous operation mode.
Connection to AUX1 is opened when SC/USB is low.

DD.

AUX2UC

Includes an 11kΩ pull-up resistor to V
System controll er auxiliary data I/ O to/ from the card

for synchronous / asynchronous operation mode.
Connection to AUX2 is opened when SC/USB is low.
Includes an 11kΩ pull-up resistor to V

DD.

SC/USB 13 I Figure 19 S mart Card In terface enable, USB interface disa ble.

Pin is provided with a weak pull-up.
When high, the 73S8009CN operates in

synchronous / asy nchronous operation m ode.
When low, CLK, RST I/O, AUX1, and AUX2 are

tri-stated. Pin AUX 1 is conn ected to pin DP and pin
AUX2 is connected to pin DM.

DP 25 IO Figure 14 USB D+ connection to / from USB cont r ol ler.

When SC/USB is set low, th is pin is electrically
connected to th e AUX1 pin, otherwise it is isolated.

6 Rev. 1.4

DS_8009CN_026 73S8009CN Data Sheet

6 I Figure 19

8 O Figure 12

Pin
Name

Pin
Number

Type

Equivalent

Circuit

Description

DM 23 IO Figure 14 USB D- conn ection to / from U SB con troller.

When SC/USB is set low, th is pin is electrically
connected to th e AUX1 pin, otherwise it is isolated.

CMDVCC%
CMDVCC#

4
5

I
I

Figure 19

Log i c low on on e or both of these pins will cause the
LDO regulator to ramp the Vcc supply t o the smart
card and smart car d inter face to the value described
in the following table:

CMDVCC% CMDVCC# Vcc Output Voltage
0 0 1.8V
0 1 5.0V
1 0 3.0V
1 1 Vcc Off

Note: See Card Power S upply and Voltag e
Supervision for m or e details.

RSTIN

Reset Input: This signal is the reset command to th e
card.

RDY

Signal to control l er ind i cating th e 73S8009CN is
ready because V

is above the required value aft er

CC

CMDVCC% and/or CMDVCC# is asser ted low. A
20kΩ pull-up resistor to V

is provided int ern ally.

DD

Pull-up is disabled in Power down state and CS=0
modes.

ON/OFF 24 I Figure 11 P owe r cont r ol pin . Connected to normal ly open

SPST switch to ground. Closing switch for duration
great er than de-bounce period will turn 73S8009CN
circuit “on”. If t he 73S8009CN i s “on,” closing the
switch will turn 73S8009CN to “off” state aft er the
de-bounce period and OFF_REQ/OFF_ACK
han dshake. Can be contr ol led b y a host processor
digital output.

OFF_REQ 11 O Figure 19 Digi tal output. Requ est to the host system control ler

to turn the 73S8009CN off. If ON_OFF switch is
closed (to ground) for de-bounce duration and circuit
is “on,” OFF_REQ will go high (request to turn OFF).
Connected to O FF_ACK via 100kΩ internal resi stor.

OFF_ACK 13 I Figure 19 S etting OFF_ ACK high will power “off” a ll analog

functions and disconnect the 73S8009CN from V

PC

The pin has an internal 100kΩ resistor connection to
OFF_REQ so that when not connected or n o host
interaction is requi r ed, th e Acknowledge wi l l be tr ue
and the circuit will turn “ off” after the deacti vation
sequence i s comp l eted.

Miscellaneous

.

CLKIN 7 I Figure 19 Clock signal source for the card clock.
TEST1 10 – – Fact ory test pin. This pin must be tied to GND.
TEST2 30 – – Fact ory test pin. This pin must be tied to GND.

Rev. 1.4 7

73S 8009CN Data Sh eet DS_8009CN_026

Pin
Name

Power Supply and Ground

VDD 29 PSO Figure 13 S ystem i nterface sup ply voltage output and supply

VPC 26 PSI Figure 13 Power supply source for main voltage co nverter

LIN 27 PSI Figure 13

VP 15 PSO Figure 13 In termediate output of main converter circuit.

GND 28, 31 GND – Ground.

Pin
Number

Type

Equivalent

Circuit

Description

voltage for co mpanion controller circuit (40mA
maximum so urce ca pability). R equi r es a minimum of
two 0.1µF capaci tors t o ground for proper
decoupling.

circuit. A 10µF and a 0.1µF ceramic capacit or must
be connected to this pin.

Connection to 10µH inductor for internal step up
converter. N ote: inductor mu st be rat ed for 400mA
maximum peak current.

Requires an external 4.7µF low ESR filter capacitor
to GND.

8 Rev. 1.4

DS_8009CN_026 73S8009CN Data Sheet

Parameter

Rating

Parameter

Rating

2 Electrical Specifications

This section provides the following:

 Absolute maximum ratings
 Recommended operating conditions
 Smart card inter face requirements
 Digital signals characteristics
 Volt age / temperature fault d etection cir cuits
 Therm al characteristics

2.1 Absolute Maximum Ratings

Table 2 l i sts the maximum operating condit ions for the 73S8009CN. Permanent device damage may
occur if absolute maxim um ratings are exceeded. Exposure to the extremes of the absol ute maximum
rating for extended p er iods may affect device reliability.

Table 2: Absolute Maximum Device Ratings

Sup ply Voltage VPC -0.5 to 7. 0 VDC
VDD -0.5 to 4. 0 VDC
Input Voltage for Di gital Inputs -0.3 to (VDD +0.5) VDC
Stor age Temperatu r e -65 to 150° C
Pin Voltag e ( except card interface) -0.3 to (VDD + 0.5) VDC
Pin Voltag e ( card interface) -0.3 to (VCC + 0.3) VDC
Pin Voltage, LIN pin 0.3 to 6.5 VDC
ESD Toleran ce – Card interface, DP and DM pins +/- 6kV
ESD Toleran ce – Other pins +/- 2kV
Pin Current, except LIN
Pin Cur r e nt, LIN + 500 mA in, -20 0 m A out

± 200 m A

2.2 Recommended Operating Conditions

Function operation should be restr icted to the r ecommended operating conditions sp ecified i n Table 3.

Table 3: Recommended Operating Conditions

Sup ply voltag e VPC 2.7 to 6.5 VDC
Ambient operating temperature -40°C to +85°C

Rev. 1.4 9