Terasic TSOM User Manual
TSoM User Manual
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TABLE OF CONTENTS
Chapter 1 Introduction ................................................................................................................... 2
1.1 TSoM Design Package ........................................................................................................................ 2
1.2 Getting Help ........................................................................................................................................ 2
Chapter 2 Board Specification ......................................................................................................... 3
2.1 Layout and Components ..................................................................................................................... 3
2.2 Block Diagram .................................................................................................................................... 3
2.3 Mechanical Specifications .................................................................................................................. 5
2.4 Power Requirement ............................................................................................................................. 5
Chapter 3 System Interface ............................................................................................................. 7
3.1 Device Configuration .......................................................................................................................... 7
3.2 Clock System .................................................................................................................................... 10
3.3 Reset System ..................................................................................................................................... 11
3.4 260-pin Edge Connector ................................................................................................................... 11
Chapter 4 HPS Fabric Components ............................................................................................... 13
4.1 USB 2.0 ............................................................................................................................................. 13
4.2 Gigabit Ethernet ................................................................................................................................ 14
4.3 eMMC ............................................................................................................................................... 15
4.4 HPS 3.3V GPIO ................................................................................................................................ 16
4.5 DDR3 ................................................................................................................................................ 18
Chapter 5 FPGA Fabric Components ............................................................................................. 21
5.1 DDR3 ................................................................................................................................................ 21
5.2 FPGA IOs on 260-Pin Edge Connector ............................................................................................ 23
TSoM User Manual
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March 8, 2019
Chapter 1
Introduction
TSoM (Terasic SoC System on Module) are small, integrated single-board computers with
Cyclone® V SoCs at the core. The SoC SoM includes DDR3 memory, flash memory, power
management, common interface controllers, and board support package (BSP) software to help you
create a fully customized embedded design without starting from scratch.
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The TSoM design package contains all the documents and supporting materials associated with
TSoM module, including the user manual, system builder, reference designs, and device datasheets.
Users can download this design package from the link: http://TSoM.terasic.com/cd.
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Here are the addresses where you can get help if you encounter any problems:
Terasic Technologies
9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
Email: support@terasic.com
Tel.: +886-3-575-0880
Website: TSoM.terasic.com
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Chapter 2
Board Specification
This chapter provides an introduction to the features and design characteristics of the module.
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Figure 2-1 shows a photograph of the module. It depicts the layout of the module and indicates the
location of the connectors and key components.
Note: The Cyclone® V system-on-a-chip (SoC) is composed of two distinct portions: a single or
dual-core Arm® Cortex® A9 hard processor system (HPS) and an FPGA. The HPS architecture
integrates a wide set of peripherals that reduce board size and increase performance within a
system.
Figure 2-1 Mechanical Layout of the TSoM Module
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Figure 2-2 is the block diagram of the module. The most FPGA I/Os of TSoM module are all
connected to the onboard 260-pin Edge connector, then it’s easy to connected to customer’s main
board.
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Figure 2-2 Block diagram of the TSoM Module
Detailed information about Figure 2-2 are listed below.
◼ Module:
⚫ FPGA: Cyclone V SE 5CSEBA6U23I7NDK (110K LEs)
⚫ Interface: DDR4 Edge (include 3.3V power source)
⚫ Dimension: 50 mm x 70 mm
◼ FPGA Fabric side:
⚫ DDR3 SDRAM 1GB, 32bit – 303MHz (Soft IP)
⚫ LVDS Transmitter x15 & LVDS Receiver x17 pairs & GPIO x3 ( Total GPIO x67)
⚫ Optional EPCS64
◼ HPS Fabric side:
⚫ Boot Selection DIP Switch: boot from eMMC or MicroSD Card
⚫ DDR3 SDRAM 1GB, 32bit - 400MHz
⚫ USB 2.0 PHY
⚫ Gigabit Ethernet PHY
⚫ 3.3V GPIO x25 (Can/UART/SPI/I2C/Trace Buses)
⚫ 1.5V GPI x4 (Input pins)
⚫ Optional eMMC 8GB
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Figure 2-3 is the Mechanical Layout of TSoM module and Table 2-1 shows the mechanical data of
the TSoM module.
Figure 2-3 Mechanical Layout of the TSoM Module
Table 2-1 Mechanical data of the TSoM Module
Symbol
Value
Size
70 x50mm
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The TSoM module is powered by the 260-pin edge connector. The user only needs to supply
3.3V/6A to the 260-pin edge connector of the TSoM module. The power circuit on the TSoM
module can convert 3.3V to 1.1V/1.2V/1.5V/1.8V/2.5V, which then is supplied to the FPGA and
other components. Figure 2-4 shows the power tree of TSoM module.
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Figure 2-4 Power Tree of the TSoM Module
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Chapter 3
System Interface
This chapter will introduce the system level interfaces on the TSoM module. Users can get the Boot
method of the HPS, the clock and reset system on the module, and the detailed pin distribution of
the 260-pin edge connector connected externally.
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This section describes the various interfaces on the TSoM module that can be configured with
FPGAs and HPS. Users can learn about the JTAG interface on TSoM module, the sources that can
be used as boot devices on the HPS side, and the configuration chips on the FPGA side through this
section.
◼ JTAG
Figure 3-1 is the JTAG interface on TSoM module, users can configure the FPGA from host PC
through the JTAG interface, the HPS is also included in the JTAG chain on TSoM module which
allows user to debug and develop the HPS ARM through the JTAG interface. The JTAG signals
come from the 260-pin edge connector, USB Blaster circuit or external Blaster connector need to be
reserved on customer’s main board for the JTAG communication with the FPGA on the TSoM
module.
Figure 3-1 JTAG Interface on the TSoM Module
◼ HPS Boot Mode
As shown in Figure 3-2, The TSoM module has two HPS boot source, one is the 8G eMMC
(Embedded Multimedia Card) memory, another is the external boot device on the 260-pin edge
connector. When the 260-pin edge connector is connected to the main board which contains
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external SD card socket or QSPI flash, the external SD card socket is used as the HPS boot source.
Only one of the two boot sources can be chosen for the boot source on TSoM board . User can
control the multiplexer and choose eMMC or external boot device as the boot source through SW1,
as shown in Table 3-1.
Figure 3-2 Boot Source on the TSoM Module
Table 3-1 SW1 Setting for Boot Source
SW1 Status
Boot Source
ON Position
eMMC device
OFF Position
External SD card
In addition, the QSPI interface on the TSoM HPS side is connected to the 260-pin edge connector
(HPS_V3P3_GPIO[24..19]), so user also can use the external QSPI flash as the HSP boot source by
connecting QSPI flash on the external main board to the TSoM 260-pin edge connector. But please
note that the HPS boot source setting control pins (HPS_BOOTSEL[2:0]) are by default set as
SD/MMC mode by the resistors, as shown in Figure 3-3. To set the external QSPI flash as the HPS
source, user needs to set HPS_BOOTSEL[2:0] as "111". Figure 3-4 shows the resistors setting.
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Figure 3-3 Using QSPI Flash as HPS boot source on the TSoM Module
Figure 3-4 HPS_BOTSEL[2..0] resistors setting
◼ EPCS
There is an EPCS64 configuration device reserved on the TSoM module. The EPCS device is a
flash memory device that can store configuration data that you use for FPGA configuration purpose
after powering on. You can use the EPCS device on all FPGAs that support AS x1configuration
scheme. User needs to modify the setting resistors of the FPGA MSEL pins if they want to use the
EPCS64 device. The factory setting of the MSEL[4:0] on the TSoM module is FPPx32 mode which
is used to configure FPGA from HPS. If user wants to the EPCS64 device, he can modify the
resistors as shown in Figure 3-5 to set the MSEL[4:0] as "10010" to switch to AS mode. Figure 3-6
and Figure 3-7 show the resistors actual position on the TSoM module (Top and Bottom Side).
Figure 3-5 MSEL[4:0] Setting Resistors (FPPx32 Mode)
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Figure 3-6 MSEL[4:0] Setting Resistors on the TSoM Module (Top Side)
Figure 3-7 MSEL[4:0] Setting Resistors on the TSoM Module (Bottom Side)
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The clock source on the TSoM module is provided by an Si5350C clock generator, which can
generate several groups of clocks for the devices on the TSoM module. The Si5350C generates
25MHz clock for the clock groups in the HPS, and provides two 50MHz clocks for the FPGA fabric
to drive customer’s design. Users also can multiple or devise the 50MHz clock through the FPGA
internal PLL. The Si5350C also provides clock for Ethernet PHY and USB OTG PHY.
Besides the Si5350C clock generator, users can input/output clock to the FPGA through the 260-pin
edge connector. There are four pairs LVDS clock inputs and two pairs LVDS clock outputs defined
on the 260-pin edge connector. These I/O are all connected to the dedicated clock pin of the FPGA
and can also be used as Single-end.
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Figure 3-8 Clock System of the TSoM Module
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The TSoM module provides warm reset and cold reset function for the HPS, as shown in the Figure
3-9. The cold reset comes from external mainboard and is used for HPS Ethernet PHY, USB OTG
PHY and eMMC memory through the 260-pin edge connector. The HPS_nRST pin is connected to
the 260-pin edge connector to be reserved for Intel DS-5 software tool to reset the HPS and connect
to the USB Blaster connector of the mainboard.
Figure 3-9 Reset System of the TSoM Module
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The TSoM module can be connected to external mainboard through the 260-pin edge connector
with the same specification (See Figure 3-10.), all the externally connected signals on the TSoM
module are communicated with and transferred to external main board through the edge connector,
which includes the FPGA and HPS I/O, the circuit of Ethernet PHY and USB OTG PHY, and also
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