Terasic TR10a-LPQ User Manual
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CONTENTS
Chapter 1 Overview ................................................................................... 4
1.1 General Description............................................................................... 4
1.2 Key Features ......................................................................................... 5
1.3 Block Diagram ....................................................................................... 6
Chapter 2 Board Components ................................................................. 9
2.1 Board Overview ..................................................................................... 9
2.2 Configuration, Status and Setup .......................................................... 10
2.3 General User Input/Output .................................................................. 14
2.4 Temperature Sensor and Fan Control .................................................. 17
2.5 Power Monitor ................................ ..................................................... 18
2.6 Clock Circuit ........................................................................................ 19
2.7 FLASH Memory ................................................................................... 22
2.8 QDRII+ SRAM ..................................................................................... 24
2.9 QSPF+ Ports ....................................................................................... 35
2.10 PCI Express ...................................................................................... 37
2.11 2x5 Timing Header ............................................................................ 40
Chapter 3 Flash Programming ............................................................... 41
3.1 FPGA Configure Operation .............................................................. 41
3.2 CFI Flash Memory Map .................................................................... 42
3.3 Flash Example Designs .................................................................... 43
3.4 Flash_Programming Example .......................................................... 44
3.5 Flash_Factory Example .................................................................... 45
3.6 Flash_User Example ........................................................................ 47
3.7 Flash_Tool Example ................................ ......................................... 48
3.8 Programming Batch File ................................................................... 48
3.9 Restore Factory Settings .................................................................. 49
Chapter 4 Peripheral Reference Design ................................................ 51
4.1 Configure Si5340A in RTL ................................................................... 51
4.2 Nios II control for SI5340 ..................................................................... 57
Chapter 5 Memory Reference Design .................................................... 60
5.1 QDRII+ SRAM Test ............................................................................. 60
5.2 QDRII+ SRAM Test by Nios II .............................................................. 63
Chapter 6 PCI Express Reference Design ............................................. 67
6.1 PCI Express System Infrastructure ...................................................... 67
6.2 PC PCI Express Software SDK ........................................................... 68
6.3 PCI Express Software Stack ............................................................... 69
6.4 PCIe Design - Fundamental ................................................................ 79
6.5 PCIe Design – QDRII+ ........................................................................ 86
6.6 PCIe Design: PCIe_Fundamental_x2 .................................................. 97
Chapter 7 Transceiver Verification ...................................................... 105
7.1 Function of the Transceiver Test Code .............................................. 105
7.2 Loopback Fixture ............................................................................... 105
7.3 Testing ............................................................................................... 107
Chapter 8 TR10a-LPQ Dashboard ........................................................ 109
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8.1 Dashboard Connected via USB Blaster II ........................................... 110
8.2 Dashboard Connected via UART ....................................................... 116
Additional Information ................................................................................ 128
Getting Help ............................................................................................ 128
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Chapter 1
Overview
his chapter provides an overview of the TR10a-LPQ Development Board and
installation guide.
1.1 General Description
The Terasic TR10a-LPQ Arria 10 GX FPGA Development Kit provides the ideal
hardware solution for designs that demand high capacity and bandwidth memory
interfacing, ultra-low latency communication, and power efficiency. With a Low-Profile
form-factor package, the TR10a-LPQ is designed for the most demanding high-end
applications, empowered with the top-of-the-line Altera Arria 10 GX, delivering the best
system-level integration and flexibility in the industry.
The Arria® 10 GX FPGA features integrated transceivers that transfer at a maximum of
12.5 Gbps, allowing the TR10a-LPQ to be fully compliant with version 3.0 of the PCI
Express standard, as well as allowing an ultra low-latency, straight connections to two
external 40G QSFP+ modules. Not relying on an external PHY will accelerate
mainstream development of network applications enabling customers to deploy designs
for a broad range of high-speed connectivity applications. For designs that demand high
capacity and high speed for memory and storage, the TR10a-LPQ delivers with five
independent banks of QDRII+ SRAM, high-speed parallel flash memory. The feature-
set of the TR10a-LPQ fully supports all high-intensity applications such as low-latency
trading, cloud computing, high-performance computing, data acquisition, network
processing, and signal processing.
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1.2 Key Features
The following hardware is implemented on the TR10a-LPQ board:
◼ FPGA
⚫ Altera Arria® 10 GX FPGA (10AX115N2F45E1SG)
◼ FPGA Configuration
⚫ On-Board USB Blaster II for FPGA programming
⚫ Fast passive parallel (FPPx16) configuration via MAX II CPLD and flash
memory
◼ General user input/output
⚫ 4 LEDs
⚫ 2 push-buttons
⚫ 2 dip switches
◼ Clock System
⚫ 50MHz Oscillator
⚫ Programmable clock generators Si5340A and Si53306
◼ Memory
⚫ QDRII+ SRAM
⚫ FLASH
◼ Communication Ports
⚫ Two QSFP+ connectors
⚫ Dual PCI Express (PCIe) x8 edge connector
⚫ One 2x5 GPIO timing expansion header
◼ System Monitor and Control
⚫ Temperature sensor
⚫ Fan control
⚫ Power monitor
⚫ UART to USB for board management
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◼ Power
⚫ PCI Express 4-pin power connector, 12V DC Input
⚫ PCI Express edge connector power
◼ Mechanical Specification
⚫ PCI Express Low-Profile x16
1.3 Block Diagram
Figure 1-1 shows the block diagram of the TR10a-LPQ board. To provide maximum
flexibility for the users, all key components are connected to the Arria 10 GX FPGA
device. Thus, users can configure the FPGA to implement any system design.
Figure 1-1 Block diagram of the TR10a-LPQ board
Below is more detailed information regarding the blocks in Figure 1-1.
◼ Arria 10 GX FPGA
⚫ 10AX115N2F45E1SG
⚫ 1,150K logic elements (LEs)
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⚫ 67-Mbits embedded memory
⚫ 48 transceivers (12.5Gbps)
⚫ 3,036 18-bit x 19-bit multipliers
⚫ 1,518 Variable-precision DSP blocks
⚫ 4 PCI Express hard IP blocks
⚫ 768 user I/Os
⚫ 384 LVDS channels
⚫ 32 phase locked loops (PLLs)
◼ FPGA Configuration
⚫ On-board USB Blaster II for use with the Quartus Prime Programmer
⚫ MAX 10 CPLD System Controller and Fast Passive Parallel (FPP x16)
configuration
◼ Memory devices
⚫ 40MB QDRII+ SRAM
⚫ 128MB FLASH
◼ General user I/O
⚫ 4 user controllable LEDs
⚫ 2 user push buttons
⚫ 2 user dip switches
◼ On-Board Clock
⚫ 50MHz oscillator
⚫ Programming PLL providing clock for 40G QSFP+ transceiver
⚫ Programming PLL providing clock for PCIe transceiver
⚫ Programming PLL providing clocks for QDRII+ SRAM
◼ Four QSFP+ ports
⚫ Two QSFP+ connector (40 Gbps+)
◼ Dual PCI Express x8 edge connector
⚫ Support for Dual PCIe x8 Gen1/2/3
⚫ Edge connector for PC motherboard with x16 PCI Express slot
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◼ System Monitor and Control
⚫ Temperature sensor
⚫ Fan control
⚫ Power monitor
⚫ UART to USB for board management
◼ Power Source
⚫ PCI Express 4-pin DC 12V power
⚫ PCI Express edge connector power
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Chapter 2
Board Components
his chapter introduces all the important components on the TR10a-LPQ.
2.1 Board Overview
Figure 2-1 and Figure 2-2 are the top and bottom view of the TR10a-LPQ development
board. It depicts the layout of the board and indicates the location of the connectors and
key components. Users can refer to this figure for relative location of the connectors
and key components.
Figure 2-1 FPGA Board (Top)
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Figure 2-2 FPGA Board (Bottom)
2.2 Configuration, Status and Setup
◼ Configure
The FPGA board supports two configuration methods for the Arria 10 FPGA:
⚫ Configure the FPGA using the on-board USB-Blaster II.
⚫ Flash memory configuration of the FPGA using stored images from the flash
memory on power-up.
For programming by on-board USB-Blaster II, the following procedures show how to
download a configuration bit stream into the Arria 10 GX FPGA:
⚫ Make sure that power is provided to the FPGA board
⚫ Connect your PC to the FPGA board using a micro-USB cable and make sure
the USB-Blaster II driver is installed on PC.
⚫ Launch Quartus Prime programmer and make sure the USB-Blaster II is
detected.
⚫ In Quartus Prime Programmer, add the configuration bit stream file (.sof),
check the associated “Program/Configure” item, and click “Start” to start
FPGA programming.
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◼ Status LED
The FPGA Board development board includes board-specific status LEDs to indicate
board status as shown in Figure 2-3. Please refer to Table 2-1 for the description of the
LED indicator.
Figure 2-3 Status LED on the TR10a-LPQ
Table 2-1 Status LED
Board
Reference
LED Name
Description
D10
12-V Power
Illuminates when 12-V power is active.
D9
3.3-V Power
Illuminates when 3.3-V power is active.
D6
LED_MAX_CONF_DONE
Illuminates when the FPGA is successfully
configured. Driven by the MAX 10 CPLD
System Controller.
D8
LED_MAX_LOAD
Illuminates when the MAX 10 CPLD System
Controller. is actively configuring the FPGA.
Driven by the MAX 10 CPLD System
Controller. with the Embedded Blaster CPLD.
D7
LED_MAX_ERROR
Illuminates when the MAX 10 CPLD System
Controller. fails to configure the FPGA. Driven
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by the MAX 10 CPLD System Controller.
D5
LED_BOOT_PAGE
Illuminates when FPGA is configured by the
factory configuration bit stream.
D3
LED_PR_DONE
Illuminates when FPGA partial reconfiguration
is done
D4
LED_CvP_CONFIG_DONE
Illuminates when FPGA Configuration via
Protocol (CvP) is done
LED6
LED_FPGA_PDN
Illuminates when the temperature of the FPGA
is too high and exceeds the set value, the
FPGA power is automatically turned off.
D1
JTAG_LED
Indicates transmit or receive activity of the
JTAG chain. The LED flickers if the link is in
use and active.
D2
FAN_ALERT_n
Illuminates when the temperature of the FPGA
exceeds the set value.
◼ Setup PCI Express Control DIP switch
The PCI Express Control DIP switch (S1) is provided to enable or disable different
configurations of the PCIe Connector. Table 2-2 lists the switch controls and description.
Figure 2-4 Setup PCI Express Control DIP switch
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Table 2-2 S1 PCIe Control DIP Switch
Board
Reference
Signal Name
Description
Default
S1.5
PCIE_PRSNT2n_x1
On : Enable x1 presence detect
Off: Disable x1 presence detect
Off
S1.6
PCIE_PRSNT2n_x4
On : Enable x4 presence detect
Off: Disable x4 presence detect
Off
S1.7
PCIE_PRSNT2n_x8
On : Enable x8 presence detect
Off: Disable x8 presence detect
Off
S1.8
PCIE_PRSNT2n_x16
On: Enable dual x8 presence
detect
Off: Disable dual x8 presence
detect
On
◼ Setup Configure Mode
The position 1~3 of DIP switch S1 are used to specify the configuration mode of the
FPGA. As currently only one mode is supported, please set all positions as shown in
Figure 2-5.
Figure 2-5 Position of DIP switch S1 for Configure Mode
◼ Select Flash Image for Configuration
The position 4 of DIP switch S1 is used to specify the image for configuration of the
FPGA. Setting Position 4 of S1 to “1” (down position) specifies the default factory image
to be loaded, as shown in Figure 2-6. Setting Position 4 of S1 to “0” (up position)
specifies the TR10a-LPQ to load a user-defined image, as shown in Figure 2-7.
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Figure 2-6 Position of DIP switch S1 for Image Select – Factory Image Load
Figure 2-7 Position of DIP switch S1 for Image Select – User Image Load
2.3 General User Input/Output
This section describes the user I/O interface to the FPGA.
◼ User Defined Push-buttons
The FPGA board includes four user defined push-buttons that allow users to interact
with the Arria 10 GX device. Each push-button provides a high logic level or a low logic
level when it is not pressed or pressed, respectively. Table 2-3 lists the board references,
signal names and their corresponding Arria 10 GX device pin numbers.
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Figure 2-8 User Defined Buttons
Table 2-3 Push-button Pin Assignments, Schematic Signal Names, and
Functions
Board
Reference
Schematic
Signal Name
Description
I/O
Standard
Arria 10 GX
Pin Number
PB0
BUTTON0
High Logic Level when the
button is not pressed
1.8-V
PIN_AR6
PB1
BUTTON1
1.8-V
PIN_AP6
PB4
CPU_RESET_n
1.8-V
AP24
◼ User-Defined Dip Switch
There are two dip switches on the FPGA board to provide additional FPGA input control.
When a dip switch is in the DOWN position or the UPPER position, it provides a high
logic level or a low logic level to the Arria 10 GX FPGA, respectively, as shown in Figure
2-9.
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Figure 2-9 2 Dip switches
Table 2-4 lists the signal names and their corresponding Arria 10 GX device pin
numbers.
Table 2-4 Dip Switch Pin Assignments, Schematic Signal Names, and Functions
Board
Reference
Schematic
Signal Name
Description
I/O
Standard
Arria 10 GX
Pin Number
SW0
SW0
High logic level when SW in the
UPPER position.
1.8-V
PIN_ AU35
SW1
1.8-V
PIN_AH33
◼ User-Defined LEDs
The FPGA board consists of 4 user-controllable LEDs to allow status and debugging
signals to be driven to the LEDs from the designs loaded into the Arria 10 GX device.
Each LED is driven directly by the Arria 10 GX FPGA. The LED is turned on or off when
the associated pins are driven to a low or high logic level, respectively, as shown in
Figure 2-10. A list of the pin names on the FPGA that are connected to the LEDs is
given in Table 2-5.
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Figure 2-10 Four User LEDs
Table 2-5 User LEDs Pin Assignments, Schematic Signal Names, and Functions
Board
Reference
Schematic
Signal Name
Description
I/O
Standard
Arria 10 GX
Pin Number
LED0
LED0
Driving a logic 0 on the I/O port
turns the LED ON.
Driving a logic 1 on the I/O port
turns the LED OFF.
1.8-V
PIN_Y13
LED1
LED1
1.8-V
PIN_Y14
LED2
LED2
1.8-V
PIN_W11
LED3
LED3
1.8-V
PIN_V10
2.4 Temperature Sensor and Fan Control
The TR10a-LPQ has an automatic management system for the temperature of the
FPGA, the fan speed, and the power supply of the FPGA. As shown in Figure 2-11. The
MAX10 FPGA is the main control device on the board.
The temperature of the Arria 10 FPGA is obtained through the TMP441 temperature
sensor and the MAX10 FPGA can read it from TMP441 via I2C bus. The MAX10 FPGA
will adjust the fan speed automatically according to the temperature of the Arria 10
FPGA.
When the board power is on, the fan speed is preset to 3000 rpm. As the temperature
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of the Arria10 FPGA rises, the MAX10 will increase the fan speed to decrease the
temperature of the FPGA.
In order to avoid the failure of the fan on the FPGA and stop the rotation and cause the
FPGA temperature to rise rapidly. When the FPGA temperature reaches 95 degrees
(The setting threshold value), the MAX10 will cut off the power supply to the Arria10
FPGA to avoid damage caused by excessive FPGA temperature.
Figure 2-11 The Temperature, Fan Speed and FPGA power control system
2.5 Power Monitor
The TR10a-LPQ has implemented a power monitor chip to monitor the board input
power voltage and current. Figure 2-12 shows the connection between the power
monitor chip and the Arria 10 GX FPGA. The power monitor chip monitors both shunt
voltage drops and board input power voltage allows user to monitor the total board
power consumption. Programmable calibration value, conversion times, and averaging,
combined with an internal multiplier, enable direct readouts of current in amperes and
power in watts. Table 2-6 shows the pin assignment of power monitor I2C bus.
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Figure 2-12 Connections between the Power Monitor chip and the Arria 10 GX
FPGA
Table 2-6 Pin Assignment of Power Monitor I2C bus
Schematic
Signal Name
Description
I/O
Standard
Arria 10 GX
Pin Number
POWER_MONITOR_I2C_SCL
Power Monitor SCL
1.8V
PIN_AT26
POWER_MONITOR_I2C_SDA
Power Monitor SDA
1.8V
PIN_AP25
POWER_MONITOR_ALERT_N
Power Monitor ALERT
1.8V
PIN_BD23
2.6 Clock Circuit
The development board includes four 50 MHz oscillators and two programmable clock
generators. Figure 2-13 shows the default frequencies of on-board all external clocks
going to the Arria 10 GX FPGA.
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Figure 2-13 Clock circuit of the FPGA Board
A clock buffer is used to duplicate the 50 MHz oscillator, so there are six 50MHz clocks
fed into different five FPGA banks. The two programming clock generators are low-jitter
oscillators which are used to provide special and high quality clock signals for high-
speed transceivers and high bandwidth memory. Through I2C serial interface, the clock
generator controllers in the Arria 10 GX FPGA can be used to program the Si5340A and
Si5340B to generate 40G Ethernet QSFP+ and high bandwidth memory reference
clocks respectively.
Table 2-7 lists the clock source, signal names, default frequency and their
corresponding Arria 10 GX device pin numbers.
Table 2-7 Clock Source, Signal Name, Default Frequency, Pin Assignments and
Functions
Source
Schematic
Signal Name
Default
Frequency
I/O
Standard
Arria 10 GX
Pin
Number
Application
U38
CLK_50_B2H
50.0 MHz
1.8V
PIN_AP34
User Application
CLK_50_B2I
1.8V
PIN_C30
User Application
CLK_50_B2J
1.8V
PIN_W36
User Application
CLK_50_B3C
1.8V
PIN_AK12
User Application
CLK_50_B3D
1.8V
PIN_AJ11
User Application
Y6
CLK_100_B2J
100.0MHz
1.8V
PIN_AC32
User Application
Y2
OSC_100_CLKUSR
100.0MHz
1.8V
PIN_AV26
User-supplied
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configuration
clock
U2
(Si5340A)
QSFPA_REFCLK_p
644.53125
MHz
LVDS
PIN_AH5
40G QSFP+ A
port
QSFPB_REFCLK_p
644.53125
MHz
LVDS
PIN_AD5
40G QSFP+ B
port
QDRIIE_REFCLK_p
275 MHz
LVDS
PIN_AT27
QDRII+ reference
clock for E port
U13
QDRIIA_REFCLK_p
275 MHz
LVDS
PIN_L9
QDRII+ reference
clock for A port
QDRIIB_REFCLK_p
275 MHz
LVDS
PIN_N18
QDRII+ reference
clock for B port
QDRIIC_REFCLK_p
275 MHz
LVDS
PIN_M34
QDRII+ reference
clock for C port
QDRIID_REFCLK_p
275 MHz
LVDS
PIN_BB18
QDRII+ reference
clock for D port
Table 2-8 lists the programmable oscillator control pins, signal names, I/O standard and
their corresponding Arria 10 GX device pin numbers.
Table 2-8 Programmable oscillator control pin, Signal Name, I/O standard, Pin
Assignments and Descriptions
Programmable
Oscillator
Schematic
Signal Name
I/O
Standard
Arria 10 GX
Pin Number
Description
Si5340A
(U2)
Si5340A_I2C_SCL
1.8-V
PIN_F24
I2C bus, connected
with Si5340A
Si5340A_I2C_SDA
1.8-V
PIN_G24
Si5340A_RST
1.8-V
PIN_C27
Si5340A reset
signal
Si5340A_INTR
1.8-V
PIN_C28
Si5340A interrupt
signal
Si5340A_OE_n
1.8-V
PIN_AP39
Si5340A output
enable signal
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2.7 FLASH Memory
The development board has one 1Gb CFI-compatible synchronous flash device for non-
volatile storage of FPGA configuration data, user application data, and user code space.
Each interface has a 16-bit data bus and the device combined allow for FPP x16
configuration. This device is part of the shared flash and MAX (FM) bus, which connects
to the flash memory and MAX V CPLD System Controller. Figure 2-14 shows the
connections between the Flash, MAX and Arria 10 GX FPGA.
Figure 2-14 Connection between the Flash, Max and Arria 10 GX FPGA
Table 2-9 lists the flash pin assignments, signal names, and functions.
Table 2-9 Flash Memory Pin Assignments, Schematic Signal Names, and
Functions
Schematic
Signal Name
Description
I/O Standard
Arria 10 GX Pin
Number
FLASH_A1
Address bus
1.8-V
PIN_AE14
FLASH_A2
Address bus
1.8-V
PIN_AT7
FLASH_A3
Address bus
1.8-V
PIN_AC11
FLASH_A4
Address bus
1.8-V
PIN_AC13
FLASH_A5
Address bus
1.8-V
PIN_AC12
FLASH_A6
Address bus
1.8-V
PIN_AF14
FLASH_A7
Address bus
1.8-V
PIN_AD13
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FLASH_A8
Address bus
1.8-V
PIN_AG14
FLASH_A9
Address bus
1.8-V
PIN_AJ13
FLASH_A10
Address bus
1.8-V
PIN_AE13
FLASH_A11
Address bus
1.8-V
PIN_AB14
FLASH_A12
Address bus
1.8-V
PIN_AH12
FLASH_A13
Address bus
1.8-V
PIN_AK13
FLASH_A14
Address bus
1.8-V
PIN_AL12
FLASH_A15
Address bus
1.8-V
PIN_AV7
FLASH_A16
Address bus
1.8-V
PIN_AJ10
FLASH_A17
Address bus
1.8-V
PIN_AH13
FLASH_A18
Address bus
1.8-V
PIN_AN12
FLASH_A19
Address bus
1.8-V
PIN_AU9
FLASH_A20
Address bus
1.8-V
PIN_AV6
FLASH_A21
Address bus
1.8-V
PIN_AT6
FLASH_A22
Address bus
1.8-V
PIN_AR9
FLASH_A23
Address bus
1.8-V
PIN_AB13
FLASH_A24
Address bus
1.8-V
PIN_AF12
FLASH_A25
Address bus
1.8-V
PIN_AT9
FLASH_A26
Address bus
1.8-V
PIN_AV8
FLASH_A27
Address bus (Reserve)
1.8-V
PIN_AB12
FLASH_D0
Data bus
1.8-V
PIN_AN11
FLASH_D1
Data bus
1.8-V
PIN_AT12
FLASH_D2
Data bus
1.8-V
PIN_AP8
FLASH_D3
Data bus
1.8-V
PIN_AT11
FLASH_D4
Data bus
1.8-V
PIN_AR11
FLASH_D5
Data bus
1.8-V
PIN_AR7
FLASH_D6
Data bus
1.8-V
PIN_AU8
FLASH_D7
Data bus
1.8-V
PIN_AR8
FLASH_D8
Data bus
1.8-V
PIN_AN10
FLASH_D9
Data bus
1.8-V
PIN_AR12
FLASH_D10
Data bus
1.8-V
PIN_AP10
FLASH_D11
Data bus
1.8-V
PIN_AP11
FLASH_D12
Data bus
1.8-V
PIN_AT10
FLASH_D13
Data bus
1.8-V
PIN_AP9
FLASH_D14
Data bus
1.8-V
PIN_AU7
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FLASH_D15
Data bus
1.8-V
PIN_AU10
FLASH_CLK
Clock
1.8-V
PIN_AM12
FLASH_RESET_n
Reset
1.8-V
PIN_AE12
FLASH_CE_n
Chip enable of flash
1.8-V
PIN_AL11
FLASH_OE_n
Output enable
1.8-V
PIN_AH10
FLASH_WE_n
Write enable
1.8-V
PIN_AG12
FLASH_ADV_n
Address valid
1.8-V
PIN_AD14
FLASH_RDY_BS
Y_n
Ready of flash
1.8-V
PIN_AG13
2.8 QDRII+ SRAM
The development board supports five independent QDRII+ SRAM memory devices for
very-high speed and low-latency memory access. Each of QDRII+ has a x18 interface,
providing addressing to a device of up to a 8MB (not including parity bits). The QDRII+
has separate read and write data ports with DDR signaling at up to 550 MHz.
Table 2-10, Table 2-11, Table 2-12, Table 2-13 and
Table 2-14 lists the QDRII+ SRAM Bank A, B, C, D and E pin assignments, signal
names relative to the Arria 10 GX device, in respectively.
Table 2-10 QDRII+ SRAM A Pin Assignments, Schematic Signal Names, and
Functions
Schematic
Signal Name
Description
I/O Standard
Arria 10 GX Pin
Number
QDRIIA_A0
Address bus[0]
1.8-V HSTL Class I
PIN_V12
QDRIIA_A1
Address bus[1]
1.8-V HSTL Class I
PIN_V13
QDRIIA_A2
Address bus[2]
1.8-V HSTL Class I
PIN_N10
QDRIIA_A3
Address bus[3]
1.8-V HSTL Class I
PIN_M10
QDRIIA_A4
Address bus[4]
1.8-V HSTL Class I
PIN_P11
QDRIIA_A5
Address bus[5]
1.8-V HSTL Class I
PIN_N11
QDRIIA_A6
Address bus[6]
1.8-V HSTL Class I
PIN_M9
QDRIIA_A7
Address bus[7]
1.8-V HSTL Class I
PIN_M8
QDRIIA_A8
Address bus[8]
1.8-V HSTL Class I
PIN_N7
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QDRIIA_A9
Address bus[9]
1.8-V HSTL Class I
PIN_N8
QDRIIA_A10
Address bus[10]
1.8-V HSTL Class I
PIN_P10
QDRIIA_A11
Address bus[11]
1.8-V HSTL Class I
PIN_P9
QDRIIA_A12
Address bus[12]
1.8-V HSTL Class I
PIN_N6
QDRIIA_A13
Address bus[13]
1.8-V HSTL Class I
PIN_M7
QDRIIA_A14
Address bus[14]
1.8-V HSTL Class I
PIN_L10
QDRIIA_A15
Address bus[15]
1.8-V HSTL Class I
PIN_L7
QDRIIA_A16
Address bus[16]
1.8-V HSTL Class I
PIN_K7
QDRIIA_A17
Address bus[17]
1.8-V HSTL Class I
PIN_K8
QDRIIA_A18
Address bus[18]
1.8-V HSTL Class I
PIN_J9
QDRIIA_A19
Address bus[19]
1.8-V HSTL Class I
PIN_L6
QDRIIA_A20
Address bus[20]
1.8-V HSTL Class I
PIN_K6
QDRIIA_A21
Address bus[21]
1.8-V HSTL Class I
PIN_J6
QDRIIA_D0
Write data bus[0]
1.8-V HSTL Class I
PIN_C13
QDRIIA_D1
Write data bus[1]
1.8-V HSTL Class I
PIN_D13
QDRIIA_D2
Write data bus[2]
1.8-V HSTL Class I
PIN_E13
QDRIIA_D3
Write data bus[3]
1.8-V HSTL Class I
PIN_B13
QDRIIA_D4
Write data bus[4]
1.8-V HSTL Class I
PIN_E11
QDRIIA_D5
Write data bus[5]
1.8-V HSTL Class I
PIN_C12
QDRIIA_D6
Write data bus[6]
1.8-V HSTL Class I
PIN_B12
QDRIIA_D7
Write data bus[7]
1.8-V HSTL Class I
PIN_A12
QDRIIA_D8
Write data bus[8]
1.8-V HSTL Class I
PIN_D11
QDRIIA_D9
Write data bus[9]
1.8-V HSTL Class I
PIN_E9
QDRIIA_D10
Write data bus[10]
1.8-V HSTL Class I
PIN_C8
QDRIIA_D11
Write data bus[11]
1.8-V HSTL Class I
PIN_D8
QDRIIA_D12
Write data bus[12]
1.8-V HSTL Class I
PIN_D9
QDRIIA_D13
Write data bus[13]
1.8-V HSTL Class I
PIN_D10
QDRIIA_D14
Write data bus[14]
1.8-V HSTL Class I
PIN_B10
QDRIIA_D15
Write data bus[15]
1.8-V HSTL Class I
PIN_A10
QDRIIA_D16
Write data bus[16]
1.8-V HSTL Class I
PIN_A11
QDRIIA_D17
Write data bus[17]
1.8-V HSTL Class I
PIN_C11
QDRIIA_Q0
Read Data bus[0]
1.8-V HSTL Class I
PIN_H12
QDRIIA_Q1
Read Data bus[1]
1.8-V HSTL Class I
PIN_K12
QDRIIA_Q2
Read Data bus[2]
1.8-V HSTL Class I
PIN_J14
QDRIIA_Q3
Read Data bus[3]
1.8-V HSTL Class I
PIN_H11
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QDRIIA_Q4
Read Data bus[4]
1.8-V HSTL Class I
PIN_K13
QDRIIA_Q5
Read Data bus[5]
1.8-V HSTL Class I
PIN_G10
QDRIIA_Q6
Read Data bus[6]
1.8-V HSTL Class I
PIN_L12
QDRIIA_Q7
Read Data bus[7]
1.8-V HSTL Class I
PIN_P13
QDRIIA_Q8
Read Data bus[8]
1.8-V HSTL Class I
PIN_M13
QDRIIA_Q9
Read Data bus[9]
1.8-V HSTL Class I
PIN_T14
QDRIIA_Q10
Read Data bus[10]
1.8-V HSTL Class I
PIN_R13
QDRIIA_Q11
Read Data bus[11]
1.8-V HSTL Class I
PIN_R12
QDRIIA_Q12
Read Data bus[12]
1.8-V HSTL Class I
PIN_R14
QDRIIA_Q13
Read Data bus[13]
1.8-V HSTL Class I
PIN_N13
QDRIIA_Q14
Read Data bus[14]
1.8-V HSTL Class I
PIN_M14
QDRIIA_Q15
Read Data bus[15]
1.8-V HSTL Class I
PIN_N12
QDRIIA_Q16
Read Data bus[16]
1.8-V HSTL Class I
PIN_L14
QDRIIA_Q17
Read Data bus[17]
1.8-V HSTL Class I
PIN_M12
QDRIIA_BWS_n0
Byte Write select[0]
1.8-V HSTL Class I
PIN_C10
QDRIIA_BWS_n1
Byte Write select[1]
1.8-V HSTL Class I
PIN_E8
QDRIIA_K_P
Clock P
Differential 1.8-V HSTL
Class I
PIN_F12
QDRIIA_K_N
Clock N
Differential 1.8-V HSTL
Class I
PIN_E12
QDRIIA_CQ_P
Echo clock P
1.8-V HSTL Class I
PIN_J13
QDRIIA_CQ_N
Echo clock N
1.8-V HSTL Class I
PIN_H13
QDRIIA_RPS_n
Report Select
1.8-V HSTL Class I
PIN_U9
QDRIIA_WPS_n
Write Port Select
1.8-V HSTL Class I
PIN_U8
QDRIIA_DOFF_n
DLL enable
1.8-V HSTL Class I
PIN_R9
QDRIIA_ODT
On-Die Termination
Input
1.8-V HSTL Class I
PIN_T10
QDRIIA_QVLD
Valid Output
1.8-V HSTL Class I
PIN_K14
Table 2-11 QDRII+ SRAM B Pin Assignments, Schematic Signal Names, and
Functions
Schematic
Signal Name
Description
I/O Standard
Arria 10 GX Pin
Number
QDRIIB_A0
Address bus[0]
1.8-V HSTL Class I
PIN_L16
QDRIIB_A1
Address bus[1]
1.8-V HSTL Class I
PIN_L15
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QDRIIB_A2
Address bus[2]
1.8-V HSTL Class I
PIN_E14
QDRIIB_A3
Address bus[3]
1.8-V HSTL Class I
PIN_D14
QDRIIB_A4
Address bus[4]
1.8-V HSTL Class I
PIN_G14
QDRIIB_A5
Address bus[5]
1.8-V HSTL Class I
PIN_F14
QDRIIB_A6
Address bus[6]
1.8-V HSTL Class I
PIN_D15
QDRIIB_A7
Address bus[7]
1.8-V HSTL Class I
PIN_C15
QDRIIB_A8
Address bus[8]
1.8-V HSTL Class I
PIN_F15
QDRIIB_A9
Address bus[9]
1.8-V HSTL Class I
PIN_F16
QDRIIB_A10
Address bus[10]
1.8-V HSTL Class I
PIN_H15
QDRIIB_A11
Address bus[11]
1.8-V HSTL Class I
PIN_G15
QDRIIB_A12
Address bus[12]
1.8-V HSTL Class I
PIN_E16
QDRIIB_A13
Address bus[13]
1.8-V HSTL Class I
PIN_D16
QDRIIB_A14
Address bus[14]
1.8-V HSTL Class I
PIN_E17
QDRIIB_A15
Address bus[15]
1.8-V HSTL Class I
PIN_G17
QDRIIB_A16
Address bus[16]
1.8-V HSTL Class I
PIN_G18
QDRIIB_A17
Address bus[17]
1.8-V HSTL Class I
PIN_L17
QDRIIB_A18
Address bus[18]
1.8-V HSTL Class I
PIN_K17
QDRIIB_A19
Address bus[19]
1.8-V HSTL Class I
PIN_H17
QDRIIB_A20
Address bus[20]
1.8-V HSTL Class I
PIN_H18
QDRIIB_A21
Address bus[21]
1.8-V HSTL Class I
PIN_K18
QDRIIB_D0
Write data bus[0]
1.8-V HSTL Class I
PIN_C18
QDRIIB_D1
Write data bus[1]
1.8-V HSTL Class I
PIN_G19
QDRIIB_D2
Write data bus[2]
1.8-V HSTL Class I
PIN_J19
QDRIIB_D3
Write data bus[3]
1.8-V HSTL Class I
PIN_D19
QDRIIB_D4
Write data bus[4]
1.8-V HSTL Class I
PIN_K19
QDRIIB_D5
Write data bus[5]
1.8-V HSTL Class I
PIN_L19
QDRIIB_D6
Write data bus[6]
1.8-V HSTL Class I
PIN_B20
QDRIIB_D7
Write data bus[7]
1.8-V HSTL Class I
PIN_M19
QDRIIB_D8
Write data bus[8]
1.8-V HSTL Class I
PIN_B19
QDRIIB_D9
Write data bus[9]
1.8-V HSTL Class I
PIN_N20
QDRIIB_D10
Write data bus[10]
1.8-V HSTL Class I
PIN_M20
QDRIIB_D11
Write data bus[11]
1.8-V HSTL Class I
PIN_L21
QDRIIB_D12
Write data bus[12]
1.8-V HSTL Class I
PIN_L20
QDRIIB_D13
Write data bus[13]
1.8-V HSTL Class I
PIN_F20
QDRIIB_D14
Write data bus[14]
1.8-V HSTL Class I
PIN_F19
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QDRIIB_D15
Write data bus[15]
1.8-V HSTL Class I
PIN_H20
QDRIIB_D16
Write data bus[16]
1.8-V HSTL Class I
PIN_J20
QDRIIB_D17
Write data bus[17]
1.8-V HSTL Class I
PIN_G20
QDRIIB_Q0
Read Data bus[0]
1.8-V HSTL Class I
PIN_G23
QDRIIB_Q1
Read Data bus[1]
1.8-V HSTL Class I
PIN_F21
QDRIIB_Q2
Read Data bus[2]
1.8-V HSTL Class I
PIN_G22
QDRIIB_Q3
Read Data bus[3]
1.8-V HSTL Class I
PIN_H23
QDRIIB_Q4
Read Data bus[4]
1.8-V HSTL Class I
PIN_H21
QDRIIB_Q5
Read Data bus[5]
1.8-V HSTL Class I
PIN_H22
QDRIIB_Q6
Read Data bus[6]
1.8-V HSTL Class I
PIN_J23
QDRIIB_Q7
Read Data bus[7]
1.8-V HSTL Class I
PIN_K22
QDRIIB_Q8
Read Data bus[8]
1.8-V HSTL Class I
PIN_L22
QDRIIB_Q9
Read Data bus[9]
1.8-V HSTL Class I
PIN_B23
QDRIIB_Q10
Read Data bus[10]
1.8-V HSTL Class I
PIN_A21
QDRIIB_Q11
Read Data bus[11]
1.8-V HSTL Class I
PIN_F22
QDRIIB_Q12
Read Data bus[12]
1.8-V HSTL Class I
PIN_E22
QDRIIB_Q13
Read Data bus[13]
1.8-V HSTL Class I
PIN_C21
QDRIIB_Q14
Read Data bus[14]
1.8-V HSTL Class I
PIN_A22
QDRIIB_Q15
Read Data bus[15]
1.8-V HSTL Class I
PIN_E23
QDRIIB_Q16
Read Data bus[16]
1.8-V HSTL Class I
PIN_B22
QDRIIB_Q17
Read Data bus[17]
1.8-V HSTL Class I
PIN_C22
QDRIIB_BWS_n0
Byte Write select[0]
1.8-V HSTL Class I
PIN_C20
QDRIIB_BWS_n1
Byte Write select[1]
1.8-V HSTL Class I
PIN_E19
QDRIIB_K_p
Clock P
Differential 1.8-V HSTL
Class I
PIN_K21
QDRIIB_K_n
Clock N
Differential 1.8-V HSTL
Class I
PIN_J21
QDRIIB_CQ_p
Echo clock P
1.8-V HSTL Class I
PIN_D23
QDRIIB_CQ_n
Echo clock N
1.8-V HSTL Class I
PIN_C23
QDRIIB_RPS_n
Report Select
1.8-V HSTL Class I
PIN_J16
QDRIIB_WPS_n
Write Port Select
1.8-V HSTL Class I
PIN_K16
QDRIIB_DOFF_n
PLL Turn Off
1.8-V HSTL Class I
PIN_H16
QDRIIB_ODT
On-Die Termination
Input
1.8-V HSTL Class I
PIN_M17
QDRIIB_QVLD
Valid Output
1.8-V HSTL Class I
PIN_K23
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Indicator
Table 2-12 QDRII+ SRAM C Pin Assignments, Schematic Signal Names, and
Functions
Schematic
Signal Name
Description
I/O Standard
Arria 10 GX Pin
Number
QDRIIC_A0
Address bus[0]
1.8-V HSTL Class I
PIN_Y32
QDRIIC_A1
Address bus[1]
1.8-V HSTL Class I
PIN_W33
QDRIIC_A2
Address bus[2]
1.8-V HSTL Class I
PIN_P34
QDRIIC_A3
Address bus[3]
1.8-V HSTL Class I
PIN_P33
QDRIIC_A4
Address bus[4]
1.8-V HSTL Class I
PIN_L32
QDRIIC_A5
Address bus[5]
1.8-V HSTL Class I
PIN_K32
QDRIIC_A6
Address bus[6]
1.8-V HSTL Class I
PIN_R34
QDRIIC_A7
Address bus[7]
1.8-V HSTL Class I
PIN_R33
QDRIIC_A8
Address bus[8]
1.8-V HSTL Class I
PIN_T32
QDRIIC_A9
Address bus[9]
1.8-V HSTL Class I
PIN_R32
QDRIIC_A10
Address bus[10]
1.8-V HSTL Class I
PIN_N32
QDRIIC_A11
Address bus[11]
1.8-V HSTL Class I
PIN_M32
QDRIIC_A12
Address bus[12]
1.8-V HSTL Class I
PIN_T31
QDRIIC_A13
Address bus[13]
1.8-V HSTL Class I
PIN_R31
QDRIIC_A14
Address bus[14]
1.8-V HSTL Class I
PIN_K38
QDRIIC_A15
Address bus[15]
1.8-V HSTL Class I
PIN_L37
QDRIIC_A16
Address bus[16]
1.8-V HSTL Class I
PIN_K36
QDRIIC_A17
Address bus[17]
1.8-V HSTL Class I
PIN_N33
QDRIIC_A18
Address bus[18]
1.8-V HSTL Class I
PIN_M33
QDRIIC_A19
Address bus[19]
1.8-V HSTL Class I
PIN_L39
QDRIIC_A20
Address bus[20]
1.8-V HSTL Class I
PIN_K39
QDRIIC_A21
Address bus[21]
1.8-V HSTL Class I
PIN_L35
QDRIIC_D0
Write data bus[0]
1.8-V HSTL Class I
PIN_E34
QDRIIC_D1
Write data bus[1]
1.8-V HSTL Class I
PIN_D36
QDRIIC_D2
Write data bus[2]
1.8-V HSTL Class I
PIN_E36
QDRIIC_D3
Write data bus[3]
1.8-V HSTL Class I
PIN_D35
QDRIIC_D4
Write data bus[4]
1.8-V HSTL Class I
PIN_E37
QDRIIC_D5
Write data bus[5]
1.8-V HSTL Class I
PIN_F39
QDRIIC_D6
Write data bus[6]
1.8-V HSTL Class I
PIN_F37
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QDRIIC_D7
Write data bus[7]
1.8-V HSTL Class I
PIN_G39
QDRIIC_D8
Write data bus[8]
1.8-V HSTL Class I
PIN_F36
QDRIIC_D9
Write data bus[9]
1.8-V HSTL Class I
PIN_G30
QDRIIC_D10
Write data bus[10]
1.8-V HSTL Class I
PIN_D33
QDRIIC_D11
Write data bus[11]
1.8-V HSTL Class I
PIN_H30
QDRIIC_D12
Write data bus[12]
1.8-V HSTL Class I
PIN_D34
QDRIIC_D13
Write data bus[13]
1.8-V HSTL Class I
PIN_G29
QDRIIC_D14
Write data bus[14]
1.8-V HSTL Class I
PIN_E33
QDRIIC_D15
Write data bus[15]
1.8-V HSTL Class I
PIN_E31
QDRIIC_D16
Write data bus[16]
1.8-V HSTL Class I
PIN_F31
QDRIIC_D17
Write data bus[17]
1.8-V HSTL Class I
PIN_F30
QDRIIC_Q0
Read Data bus[0]
1.8-V HSTL Class I
PIN_P31
QDRIIC_Q1
Read Data bus[1]
1.8-V HSTL Class I
PIN_N31
QDRIIC_Q2
Read Data bus[2]
1.8-V HSTL Class I
PIN_G33
QDRIIC_Q3
Read Data bus[3]
1.8-V HSTL Class I
PIN_G32
QDRIIC_Q4
Read Data bus[4]
1.8-V HSTL Class I
PIN_J31
QDRIIC_Q5
Read Data bus[5]
1.8-V HSTL Class I
PIN_G34
QDRIIC_Q6
Read Data bus[6]
1.8-V HSTL Class I
PIN_L31
QDRIIC_Q7
Read Data bus[7]
1.8-V HSTL Class I
PIN_L30
QDRIIC_Q8
Read Data bus[8]
1.8-V HSTL Class I
PIN_J30
QDRIIC_Q9
Read Data bus[9]
1.8-V HSTL Class I
PIN_P28
QDRIIC_Q10
Read Data bus[10]
1.8-V HSTL Class I
PIN_N28
QDRIIC_Q11
Read Data bus[11]
1.8-V HSTL Class I
PIN_M28
QDRIIC_Q12
Read Data bus[12]
1.8-V HSTL Class I
PIN_M29
QDRIIC_Q13
Read Data bus[13]
1.8-V HSTL Class I
PIN_N30
QDRIIC_Q14
Read Data bus[14]
1.8-V HSTL Class I
PIN_M30
QDRIIC_Q15
Read Data bus[15]
1.8-V HSTL Class I
PIN_L29
QDRIIC_Q16
Read Data bus[16]
1.8-V HSTL Class I
PIN_K29
QDRIIC_Q17
Read Data bus[17]
1.8-V HSTL Class I
PIN_J29
QDRIIC_BWS_n0
Byte Write select[0]
1.8-V HSTL Class I
PIN_F34
QDRIIC_BWS_n1
Byte Write select[1]
1.8-V HSTL Class I
PIN_C37
QDRIIC_K_p
Clock P
Differential 1.8-V
HSTL Class I
PIN_F32
QDRIIC_K_n
Clock N
Differential 1.8-V
HSTL Class I
PIN_E32
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