Terasic THDB-HDMI User Manual

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THDB-HDMI

Terasic HDMI Video Daughter Board
User Manual

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CONTENTS

Chapter 1 Introduction ...................................................................................... 2

1.1 About the KIT .......................................................................................................................................... 2

1.2 Assemble the HDMI Board ...................................................................................................................... 3

1.3 Getting Help ............................................................................................................................................. 3

Chapter 2 HDMI Board ....................................................................................... 4

2.1 Features .................................................................................................................................................... 4

2.2 Layout and Componets ............................................................................................................................ 7

2.3 Block Diagram of HDMI Signal Transmission ........................................................................................ 8

2.4 Block Diagram of HDMI Signal Receiving ........................................................................................... 10

2.5 Generate Pin Assignments ..................................................................................................................... 11

2.6 Pin Definition of HSTC Connector ........................................................................................................ 13

Chapter 3 Demonstration ................................................................................ 21

3.1 Introduction ............................................................................................................................................ 21

3.2 System Requirements ............................................................................................................................. 21

3.3 Setup the Demonstration ........................................................................................................................ 22

3.4 Operation................................................................................................................................................ 23

Chapter 4 Case Study ....................................................................................... 27

4.1 Overview ................................................................................................................................................ 27

4.2 System Function Block .......................................................................................................................... 27

4.3 NIOS Program ....................................................................................................................................... 31

Chapter 5 Appendix ......................................................................................... 35

5.1 Revision History .................................................................................................................................... 35

5.2 Always Visit THDB-HDMI Webpage for Update.................................................................................. 35

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Chapter 1

Introduction

THDB-HDMI is a HDMI transmitter/receiver daughter board with HSTC (High Speed Terasic
Connector) interface. Host boards, supporting HSTC-compliant connectors, can control the HDMI
daughter board through the HSTC interface.

This THDB-HDMI kit contains complete reference designs with source code written in Verilog and
C, for HDMI signal transmitting and receiving. Based on reference designs, users can easily and
quickly develop their applications.

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This section describes the package content.

The THDB-HDMI package, as shown in Figure 1-1, contains:

 THDB-HDMI board x 1
 System CD-ROM x 1

The CD contains technical documents of the HDMI receiver and transmitter, and one reference
design for HDMI transmitting and receiving with source code.

Figure 1-1 THDB-HDMI Package

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This section describes how to connect the HDMI daughter board to a main board, and use DE3 as
an example.

The HDMI board connects to main boards through the HSTC interface. For DE3, the HDMI
daughter board can be connected to any one of four HSTC connectors on DE3.

Figure 1-2 shows a HDMI daughter board connected to the HSTC connector of DE3. Due to high

speed data rate in between, users are strongly recommended to screw the two boards together.

Note. Do not attempt to connect/remove the HDMI daughter board to/from the main board when the
power is on, or the hardware could be damaged.

Figure 1-2 Connect HDMI daughter board to DE3 board

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Here are some places to get help if you encounter any problem:

 Email to [e-mail]
 Taiwan: [phone]
 China : [phone]

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

Chapter 2

HDMI Board

This chapter will illustrate technical details of HDMI board. Users may modify the reference
designs for various purposes accordingly.

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This section describes the major features of the HDMI board.

 Board Features:

 One HSTC interface for connection purpose
 One HDMI transmitter with single transmitting port
 One HDMI receiver with dual receiving ports
 Two 2K EEPROM for storing EDID of two receiver ports separately
 Powered from 3.3V pins of HSTC connector

 HDMI Transmitter Features:

1. HDMI 1.4 transmitter

2. Compliant with HDMI 1.3, HDMI1.4a 3D,HDCP 1.4 and DVI 1.1 specifications

3. Supporting link speeds of up to 2.25 Gbps (link clock rate of 225MHZ)

4. Supporting diverse 3D formats which are compliant with HDMI 1.4a 3D specification.

o Supporting 3D video up to 1080P@23.98/24/30Hz,1080i@50/59.94/60/Hz
o Supporting formats: framing packing, side-by-side(half),top-and-bottom

5. Various video input interface supporting digital video standards such as:

o 24/30/36-bit RGB/YCbCr 4:4:4
o 16/20/24-bit YCbCr 4:2:2
o 8/10/12-bit YCbCr 4:2:2 (CCIR-656)

6. Bi-direction Color Space Conversion (CSC) between RGB and YCbCr color space with
programmable coefficients

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7. Up/down sampling between YCbCr 4:4:4 and YCbCr 4:2:2

8. Either for conversion from 12-bit/10-bit to component to 8-bit

9. Support Gammat Metadata packet

10. Digital audio input interface supporting:

o Up to four I2S interface supporting 8-channel audio, with sample rates of 32~192

kHz and sample sizes of 16~24 bits

o S/PDIF interface supporting PCM, Dolby Digital, DTS digital audio at up to 192kHz

frame rate

o Support for high-bit-rate (HBR) audio such as DTS-HD and Dolby TrueHD through

the four I2S interface or the S/PDIF interface, with frame rates as high as 768kHz

o Support for 8-channel DSD audio through dedicated inputs
o Compatible with IEC 60958 and IEC 61937
o Audio down-sampling of 2X and 4X

11. Software programmable, auto-calibrated TMDS source terminations provide for optimal
source signal quality

12. Software programmable HDMI output current level

13. MCLK input is optional for audio operation. Users could opt to implement audio input
interface with or without MCLK

14. Integrated pre-programmed HDCP keys

15. Purely hardware HDCP engine increasing the robustness and security of HDCP operation

16. Monitor detection through Hot Plug Detection and Receiver Termination Detection

17. Embedded full-function pattern generator

18. Intelligent, programmable power management

Table 2-1 lists supported input video format:

Table 2-1 Input video formats supported by the HDMI board

Input Pixel Clock Frequency(MHz)

Color
space

Video
Format

Bus
Width

Hsync/
Vsync

480i

480p

XGA

720p

1080i

SXGA

1080p

UXGA

RGB

4:4:4
24

Separate

13.5

27

65

74.25

74.25

108

148.5

162

30/36

13.5

27

65

74.25

74.25

108

148.5

12/15/18

Separate

13.5

27

65

74.25

74.25

YCbCr
4:4:4
24

Separate

13.5

27

65

74.25

74.25

108

148.5

162

30/36

13.5

27

65

74.25

74.25

108

148.5

12/15/18

Separate

13.5

27

65

74.25

74.25

4:2:2

16/20/24
Separate

13.5

27

74.25

74.25

148.5

Embedded

13.5

27

74.25

74.25

148.5

6

12/15/18
Separate

27

54

148.5

148.5

Embedded

27

54

148.5

148.5

 HDMI Receiver Features:

1. Dual-Port HDMI 1.4 receiver

2. Compliant with HDMI 1.3, HDMI1.4a 3D,HDCP 1.4 and DVI 1.1 specifications

3. Supporting link speeds of up to 2.25 Gbps (link clock rate of 225MHZ)

4. Supporting diverse 3D formats which are compliant with HDMI 1.4a 3D specification.

o Supporting 3D video up to 1080P@23.98/24/30Hz,1080i@50/59.94/60/Hz
o Supporting formats: framing packing, side-by-side(half),top-and-bottom

5. Various video input interface supporting digital video standards such as:

o 24/30/36-bit RGB/YCbCr 4:4:4
o 16/20/24-bit YCbCr 4:2:2
o 8/10/12-bit YCbCr 4:2:2 (ITU BT-656)
o 12/15/18-bit double data rate interface (data bus width halved, clocked with both

rising and falling edges) for RGB/YCbCr 4:4:4

o 24/30/36-bit double data rate interface (full bus width, pixel clock rate halved,

clocked with both rising and falling edges)

o Input channel swap
o MSB/LSB swap

6. Bi-direction Color Space Conversion (CSC) between RGB and YCbCr color space with
programmable coefficients

7. Up/down sampling between YCbCr 4:4:4 and YCbCr 4:2:2

8. Dither for conversion from 12-bit/10-bit to component to 10-bit/8-bit

9. Support Gammat Metadata packet

10. Digital audio output interface supporting:

o Up to four I2S interface supporting 8-channel audio, with sample rates of 32~192

kHz and sample sizes of 16~24 bits

o S/PDIF interface supporting PCM, Dolby Digital, DTS digital audio at up to 192kHz

frame rate

o Optional support for 8-channel DSD audio up to 8 channels at 88.2kHz sample rate
o Support for high-bit-rate (HBR) audio such as DTS-HD and Dolby TrueHD through

the four I2S interface or the S/PDIF interface, with frame rates as high as 768kHz

o Automatic audio error detection for programmable soft mute, preventing annoying

harsh output sound due to audio error or hot-unplug

11. Auto-calibrated input termination impedance provides process-, voltage- and

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temperature-invariant matching to the input transmission lines.

12. Integrated pre-programmed HDCP keys

13. Intelligent, programmable power management

Table 2-2 lists the supported output video formats:

Table 2-2 Output video formats supported by the HDMI board

Output Pixel Clock Frequency(MHz)

Color
space

Video
Format

Bus
Width

Hsync/
Vsync

480i

480p

XGA

720p

1080i

SXGA

1080p

UXGA

RGB

4:4:4
24

Separate

13.5

27

65

74.25

74.25

108

148.5

162

30/36

13.5

27

65

74.25

74.25

108

148.5

12/15/18

Separate

13.5

27

65

74.25

74.25

YCbCr

4:4:4
24

Separate

13.5

27

65

74.25

74.25

108

148.5

162

30/36

13.5

27

65

74.25

74.25

108

148.5

12/15/18

Separate

13.5

27

65

74.25

74.25

4:2:2
16/20/24

Separate

13.5

27

74.25

74.25

148.5

Embedded

13.5

27

74.25

74.25

148.5

12/15/18
Separate

27

54

148.5

148.5

Embedded

27

54

148.5

148.5

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The photo of the HDMI board is shown in Figure 2-1 and Figure 2-2. It indicates the location of
the connectors and key components.

Figure 2-1 HDMI transmitter and receiver on the front of the HDMI board

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Figure 2-2 On the back of the HDMI board with HSTC connector and HDMI ports

 The THDB-HDMI board includes the following key components:

 Receiver (U3)
 Receiver port 1/2 (J2/J3)
 Transmitter (U6)
 Transmitter port (J4)
 27MHZ OSC (Y1)
 HSTC expansion connector (J1)
 Receiver I2C EEPORM (U4/U5)
 RX Regulator (REG1)
 TX Regulator (REG2)
 Level shifter (U2)

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This section describes the block diagram of HDMI signal transmission.

Figure 2-3 shows the block diagram of HDMI signal transmission. Please refer to the schematic

included in the CD for more details. The HDMI transmitter is controlled through I2C interface,
where the host works as master and the transmitter works as a slave. Because the pin PCADR is
pulled low, the transmitter I2C device address is set to 0x98. Through the I2C interface, the host
board can access the internal registers of transmitter to control its behavior.

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Figure 2-3 The block diagram of the HDMI signal transmission

The host can use reset pin TX_RST_N to reset the transmitter, and listen to the interrupt pin
TX_INT_N to detect change of the transmitter status. When interrupt happens, the host needs to
read the internal register to find out which event is triggered and perform proper actions for the
interrupt.

Here are the steps 1-2-3 to control the transmitter:

1. Reset the transmitter from the TX_RST_N pin

2. Initialize the transmitter through the I2C interface

3. Polling the interrupt pin INT_N continuously.

 If a HDMI sink device is detected (HDP flag is on):

o Read and parse EDID to determine the capacity of the attached HDMI sink device.
o Configure desired output video/audio, including color space and color depth.
o Perform HDCP authentication
o Output video/audio signals to the Video/Audio bus.

 Stop video output if a video sink device is removed (HPD flag is off).
 Perform proper actions according to various interrupt events.

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This section describes the block diagram of HDMI signal receiving.

Figure 2-4 shows the block diagram of HDMI signal receiving. Please refer to the schematic

included in the CD for more details. The HDMI receiver is controlled through the I2C interface,
where the host works as master and the transmitter works as a slave. Because the pin PCADR is
pulled low, the transmitter I2C device address is set to 0x90. Through the I2C interface, the host
board can access the internal registers of receiver to control its behavior. The receiver can support
two receiving ports, but only one port can be activated at the same time.

Figure 2-4 The block diagram of HDMI signal receiving

The host can use the reset pin RX_RST_N to reset the receiver, and listen to the interrupt pin
RX_INT_N to detect change of the receiver status. When interrupt happens, the host needs to read
the internal register to find out which event is triggered and perform proper actions for the interrupt.

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Here are the steps to control the receiver:

1. Reset the receiver from the RX_RST_N pin

2. Read the EEPROM (EDID) to check whether the EEPROM contents need to be updated.
When writing data to EEPROM, remember to pull-low the EEPROM write protection pin
EDID_WP. Finally, make sure EDID_WP is pulled high and configure the both I2C pins as
input pins, so the attached HSTC source device can read the EDID successfully.

3. Initialize the receiver through the I2C interface

4. Pull-Low the RX1_HPD_N and RX2_PHD_N pins to enable HPD pins of receiving ports.

5. Set receiver port 1 as active port.

6. Polling the interrupt pin RX_INT_N. Switch to another receiver port every three seconds and
activate it if no HDMI source device found on the current active port.

 If a HDMI source device is detected:

o Perform HDCP authentication.
o Read the input video format, including color space and color depth.
o Configure input and output color space.

 Perform proper actions according to various interrupt events.

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This section describes how to automatically generate a top-level project, including HDMI pin
assignments.

Users can easily create the HDMI board pin assignments by utilizing the DE3_System Builder V

1.3.1 or later. Here are the procedures to generate a top-level project for THDB-HDMI.

1. Launch DE3-System Builder

2. Add a DE3 board. Enable the HSTC-C connector and type desired pin pre-fix name in the
dialog of DE3 Configuration.