Terasic MAX10-Plus User Manual
MAX 10 Plus User
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Manual
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CONTENTS
Chapter 1 MAX 10 Plus Development Kit ..................................................................4
1.1 Package Contents........................................................................................................................ 4
1.2 MAX 10 Plus System CD ........................................................................................................... 5
1.3 Getting Help ............................................................................................................................... 5
Chapter 2 Introduction of the MAX 10 Plus ...............................................................6
2.1 Layout and Components ............................................................................................................. 6
2.2 Block Diagram of the MAX 10 Plus .......................................................................................... 7
Chapter 3 Using the MAX 10 Plus .............................................................................10
3.1 Configuration of MAX 10 FPGA on MAX 10 Plus ................................................................. 10
3.2 Board Status Elements .............................................................................................................. 14
3.3 Clock Circuitry ......................................................................................................................... 15
3.4 Peripherals Connected to the FPGA ......................................................................................... 16
3.4.1 User Push-buttons, Switches, LEDs ...................................................................................... 16
3.4.2 7-segment Displays ................................................................................................................ 19
3.4.3 Power Monitor ....................................................................................................................... 20
3.4.4 2x6 TMD Expansion Header ................................................................................................. 21
3.4.5 24-bit Audio CODEC ............................................................................................................ 22
3.4.6 Two Analog Input SMA Connectors ..................................................................................... 23
3.4.7 DDR3 Memory ...................................................................................................................... 23
3.4.8 QSPI Flash ............................................................................................................................. 25
3.4.9 Ethernet .................................................................................................................................. 26
3.4.10 HDMI RX .............................................................................................................................. 28
3.4.11 2x10 ADC Header ................................................................................................................. 29
3.4.12 Potentiometer ......................................................................................................................... 30
3.4.13 On-board Microphone ............................................................................................................ 30
3.4.14 PS/2 Serial Port ...................................................................................................................... 30
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3.4.15 Digital-to-Analog Converter (DAC) ...................................................................................... 31
3.4.16 UART to USB ........................................................................................................................ 32
3.4.17 Ambient Light Sensor ............................................................................................................ 33
3.4.18 Humidity and Temperature Sensor ........................................................................................ 33
3.4.19 Accelerometer Sensor ............................................................................................................ 34
3.4.20 Micro SD Card Socket ........................................................................................................... 35
3.4.21 Power Distribution System .................................................................................................... 35
Chapter 4 The MAX 10 Plus System Builder ...........................................................37
4.1 Introduction .............................................................................................................................. 37
4.2 General Design Flow ................................................................................................................ 37
4.3 Using MAX 10 Plus System Builder ........................................................................................ 38
Chapter 5 RTL Example Codes .................................................................................44
5.1 PS/2 Mouse Demonstration ...................................................................................................... 44
5.2 ADC Potentiometer .................................................................................................................. 46
5.3 DAC Demonstration ................................................................................................................. 48
5.4 ADC/MIC/LED Demonstration ................................................................................................ 51
Chapter 6 NIOS Based Example Codes ....................................................................54
6.1 Power Monitor .......................................................................................................................... 54
6.2 UART to USB Control LED ..................................................................................................... 58
6.3 SD Card Audio Demonstration ................................................................................................. 61
6.4 DDR3 SDRAM Test by Nios II ................................................................................................ 65
6.5 Ethernet Socket server .............................................................................................................. 68
6.6 Digital Accelerometer Demonstration ...................................................................................... 75
6.7 Humidity/Temperature Sensor .................................................................................................. 77
Chapter 7 Programming the Configuration Flash Memory ...................................79
7.1 Internal Configuration .............................................................................................................. 79
7.2 Using Dual Compressed Images............................................................................................... 81
7.3 Nios II Load In Single Boot Image .......................................................................................... 84
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Chapter 1
MAX 10 Plus Development Kit
The MAX 10 Plus board from Terasic is a full featured embedded evaluation kit based upon the
MAX10 family of Intel FPGAs. It offers a comprehensive design environment with everything
embedded developers need to create a processing-based system.
The MAX 10 Plus board delivers an integrated platform that includes hardware, design tools,
intellectual property and reference designs for developing a wide range of audio, video and many
other exciting applications.
The fully integrated kit allows developers to rapidly customize their processor and IP to suit their
specific needs, rather than constraining their software around the fixed feature set of the processor.
The all-in-one embedded solution, the MAX 10 Plus, making the best use of the parallel nature of
FPGAs.
1.1 Package Contents
Figure 1-1 shows a photograph of the MAX 10 Plus board package.
Figure 1-1 The MAX 10 Plus Board Package Contents
The MAX 10 Plus board package includes:
1. MAX 10 Plus board
2. MAX 10 Plus Quick Start Guide
3. 5V DC power adapter
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4. One USB cables (Type A to Mini-B) for USB control and FPGA programming and control
1.2 MAX 10 Plus System CD
The MAX 10 Plus System CD contains all the documents and supporting materials associated with
MAX 10 Plus, including the user manual, system builder, reference designs, and device datasheets.
Users can download this system CD from the link: http:// max10-plus.terasic.com/cd.
1.3 Getting Help
Here are the addresses where you can get help if you encounter any problems:
• Terasic Technologies
• 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
Email: support@terasic.com
Tel.: +886-3-575-0880
Website: max10-plus.terasic.com
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Chapter 2
Introduction of the MAX 10 Plus
2.1 Layout and Components
Figure 2-1 shows a photograph of the board. It depicts the layout of the board and indicates the
location of the connectors and key components.
Figure 2-1 MAX 10 Plus Development Board (top view)
The MAX 10 Plus board has many features that allow users to implement a wide range of designed
circuits, from simple circuits to various multimedia projects.
The following hardware is provided on the board:
• Intel MAX® 10 10M50DAF484C6G device
• USB-Blaster II onboard for programming; JTAG Mode
• 256MB DDR3 SDRAM (64Mx16 and 128Mx8)
• 64MB QSPI Flash
• Micro SD card socket
• Five push-buttons
• Ten slide switches
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• Ten red user LEDs
• Two 7-segment displays
• Three 50MHz clock sources from the clock generator
• 24-bit CD-quality audio CODEC with line-in, line-out jacks
• On-board microphone
• HDMI RX, incorporates HDM v1.4a features, including 3D video supporting
• Gigabit Ethernet PHY with RJ45 connector
• UART to USB, USB Mini-B connector
• One ambient light sensor
• One humidity and temperature sensor
• One accelerometer
• One external 16bit digital-to-analog converter (DAC) device with SMA output
• Potentiometer input to ADC
• Two MAX 10 FPGA ADC SMA inputs
• One 2x10 ADC header with 16 analog inputs connected to MAX10 ADCs
2.2 Block Diagram of the MAX 10 Plus
Figure 2-2 is the block diagram of the board. All the connections are established through the MAX
10 FPGA device to provide maximum flexibility for users. Users can configure the FPGA to
implement any system design.
Figure 2-2 Block Diagram of MAX 10 Plus Board
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FPGA Device
• MAX 10 10M50DAF484C6G Device
• Integrated dual ADCs, each ADC supports 1 dedicated analog input and 8 dual function pins
• 50K programmable logic elements
• 1,638Kbits embedded memory
• 5,888Kbits user flash memory
• 4 PLLs
Configuration and Debug
• On-board USB-Blaster II (Mini USB type B connector)
• Optional JTAG direct via 10-pin header
• One slide switch for dual boot image selection
Memory Device
• 256MB DDR3 SDRAM (64Mx16 and 128Mx8)
• 512MB QSPI Flash
• Micro SD card socket
Communication and Expansion Header
• Gigabit Ethernet PHY with RJ45 connector
• UART to USB, USB Mini-B connector
• PS/2 mouse/keyboard connector
• 2x6 TMD (Terasic Mini Digital) Expansion Header
Audio
• 24-bit CD-quality audio CODEC with line-in, line-out jacks
Video Input
• HDMI RX, incorporates HDM v1.4a features, including 3D video supporting
Analog
• Two MAX 10 FPGA ADC SMA inputs
• Potentiometer input to ADC
• On-Board MIC input to ADC
• 2x10 ADC header with 16 analog inputs connected to MAX10 ADCs
• One DAC SMA output
Switches, Buttons, and Indicators
• Five push-buttons
• Ten slide switches
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• Ten red user LEDs
• Two 7-segment displays
Sensors
• Ambient light sensor
• Humidity and temperature sensor
• Accelerometer
• Power monitor
Power
• 5V/3A DC input
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Chapter 3
Using the MAX 10 Plus
This chapter provides an instruction to use the board and describes the peripherals.
3.1 Configuration of MAX 10 FPGA on MAX 10 Plus
There are two types of configuration method supported by MAX 10 Plus:
1. JTAG configuration: configuration using JTAG port.
JTAG configuration scheme allows you to directly configure the device core through JTAG pins -
TDI, TDO, TMS, and TCK pins. The Quartus II software automatically generates .sof that is used
for JTAG configuration with a download cable in the Quartus II software programmer.
2. Internal configuration: configuration using internal flash.
Before internal configuration, you need to program the configuration data into the configuration
flash memory (CFM) which provides non-volatile storage for the bit stream. The information is
retained within CFM even if the MAX 10 Plus is turned off. When the board is powered on, the
configuration data in the CFM is automatically loaded into the MAX 10 FPGA.
◼ JTAG Chain on MAX 10 Plus
The FPGA device can be configured through JTAG interface on MAX 10 Plus board, but the JTAG
chain must form a closed loop, which allows Quartus II programmer to the detect FPGA device.
Figure 3-1 illustrates the JTAG chain on MAX 10 Plus.
Figure 3-1 Path of the JTAG Chain
◼ Configure the FPGA in JTAG Mode
The following shows how the FPGA is programmed in JTAG mode step by step.
1. Open the Quartus II programmer and click Auto Detect, as circled in Figure 3-2.
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Figure 3-2 Detect FPGA Device in JTAG Mode
2. Select detected device associated with the board, as circled in Figure 3-3.
Figure 3-3 Select 10M50DAES Device
3. FPGA is detected, as shown in Figure 3-4.
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Figure 3-4 FPGA Detected in Quartus Programmer
4. Right click on the FPGA device and open the .sof file to be programmed, as highlighted in
Figure 3-5.
Figure 3-5 Open the .sof File to be Programmed into the FPGA Device
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5. Select the .sof file to be programmed, as shown in Figure 3-6.
Figure 3-6 Select the .sof File to be Programmed into the FPGA Device
6. Click Program/Configure check box and then click Start button to download the .sof file
into the FPGA device, as shown in Figure 3-7.
Figure 3-7 Program. sof File into the FPGA Device
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◼ Internal Configuration
• The configuration data to be written to CFM will be part of the programmer object file (.pof).
This configuration data is automatically loaded from the CFM into the MAX 10 devices when
the board is powered up.
• Please refer to Chapter 7 Programming the Configuration Flash Memory for the basic
programming instruction on the configuration flash memory (CFM).
Figure 3-8 High-Level Overview of Internal Configuration for MAX 10 Devices
3.2 Board Status Elements
In addition to the 10 LEDs that FPGA device can control, there are 4 indicators which can indicate
the board status (See Figure 3-9), please refer the details in Table 3-1.
Figure 3-9 LED Indicators on MAX 10 Plus
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Table 3-1 LED Indicators
Board Reference
LED Name
Description
D13
5V Power
Illuminate when 5V power is active.
D14
2.5V Power
Illuminate when 2.5V power is active.
D16
1.2V Power
Illuminate when 1.2V power is active.
D6
CONF_DONE
Illuminate when configuration data is loaded into MAX 10 device
without error.
D7
JTAG_RX
Illuminate during data is uploaded from MAX 10 device to PC through
UB2.
D8
JTAG_TX
Illuminate during configuration data is loaded into MAX 10 device
from UB2.
TXD
TXD
Illuminate during transmitting data via USB.
RXD
RXD
Illuminate during receiving data via USB.
3.3 Clock Circuitry
Figure 3-10 shows the default frequency of all external clocks to the MAX 10 FPGA. A clock
generator is used to distribute clock signals with low jitter. The three 50MHz clock signals
connected to the FPGA are used as clock sources for user logic. One 25MHz clock signal is
connected to the clock input of Gigabit Ethernet Transceiver. One 24MHz clock signal is connected
to the clock inputs of USB microcontroller of USB Blaster II. One 28.63636MHz clock signal is
connected to the clock input of HDMI Receiver chip. The other 50MHz clock signal is connected to
MAX CPLD of USB Blaster II. One 10MHz clock signal is connected to the PLL1 and PLL3 of
FPGA, the outputs of these two PLLs can drive ADC clock. The associated pin assignment for
clock inputs to FPGA I/O pins is listed in Table 3-2.
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Figure 3-10 Block Diagram of the Clock Distribution on MAX 10 Plus
Table 3-2 Pin Assignment of Clock Inputs
Signal Name
FPGA Pin No.
Description
I/O Standard
MAX10_CLK1_50
PIN_N5
50MHz clock input
2.5V
MAX10_CLK2_50
PIN_V9
50MHz clock input
3.3V
MAX10_CLK3_50
PIN_N14
50MHz clock input
1.5V
ADC_CLK_10
PIN_M9
10MHz clock input
3.3V
3.4 Peripherals Connected to the FPGA
This section describes the interfaces connected to the FPGA. User can control or monitor different
interfaces with user logic from the FPGA.
3.4.1 User Push-buttons, Switches, LEDs
The board has five push-buttons connected to the FPGA, as shown in Figure 3-11. MAX 10 devices
support Schmitt trigger input on all I/O pins. A Schmitt trigger feature introduces hysteresis to the
input signal for improved noise immunity, especially for signal with slow edge rate and act as
switch debounce in Figure 3-12 for the push-buttons connected.
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Figure 3-11 Connections between the Push-buttons and the MAX 10 FPGA
Figure 3-12 Switch Debouncing
There are two ten switches connected to the FPGA, as shown in Figure 3-13. These switches are
used as level-sensitive data inputs to a circuit. Each switch is connected directly and individually to
the FPGA. When the switch is set to the DOWN position (towards the edge of the board), it
generates a low logic level to the FPGA. When the switch is set to the UP position, a high logic
level is generated to the FPGA.
Pushbutton releasedPushbutton depressed
Before
Debouncing
Schmitt Trigger
Debounced
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Figure 3-13 Connections between the Slide Switches and the MAX 10 FPGA
There are also ten user-controllable LEDs connected to the FPGA. Each LED is driven directly and
individually by the MAX 10 FPGA; driving its associated pin to a high logic level or low level to
turn the LED on or off, respectively. Figure 3-14 shows the connections between LEDs and MAX
10 FPGA. Table 3-3, Table 3-4 and Table 3-5 list the pin assignment of user push-buttons, switches,
and LEDs.
Figure 3-14 Connections between the LEDs and the MAX 10 FPGA
Table 3-3 Pin Assignment of Push-buttons
Signal Name
FPGA Pin No.
Description
I/O Standard
KEY[0]
PIN_T22
Push-button[0]
1.5V
KEY[1]
PIN_U22
Push-button[1]
1.5V
KEY[2]
PIN_AA22
Push-button[2]
1.5V
KEY[3]
PIN_AA21
Push-button[3]
1.5V
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KEY[4]
PIN_R22
Push-button[4]
1.5V
Table 3-4 Pin Assignment of Slide Switches
Signal Name
FPGA Pin No.
Description
I/O Standard
SW[0]
PIN_N22
Slide Switch[0]
1.5V
SW[1]
PIN_M22
Slide Switch[1]
1.5V
SW[2]
PIN_N21
Slide Switch[2]
1.5V
SW[3]
PIN_L22
Slide Switch[3]
1.5V
SW[4]
PIN_J22
Slide Switch[4]
1.5V
SW[5]
PIN_H22
Slide Switch[5]
1.5V
SW[6]
PIN_J21
Slide Switch[6]
1.5V
SW[7]
PIN_C21
Slide Switch[7]
1.5V
SW[8]
PIN_G19
Slide Switch[8]
1.5V
SW[9]
PIN_H21
Slide Switch[9]
1.5V
Table 3-5 Pin Assignment of LEDs
Signal Name
FPGA Pin No.
Description
I/O Standard
LEDR[0]
PIN_C2
LEDR [0]
3.3V
LEDR[1]
PIN_B3
LEDR [1]
3.3V
LEDR[2]
PIN_A3
LEDR [2]
3.3V
LEDR[3]
PIN_C3
LEDR [3]
3.3V
LEDR[4]
PIN_A4
LEDR [4]
3.3V
LEDR[5]
PIN_B4
LEDR [5]
3.3V
LEDR[6]
PIN_C4
LEDR [6]
3.3V
LEDR[7]
PIN_B5
LEDR [7]
3.3V
LEDR[8]
PIN_C5
LEDR [8]
3.3V
LEDR[9]
PIN_D5
LEDR [9]
3.3V
3.4.2 7-segment Displays
The MAX 10 Plus has two 7-segment displays. These displays are paired to display numbers in
various sizes. Figure 3-15 shows the connection of seven segments (common anode) to pins on
MAX 10 FPGA. The segment can be turned on or off by applying a low logic level or high logic
level from the FPGA, respectively.
Each segment in a display is indexed from 0 to 6, with corresponding positions given in Figure
3-15. Table 3-6 shows the pin assignment of FPGA to the 7-segment displays.
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Figure 3-15 Connections between the 7-segment Display HEX0 and the MAX 10 FPGA
Table 3-6 Pin Assignment of 7-segment Displays
Signal Name
FPGA Pin No.
Description
I/O Standard
HEX0[0]
PIN_D6
Seven Segment Digit 0[0]
3.3V
HEX0[1]
PIN_A5
Seven Segment Digit 0[1]
3.3V
HEX0[2]
PIN_C6
Seven Segment Digit 0[2]
3.3V
HEX0[3]
PIN_A6
Seven Segment Digit 0[3]
3.3V
HEX0[4]
PIN_F7
Seven Segment Digit 0[4]
3.3V
HEX0[5]
PIN_D7
Seven Segment Digit 0[5]
3.3V
HEX0[6]
PIN_B7
Seven Segment Digit 0[6]
3.3V
HEX1[0]
PIN_C7
Seven Segment Digit 1[0]
3.3V
HEX1[1]
PIN_C8
Seven Segment Digit 1[1]
3.3V
HEX1[2]
PIN_D8
Seven Segment Digit 1[2]
3.3V
HEX1[3]
PIN_D10
Seven Segment Digit 1[3]
3.3V
HEX1[4]
PIN_E10
Seven Segment Digit 1[4]
3.3V
HEX1[5]
PIN_H11
Seven Segment Digit 1[5]
3.3V
HEX1[6]
PIN_E6
Seven Segment Digit 1[6]
3.3V
3.4.3 Power Monitor
The MAX 10 Plus has implemented three power monitor chips to monitor the FPGA core power
and VCCIO power voltage and current. Figure 3-16 shows the connection between the power
monitor chip and the MAX 10 FPGA. Through the I2C serial interface, the power monitor can be
configured to measure remote voltage and remote current. Programmable calibration value,
conversion times, and averaging, combined with an internal multiplier, enable direct readouts of
current in amperes and power in watts. Table 3-7 shows the pin assignment of power monitor I2C
bus.
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Figure 3-16 Connections between the Power Monitor Chip and the MAX 10 FPGA
Table 3-7 Pin Assignment of Power Monitor I2C Bus
Signal Name
FPGA Pin No.
Description
I/O Standard
PM_I2C_SCL
PIN_E8
Power Monitor SCL
3.3V
PM_I2C_SDA
PIN_E9
Power Monitor SDA
3.3V
3.4.4 2x6 TMD Expansion Header
The board has one 2x6 TMD (Terasic Mini Digital) expansion header. The TMD header has 8
digital GPIO user pins connected to the MAX 10 FPGA, two 3.3V power pins and two ground pins.
There are two Transient Voltage Suppressor diode arrays used to implement ESD protection for 8
GPIO user pins.
Figure 3-17 shows the connection between the TMD header and MAX 10 FPGA. Table 3-8 shows
the pin assignment of 2x6 TMD header.
Figure 3-17 Connections between the 2x6 TMD Header and MAX 10 FPGA
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Table 3-8 Pin Assignment of 2x6 TMD Header
Signal Name
FPGA Pin No.
Description
I/O Standard
GPIO[0]
PIN_Y17
GPIO Connection [0]
3.3V
GPIO[1]
PIN_AA17
GPIO Connection [1]
3.3V
GPIO[2]
PIN_V16
GPIO Connection [2]
3.3V
GPIO[3]
PIN_W15
GPIO Connection [3]
3.3V
GPIO[4]
PIN_AB16
GPIO Connection [4]
3.3V
GPIO[5]
PIN_AA16
GPIO Connection [5]
3.3V
GPIO[6]
PIN_Y16
GPIO Connection [6]
3.3V
GPIO[7]
PIN_W16
GPIO Connection [7]
3.3V
3.4.5 24-bit Audio CODEC
The MAX 10 Plus offers high-quality 24-bit audio via the Texas Instruments TLV320AIC3254
audio CODEC (Encoder/Decoder). This chip on MAX 10 Plus supports, line-in, line-out and
microphone-in ports with adjustable sample rate from 8KHz to 192KHz. The connection of the
audio circuitry to the FPGA is shown in Figure 3-18, and the associated pin assignment to the
FPGA is listed in Table 3-9. More information about the TLV320AIC3254 CODEC is available in
its datasheet, which can be found on the manufacturer’s website, or in the directory
\Datasheet\Audio CODEC of MAX 10 Plus System CD.
Figure 3-18 Connections between the FPGA and Audio CODEC
Table 3-9 Pin Assignment of Audio CODEC
Signal Name
FPGA
Pin No.
Description
I/O
Standard
AUDIO_MCLK
PIN_J11
Master output Clock
2.5V
AUDIO_BCLK
PIN_J12
Audio serial data bus (primary) bit clock
2.5V
AUDIO_WCLK
PIN_H12
Audio serial data bus (primary) word clock
2.5V
AUDIO_DIN_MFP1
PIN_J13
Audio serial data bus data output/digital microphone output
2.5V
AUDIO_DOUT_MFP2
PIN_H13
Audio serial data bus data input/general purpose input
2.5V
AUDIO_SCLK_MFP3
PIN_H14
SPI serial Clock/headphone-detect output
2.5V
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AUDIO_SCL_SS_n
PIN_F15
I2C Clock/SPI interface mode chip-select signal
2.5V
AUDIO_SDA_MOSI
PIN_F16
I2C Data/SPI interface mode serial data output
2.5V
AUDIO_MISO_MFP4
PIN_E13
Serial data input/General purpose input
2.5V
AUDIO_SPI_SELECT
PIN_E14
Control mode select pin
2.5V
AUDIO_RESET_n
PIN_D13
Reset signal
2.5V
AUDIO_GPIO_MFP5
PIN_D14
General Purpose digital IO/CLKOUT input
2.5V
3.4.6 Two Analog Input SMA Connectors
The MAX 10 Plus implements two analog input SMA connectors. The analog inputs are amplified
and translated by Texas Instruments INA159 gain of 0.2 level translation difference amplifier, then
the amplifier’s outputs are fed to dedicated single-ended analog input pins for MAX 10 build-in
ADC1 and ADC2 respectively. With the amplifiers, the analog input of two SMAs support from
-6.25V to +6.25V range. Figure 3-19 shows the connection of SMA connectors to the FPGA.
Figure 3-19 Connection of SMA Connectors to the FPGA
3.4.7 DDR3 Memory
The board supports 256MB of DDR3 SDRAM comprising of one 16bit (64Mx16) DDR3 device
and one 8bit (128Mx8) device. The DDR3 devices shipped with this board are running at 300MHz
with the soft IP of MAX 10 external memory interface solution. Figure 3-20 shows the connections
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between the DDR3 and MAX 10 FPGA. Table 3-10 shows the DDR3 interface pin assignments.
Figure 3-20 Connections between the DDR3 and FPGA
Table 3-10 Pin Assignment of FPGA DDR3 Memory
Signal Name
FPGA Pin No.
Description
I/O Standard
DDR3_A[0]
PIN_U20
DDR3 Address[0]
SSTL-15 Class I
DDR3_A[1]
PIN_F19
DDR3 Address[1]
SSTL-15 Class I
DDR3_A[2]
PIN_V20
DDR3 Address[2]
SSTL-15 Class I
DDR3_A[3]
PIN_G20
DDR3 Address[3]
SSTL-15 Class I
DDR3_A[4]
PIN_F20
DDR3 Address[4]
SSTL-15 Class I
DDR3_A[5]
PIN_E20
DDR3 Address[5]
SSTL-15 Class I
DDR3_A[6]
PIN_E21
DDR3 Address[6]
SSTL-15 Class I
DDR3_A[7]
PIN_Y20
DDR3 Address[7]
SSTL-15 Class I
DDR3_A[8]
PIN_C22
DDR3 Address[8]
SSTL-15 Class I
DDR3_A[9]
PIN_D22
DDR3 Address[9]
SSTL-15 Class I
DDR3_A[10]
PIN_J14
DDR3 Address[10]
SSTL-15 Class I
DDR3_A[11]
PIN_E22
DDR3 Address[11]
SSTL-15 Class I
DDR3_A[12]
PIN_G22
DDR3 Address[12]
SSTL-15 Class I
DDR3_A[13]
PIN_D19
DDR3 Address[13]
SSTL-15 Class I
DDR3_A[14]
PIN_C20
DDR3 Address[14]
SSTL-15 Class I
DDR3_BA[0]
PIN_W22
DDR3 Bank Address[0]
SSTL-15 Class I
DDR3_BA[1]
PIN_Y21
DDR3 Bank Address[1]
SSTL-15 Class I
DDR3_BA[2]
PIN_Y22
DDR3 Bank Address[2]
SSTL-15 Class I
DDR3_CAS_n
PIN_U19
DDR3 Column Address Strobe
SSTL-15 Class I
DDR3_CKE
PIN_V18
Clock Enable pin for DDR3
SSTL-15 Class I
DDR3_CLK_n
PIN_E18
Clock n for DDR3
DIFFERENTIAL 1.5-V
SSTL Class I
DDR3_CLK_p
PIN_D18
Clock p for DDR3
Differential 1.5-V SSTL
MAX 10 Plus User
Manual
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Class I
DDR3_CS_n
PIN_W20
DDR3 Chip Select
SSTL-15 Class I
DDR3_DM[0]
PIN_J15
DDR3 Data Mask[0]
SSTL-15 Class I
DDR3_DM[1]
PIN_N19
DDR3 Data Mask[1]
SSTL-15 Class I
DDR3_DQ[0]
PIN_J18
DDR3 Data[0]
SSTL-15 Class I
DDR3_DQ[1]
PIN_H19
DDR3 Data[1]
SSTL-15 Class I
DDR3_DQ[2]
PIN_K20
DDR3 Data[2]
SSTL-15 Class I
DDR3_DQ[3]
PIN_H18
DDR3 Data[3]
SSTL-15 Class I
DDR3_DQ[4]
PIN_K18
DDR3 Data[4]
SSTL-15 Class I
DDR3_DQ[5]
PIN_H20
DDR3 Data[5]
SSTL-15 Class I
DDR3_DQ[6]
PIN_K19
DDR3 Data[6]
SSTL-15 Class I
DDR3_DQ[7]
PIN_J20
DDR3 Data[7]
SSTL-15 Class I
DDR3_DQ[8]
PIN_L18
DDR3 Data[8]
SSTL-15 Class I
DDR3_DQ[9]
PIN_M18
DDR3 Data[9]
SSTL-15 Class I
DDR3_DQ[10]
PIN_M14
DDR3 Data[10]
SSTL-15 Class I
DDR3_DQ[11]
PIN_N20
DDR3 Data[11]
SSTL-15 Class I
DDR3_DQ[12]
PIN_L20
DDR3 Data[12]
SSTL-15 Class I
DDR3_DQ[13]
PIN_M20
DDR3 Data[13]
SSTL-15 Class I
DDR3_DQ[14]
PIN_M15
DDR3 Data[14]
SSTL-15 Class I
DDR3_DQ[15]
PIN_L19
DDR3 Data[15]
SSTL-15 Class I
DDR3_DQ[16]
PIN_T19
DDR3 Data[15]
SSTL-15 Class I
DDR3_DQ[17]
PIN_R20
DDR3 Data[15]
SSTL-15 Class I
DDR3_DQ[18]
PIN_R15
DDR3 Data[15]
SSTL-15 Class I
DDR3_DQ[19]
PIN_P15
DDR3 Data[15]
SSTL-15 Class I
DDR3_DQ[20]
PIN_P19
DDR3 Data[15]
SSTL-15 Class I
DDR3_DQ[21]
PIN_P14
DDR3 Data[15]
SSTL-15 Class I
DDR3_DQ[22]
PIN_R14
DDR3 Data[15]
SSTL-15 Class I
DDR3_DQ[23]
PIN_P20
DDR3 Data[15]
SSTL-15 Class I
DDR3_DQS_n[0]
PIN_K15
DDR3 Data Strobe n[0]
Differential 1.5-V SSTL
Class I
DDR3_DQS_n[1]
PIN_L15
DDR3 Data Strobe n[1]
Differential 1.5-V SSTL
Class I
DDR3_DQS_p[0]
PIN_K14
DDR3 Data Strobe p[0]
Differential 1.5-V SSTL
Class I
DDR3_DQS_p[1]
PIN_L14
DDR3 Data Strobe p[1]
Differential 1.5-V SSTL
Class I
DDR3_ODT
PIN_V22
DDR3 On-die Termination
SSTL-15 Class I
DDR3_RAS_n
PIN_N18
DDR3 Row Address Strobe
SSTL-15 Class I
DDR3_RESET_n
PIN_B22
DDR3 Reset
SSTL-15 Class I
DDR3_WE_n
PIN_W19
DDR3 Write Enable
SSTL-15 Class I
3.4.8 QSPI Flash
The MAX 10 Plus supports a 512M-bit serial NOR flash device for non-volatile storage, user data
and program. This device has a 4-bit data interface and uses 3.3V CMOS signaling standard.
Connections between MAX 10 FPGA and Flash are shown in Figure 3-21. Table 3-11 shows the
MAX 10 Plus User
Manual
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DDR3 interface pin assignments.
Figure 3-21 Connections between MAX 10 FPGA and QSPI Flash
Table 3-11 Pin Assignment of QSPI Flash
Signal Name
FPGA Pin No.
Description
I/O
Standard
FLASH_DATA[0]
PIN_AB18
FLASH Data[0]
3.3V
FLASH_DATA[1]
PIN_AA19
FLASH Data[1]
3.3V
FLASH_DATA[2]
PIN_AB19
FLASH Data[2]
3.3V
FLASH_DATA[3]
PIN_AA20
FLASH Data[3]
3.3V
FLASH_DCLK
PIN_AB17
FLASH Data Clock
3.3V
FLASH_NCSO
PIN_AB21
FLASH Chip Enable
3.3V
FLASH_RESET_n
PIN_AB20
FLASH Chip Reser
3.3V
3.4.9 Ethernet
The board supports Gigabit Ethernet transfer by an external Marvell 88E1111 PHY chip. The
88E1111 chip with integrated 10/100/1000 Mbps Gigabit Ethernet transceiver support
GMII/MII/RGMII/TBI MAC interfaces. Figure 3-22 shows the connections between the MAX 10
FPGA, Ethernet PHY, and RJ-45 connector. The pin assignment associated to Gigabit Ethernet
interface is listed in Table 3-12.
MAX 10 Plus User
Manual
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Figure 3-22 Connections between the MAX 10 FPGA and Gigabit Ethernet
Table 3-12 Pin Assignment of Ethernet PHY
Signal Name
FPGA Pin No.
Description
I/O
Standard
NET_TX_EN
PIN_C10
GMII and MII transmit enable
2.5V
NET_TX_ER
PIN_C12
GMII and MII transmit error
2.5V
NET_TX_CLK
PIN_E11
MII transmit clock
3.3V
NET_TX_D[0]
PIN_A12
MII transmit data[0]
2.5V
NET_TX_D[1]
PIN_B12
MII transmit data[1]
2.5V
NET_TX_D[2]
PIN_A13
MII transmit data[2]
2.5V
NET_TX_D[3]
PIN_A14
MII transmit data[3]
2.5V
NET_RX_DV
PIN_A8
GMII and MII receive data valid
2.5V
NET_RX_ER
PIN_B8
GMII and MII receive data valid
2.5V
NET_RX_D[0]
PIN_A10
GMII and MII receive data[0]
2.5V
NET_RX_D[1]
PIN_B10
GMII and MII receive data[1]
2.5V
NET_RX_D[2]
PIN_A11
GMII and MII receive data[2]
2.5V
NET_RX_D[3]
PIN_B11
GMII and MII receive data[3]
2.5V
NET_RX_CLK
PIN_J10
GMII and MII receive clock
3.3V
NET_RST_n
PIN_C14
Hardware Reset Signal
2.5V
NET_MDIO
PIN_E12
Management Data
2.5V
NET_MDC
PIN_D12
Management Data Clock Reference
2.5V
NET_RX_COL
PIN_C9
GMII and MII collision
2.5V
NET_RX_CRS
PIN_A9
GMII and MII carrier sense
2.5V
NET_GTX_CLK
PIN_C11
GMII Transmit Clock
2.5
NET_LINK100
PIN_A7
Parallel LED output of 100BASE-TX link
2.5V
NET_INT_n
PIN_C13
Interrupt open drain output
2.5V
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