Terasic HAN Pilot Platform Hardware Manual
HAN Pilot Platform
Hardware Manual
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July 5, 2019
TABLE OF CONTENTS
Chapter 1 Overview ....................................................................................................................... 3
1.1 The Package Contents ................................................................................................................................ 4
1.2 HAN Pilot Platform System CD ................................................................................................................. 4
1.3 Getting Help ............................................................................................................................................... 4
Chapter 2 Board Components ........................................................................................................ 6
2.1 Components and Layout ............................................................................................................................. 6
2.2 Block Diagram ............................................................................................................................................ 9
Chapter 3 Board Settings and Status Component ........................................................................ 11
3.1 Board Setting Switches ............................................................................................................................. 11
3.2 Board Setting Headers .............................................................................................................................. 12
3.3 Status LED ................................................................................................................................................ 15
3.4 JTAG Interface ......................................................................................................................................... 17
Chapter 4 FPGA Fabric Components ........................................................................................... 19
4.1 User Interface (LED/7-SEG/Button/Switch) ............................................................................................ 19
4.2 USB Type-C Port ...................................................................................................................................... 21
4.3 SFP+ Connector........................................................................................................................................ 26
4.4 SATA ........................................................................................................................................................ 29
4.5 PCIe .......................................................................................................................................................... 32
4.6 DDR4 ........................................................................................................................................................ 34
4.7 HDMI Transmitter and Receiver .............................................................................................................. 43
4.8 Gigabit Ethernet ........................................................................................................................................ 45
4.9 FMC Connector ........................................................................................................................................ 46
4.10 Temperature Sensor, Fan Control and Power Monitor ........................................................................... 54
4.11 Gyroscope, Accelerometer and Magnetometer ....................................................................................... 55
Chapter 5 HPS Fabric Components ............................................................................................. 57
5.1 User Push-buttons and LEDs .................................................................................................................... 57
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5.2 Gigabit Ethernet ........................................................................................................................................ 57
5.3 UART to USB ........................................................................................................................................... 59
5.4 Micro SD Card Socket .............................................................................................................................. 60
5.5 USB OTG ................................................................................................................................................. 60
5.6 GPIO Header ............................................................................................................................................ 61
5.7 DDR4 (HPS) ............................................................................................................................................. 62
Chapter 6 System Clocks ............................................................................................................. 67
Chapter 7 Power .......................................................................................................................... 69
Chapter 8 HAN Pilot Platform System Builder .............................................................................. 70
8.1 Introduction .............................................................................................................................................. 70
8.2 General Design Flow ................................................................................................................................ 70
8.3 Using HAN Pilot Platform System Builder .............................................................................................. 71
Chapter 9 Appendix ..................................................................................................................... 79
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Chapter 1
Overview
The HAN Pilot Platform provides users a combination of ARM software and FPGA hardware
development platforms. It has a vast memory device and peripherals on the hardware. This kit also
includes resourceful reference designs to help users to accomplish their design needs. The hardware
offers in the HAN Pilot Platform has the maximum capacity with 660K LEs in Arria 10 SoC FPGA
and featuring various types of high-speed image interface such as: HDMI, Display Port, and
12G-SDI and a large capacity of DDR4 memory. The board’s high speed network interface, Gigabit
Ethernet and SFP+10GbE, provides hardware resources for network communications related
applications.
The HPS can be reboot with any of these three removable daughter cards: MicroSD Card, Nand
Flash, and QSPI Flash. The FPGA on the main board can be connected to DDR4-SODIMM Socket
in addition to the DDR4 memory module. The FPGA on the main board can also be connected to
the Terasic QDR Memory Module as well. Beside the DDR4 memory module, you can also directly
connect to the FPGA on the main board via the High Pin Count FMC expansion port to expand
variety of functions.
The PCIe Gen3 x4 Connector interface comes with the Terasic PCA PCIe and PCIe Cable, which
can be used to connect the Host PC to allow data between the FPGA and the Host PC. The USB
Type-C interface on the motherboard allows the motherboard to obtain power for the host PC. The
Host PC displays information and images through the high-speed transmission USB 3.0 or the
Display Port.
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TThhee PPaacckkaaggee CCoonntteennttss
Figure 1-1 Package Contents
1. HAN Pilot Platform Kit
2. MicroSD Card (Installed) and Card Reader
3. Fan (Installed)
4. Two Type A to Mini-B USB Cables
5. 12V DC Power Supply (Installed)
6. AC Power Cord (USA)
7. One 4GB DDR4 ECC SO-DIMM Module (Installed)
8. Screws, Copper Stands, and Silicon Footstands
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HHAANN PPiilloott PPllaattffoorrmm SSyysstteemm CCDD
The HAN Pilot Platform System CD contains all the documents and supporting materials associated
with HAN Pilot Platform, including the user manual, system builder, reference designs and device
datasheets.
Users can download this system CD from the link: http://HAN Pilot Platform.terasic.com/cd.
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GGeettttiinngg HHeellpp
Here are the addresses where you can get help if you encounter any problems:
▪ Terasic Technologies
▪ 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
▪ Email: support@terasic.com
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▪ Tel.: +886-3-575-0880
▪ Website: HAN Pilot Platform.terasic.com
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Chapter 2
Board Components
This chapter provides an introduction to the features and design characteristics of the board.
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CCoommppoonneennttss aanndd LLaayyoouutt
Figure 2-1 and Figure 2-2 shows a photograph of the board. It depicts the layout of the board and
indicates the location of the connectors and key components.
Figure 2-1 HAN Pilot Platform (top view)
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Figure 2-2 HAN Pilot Platform (bottom view)
The HAN Pilot Platform has many features that allow users to implement a wide range of designed
circuits, from simple circuits to various multimedia projects.
The following hardware are provided on the board:
◼ FPGA Device
• Intel ® Arria10® SoC 10AS066K3F40E2SG device (660K LEs)
• USB-Blaster II onboard for programming; JTAG Mode
• Serial configuration device – EPCQL1024
• One DDR4 SO-DIMM Socket, support ECC
• On-board 1GB DDR4-2400, 32-bit data width
• USB Type-C Interface
• Power Delivery
• DisplayPort TX/RX with 4 lanes
• USB 3.0/2.0
• HDMI TX/RX 2.0 for 4K2K@60- FPGA Transceiver
• PCIe Cabling Socket at Gen3 x4
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• SFP+ Socket x4, 40Gbps
• SATA 3.0 Host and SATA Device x2 (SATA Connector x4)
• One Gigabit Ethernet Port
• SMA Clock-In and Clock-Out
• High Pin Count FMC Connector. Support VADJ 1.2V/1.5V/1.8V.
• Accelerometer, Gyroscope and Magnetometer
• Temperature Sensor
• Fan Control
• LED x2, KEY x2, Switch x2, 7-Segment x2
◼ HPS (Hard Processor System)
• 1.5GHz Dual-core ARM Cortex-A9 processor
• Boost Flash Slot:
• 1024 Mb QSPI Flash
• Nand Flash
• MicroSD Socket
• On-board 1GB DDR4-2400, 32-bit data width
• 1 Gigabit Ethernet PHY with RJ45 connector
• USB OTG Port, USB mini-AB connector
• UART to USB, USB Mini-B connector
• RTC
• One user button and one user LED
• Warm reset button and cold reset button
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2.2 Block Diagram
Figure 2-3 is the block diagram of the board. All the connections are established through the Arria
10 SoC FPGA device to provide maximum flexibility for users. Users can configure the FPGA to
implement any system design.
Detailed information about Figure 2-3 are listed below.
▪ Arria 10 SoC 10AS066K3F40E2SG/10AS057K3F40E2SG FPGA
▪ Dual-core ARM Cortex-A9 (HPS)
▪ 660K programmable logic elements
▪ 42,660 Kbits embedded memory
▪ Hard memory controllers x5
▪ Transceivers x48(17.4 Gbps)
▪ 18-bit x 19-bit multipliers x3,356
▪ Accelerometer & Gyroscope Device MPU9250
▪ Configuration
▪ EPCQ1024L Serial Configuration Device
▪ Onboard USB-Blaster II (Mini-B USB connector)
▪ Memory Device
▪ On-board 1GB DDR4-2400, 32-bit data width
▪ Two DDR4 SO-DIMM SDRAM socket
▪ Micro SD card socket
▪ Communication
▪ USB OTG (Mini-AB USB connector)
▪ UART-to-USB (Mini-B USB Connector)
▪ Giga Ethernet x2
▪ PCIe Gen3 x4 Cabling Socket
▪ Expansion Ports
▪ FMC connector
▪ one HPC (high-pin count) FMC connector with xcvr
▪ Adjustable VADJ:1.2V/1.5V/1.8V
▪ Multimedia Interface
▪ HDMI TX and RX ports
▪ Clock
▪ Two SMA connectors for SMA Clock-In and Clock-Out
▪ On-board PLLs
▪ General user input/output
▪ Buttons x3 (FPGA x2, HPS x1)
▪ Switches x2 on FPGA
▪ LEDs x3 (FPGA x2, HPS x1)
▪ 7-segment displays x2
▪ System Monitor and Control
▪ Temperature Sensor on FPGA
▪ 12V Power Monitor
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▪ Power Controller
▪ I2C Fan Control
▪ Power
▪ 12V DC input
Figure 2-3 Block diagram of HAN Pilot Platform
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Chapter 3
Board Settings and Status
Component
This chapter describes all the setting devices on HAN Pilot Platform board and their functions, such
as Switches and Headers. We also will describe the function of some status LEDs. The JTAG
interface will be described at the end of this chapter.
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◼ Mode Select Switches
Mode Select Switch (SW5) is used to set the HAN Pilot Platform FPGA MSEL pin value. These
MSEL pins determined the Configuration Mode of the FPGA. Table 3-1 list the MSEL setting for
configuration scheme of FPGA, when MSEL is set to AS mode (Factory default setting), FPGA will
be booted from EPCQ device (See Figure 3-1). When MSEL is set to FPP mode (See Figure 3-2),
FPGA can be configured by HPS Fabric (From Micro SD Card).
Table 3-1 MSEL setting for configuration scheme of FPGA
Configuration Scheme
SW5 MSEL[2..0] Setting
Description
AS Mode (Factory Default)
010
FPGA boot from EPCQ
FPP Mode
000
FPGA boot from Micro SD Card
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Figure 3-1 The AS mode setting of SW5
Figure 3-2 The FPP mode setting of SW5
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◼ JTAG Interface Header
J17 is the header used to set the JTAG bus of FMC connector connect to JTAG interface of HAN
Pilot Platform system. The FMC connector will not be included in the JTAG chain if the headers are
set to open (See Figure 3-3). Table 3-2 list the setting of the J17 header.
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Table 3-2 JTAG Interface Headers Setting
Header
Setting
Descriptions
J17
Open (Default Setting)
Disable the JTAG interface of the FMC connector into the JTAG
chain
Figure 3-3 The FMC JTAG Header
◼ FMC_VCCIO Select Header
JP2 is used to set the VCCIO voltage of FPGA I/O on FMC connector, as 1.2V/1.5V/1.8V are
supported, the FMC connector can support various I/0 standard FMC daughtercards. Table 3-3 list
the FMC_VCCIO Headers Setting.
Table 3-3 FMC_VCCIO Headers Setting
JP2 Setting
FMC VCCIO Voltage
1.2V
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1.5V
1.8V (Default Setting)
Figure 3-4 The FMC VCCIO select header
◼ PMODE Select Header
The USB 3.0 Controller (Cypress FX3) on the HAN Pilot Platform can be booted from the
different sources, selected by the configuration of the PMODE header (JP4/JP5/JP6) on HAN
Pilot Platform. Table 3-4 shows the boot options and associated settings. The default boot device
is the from a serial flash via SPI interface.
Table 3-4 PMODE Headers Setting
PMODE [2:0] (JP6/JP5/JP4) Setting
Boot Source
F00
Sync ADMux (16-bit)
F01
Async ADMux (16-bit)
F11
USB boot
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F0F
Async SRAM (16-bit)
F1F
I2C, On Failure, USB Boot is Enabled
1FF
I2C only
0F1(Default)
SPI, On Failure, USB Boot is Enabled
◼ Note: F indicates Floating
Figure 3-5 The PMODE select header
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SSttaattuuss LLEEDD
This section describes the all status LED for the interfaces on HAN Pilot Platform board. Figure
3-6 shows all the status LED on the HAN Pilot Platform. Following are the detailed descriptions of
these interface LED.
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Figure 3-6 The status LED on the HAN Pilot Platform board
◼ UART Interface
Table 3-5 list the two status LEDs for UART interface.
Table 3-5 Status LED for UART Interface
Component
Reference
Status
Descriptions
TXD1
UART_TXD
ON
Transmitting
RXD1
UART_ＲXD
ON
Receiving
◼ SFP Interface
Table 3-6 list the four status LEDs for SFP interface.
Table 3-6 Indicator LED for SFP Interface
Component
Reference
Status
Descriptions
D4
SFPA_MOD0_PRSNT_n
ON
Indicate that the SFP module is
present on the SFPA
D3
SFPB_MOD0_PRSNT_n
ON
Indicate that the SFP module is
present on the SFPB
D2
SFPC_MOD0_PRSNT_n
ON
Indicate that the SFP module is
present on the SFPC
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D1
SFPD_MOD0_PRSNT_n
ON
Indicate that the SFP module is
present on the SFPD
◼ Ethernet Interface
Table 3-7 list the four status LEDs for Ethernet interface.
Table 3-7 Status LED for Ethernet Interface
Component
Reference
Status
Descriptions
D8
ETH_LED_TX
ON
Transmitting
D9
ETH_LED_RX
ON
Receiving
D10
ETH_LINK1000
ON
1000Mbps Link UP
D11
ETH_LINK100
ON
100Mbps Link UP
◼ Power
Table 3-8 list the two status LEDs for power.
Table 3-8 Status LED for Power
Component
Reference
Status
Descriptions
D31
12V~20V Power Indicator
ON
Illuminates when 12V~20V Power Supply is active
◼ USB Blaster
Table 3-9 list the two status LEDs for USB Blaster interface.
Table 3-9 Status LED for USB Blaster Interface
Component
Reference
Status
Descriptions
D5
JTAG_TX
ON
Illuminates when JTAG interface is transmitting data
D6
JTAG_RX
ON
Illuminates when JTAG interface is receiving data
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JJTTAAGG IInntteerrffaaccee
Figure 3-7 shows the JTAG interface of HAN Pilot Platform. Users can access to the JTAG
interface through the USB Blaster II circuit or connect external blaster to external blaster header. All
the devices which implement JTAG are connect to MAX II device, and switch via MAX II internal
switch logic. By using headers J17, users can include FMC connector JTAG interface in the HAN
Pilot Platform JTAG Chain, or exclude them from the JTAG Chain. The default JTAG path for
HAN Pilot Platform is: USB Blaster II ==> HPS ==> FPGA ==> (Bypass FMC connector) ==>
USB Blaster II. When the External JTAG connector is connected to the external blaster, the On
board's USB blaster II function will be replaced by the external blaster.
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Figure 3-7 JTAG interface of HAN Pilot Platform
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Chapter 4
FPGA Fabric Components
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The board has two push-buttons connected to the FPGA, as shown in Figure 4-1. The two
push-buttons named KEY0 and KEY1 are connected directly to the Arria 10 SoC FPGA. Table 4-1
list the pin assignment of user push-buttons.
Figure 4-1 Connections between the push-buttons and the Arria 10 SoC FPGA
Table 4-1 Pin Assignment of Push-buttons
Signal Name
FPGA Pin Number
Description
I/O Standard
KEY[0]
PIN_AU15
Push-button[0]
1.8V
KEY[1]
PIN_AT15
Push-button[1]
1.8V
CPU_RESET_n
PIN_AN18
CPU_RESET button
1.8V
There are two slide switches connected to the FPGA, as shown in Figure 4-2. These switches are
not debounced and to be used as level-sensitive data inputs to a circuit. Each switch is connected
directly and individually to the FPGA. When the switch is set to the DOWN position (towards the
edge of the board), it generates a low logic level to the FPGA. When the switch is set to the UP
position, a high logic level is generated to the FPGA. Table 4-2 list the pin assignment of switches.
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Figure 4-2 Connections between the switches and the Arria 10 SoC FPGA
Table 4-2 Pin Assignment of Switches
Signal Name
FPGA Pin Number
Description
I/O Standard
SW[0]
PIN_AJ19
Slide Switch[0]
1.8 V
SW[1]
PIN_AV16
Slide Switch[1]
1.8 V
There are also two user-controllable LEDs connected to the FPGA. Each LED is driven directly and
individually by the Arria 10 SoC FPGA; driving its associated pin to a high logic level or low level
to turn the LED on or off, respectively. Figure 4-3 shows the connections between LEDs and Arria
10 SoC FPGA. Table 4-3 list the pin assignment of LEDs.
Figure 4-3 Connections between the LEDs and the Arria 10 SoC FPGA
Table 4-3 Pin Assignment of LEDs
Signal Name
FPGA Pin Number
Description
I/O Standard
LEDG[0]
PIN_C26
LED [0]
1.8 V
LEDG[1]
PIN_B24
LED [1]
1.8 V
The DE10-Advanced board has two 7-segment displays. These displays are paired to display
numbers in various sizes. Figure 4-4 shows the connection of seven segments (common anode) to
pins on Arria 10 SoC FPGA. The segment can be turned on or off by applying a low logic level or
high logic level from the FPGA, respectively. Each segment in a display is indexed from 0 to 6,
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with corresponding positions given in Figure 4-4. Table 4-4 shows the pin assignment of FPGA to
the 7-segment displays.
Figure 4-4 Connections between the 7-segment and the Arria 10 SoC FPGA
Table 4-4 Pin Assignment of 7-segment
Signal Name
FPGA Pin Number
Description
I/O Standard
HEX0[0]
PIN_AT32
Seven Segment Digit 0[0]
1.8V
HEX0[1]
PIN_AR32
Seven Segment Digit 0[1]
1.8V
HEX0[2]
PIN_AU32
Seven Segment Digit 0[2]
1.8V
HEX0[3]
PIN_AU30
Seven Segment Digit 0[3]
1.8V
HEX0[4]
PIN_AT30
Seven Segment Digit 0[4]
1.8V
HEX0[5]
PIN_AU29
Seven Segment Digit 0[5]
1.8V
HEX0[6]
PIN_AV29
Seven Segment Digit 0[6]
1.8V
HEX0_DP
PIN_AU31
Seven Segment Digit 0_DP
1.8V
HEX1[0]
PIN_AT28
Seven Segment Digit 1[0]
1.8V
HEX1[1]
PIN_AT29
Seven Segment Digit 1[1]
1.8V
HEX1[2]
PIN_AR30
Seven Segment Digit 1[2]
1.8V
HEX1[3]
PIN_AM27
Seven Segment Digit 1[3]
1.8V
HEX1[4]
PIN_AL27
Seven Segment Digit 1[4]
1.8V
HEX1[5]
PIN_AK27
Seven Segment Digit 1[5]
1.8V
HEX1[6]
PIN_AM26
Seven Segment Digit 1[6]
1.8V
HEX1_DP
PIN_AR31
Seven Segment Digit 1_DP
1.8V
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UUSSBB TTyyppee--CC PPoorrtt
The HAN Pilot Platform board features one USB Type-C connector. It is designed for high-speed
data transmission with computers and image output applications. Figure 4-5 shows the block
diagram of the connection between USB Type-C port and FPGA.
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Figure 4-5 Block diagram of the connection between USB Type-C port and FPGA
As shown in Figure 4-5, it connects to FPGA through several switch circuits and USB controllers,
users can switch USB Type-C connector to a variety of applications as below:
▪ USB 3.0 Device to USB Host PC
▪ USB 2.0 OTG
▪ DisplayPort Source Application (Need DP Source IP)
The USB Type-C Port Controller will detect the type of USB device connected to the Type-C
connector, automatically switches the "USB and DP" switch (U11), and connects the USB Type-C
connector to the appropriate application in the HAN Pilot kit. If user connects a Display port
monitor to the USB type-C connector of the Han Pilot kit, the "USB and DP" switch will be
switched to the transceiver path of the FPGA by the USB type-C Port Controller, which is useful for
the Display port output application. Similarly, when a USB 3.0 host device is connected to the USB
Type-C connector, the "USB and DP" switch will be switched to the path of the cypress FX3.0 USB
controller for USB 3.0 applications.
We will describe the circuits diagram and these functions in detail below.
◼ Display Port
As shown in Figure 4-6, USB Type-C port can connect to FPGA transceiver. Users can implement
a Display port source mode IP in the FPGA, the HAN Pilot Platform board will implement the
features of display port source. Through the USB Type-C cable, users can connect HAN Pilot
Platform board to the monitor which supports Display port interface. Then the image processed by
FPGA can be displayed on the monitor. The display port provides data rate up to 5.4Gbps per lane
and 4 lanes in total, it supports DisplayPort 1.2a Spec. Table 4-5 list the pin assignment of
DisplayPorts.
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Figure 4-6 USB Type-C Application: DisplayPort TX Source
Table 4-5 DisplayPort Signal Names and Functions
Signal Name
FPGA Pin
Number
Description
I/O Standard
DP_REFCLK_p
AM31
Display reference clock form
PLL
LVDS
DP_TX_p[0]
AW37
TX Lane 1
HSSI Differential I/O
DP_TX_p[1]
AV39
TX Lane 2
HSSI Differential I/O
DP_TX_p[2]
AU37
TX Lane 3
HSSI Differential I/O
DP_TX_p[3]
AT39
TX Lane 4
HSSI Differential I/O
DP_AUX_p
AM22
Display port AUX port
DIFFERENTIAL 1.8-V SSTL
CLASS I
DP_DX_SEL
AB27
Display Port channel TX or
RX(Reserve) select.
DP_DX_SEL = 0 : USB
TypeC in Display TX mode .
DP_DX_SEL = 1(Reserve):
USB TypeC in Display RX
mode
1.8 V
DP_AUX_SEL
AC28
AUX/DDC Selection Control
Pin in Conjunction with
Dx_SEL Pin
1.8 V
USBDP_SW_CNF0
AA27
Display port Switch
Configure 0
1.8 V
USBDP_SW_CNF1
AB26
Display port Switch
Configure 1
1.8 V
USBDP_SW_CNF2
AB25
Display port Switch
1.8 V
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