Terasic DE5-Net User Manual
DE5-Net User Manual
www.terasic.com
August 4, 2017
1
DE5-Net User Manual
www.terasic.com
August 4, 2017
2
CONTENTS
CHAPTER 1
OVERVIEW
........................................................................................................................................ 4
1.1 GENERAL DESCRIPTION ............................................................................................................................................ 4
1.2 KEY FEATURES .......................................................................................................................................................... 5
1.3 BLOCK DIAGRAM ...................................................................................................................................................... 6
CHAPTER 2
BOARD COMPONENTS
.................................................................................................................. 10
2.1 BOARD OVERVIEW .................................................................................................................................................. 10
2.2 CONFIGURATION, STATUS AND SETUP ..................................................................................................................... 11
2.3 GENERAL USER INPUT/OUTPUT .............................................................................................................................. 14
2.4 TEMPERATURE SENSOR AND FAN CONTROL ............................................................................................................ 17
2.5 CLOCK CIRCUIT ...................................................................................................................................................... 18
2.6 RS-422 SERIAL PORT ................................ ................................ ................................................................ .............. 21
2.7 FLASH MEMORY ................................................................................................................................................... 22
2.8 DDR3 SO-DIMM ................................................................................................................................................... 25
2.9 QDRII+ SRAM ...................................................................................................................................................... 32
2.10 SPF+ PORTS .......................................................................................................................................................... 39
2.11 PCI EXPRESS ......................................................................................................................................................... 42
2.12 SATA ................................ ................................................................ ................................ .................................... 44
CHAPTER 3
SYSTEM BUILDER
......................................................................................................................... 48
3.1 INTRODUCTION ....................................................................................................................................................... 48
3.2 GENERAL DESIGN FLOW ......................................................................................................................................... 49
3.3 USING SYSTEM BUILDER ........................................................................................................................................ 50
CHAPTER 4
FLASH PROGRAMMING
................................................................................................................. 57
4.1 CFI FLASH MEMORY MAP ...................................................................................................................................... 57
4.2 FPGA CONFIGURE OPERATION ............................................................................................................................... 58
4.3 FLASH PROGRAMMING WITH USERS DESIGN .......................................................................................................... 58
4.4 RESTORE FACTORY SETTINGS ................................................................................................................................. 60
CHAPTER 5
PROGRAMMABLE OSCILLATOR
................................................................................................. 62
5.1 OVERVIEW .............................................................................................................................................................. 62
5.2 SI570 EXAMPLE BY RTL ......................................................................................................................................... 66
DE5-Net User Manual
www.terasic.com
August 4, 2017
3
5.3 SI570 AND CDCM PROGRAMMING BY NIOS II ........................................................................................................ 73
CHAPTER 6
MEMORY REFERENCE DESIGN
.................................................................................................. 78
6.1 QDRII+ SRAM TEST ............................................................................................................................................. 78
6.2 DDR3 SDRAM TEST ............................................................................................................................................. 81
6.3 DDR3 SDRAM TEST BY NIOS II ............................................................................................................................ 83
CHAPTER 7
PCI EXPRESS REFERENCE DESIGN
....................................................................................... 87
7.1 PCI EXPRESS SYSTEM INFRASTRUCTURE ................................................................................................................ 87
7.2 FPGA PCI EXPRESS SYSTEM DESIGN ..................................................................................................................... 88
7.3 PC PCI EXPRESS SYSTEM DESIGN .......................................................................................................................... 93
7.4 FUNDAMENTAL COMMUNICATION ......................................................................................................................... 105
7.5 EXAMPLE 2: IMAGE PROCESS APPLICATION .......................................................................................................... 110
CHAPTER 8
TRANSCEIVER VERIFICATION
.................................................................................................. 115
8.1 TEST CODE ............................................................................................................................................................ 115
8.2 LOOPBACK FIXTURE ............................................................................................................................................. 115
8.3 TESTING ................................................................................................................................................................ 117
ADDITIONAL INFORMATION
................................................................................................................................... 119
DE5-Net User Manual
www.terasic.com
August 4, 2017
4
Chapter 1
Overview
This chapter provides an overview of the DE5-Net Development Board and installation guide.
11..1
1
GGeenneerraall DDeessccrriippttiioonn
The Terasic DE5-Net Stratix V GX FPGA Development Kit provides the ideal hardware solution
for designs that demand high capacity and bandwidth memory interfacing, ultra-low latency
communication, and power efficiency. With a full-height, 3/4-length form-factor package, the
DE5-Net is designed for the most demanding high-end applications, empowered with the
top-of-the-line Altera Stratix V GX, delivering the best system-level integration and flexibility in
the industry.
The Stratix® V GX FPGA features integrated transceivers that transfer at a maximum of 12.5 Gbps,
allowing the DE5-Net to be fully compliant with version 3.0 of the PCI Express standard, as well as
allowing an ultra low-latency, straight connections to four external 10G SFP+ modules. Not relying
on an external PHY will accelerate mainstream development of network applications enabling
customers to deploy designs for a broad range of high-speed connectivity applications. For designs
that demand high capacity and high speed for memory and storage, the DE5-Net delivers with two
independent banks of DDR3 SO-DIMM RAM, four independent banks of QDRII+ SRAM,
high-speed parallel flash memory, and four SATA ports. The feature-set of the DE5-Net fully
supports all high-intensity applications such as low-latency trading, cloud computing,
high-performance computing, data acquisition, network processing, and signal processing.
DE5-Net User Manual
www.terasic.com
August 4, 2017
5
11..2
2
KKeeyy FFeeaattuurreess
The following hardware is implemented on the DE5-Net board:
FPGA
Altera Stratix® V GX FPGA (5SGXEA7N2F45C2)
FPGA Configuration
On-Board USB Blaster II or JTAG header for FPGA programming
Fast passive parallel (FPPx32) configuration via MAX II CPLD and flash memory
General user input/output:
10 LEDs
4 push-buttons
4 slide switches
2 seven-segment displays
Clock System
50MHz Oscillator
Programmable oscillators Si570, CDCM61001 and CDCM61004
One SMA connector for external clock input
One SMA connector for clock output
Memory
DDR3 SO-DIMM SDRAM
QDRII+ SRAM
FLASH
Communication Ports
Four SFP+ connectors
Two Serial ATA host ports
Two Serial ATA device ports
PCI Express (PCIe) x8 edge connector
One RS422 transceiver with RJ45 connector
DE5-Net User Manual
www.terasic.com
August 4, 2017
6
System Monitor and Control
Temperature sensor
Fan control
Power
PCI Express 6-pin power connector, 12V DC Input
PCI Express edge connector power
Mechanical Specification
PCI Express full-height and 3/4-length
11..3
3
BBlloocckk DDiiaaggrraamm
94H94HFigure 1-1 shows the block diagram of the DE5-Net board. To provide maximum flexibility for the
users, all key components are connected with the Stratix V GX FPGA device. Thus, users can
configure the FPGA to implement any system design.
DE5-Net User Manual
www.terasic.com
August 4, 2017
7
Figure 1-1 Block diagram of the DE5-Net board
Below is more detailed information regarding the blocks in Figure 1-1.
Stratix V GX FPGA
5SGXEA7N2F45C2
622,000 logic elements (LEs)
50-Mbits embedded memory
48 transceivers (12.5Gbps)
512 18-bit x 18-bit multipliers
256 27-bit x 27-bit DSP blocks
DE5-Net User Manual
www.terasic.com
August 4, 2017
8
2 PCI Express hard IP blocks
840 user I/Os
210 full-duplex LVDS channels
28 phase locked loops (PLLs)
JTAG Header and FPGA Configuration
On-board USB Blaster II or JTAG header for use with the Quartus II Programmer
MAXII CPLD EPM2210 System Controller and Fast Passive Parallel (FPP) configuration
Memory devices
32MB QDRII+ SRAM
Up to 8GB DDR3 SO-DIMM SDRAM
256MB FLASH
General user I/O
10 user controllable LEDs
4 user push buttons
4 user slide switches
2 seven-segment displays
On-Board Clock
50MHz oscillator
Programming PLL providing clock for 10G SFP+ transceiver
Programming PLL providing clock for SATA or 1G SFP+ transceiver
Four Serial ATA ports
SATA 3.0 standard at 6Gbps signaling rate
DE5-Net User Manual
www.terasic.com
August 4, 2017
9
Four SFP+ ports
Four SFP+ connector (10 Gbps+)
PCI Express x8 edge connector
Support for PCIe Gen1/2/3
Edge connector for PC motherboard with x8 or x16 PCI Express slot
Power Source
PCI Express 6-pin DC 12V power
PCI Express edge connector power
10
Chapter 2
Board Components
This chapter introduces all the important components on the DE5-Net.
22..1
1
BBooaarrdd OOvveerrvviieeww
Figure 2-1 is the top and bottom view of the DE5-Net development board. It depicts the layout of
the board and indicates the location of the connectors and key components. Users can refer to this
figure for relative location of the connectors and key components.
Figure 2-1 FPGA Board (Top)
DE5-Net User Manual
www.terasic.com
August 4, 2017
11
Figure 2-2 FPGA Board (Bottom)
22..2
2
CCoonnffiigguurraattiioonn,, SSttaattuuss aanndd SSeettuupp
Configure
The FPGA board supports two configuration methods for the Stratix V FPGA:
Configure the FPGA using the on-board USB-Blaster II.
Flash memory configuration of the FPGA using stored images from the flash memory on
power-up.
For programming by on-board USB-Blaster II, the following procedures show how to download a
configuration bit stream into the Stratix V GX FPGA:
Make sure that power is provided to the FPGA board
Connect your PC to the FPGA board using a mini-USB cable and make sure the USB-Blaster
II driver is installed on PC.
Launch Quartus II programmer and make sure the USB-Blaster II is detected.
In Quartus II Programmer, add the configuration bit stream file (.sof), check the associated
“Program/Configure” item, and click “Start” to start FPGA programming.
DE5-Net User Manual
www.terasic.com
August 4, 2017
12
Status LED
The FPGA Board development board includes board-specific status LEDs to indicate board status.
Please refer to Table 2-1 for the description of the LED indicator.
Table 2-1 Status LED
Board
Reference
LED Name
Description
D2
12-V Power
Illuminates when 12-V power is active.
D1
3.3-V Power
Illuminates when 3.3-V power is active.
D15
CONF DONE
Illuminates when the FPGA is successfully configured.
Driven by the MAX II CPLD EPM2210 System Controller.
D16
Loading
Illuminates when the MAX II CPLD EPM2210 System
Controller is actively configuring the FPGA. Driven by the
MAX II CPLD EPM2210 System Controller with the
Embedded Blaster CPLD.
D17
Error
Illuminates when the MAX II CPLD EPM2210 System
Controller fails to configure the FPGA. Driven by the MAX II
CPLD EPM2210 System Controller.
D18
PAGE
Illuminates when FPGA is configured by the factory
configuration bit stream.
Setup PCI Express Control DIP switch
The PCI Express Control DIP switch (SW7) is provided to enable or disable different
configurations of the PCIe Connector. Table 2-2 lists the switch controls and description.
Table 2-2 SW3 PCIe Control DIP Switch
Board
Reference
Signal Name
Description
Default
SW7.1
PCIE_PRSNT2n_x1
On : Enable x1 presence detect
Off: Disable x1 presence detect
Off
SW7.2
PCIE_PRSNT2n_x4
On : Enable x4 presence detect
Off: Disable x4 presence detect
Off
SW7.3
PCIE_PRSNT2n_x8
On : Enable x8 presence detect
Off: Disable x8 presence detect
On
DE5-Net User Manual
www.terasic.com
August 4, 2017
13
Setup Configure Mode Control DIP switch
The Configure Mode Control DIP switch (SW6) is provided to specify the configuration mode of
the FPGA. As currently only one mode is supported, please set all positions as shown in 9Figure 2-3.
Figure 2-3 6-Position DIP switch for Configure Mode
Select Flash Image for Configuration
The Image Select DIP switch (SW5) is provided to specify the image for configuration of the FPGA.
Setting Position 2 of SW5 to high (right) specifies the default factory image to be loaded, as shown
in Figure 2-4. Setting Position 2 of SW5 to low (left) specifies the DE5-Net to load a user-defined
image, as shown in 1Figure 2-5.
Figure 2-4 2-position DIP switch for Image Select – Factory Image Load
DE5-Net User Manual
www.terasic.com
August 4, 2017
14
Figure 2-5 2-position DIP switch for Image Select – User Image Load
22..3
3
GGeenneerraall UUsseerr IInnppuutt//OOuuttppuutt
This section describes the user I/O interface to the FPGA.
User Defined Push-buttons
The FPGA board includes four user defined push-buttons that allow users to interact with the Stratix
V GX device. Each push-button provides a high logic level or a low logic level when it is not
pressed or pressed, respectively. Table 2-3 lists the board references, signal names and their
corresponding Stratix V GX device pin numbers.
Table 2-3 Push-button Pin Assignments, Schematic Signal Names, and Functions
Board
Reference
Schematic
Signal Name
Description
I/O
Standard
Stratix V GX
Pin Number
PB6
BUTTON0
High Logic Level when the button is
not pressed
2.5-V
PIN_AK15
PB5
BUTTON1
2.5-V
PIN_AK14
PB4
BUTTON2
2.5-V
PIN_AL14
PB3
BUTTON3
2.5-V
PIN_AL15
User-Defined Slide Switch
There are four slide switches on the FPGA board to provide additional FPGA input control. When a
slide switch is in the DOWN position or the UPPER position, it provides a low logic level or a high
logic level to the Stratix V GX FPGA, respectively, as shown in 0Figure 2-6.
DE5-Net User Manual
www.terasic.com
August 4, 2017
15
Figure 2-6 4 Slide switches
Table 2-4 lists the signal names and their corresponding Stratix V GX device pin numbers.
Table 2-4 Slide Switch Pin Assignments, Schematic Signal Names, and Functions
Board
Reference
Schematic
Signal Name
Description
I/O
Standard
Stratix V GX
Pin Number
SW0
SW0
High logic level when SW in the UPPER
position.
1.8-V
PIN_B25
SW1
SW1
1.8-V
PIN_A25
SW2
SW2
1.8-V
PIN_B23
SW3
SW3
1.8-V
PIN_A23
User-Defined LEDs
The FPGA board consists of 10 user-controllable LEDs to allow status and debugging signals to be
driven to the LEDs from the designs loaded into the Stratix V GX device. Each LED is driven
directly by the Stratix V GX FPGA. The LED is turned on or off when the associated pins are
driven to a low or high logic level, respectively. A list of the pin names on the FPGA that are
connected to the LEDs is given in Table 2-5.
Table 2-5 User LEDs Pin Assignments, Schematic Signal Names, and Functions
Board
Reference
Schematic
Signal Name
Description
I/O
Standard
Stratix V GX
Pin Number
DE5-Net User Manual
www.terasic.com
August 4, 2017
16
D8
LED0
Driving a logic 0 on the I/O port turns the LED
ON.
Driving a logic 1 on the I/O port turns the LED
OFF.
2.5-V
PIN_AW37
D9
LED1
2.5-V
PIN_AV37
D10
LED2
2.5-V
PIN_BB36
D11
LED3
2.5-V
PIN_BB39
D7-1
LED_BRACKET0
2.5-V
PIN_AH15
D7-3
LED_BRACKET1
2.5-V
PIN_AH13
D7-5
LED_BRACKET2
2.5-V
PIN_AJ13
D7-7
LED_BRACKET3
2.5-V
PIN_AJ14
J8-10
LED_RJ45_L
2.5-V
PIN_AG15
J8-12
LED_RJ45_R
2.5-V
PIN_AG16
7-Segment Displays
The FPGA board has two 7-segment displays. As indicated in the schematic in Figure 2-7, the
seven segments are connected to pins of the Stratix V GX FPGA. Applying a low or high logic level
to a segment will turn it on or turn it off, respectively.
Each segment in a display is identified by an index listed from 0 to 6 with the positions given in
Figure 2-8. In addition, the decimal point is identified as DP. Table 2-6 shows the mapping of the
FPGA pin assignments to the 7-segment displays.
Figure 2-7 Connection between 7-segment displays and Stratix V GX FPGA
DE5-Net User Manual
www.terasic.com
August 4, 2017
17
Figure 2-8 Position and index of each segment in a 7-segment display
Table 2-6 User LEDs Pin Assignments, Schematic Signal Names, and Functions
Board
Reference
Schematic
Signal
Name
Description
I/O
Standard
Stratix V GX
Pin Number
HEX1
HEX1_D0
User-Defined 7-Segment Display. Driving logic 0 on
the I/O port turns the 7-segment signal ON. Driving
logic 1 on the I/O port turns the 7-segment signal
OFF.
1.5-V
PIN_H18
HEX1
HEX1_D1
1.5-V
PIN_G16
HEX1
HEX1_D2
1.5-V
PIN_F16
HEX1
HEX1_D3
1.5-V
PIN_A7
HEX1
HEX1_D4
1.5-V
PIN_B7
HEX1
HEX1_D5
1.5-V
PIN_C9
HEX1
HEX1_D6
1.5-V
PIN_D10
HEX1
HEX1_DP
1.5-V
PIN_E9
HEX0
HEX0_D0
1.5-V
PIN_G8
HEX0
HEX0_D1
1.5-V
PIN_H8
HEX0
HEX0_D2
1.5-V
PIN_J9
HEX0
HEX0_D3
1.5-V
PIN_K10
HEX0
HEX0_D4
1.5-V
PIN_K8
HEX0
HEX0_D5
1.5-V
PIN_K9
HEX0
HEX0_D6
1.5-V
PIN_N8
HEX0
HEX0_DP
1.5-V
PIN_P8
22..4
4
TTeemmppeerraattuurree SSeennssoorr aanndd FFaann CCoonnttrrooll
The FPGA board is equipped with a temperature sensor, MAX1619, which provides temperature
sensing and over-temperature alert. These functions are accomplished by connecting the
temperature sensor to the internal temperature sensing diode of the Stratix V GX device. The
temperature status and alarm threshold registers of the temperature sensor can be programmed by a
DE5-Net User Manual
www.terasic.com
August 4, 2017
18
two-wire SMBus, which is connected to the Stratix V GX FPGA. In addition, the 7-bit POR slave
address for this sensor is set to ‘0011000b’.
An optional 3-pin +12V fan located on J15 of the FPGA board is intended to reduce the temperature
of the FPGA. Users can control the fan to turn on/off depending on the measured system
temperature. The FAN is turned on when the FAN_CTRL pin is driven to a high logic level.
The pin assignments for the associated interface are listed in Table 2-7.
Table 2-7 Temperature Sensor Pin Assignments, Schematic Signal Names, and Functions
Schematic
Signal Name
Description
I/O Standard
Stratix V GX Pin
Number
TEMPDIODEp
Positive pin of temperature diode in
Stratix V
1.8-V
PIN_P6
TEMPDIODEn
Negative pin of temperature diode in
Stratix V
1.8-V
PIN_P7
TEMP_CLK
SMBus clock
2.5-V
PIN_D21
TEMP_DATAT
SMBus data
2.5-V
PIN_D20
TEMP_OVERT_n
SMBus alert (interrupt)
2.5-V
PIN_C22
TEMP_INT_n
SMBus alert (interrupt)
2.5-V
PIN_C21
FAN_CTRL
Fan control
2.5-V
PIN_AR32
22..5
5
CClloocckk CCiirrccuuiitt
The development board includes one 50 MHz and three programmable oscillators. Figure 2-9
shows the default frequencies of on-board all external clocks going to the Stratix V GX FPGA. The
figures also show an off-board external clock from PCI Express Host to the FPGA.
DE5-Net User Manual
www.terasic.com
August 4, 2017
19
Figure 2-9 Clock circuit of the FPGA Board
A clock buffer is used to duplicate the 50 MHz oscillator, so each bank of FPGA I/O bank 3/4/7/8
has two clock inputs. The three programming oscillators are low-jitter oscillators which are used to
provide special and high quality clock signals for high-speed transceivers. Figure 2-10 shows the
control circuits of programmable oscillators. The clock generator controller in the MAX II CPLD
can be used to program the CDCM61001 and CDCM61004 to generate 1G Ethernet SFP+ and
SATA reference clocks respectively. The Si570 programmable clock generator is programmed via
an I2C serial interface to generate the 10G Ethernet SFP+ reference clock. Two SMA connectors
provide external clock input and clock output respectively.
DE5-Net User Manual
www.terasic.com
August 4, 2017
20
Figure 2-10 Control circuits of Programmable Oscillators
1Table 2-8 lists the clock source, signal names, default frequency and their corresponding Stratix V
GX device pin numbers.
Table 2-8 Clock Source, Signal Name, Default Frequency, Pin Assignments and Functions
Source
Schematic
Signal Name
Default
Frequency
I/O Standard
Stratix V GX Pin
Number
Application
Y4
OSC_50_B3B
50.0 MHz
2.5-V
PIN_AW35
OSC_50_B3D
1.8-V
PIN_BC28
OSC_50_B4A
1.8-V
PIN_AP10
OSC_50_B4D
1.8-V
PIN_AY18
OSC_50_B7A
1.5-V
PIN_M8
OSC_50_B7D
1.5-V
PIN_J18
OSC_50_B8A
1.5-V
PIN_R36
OSC_50_B8D
1.8-V
PIN_R25
J13
SMA_CLKIN
User
Defined
2.5V
PIN_BB33
External Clock
Input
J14
SMA_CLKOUT
User
Defined
2.5V
PIN_AV34
Clock Output
U49
SFP_REFCLK _p
100.0 MHz
LVDS
PIN_AK7
10G SFP+
U53
SFP1G_REFCLK_p
125.0 MHz
LVDS
PIN_AH6
1G SFP+
U28
SATA_HOST_REFCLK_p
125.0 MHz
LVDS
PIN_V6
SATA HOST
U28
SATA_DEVICE_REFCLK_p
125.0 MHz
LVDS
PIN_V39
SATA DEVICE
J17
PCIE_REFCLK_p
From Host
LVDS
PIN_AK38
PCI Express
DE5-Net User Manual
www.terasic.com
August 4, 2017
21
Table 2-9 lists the programmable oscillator control pins, signal names, I/O standard and their
corresponding Stratix V GX device pin numbers.
Table 2-9 Programmable oscillator control pin, Signal Name, I/O standard, Pin Assignments
and Descriptions
Programmable
Oscillator
Schematic
Signal Name
I/O Standard
Stratix V GX Pin
Number
Description
Si570
(U49)
CLOCK_SCL
2.5-V
PIN_AE15
I2C bus, direct
connected with Si570
CLOCK_SDA
2.5-V
PIN_AE16
CDCM61001
(U53)
PLL_SCL
2.5-V
PIN_AF32
I2C bus, connected
with MAX II CPLD
PLL_SDA
2.5-V
PIN_AG32
CDCM61004
(U28)
PLL_SCL
2.5-V
PIN_AF32
I2C bus, connected
with MAX II CPLD
PLL_SDA
2.5-V
PIN_AG32
22..6
6
RRSS--442222 SSeerriiaall PPoorrtt
The RS-422 is designed to perform communication between boards, allowing a transmission speed
of up to 20 Mbps. Figure 2-11 shows the RS-422 block diagram of the development board. The
full-duplex LTC2855 is used to translate the RS-422 signal, and the RJ45 is used as an external
connector for the RS-422 signal.
Figure 2-11 Block Diagram of RS-422
DE5-Net User Manual
www.terasic.com
August 4, 2017
22
Table 2-10 lists the RS-422 pin assignments, signal names and functions.
Table 2-10 RS-422 Pin Assignments, Schematic Signal Names, and Functions
Schematic
Signal Name
Description
I/O Standard
Stratix V GX Pin
Number
RS422_DE
Driver Enable. A high on DE enables
the driver. A low input will force the
driver outputs into a high impedance
state.
2.5-V
PIN_AG14
RS422_DIN
Receiver Output. The data is send to
FPGA.
PIN_AE18
RS422_DOUT
Driver Input. The data is sent from
FPGA.
PIN_AE17
RS422_RE_n
Receiver Enable. A low enables the
receiver. A high input forces the
receiver output into a high impedance
state.
PIN_AF17
RS422_TE
Internal Termination Resistance
Enable. A high input will connect a
termination resistor (120Ω typical)
between pins A and B.
PIN_AF16
22..7
7
FFLLAASSHH MMeemmoorryy
The development board has two 1Gb CFI-compatible synchronous flash devices for non-volatile
storage of FPGA configuration data, user application data, and user code space.
Each interface has a 16-bit data bus and the two devices combined allow for FPP x32 configuration.
This device is part of the shared flash and MAX (FM) bus, which connects to the flash memory and
MAX II CPLD (EPM2210) System Controller. Figure 2-12 shows the connections between the
Flash, MAX and Stratix V GX FPGA.
DE5-Net User Manual
www.terasic.com
August 4, 2017
23
Figure 2-12 Connection between the Flash, Max and Stratix V GX FPGA
Table 2-11 lists the flash pin assignments, signal names, and functions.
Table 2-11 Flash Memory Pin Assignments, Schematic Signal Names, and Functions
Schematic
Signal Name
Description
I/O Standard
Stratix V GX Pin
Number
FSM_A0
Address bus
2.5-V
PIN_AU32
FSM_A1
Address bus
2.5-V
PIN_AH30
FSM_A2
Address bus
2.5-V
PIN_AJ30
FSM_A3
Address bus
2.5-V
PIN_AH31
FSM_A4
Address bus
2.5-V
PIN_AK30
FSM_A5
Address bus
2.5-V
PIN_AJ32
FSM_A6
Address bus
2.5-V
PIN_AG33
FSM_A7
Address bus
2.5-V
PIN_AL30
FSM_A8
Address bus
2.5-V
PIN_AK33
FSM_A9
Address bus
2.5-V
PIN_AJ33
FSM_A10
Address bus
2.5-V
PIN_AN30
FSM_A11
Address bus
2.5-V
PIN_AH33
FSM_A12
Address bus
2.5-V
PIN_AK32
FSM_A13
Address bus
2.5-V
PIN_AM32
FSM_A14
Address bus
2.5-V
PIN_AM31
FSM_A15
Address bus
2.5-V
PIN_AL31
FSM_A16
Address bus
2.5-V
PIN_AN33
FSM_A17
Address bus
2.5-V
PIN_AP33
FSM_A18
Address bus
2.5-V
PIN_AT32
FSM_A19
Address bus
2.5-V
PIN_AT29
DE5-Net User Manual
www.terasic.com
August 4, 2017
24
FSM_A20
Address bus
2.5-V
PIN_AP31
FSM_A21
Address bus
2.5-V
PIN_AR30
FSM_A22
Address bus
2.5-V
PIN_AU30
FSM_A23
Address bus
2.5-V
PIN_AJ31
FSM_A24
Address bus
2.5-V
PIN_AP30
FSM_A25
Address bus
2.5-V
PIN_AN31
FSM_A26
Address bus
2.5-V
PIN_AT30
FSM_D0
Data bus
2.5-V
PIN_AG26
FSM_D1
Data bus
2.5-V
PIN_AD33
FSM_D2
Data bus
2.5-V
PIN_AE34
FSM_D3
Data bus
2.5-V
PIN_AF31
FSM_D4
Data bus
2.5-V
PIN_AG28
FSM_D5
Data bus
2.5-V
PIN_AG30
FSM_D6
Data bus
2.5-V
PIN_AF29
FSM_D7
Data bus
2.5-V
PIN_AE29
FSM_D8
Data bus
2.5-V
PIN_AG25
FSM_D9
Data bus
2.5-V
PIN_AF34
FSM_D10
Data bus
2.5-V
PIN_AE33
FSM_D11
Data bus
2.5-V
PIN_AE31
FSM_D12
Data bus
2.5-V
PIN_AF28
FSM_D13
Data bus
2.5-V
PIN_AE30
FSM_D14
Data bus
2.5-V
PIN_AG29
FSM_D15
Data bus
2.5-V
PIN_AG27
FSM_D16
Data bus
2.5-V
PIN_AP28
FSM_D17
Data bus
2.5-V
PIN_AN28
FSM_D18
Data bus
2.5-V
PIN_AU31
FSM_D19
Data bus
2.5-V
PIN_AW32
FSM_D20
Data bus
2.5-V
PIN_BD32
FSM_D21
Data bus
2.5-V
PIN_AY31
FSM_D22
Data bus
2.5-V
PIN_BA30
FSM_D23
Data bus
2.5-V
PIN_BB30
FSM_D24
Data bus
2.5-V
PIN_AM29
FSM_D25
Data bus
2.5-V
PIN_AR29
FSM_D26
Data bus
2.5-V
PIN_AV31
FSM_D27
Data bus
2.5-V
PIN_AV32
FSM_D28
Data bus
2.5-V
PIN_BC31
FSM_D29
Data bus
2.5-V
PIN_AW30
FSM_D30
Data bus
2.5-V
PIN_BC32
FSM_D31
Data bus
2.5-V
PIN_BD31
FLASH_CLK
Clock
2.5-V
PIN_AL29
DE5-Net User Manual
www.terasic.com
August 4, 2017
25
FLASH_RESET_n
Reset
2.5-V
PIN_AE28
FLASH_CE_n[0]
Chip enable of of flash-0
2.5-V
PIN_AE27
FLASH_CE_n[1]
Chip enable of of flash-1
2.5-V
PIN_BA31
FLASH_OE_n
Output enable
2.5-V
PIN_AY30
FLASH_WE_n
Write enable
2.5-V
PIN_AR31
FLASH_ADV_n
Address valid
2.5-V
PIN_AK29
FLASH_RDY_BSY_n[0]
Ready of flash-0
2.5-V
PIN_BA29
FLASH_RDY_BSY_n[1]
Ready of flash-1
2.5-V
PIN_BB32
22..8
8
DDDDRR33 SSOO--DDIIMMMM
The development board supports two independent banks of DDR3 SDRAM SO-DIMM. Each
DDR3 SODIMM socket is wired to support a maximum capacity of 8GB with a 64-bit data bus.
Using differential DQS signaling for the DDR3 SDRAM interfaces, it is capable of running at up to
800MHz memory clock for a maximum theoretical bandwidth up to 102.4Gbps. Figure 2-13 shows
the connections between the DDR3 SDRAM SO-DIMMs and Stratix V GX FPGA.
DE5-Net User Manual
www.terasic.com
August 4, 2017
26
Figure 2-13 Connection between the DDR3 and Stratix V GX FPGA
The pin assignments for DDR3 SDRAM SO-DIMM Bank-A and Bank-B are listed in 119H119HTable 2-12
and Table 2-13, in respectively.
Table 2-12 DDR3-A Bank Pin Assignments, Schematic Signal Names, and Functions
Schematic
Signal Name
Description
I/O Standard
Stratix V GX Pin
Number
DDR3A_DQ0
Data [0]
SSTL-15 Class I
PIN_A35
DDR3A_DQ1
Data [1]
SSTL-15 Class I
PIN_A34
DDR3A_DQ2
Data [2]
SSTL-15 Class I
PIN_D36
DDR3A_DQ3
Data [3]
SSTL-15 Class I
PIN_C33
DDR3A_DQ4
Data [4]
SSTL-15 Class I
PIN_B32
DDR3A_DQ5
Data [5]
SSTL-15 Class I
PIN_D35
DDR3A_DQ6
Data [6]
SSTL-15 Class I
PIN_D33
DDR3A_DQ7
Data [7]
SSTL-15 Class I
PIN_E33
DDR3A_DQ8
Data [8]
SSTL-15 Class I
PIN_A32
DDR3A_DQ9
Data [9]
SSTL-15 Class I
PIN_A31
DDR3A_DQ10
Data [10]
SSTL-15 Class I
PIN_C30
DE5-Net User Manual
www.terasic.com
August 4, 2017
27
DDR3A_DQ11
Data [11]
SSTL-15 Class I
PIN_D30
DDR3A_DQ12
Data [12]
SSTL-15 Class I
PIN_B29
DDR3A_DQ13
Data [13]
SSTL-15 Class I
PIN_E30
DDR3A_DQ14
Data [14]
SSTL-15 Class I
PIN_F31
DDR3A_DQ15
Data [15]
SSTL-15 Class I
PIN_G31
DDR3A_DQ16
Data [16]
SSTL-15 Class I
PIN_F35
DDR3A_DQ17
Data [17]
SSTL-15 Class I
PIN_G34
DDR3A_DQ18
Data [18]
SSTL-15 Class I
PIN_J33
DDR3A_DQ19
Data [19]
SSTL-15 Class I
PIN_J34
DDR3A_DQ20
Data [20]
SSTL-15 Class I
PIN_F34
DDR3A_DQ21
Data [21]
SSTL-15 Class I
PIN_E35
DDR3A_DQ22
Data [22]
SSTL-15 Class I
PIN_J31
DDR3A_DQ23
Data [23]
SSTL-15 Class I
PIN_K31
DDR3A_DQ24
Data [24]
SSTL-15 Class I
PIN_P34
DDR3A_DQ25
Data [25]
SSTL-15 Class I
PIN_R33
DDR3A_DQ26
Data [26]
SSTL-15 Class I
PIN_M34
DDR3A_DQ27
Data [27]
SSTL-15 Class I
PIN_L33
DDR3A_DQ28
Data [28]
SSTL-15 Class I
PIN_R34
DDR3A_DQ29
Data [29]
SSTL-15 Class I
PIN_T34
DDR3A_DQ30
Data [30]
SSTL-15 Class I
PIN_W34
DDR3A_DQ31
Data [31]
SSTL-15 Class I
PIN_V35
DDR3A_DQ32
Data [32]
SSTL-15 Class I
PIN_P33
DDR3A_DQ33
Data [33]
SSTL-15 Class I
PIN_P32
DDR3A_DQ34
Data [34]
SSTL-15 Class I
PIN_V33
DDR3A_DQ35
Data [35]
SSTL-15 Class I
PIN_V34
DDR3A_DQ36
Data [36]
SSTL-15 Class I
PIN_N31
DDR3A_DQ37
Data [37]
SSTL-15 Class I
PIN_M31
DDR3A_DQ38
Data [38]
SSTL-15 Class I
PIN_U32
DDR3A_DQ39
Data [39]
SSTL-15 Class I
PIN_U33
DDR3A_DQ40
Data [40]
SSTL-15 Class I
PIN_R31
DDR3A_DQ41
Data [41]
SSTL-15 Class I
PIN_W31
DDR3A_DQ42
Data [42]
SSTL-15 Class I
PIN_U30
DDR3A_DQ43
Data [43]
SSTL-15 Class I
PIN_P31
DDR3A_DQ44
Data [44]
SSTL-15 Class I
PIN_T31
DDR3A_DQ45
Data [45]
SSTL-15 Class I
PIN_Y32
DDR3A_DQ46
Data [46]
SSTL-15 Class I
PIN_T29
DDR3A_DQ47
Data [47]
SSTL-15 Class I
PIN_P30
DDR3A_DQ48
Data [48]
SSTL-15 Class I
PIN_H32
DDR3A_DQ49
Data [49]
SSTL-15 Class I
PIN_H31
DDR3A_DQ50
Data [50]
SSTL-15 Class I
PIN_L30
DDR3A_DQ51
Data [51]
SSTL-15 Class I
PIN_L29
DDR3A_DQ52
Data [52]
SSTL-15 Class I
PIN_F32
DDR3A_DQ53
Data [53]
SSTL-15 Class I
PIN_G32
DDR3A_DQ54
Data [54]
SSTL-15 Class I
PIN_M30
DE5-Net User Manual
www.terasic.com
August 4, 2017
28
DDR3A_DQ55
Data [55]
SSTL-15 Class I
PIN_N29
DDR3A_DQ56
Data [56]
SSTL-15 Class I
PIN_U29
DDR3A_DQ57
Data [57]
SSTL-15 Class I
PIN_V28
DDR3A_DQ58
Data [58]
SSTL-15 Class I
PIN_Y28
DDR3A_DQ59
Data [59]
SSTL-15 Class I
PIN_W29
DDR3A_DQ60
Data [60]
SSTL-15 Class I
PIN_V30
DDR3A_DQ61
Data [61]
SSTL-15 Class I
PIN_V29
DDR3A_DQ62
Data [62]
SSTL-15 Class I
PIN_W28
DDR3A_DQ63
Data [63]
SSTL-15 Class I
PIN_Y27
DDR3A_DQS0
Data Strobe p[0]
Differential 1.5-V SSTL Class I
PIN_C34
DDR3A_DQS_n0
Data Strobe n[0]
Differential 1.5-V SSTL Class I
PIN_B34
DDR3A_DQS1
Data Strobe p[1]
Differential 1.5-V SSTL Class I
PIN_C31
DDR3A_DQS_n1
Data Strobe n[1]
Differential 1.5-V SSTL Class I
PIN_B31
DDR3A_DQS2
Data Strobe p[2]
Differential 1.5-V SSTL Class I
PIN_H35
DDR3A_DQS_n2
Data Strobe n[2]
Differential 1.5-V SSTL Class I
PIN_G35
DDR3A_DQS3
Data Strobe p[3]
Differential 1.5-V SSTL Class I
PIN_U35
DDR3A_DQS_n3
Data Strobe n[4]
Differential 1.5-V SSTL Class I
PIN_T35
DDR3A_DQS4
Data Strobe p[4]
Differential 1.5-V SSTL Class I
PIN_T33
DDR3A_DQS_n4
Data Strobe n[4]
Differential 1.5-V SSTL Class I
PIN_T32
DDR3A_DQS5
Data Strobe p[5]
Differential 1.5-V SSTL Class I
PIN_T30
DDR3A_DQS_n5
Data Strobe n[5]
Differential 1.5-V SSTL Class I
PIN_R30
DDR3A_DQS6
Data Strobe p[6]
Differential 1.5-V SSTL Class I
PIN_J30
DDR3A_DQS_n6
Data Strobe n[6]
Differential 1.5-V SSTL Class I
PIN_H30
DDR3A_DQS7
Data Strobe p[7]
Differential 1.5-V SSTL Class I
PIN_Y30
DDR3A_DQS_n7
Data Strobe n[7]
Differential 1.5-V SSTL Class I
PIN_Y29
DDR3A_DM0
Data Mask [0]
SSTL-15 Class I
PIN_C36
DDR3A_DM1
Data Mask [1]
SSTL-15 Class I
PIN_E32
DDR3A_DM2
Data Mask [2]
SSTL-15 Class I
PIN_H34
DDR3A_DM3
Data Mask [3]
SSTL-15 Class I
PIN_L32
DDR3A_DM4
Data Mask [4]
SSTL-15 Class I
PIN_N32
DDR3A_DM5
Data Mask [5]
SSTL-15 Class I
PIN_W32
DDR3A_DM6
Data Mask [6]
SSTL-15 Class I
PIN_K30
DDR3A_DM7
Data Mask [7]
SSTL-15 Class I
PIN_T28
DDR3A_A0
Address [0]
SSTL-15 Class I
PIN_M39
DDR3A_A1
Address [1]
SSTL-15 Class I
PIN_L35
DDR3A_A2
Address [2]
SSTL-15 Class I
PIN_N38
DDR3A_A3
Address [3]
SSTL-15 Class I
PIN_L36
DDR3A_A4
Address [4]
SSTL-15 Class I
PIN_H36
DDR3A_A5
Address [5]
SSTL-15 Class I
PIN_K29
DDR3A_A6
Address [6]
SSTL-15 Class I
PIN_D37
DDR3A_A7
Address [7]
SSTL-15 Class I
PIN_K35
DDR3A_A8
Address [8]
SSTL-15 Class I
PIN_K32
DDR3A_A9
Address [9]
SSTL-15 Class I
PIN_K37
DDR3A_A10
Address [10]
SSTL-15 Class I
PIN_M38
DE5-Net User Manual
www.terasic.com
August 4, 2017
29
DDR3A_A11
Address [11]
SSTL-15 Class I
PIN_C37
DDR3A_A12
Address [12]
SSTL-15 Class I
PIN_K36
DDR3A_A13
Address [13]
SSTL-15 Class I
PIN_M33
DDR3A_A14
Address [14]
SSTL-15 Class I
PIN_K34
DDR3A_A15
Address [15]
SSTL-15 Class I
PIN_B38
DDR3A_RAS_n
Row Address Strobe
SSTL-15 Class I
PIN_P38
DDR3A_CAS_n
Column Address Strobe
SSTL-15 Class I
PIN_M36
DDR3A_BA0
Bank Address [0]
SSTL-15 Class I
PIN_M37
DDR3A_BA1
Bank Address [1]
SSTL-15 Class I
PIN_P39
DDR3A_BA2
Bank Address [2]
SSTL-15 Class I
PIN_J36
DDR3A_CK0
Clock p0
Differential 1.5-V SSTL Class I
PIN_G37
DDR3A_CK_n0
Clock n0
Differential 1.5-V SSTL Class I
PIN_F36
DDR3A_CK1
Clock p1
Differential 1.5-V SSTL Class I
PIN_J37
DDR3A_CK_n1
Clock n1
Differential 1.5-V SSTL Class I
PIN_H37
DDR3A_CKE0
Clock Enable pin 0
SSTL-15 Class I
PIN_E36
DDR3A_CKE1
Clock Enable pin 1
SSTL-15 Class I
PIN_B35
DDR3A_ODT0
On Die Termination[0]
SSTL-15 Class I
PIN_V36
DDR3A_ODT1
On Die Termination[1]
SSTL-15 Class I
PIN_W35
DDR3A_WE_n
Write Enable
SSTL-15 Class I
PIN_N37
DDR3A_CS_n0
Chip Select [0]
SSTL-15 Class I
PIN_P36
DDR3A_CS_n1
Chip Select [1]
SSTL-15 Class I
PIN_R28
DDR3A_RESET_n
Chip Reset
SSTL-15 Class I
PIN_H33
DDR3A_EVENT_n
Chip Temperature Event
SSTL-15 Class I
PIN_K19
DDR3A_SDA
Chip I2C Serial Clock
1.5V
PIN_P15
DDR3A_SCL
Chip I2C Serial Data Bus
1.5V
PIN_C15
Table 2-13 DDR3-B Pin Assignments, Schematic Signal Names, and Functions
Schematic
Signal Name
Description
I/O Standard
Stratix V GX Pin
Number
DDR3B_DQ0
Data [0]
SSTL-15 Class I
PIN_Y17
DDR3B_DQ1
Data [1]
SSTL-15 Class I
PIN_W17
DDR3B_DQ2
Data [2]
SSTL-15 Class I
PIN_V15
DDR3B_DQ3
Data [3]
SSTL-15 Class I
PIN_T15
DDR3B_DQ4
Data [4]
SSTL-15 Class I
PIN_V13
DDR3B_DQ5
Data [5]
SSTL-15 Class I
PIN_V16
DDR3B_DQ6
Data [6]
SSTL-15 Class I
PIN_W14
DDR3B_DQ7
Data [7]
SSTL-15 Class I
PIN_U15
DDR3B_DQ8
Data [8]
SSTL-15 Class I
PIN_T17
DDR3B_DQ9
Data [9]
SSTL-15 Class I
PIN_T16
DDR3B_DQ10
Data [10]
SSTL-15 Class I
PIN_R16
DE5-Net User Manual
www.terasic.com
August 4, 2017
30
DDR3B_DQ11
Data [11]
SSTL-15 Class I
PIN_P16
DDR3B_DQ12
Data [12]
SSTL-15 Class I
PIN_N16
DDR3B_DQ13
Data [13]
SSTL-15 Class I
PIN_M15
DDR3B_DQ14
Data [14]
SSTL-15 Class I
PIN_M14
DDR3B_DQ15
Data [15]
SSTL-15 Class I
PIN_L14
DDR3B_DQ16
Data [16]
SSTL-15 Class I
PIN_T14
DDR3B_DQ17
Data [17]
SSTL-15 Class I
PIN_U14
DDR3B_DQ18
Data [18]
SSTL-15 Class I
PIN_U11
DDR3B_DQ19
Data [19]
SSTL-15 Class I
PIN_T13
DDR3B_DQ20
Data [20]
SSTL-15 Class I
PIN_U12
DDR3B_DQ21
Data [21]
SSTL-15 Class I
PIN_R13
DDR3B_DQ22
Data [22]
SSTL-15 Class I
PIN_P13
DDR3B_DQ23
Data [23]
SSTL-15 Class I
PIN_N13
DDR3B_DQ24
Data [24]
SSTL-15 Class I
PIN_K12
DDR3B_DQ25
Data [25]
SSTL-15 Class I
PIN_J12
DDR3B_DQ26
Data [26]
SSTL-15 Class I
PIN_J10
DDR3B_DQ27
Data [27]
SSTL-15 Class I
PIN_H12
DDR3B_DQ28
Data [28]
SSTL-15 Class I
PIN_N11
DDR3B_DQ29
Data [29]
SSTL-15 Class I
PIN_M11
DDR3B_DQ30
Data [30]
SSTL-15 Class I
PIN_H10
DDR3B_DQ31
Data [31]
SSTL-15 Class I
PIN_H11
DDR3B_DQ32
Data [32]
SSTL-15 Class I
PIN_T10
DDR3B_DQ33
Data [33]
SSTL-15 Class I
PIN_R10
DDR3B_DQ34
Data [34]
SSTL-15 Class I
PIN_M12
DDR3B_DQ35
Data [35]
SSTL-15 Class I
PIN_L12
DDR3B_DQ36
Data [36]
SSTL-15 Class I
PIN_V10
DDR3B_DQ37
Data [37]
SSTL-15 Class I
PIN_V9
DDR3B_DQ38
Data [38]
SSTL-15 Class I
PIN_R12
DDR3B_DQ39
Data [39]
SSTL-15 Class I
PIN_P12
DDR3B_DQ40
Data [40]
SSTL-15 Class I
PIN_D14
DDR3B_DQ41
Data [41]
SSTL-15 Class I
PIN_C13
DDR3B_DQ42
Data [42]
SSTL-15 Class I
PIN_B14
DDR3B_DQ43
Data [43]
SSTL-15 Class I
PIN_B13
DDR3B_DQ44
Data [44]
SSTL-15 Class I
PIN_E14
DDR3B_DQ45
Data [45]
SSTL-15 Class I
PIN_F14
DDR3B_DQ46
Data [46]
SSTL-15 Class I
PIN_A14
DDR3B_DQ47
Data [47]
SSTL-15 Class I
PIN_A13
DDR3B_DQ48
Data [48]
SSTL-15 Class I
PIN_K13
DDR3B_DQ49
Data [49]
SSTL-15 Class I
PIN_K16
DDR3B_DQ50
Data [50]
SSTL-15 Class I
PIN_H13
DDR3B_DQ51
Data [51]
SSTL-15 Class I
PIN_H14
DDR3B_DQ52
Data [52]
SSTL-15 Class I
PIN_J13
DDR3B_DQ53
Data [53]
SSTL-15 Class I
PIN_J16
DDR3B_DQ54
Data [54]
SSTL-15 Class I
PIN_G13
Loading...