Terasic DE10-Standard User Manual
DE10-Standard
User Manual
1
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January 19, 2017
DE10-Standard
User Manual
1
www.terasic.com
January 19, 2017
CONTENTS
Chapter 1 DE10-Standard Development Kit .................................................. 4
1.1 Package Contents ....................................................................................................................... 4
1.2 DE10-Standard System CD ........................................................................................................ 5
1.3 Getting Help ............................................................................................................................... 5
Chapter 2 Introduction of the DE10-Standard Board ..................................... 7
2.1 Layout and Components ............................................................................................................. 7
2.2 Block Diagram of the DE10-Standard Board ............................................................................. 9
Chapter 3 Using the DE10-Standard Board ................................................ 13
3.1 Settings of FPGA Configuration Mode .................................................................................... 13
3.2 Configuration of Cyclone V SoC FPGA on DE10-Standard .................................................... 14
3.3 Board Status Elements.............................................................................................................. 20
3.4 Board Reset Elements .............................................................................................................. 21
3.5 Clock Circuitry ......................................................................................................................... 22
3.6 Peripherals Connected to the FPGA ......................................................................................... 23
3.6.1 User Push-buttons, Switches and LEDs ................................................................ 23
3.6.2 7-segment Displays ............................................................................................... 27
3.6.3 2x20 GPIO Expansion Header .............................................................................. 28
3.6.4 HSMC connector ................................................................................................... 30
3.6.5 24-bit Audio CODEC ............................................................................................ 34
3.6.6 I2C Multiplexer ..................................................................................................... 34
3.6.7 VGA Output ........................................................................................................... 35
3.6.8 TV Decoder ........................................................................................................... 38
3.6.9 IR Receiver ............................................................................................................ 40
3.6.10 IR Emitter LED ..................................................................................................... 40
3.6.11 SDRAM Memory .................................................................................................. 41
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3.6.12 PS/2 Serial Port ...................................................................................................... 43
3.6.13 A/D Converter and 2x5 Header ............................................................................. 44
3.7 Peripherals Connected to Hard Processor System (HPS)......................................................... 46
3.7.1 User Push-buttons and LEDs ................................................................................. 46
3.7.2 Gigabit Ethernet ..................................................................................................... 46
3.7.3 UART to USB ........................................................................................................ 48
3.7.4 DDR3 Memory ...................................................................................................... 49
3.7.5 Micro SD Card Socket ........................................................................................... 51
3.7.6 2-port USB Host .................................................................................................... 51
3.7.7 Accelerometer (G-sensor) ...................................................................................... 52
3.7.8 LTC Connector ...................................................................................................... 53
3.7.9 128x64 Dots LCD .................................................................................................. 54
Chapter 4 DE10-Standard System Builder .................................................. 56
4.1 Introduction .............................................................................................................................. 56
4.2 Design Flow ............................................................................................................................. 56
4.3 Using DE10-Standard System Builder ..................................................................................... 57
Chapter 5 Examples For FPGA .................................................................. 63
5.1 DE10-Standard Factory Configuration..................................................................................... 63
5.2 Audio Recording and Playing .................................................................................................. 64
5.3 Karaoke Machine ..................................................................................................................... 66
5.4 SDRAM Test in Nios II ............................................................................................................ 68
5.5 SDRAM Test in Verilog ........................................................................................................... 71
5.6 TV Box Demonstration ............................................................................................................ 73
5.7 PS/2 Mouse Demonstration ...................................................................................................... 75
5.8 IR Emitter LED and Receiver Demonstration ......................................................................... 78
5.9 ADC Reading ........................................................................................................................... 83
Chapter 6 Examples for HPS SoC ................................................................ 88
6.1 Hello Program .......................................................................................................................... 88
6.2 Users LED and KEY ................................................................................................................ 90
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6.3 I2C Interfaced G-sensor ........................................................................................................... 96
6.4 I2C MUX Test .......................................................................................................................... 98
6.5 SPI Interfaced Graphic LCD .................................................................................................. 101
Chapter 7 Examples for using both HPS SoC and FGPA ............................ 105
7.1 Required Background ............................................................................................................. 105
7.2 System Requirements ............................................................................................................. 106
7.3 AXI bridges in Intel SoC FPGA ............................................................................................. 106
7.4 GHRD Project ........................................................................................................................ 107
7.5 Compile and Programming .................................................................................................... 109
7.6 Develop the C Code ............................................................................................................... 110
Chapter 8 Programming the EPCS Device ................................................. 116
8.1 Before Programming Begins .................................................................................................. 116
8.2 Convert .SOF File to .JIC File ................................................................................................ 116
8.3 Write JIC File into the EPCS Device ..................................................................................... 121
8.4 Erase the EPCS Device .......................................................................................................... 123
Chapter 9 Appendix ................................................................................... 125
9.1 Revision History ..................................................................................................................... 125
9.2 Copyright Statement ............................................................................................................... 125
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Chapter 1
DE10-Standard
Development Kit
The DE10-Standard Development Kit presents a robust hardware design platform built around the
Altera System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded
cores with industry-leading programmable logic for ultimate design flexibility. Users can now
leverage the power of tremendous re-configurability paired with a high-performance, low-power
processor system. Altera’s SoC integrates an ARM-based hard processor system (HPS) consisting of
processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a
high-bandwidth interconnect backbone. The DE10-Standard development board is equipped with
high-speed DDR3 memory, video and audio capabilities, Ethernet networking, and much more that
promise many exciting applications.
The DE10-Standard Development Kit contains all the tools needed to use the board in conjunction
with a computer that runs the Microsoft Windows XP or later.
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Figure 1-1 shows a photograph of the DE10-Standard package.
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Figure 1-1 The DE10-Standard package contents
The DE10-Standard package includes:
The DE10-Standard development board
DE10-Standard Quick Start Guide
USB cable (Type A to B) for FPGA programming and control
USB cable (Type A to Mini-B) for UART control
12V DC power adapter
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The DE10-Standard System CD contains all the documents and supporting materials associated
with DE10-Standard, including the user manual, system builder, reference designs, and device
datasheets. Users can download this system CD from the link: http://de10-standard.terasic.com/cd/.
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GGeettttiinngg HHeellpp
Here are the addresses where you can get help if you encounter any problems:
Terasic Technologies
9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
Email: support@terasic.com
Tel.: +886-3-575-0880
Website: de10-standard.terasic.com
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Chapter 2
Introduction of the
DE10-Standard Board
This chapter provides an introduction to the features and design characteristics of the board.
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Figure 2-1 shows a photograph of the board. It depicts the layout of the board and indicates the
location of the connectors and key components.
Figure 2-1 DE10-Standard development board (top view)
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Figure 2-2 DE10-Standard development board (bottom view)
The DE10-Standard board has many features that allow users to implement a wide range of
designed circuits, from simple circuits to various multimedia projects.
The following hardware is provided on the board:
FPGA
Altera Cyclone® V SE 5CSXFC6D6F31C6N device
Altera serial configuration device – EPCS128
USB-Blaster II onboard for programming; JTAG Mode
64MB SDRAM (16-bit data bus)
4 push-buttons
10 slide switches
10 red user LEDs
Six 7-segment displays
Four 50MHz clock sources from the clock generator
24-bit CD-quality audio CODEC with line-in, line-out, and microphone-in jacks
VGA DAC (8-bit high-speed triple DACs) with VGA-out connector
TV decoder (NTSC/PAL/SECAM) and TV-in connector
PS/2 mouse/keyboard connector
IR receiver and IR emitter
One HSMC with Configurable I/O standard 1.5/1.8/2.5/3.3
One 40-pin expansion header with diode protection
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A/D converter, 4-pin SPI interface with FPGA
HPS (Hard Processor System)
800MHz Dual-core ARM Cortex-A9 MPCore processor
1GB DDR3 SDRAM (32-bit data bus)
1 Gigabit Ethernet PHY with RJ45 connector
2-port USB Host, normal Type-A USB connector
Micro SD card socket
Accelerometer (I2C interface + interrupt)
UART to USB, USB Mini-B connector
Warm reset button and cold reset button
One user button and one user LED
LTC 2x7 expansion header
128x64 dots LCD Module with Backlight
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Figure 2-3 is the block diagram of the board. All the connections are established through the
Cyclone V SoC FPGA device to provide maximum flexibility for users. Users can configure the
FPGA to implement any system design.
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Figure 2-3 Block diagram of DE10-Standard
Detailed information about Figure 2-3 are listed below.
FFPPGGAA DDeevviiccee
Cyclone V SoC 5CSXFC6D6F31C6N Device
Dual-core ARM Cortex-A9 (HPS)
110K programmable logic elements
5,140 Kbits embedded memory
6 fractional PLLs
2 hard memory controllers
3.125G transceivers
CCoonnffiigguurraattiioonn aanndd DDeebbuug
g
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Quad serial configuration device – EPCS128 on FPGA
Onboard USB-Blaster II (normal type B USB connector)
MMeemmoorryy DDeevviiccee
64MB (32Mx16) SDRAM on FPGA
1GB (2x256Mx16) DDR3 SDRAM on HPS
Micro SD card socket on HPS
CCoommmmuunniiccaattiioonn
Two port USB 2.0 Host (ULPI interface with USB type A connector)
UART to USB (USB Mini-B connector)
10/100/1000 Ethernet
PS/2 mouse/keyboard
IR emitter/receiver
I2C multiplexer
CCoonnnneeccttoorrss
One HSMC (8-channel Transceivers, Configurable I/O standards 1.5/1.8/2.5/3.3V)
One 40-pin expansion headers
One 10-pin ADC input header
One LTC connector (one Serial Peripheral Interface (SPI) Master ,one I2C and one GPIO
interface )
DDiissppllaayy
24-bit VGA DAC
128x64 dots LCD Module with Backlight
AAuuddiioo
24-bit CODEC, Line-in, Line-out, and microphone-in jacks
VViiddeeoo IInnppuutt
TV decoder (NTSC/PAL/SECAM) and TV-in connector
AADDCC
Interface: SPI
Fast throughput rate: 500 KSPS
Channel number: 8
Resolution: 12-bit
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Analog input range : 0 ~ 4.096
SSwwiittcchheess,, BBuuttttoonnss,, aanndd IInnddiiccaattoorrss
5 user Keys (FPGA x4, HPS x1)
10 user switches (FPGA x10)
11 user LEDs (FPGA x10, HPS x 1)
2 HPS reset buttons (HPS_RESET_n and HPS_WARM_RST_n)
Six 7-segment displays
SSeennssoorrss
G-Sensor on HPS
PPoowweerr
12V DC input
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Chapter 3
Using the
DE10-Standard Board
This chapter provides an instruction to use the board and describes the peripherals.
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When the DE10-Standard board is powered on, the FPGA can be configured from EPCS or HPS.
The MSEL[4:0] pins are used to select the configuration scheme. It is implemented as a 6-pin DIP
switch SW10 on the DE10-Standard board, as shown in Figure 3-1.
Figure 3-1 DIP switch (SW10) setting of Active Serial (AS) mode on DE10-Standard board
Table 3-1 shows the relation between MSEL[4:0] and DIP switch (SW10).
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Table 3-1 FPGA Configuration Mode Switch (SW10)
Board Reference
Signal Name
Description
Default
AS Mode
SW10.1
MSEL0
Use these pins to set the FPGA
Configuration scheme
OFF (“1”)
SW10.2
MSEL1
ON (“0”)
SW10.3
MSEL2
ON (“0”)
SW10.4
MSEL3
OFF (“1”)
SW10.5
MSEL4
ON (“0”)
SW10.6
N/A
N/A
N/A
Figure 3-1 shows MSEL[4:0] setting of AS mode, which is also the default setting on
DE10-Standard. When the board is powered on, the FPGA is configured from EPCS, which is
pre-programmed with the default code. If developers wish to reconfigure FPGA from an application
software running on Linux, the MSEL[4:0] needs to be set to “01010” before the programming
process begins.
Table 3-2 MSEL Pin Settings for FPGA Configure of DE10-Standard
MSEL[4:0]
Configure Scheme
Description
10010
AS
FPGA configured from EPCS (default)
01010
FPPx32
FPGA configured from HPS software: Linux
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There are two types of programming method supported by DE10-Standard:
1. JTAG programming: It is named after the IEEE standards Joint Test Action Group.
The configuration bit stream is downloaded directly into the Cyclone V SoC FPGA. The FPGA will
retain its current status as long as the power keeps applying to the board; the configuration
information will be lost when the power is off.
2. AS programming: The other programming method is Active Serial configuration.
The configuration bit stream is downloaded into the quad serial configuration device (EPCS128),
which provides non-volatile storage for the bit stream. The information is retained within EPCS128
even if the DE10-Standard board is turned off. When the board is powered on, the configuration
data in the EPCS128 device is automatically loaded into the Cyclone V SoC FPGA.
JTAG Chain on DE10-Standard Board
The FPGA device can be configured through JTAG interface on DE10-Standard board, but the
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JTAG chain must form a closed loop, which allows Quartus II programmer to the detect FPGA
device. Figure 3-2 illustrates the JTAG chain on DE10-Standard board.
Figure 3-2 Path of the JTAG chain
Configure the FPGA in JTAG Mode
There are two devices (FPGA and HPS) on the JTAG chain. The following shows how the FPGA is
programmed in JTAG mode step by step.
1. Open the Quartus II programmer and click “Auto Detect”, as circled in Figure 3-3
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Figure 3-3 Detect FPGA device in JTAG mode
2. Select detected device associated with the board, as circled in Figure 3-4.
Figure 3-4 Select 5CSXFC6D6 device
3. Both FPGA and HPS are detected, as shown in Figure 3-5.
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Figure 3-5 FPGA and HPS detected in Quartus programmer
4. Right click on the FPGA device and open the .sof file to be programmed, as highlighted in
Figure 3-6.
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Figure 3-6 Open the .sof file to be programmed into the FPGA device
5. Select the .sof file to be programmed, as shown in Figure 3-7.
Figure 3-7 Select the .sof file to be programmed into the FPGA device
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6. Click “Program/Configure” check box and then click “Start” button to download the .sof file
into the FPGA device, as shown in Figure 3-8.
Figure 3-8 Program .sof file into the FPGA device
Configure the FPGA in AS Mode
The DE10-Standard board uses a quad serial configuration device (EPCS128) to store
configuration data for the Cyclone V SoC FPGA. This configuration data is automatically
loaded from the quad serial configuration device chip into the FPGA when the board is
powered up.
Users need to use Serial Flash Loader (SFL) to program the quad serial configuration device
via JTAG interface. The FPGA-based SFL is a soft intellectual property (IP) core within the
FPGA that bridge the JTAG and Flash interfaces. The SFL Megafunction is available in
Quartus II. Figure 3-9 shows the programming method when adopting SFL solution.
Please refer to Chapter 9: Steps of Programming the Quad Serial Configuration Device for the
basic programming instruction on the serial configuration device.
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Figure 3-9 Programming a quad serial configuration device with SFL solution
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In addition to the 10 LEDs that FPGA device can control, there are 5 indicators which can indicate
the board status (See Figure 3-10), please refer the details in Table 3-3
Figure 3-10 LED Indicators on DE10-Standard
Table 3-3 LED Indicators
Board Reference
LED Name
Description
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D14
12-V Power
Illuminate when 12V power is active.
TXD
UART TXD
Illuminate when data is transferred from FT232R to USB Host.
RXD
UART RXD
Illuminate when data is transferred from USB Host to FT232R.
D5
JTAG_RX
Reserved
D4
JTAG_TX
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There are two HPS reset buttons on DE10-Standard, HPS (cold) reset and HPS warm reset, as
shown in Figure 3-11. Table 3-4 describes the purpose of these two HPS reset buttons. Figure 3-12
is the reset tree for DE10-Standard.
Figure 3-11 HPS cold reset and warm reset buttons on DE10-Standard
Table 3-4 Description of Two HPS Reset Buttons on DE10-Standard
Board Reference
Signal Name
Description
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KEY5
HPS_RESET_N
Cold reset to the HPS, Ethernet PHY and USB host device.
Active low input which resets all HPS logics that can be reset.
KEY7
HPS_WARM_RST_N
Warm reset to the HPS block. Active low input affects the
system reset domain for debug purpose.
Figure 3-12 HPS reset tree on DE10-Standard board
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Figure 3-13 shows the default frequency of all external clocks to the Cyclone V SoC FPGA. A
clock generator is used to distribute clock signals with low jitter. The four 50MHz clock signals
connected to the FPGA are used as clock sources for user logic. One 25MHz clock signal is
connected to two HPS clock inputs, and the other one is connected to the clock input of Gigabit
Ethernet Transceiver. Two 24MHz clock signals are connected to the clock inputs of USB
Host/OTG PHY and USB hub controller. The associated pin assignment for clock inputs to FPGA
I/O pins is listed in Table 3-5.
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Figure 3-13 Block diagram of the clock distribution on DE10-Standard
Table 3-5 Pin Assignment of Clock Inputs
Signal Name
FPGA Pin No.
Description
I/O Standard
CLOCK_50
PIN_AF14
50 MHz clock input
3.3V
CLOCK2_50
PIN_AA16
50 MHz clock input
3.3V
CLOCK3_50
PIN_Y26
50 MHz clock input
3.3V
CLOCK4_50
PIN_K14
50 MHz clock input
3.3V
HPS_CLOCK1_25
PIN_D25
25 MHz clock input
3.3V
HPS_CLOCK2_25
PIN_F25
25 MHz clock input
3.3V
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This section describes the interfaces connected to the FPGA. Users can control or monitor different
interfaces with user logic from the FPGA.
3.6.1 User Push-buttons, Switches and LEDs
The board has four push-buttons connected to the FPGA, as shown in Figure 3-14 Connections
between the push-buttons and the Cyclone V SoC FPGA. Schmitt trigger circuit is implemented and act
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as switch debounce in Figure 3-15 for the push-buttons connected. The four push-buttons named
KEY0, KEY1, KEY2, and KEY3 coming out of the Schmitt trigger device are connected directly to
the Cyclone V SoC FPGA. The push-button generates a low logic level or high logic level when it
is pressed or not, respectively. Since the push-buttons are debounced, they can be used as clock or
reset inputs in a circuit.
Figure 3-14 Connections between the push-buttons and the Cyclone V SoC FPGA
Pushbutton releasedPushbutton depressed
Before
Debouncing
Schmitt Trigger
Debounced
Figure 3-15 Switch debouncing
There are ten slide switches connected to the FPGA, as shown in Figure 3-16. These switches are
not debounced and to be used as level-sensitive data inputs to a circuit. Each switch is connected
directly and individually to the FPGA. When the switch is set to the DOWN position (towards the
edge of the board), it generates a low logic level to the FPGA. When the switch is set to the UP
position, a high logic level is generated to the FPGA
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.
Figure 3-16 Connections between the slide switches and the Cyclone V SoC FPGA
There are also ten user-controllable LEDs connected to the FPGA. Each LED is driven directly and
individually by the Cyclone V SoC FPGA; driving its associated pin to a high logic level or low
level to turn the LED on or off, respectively. Figure 3-17 shows the connections between LEDs and
Cyclone V SoC FPGA. Table 3-6, Table 3-7 and Table 3-8 list the pin assignment of user
push-buttons, switches, and LEDs.
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Figure 3-17 Connections between the LEDs and the Cyclone V SoC FPGA
Table 3-6 Pin Assignment of Slide Switches
Signal Name
FPGA Pin No.
Description
I/O Standard
SW[0]
PIN_AB30
Slide Switch[0]
Depend on JP3
SW[1]
PIN_Y27
Slide Switch[1]
Depend on JP3
SW[2]
PIN_AB28
Slide Switch[2]
Depend on JP3
SW[3]
PIN_AC30
Slide Switch[3]
Depend on JP3
SW[4]
PIN_W25
Slide Switch[4]
Depend on JP3
SW[5]
PIN_V25
Slide Switch[5]
Depend on JP3
SW[6]
PIN_AC28
Slide Switch[6]
Depend on JP3
SW[7]
PIN_AD30
Slide Switch[7]
Depend on JP3
SW[8]
PIN_AC29
Slide Switch[8]
Depend on JP3
SW[9]
PIN_AA30
Slide Switch[9]
Depend on JP3
Table 3-7 Pin Assignment of Push-buttons
Signal Name
FPGA Pin No.
Description
I/O Standard
KEY[0]
PIN_AJ4
Push-button[0]
3.3V
KEY[1]
PIN_AK4
Push-button[1]
3.3V
KEY[2]
PIN_AA14
Push-button[2]
3.3V
KEY[3]
PIN_AA15
Push-button[3]
3.3V
Table 3-8 Pin Assignment of LEDs
Signal Name
FPGA Pin No.
Description
I/O Standard
LEDR[0]
PIN_AA24
LED [0]
3.3V
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LEDR[1]
PIN_AB23
LED [1]
3.3V
LEDR[2]
PIN_AC23
LED [2]
3.3V
LEDR[3]
PIN_AD24
LED [3]
3.3V
LEDR[4]
PIN_AG25
LED [4]
3.3V
LEDR[5]
PIN_AF25
LED [5]
3.3V
LEDR[6]
PIN_AE24
LED [6]
3.3V
LEDR[7]
PIN_AF24
LED [7]
3.3V
LEDR[8]
PIN_AB22
LED [8]
3.3V
LEDR[9]
PIN_AC22
LED [9]
3.3V
3.6.2 7-segment Displays
The DE10-Standard board has six 7-segment displays. These displays are paired to display numbers
in various sizes. Figure 3-18 shows the connection of seven segments (common anode) to pins on
Cyclone V SoC FPGA. The segment can be turned on or off by applying a low logic level or high
logic level from the FPGA, respectively.
Each segment in a display is indexed from 0 to 6, with corresponding positions given in Figure
3-18. Table 3-9 shows the pin assignment of FPGA to the 7-segment displays.
Figure 3-18 Connections between the 7-segment display HEX0 and the Cyclone V SoC FPGA
Table 3-9 Pin Assignment of 7-segment Displays
Signal Name
FPGA Pin No.
Description
I/O Standard
HEX0[0]
PIN_W17
Seven Segment Digit 0[0]
3.3V
HEX0[1]
PIN_V18
Seven Segment Digit 0[1]
3.3V
HEX0[2]
PIN_AG17
Seven Segment Digit 0[2]
3.3V
HEX0[3]
PIN_AG16
Seven Segment Digit 0[3]
3.3V
HEX0[4]
PIN_AH17
Seven Segment Digit 0[4]
3.3V
HEX0[5]
PIN_AG18
Seven Segment Digit 0[5]
3.3V
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HEX0[6]
PIN_AH18
Seven Segment Digit 0[6]
3.3V
HEX1[0]
PIN_AF16
Seven Segment Digit 1[0]
3.3V
HEX1[1]
PIN_V16
Seven Segment Digit 1[1]
3.3V
HEX1[2]
PIN_AE16
Seven Segment Digit 1[2]
3.3V
HEX1[3]
PIN_AD17
Seven Segment Digit 1[3]
3.3V
HEX1[4]
PIN_AE18
Seven Segment Digit 1[4]
3.3V
HEX1[5]
PIN_AE17
Seven Segment Digit 1[5]
3.3V
HEX1[6]
PIN_V17
Seven Segment Digit 1[6]
3.3V
HEX2[0]
PIN_AA21
Seven Segment Digit 2[0]
3.3V
HEX2[1]
PIN_AB17
Seven Segment Digit 2[1]
3.3V
HEX2[2]
PIN_AA18
Seven Segment Digit 2[2]
3.3V
HEX2[3]
PIN_Y17
Seven Segment Digit 2[3]
3.3V
HEX2[4]
PIN_Y18
Seven Segment Digit 2[4]
3.3V
HEX2[5]
PIN_AF18
Seven Segment Digit 2[5]
3.3V
HEX2[6]
PIN_W16
Seven Segment Digit 2[6]
3.3V
HEX3[0]
PIN_Y19
Seven Segment Digit 3[0]
3.3V
HEX3[1]
PIN_W19
Seven Segment Digit 3[1]
3.3V
HEX3[2]
PIN_AD19
Seven Segment Digit 3[2]
3.3V
HEX3[3]
PIN_AA20
Seven Segment Digit 3[3]
3.3V
HEX3[4]
PIN_AC20
Seven Segment Digit 3[4]
3.3V
HEX3[5]
PIN_AA19
Seven Segment Digit 3[5]
3.3V
HEX3[6]
PIN_AD20
Seven Segment Digit 3[6]
3.3V
HEX4[0]
PIN_AD21
Seven Segment Digit 4[0]
3.3V
HEX4[1]
PIN_AG22
Seven Segment Digit 4[1]
3.3V
HEX4[2]
PIN_AE22
Seven Segment Digit 4[2]
3.3V
HEX4[3]
PIN_AE23
Seven Segment Digit 4[3]
3.3V
HEX4[4]
PIN_AG23
Seven Segment Digit 4[4]
3.3V
HEX4[5]
PIN_AF23
Seven Segment Digit 4[5]
3.3V
HEX4[6]
PIN_AH22
Seven Segment Digit 4[6]
3.3V
HEX5[0]
PIN_AF21
Seven Segment Digit 5[0]
3.3V
HEX5[1]
PIN_AG21
Seven Segment Digit 5[1]
3.3V
HEX5[2]
PIN_AF20
Seven Segment Digit 5[2]
3.3V
HEX5[3]
PIN_AG20
Seven Segment Digit 5[3]
3.3V
HEX5[4]
PIN_AE19
Seven Segment Digit 5[4]
3.3V
HEX5[5]
PIN_AF19
Seven Segment Digit 5[5]
3.3V
HEX5[6]
PIN_AB21
Seven Segment Digit 5[6]
3.3V
3.6.3 2x20 GPIO Expansion Header
The board has one 40-pin expansion headers. Thw header has 36 user pins connected directly to the
Cyclone V SoC FPGA. It also comes with DC +5V (VCC5), DC +3.3V (VCC3P3), and two GND
pins. The maximum power consumption allowed for a daughter card connected to one GPIO ports
is shown in Table 3-10.
DE10-Standard
User Manual
29
www.terasic.com
January 19, 2017
Table 3-10 Voltage and Max. Current Limit of Expansion Header(s)
Supplied Voltage
Max. Current Limit
5V
1A
3.3V
1.5A
Each pin on the expansion headers is connected to two diodes and a resistor for protection against
high or low voltage level. Figure 3-19 shows the protection circuitry applied to all 36 data pins.
Table 3-11 shows the pin assignment of the GPIO header.
Figure 3-19 Connections between the GPIO header and Cyclone V SoC FPGA
Table 3-11 Pin Assignment of Expansion Headers
Signal Name
FPGA Pin No.
Description
I/O Standard
GPIO[0]
PIN_W15
GPIO Connection 0[0]
3.3V
GPIO[1]
PIN_AK2
GPIO Connection 0[1]
3.3V
GPIO[2]
PIN_Y16
GPIO Connection 0[2]
3.3V
GPIO[3]
PIN_AK3
GPIO Connection 0[3]
3.3V
GPIO[4]
PIN_AJ1
GPIO Connection 0[4]
3.3V
GPIO[5]
PIN_AJ2
GPIO Connection 0[5]
3.3V
GPIO[6]
PIN_AH2
GPIO Connection 0[6]
3.3V
GPIO[7]
PIN_AH3
GPIO Connection 0[7]
3.3V
GPIO[8]
PIN_AH4
GPIO Connection 0[8]
3.3V
GPIO[9]
PIN_AH5
GPIO Connection 0[9]
3.3V
GPIO[10]
PIN_AG1
GPIO Connection 0[10]
3.3V
GPIO[11]
PIN_AG2
GPIO Connection 0[11]
3.3V
GPIO[12]
PIN_AG3
GPIO Connection 0[12]
3.3V
GPIO[13]
PIN_AG5
GPIO Connection 0[13]
3.3V
GPIO[14]
PIN_AG6
GPIO Connection 0[14]
3.3V
GPIO[15]
PIN_AG7
GPIO Connection 0[15]
3.3V
GPIO[16]
PIN_AG8
GPIO Connection 0[16]
3.3V
GPIO[17]
PIN_AF4
GPIO Connection 0[17]
3.3V
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