Terasic Altera Cyclone V GX Starter Kit User Manual

1

CONTENTS

CHAPTER 1 INTRODUCTION ................................................................................................................................. 3

PACKAGE CONTENTS ................................................................................................................................................. 3

1.1

1.2

CYCLONE V GX STARTER KIT SYSTEM CD .............................................................................................................. 4

1.3

LA YOUT A ND COMPONENTS ...................................................................................................................................... 4

1.4

BLOCK DIAGRAM OF THE CYCLONE V GX STARTER KIT BOARD .............................................................................. 8

1.5

GETTING HELP .......................................................................................................................................................... 8

CHAPTER 2 CONTROL PANEL ............................................................................................................................... 9

CONTROL PANEL SETUP ............................................................................................................................................ 9

2.1

2.2

CONTROLLING THE LEDS, 7-SEGMENT DISPLAYS ................................................................................................... 12

2.3

SWITCHES AND PUSH-BUTTONS .............................................................................................................................. 14

2.4

SRAM/LPDDR2 CONTROLLER AND PROGRAMMER ............................................................................................... 15

2.5

SD CARD ................................................................................................................................................................ 17

2.6

ADC ....................................................................................................................................................................... 17

2.7

UART-USB COMMUNICATION ................................................................................................................................ 18

2.8

HDMI-TX .............................................................................................................................................................. 19

2.9

HSMC .................................................................................................................................................................... 20

2.10

OVERALL STRUCTURE OF THE C5G CONTROL PANEL ........................................................................................... 21

CHAPTER 3 USING THE STARTER KIT .............................................................................................................. 23

CONFIGURATION, STAT US AND SETUP ..................................................................................................................... 23

3.1

3.2

GENERAL USER INPUT/OUTPUT .............................................................................................................................. 27

3.3

CLOCK CIRCUIT ...................................................................................................................................................... 33

3.4

RS-232 SERIAL PORT TO USB INTERFACE ............................................................................................................... 35

3.5

SRAM : STAT IC RANDOM ACCESS MEMORY .......................................................................................................... 36

3.6

LPDDR2 MEMORY ................................................................................................................................................. 37

3.7

MICRO SD-CARD .................................................................................................................................................... 40

3.8

HDMI TX INTERFACE ............................................................................................................................................. 42

3.9

AUDIO INTERFACE ................................................................................................................................................... 43

3.10

HSMC : HIGH-SPEED MEZZANINE CARD ............................................................................................................. 44

3.11

USING THE 2X20 GPIO EXPANSION HEADER ........................................................................................................ 49

CHAPTER 4 SYSTEM BUILDE R ........................................................................................................................... 56

INTRODUCTION ....................................................................................................................................................... 56

4.1

4.2

GENERAL DESIGN FLOW ......................................................................................................................................... 56

4.3

USING C5G SYSTEM BUILDER ................................................................................................................................ 57

1

CHAPTER 5 RTL BASED EXAMPLE CODES ...................................................................................................... 64

FACTORY CONFIGURATION ...................................................................................................................................... 64

5.1

5.2

LPDDR2 SDRAM RTL TEST ................................................................................................................................. 65

CHAPTER 6 NIOS-II BASED EXAMPLE CODES ............................................................................................... 68

SRAM .................................................................................................................................................................... 68

6.1

6.2

UART TO USB CONTROL LED ................................................................................................................................. 71

6.3

HDMI TX ............................................................................................................................................................... 75

6.4

TRANSCEIVER HSMC LOOPBACK TEST .................................................................................................................. 83

6.5

AUDIO RECORDING AND PLAYING ........................................................................................................................... 84

6.6

MICRO SD CARD FILE SYSTEM READ ...................................................................................................................... 87

6.7

SD CARD MUSIC PLAYER DEMONSTRATION ............................................................................................................. 91

2

Chapter 1

Introduction

The Cyclone V GX Starter Kit p resents a robust hardware design platform built around the Altera
Cyclone V GX FPGA, which is optimized for the lowest cost and power requirement for transceiver
applications with industry-leading programmable logic for ultimate design flexibility. With Cyclone
V FPGAs, you can get the power, cost, and performance levels you need for high-volume
applications including protocol bridging, motor control drives, broadcast video converter and
capture cards, and handheld devices. The Cyclone V GX Starter Kit development board includes
hardware such as Arduino Header, on-board USB Bl aster, audio and video capabilities and much
more. In addition, an on -board HSMC connector with high-speed transceivers all ows for an even
greater array of hardw are setups. By leveraging all of these capabilities, the Cyclone V GX Starter
Kit is the perfect solution for showcasing, evaluating, and prototyping the true potential of the
Altera Cyclone V GX FPGA.

The Cyclone V GX Start er Kit contains all components needed to use the board in conjunction with
a computer that runs the Microsoft Windows XP or later.

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Figure 1-1 shows a photograph of the Cyclone V GX Starter Kit package.

Figure 1-1 The Cyclone V GX Starter Kit package contents

3

The Cyclone V GX Starter Kit package includes:

• The Cyclone V GX Starter Kit board

• Cyclone V GX Starter Kit Quick Start Guide

• 12V DC Power Supply

• Type A Male to Type B Male USB Cable

• System CD

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The Cyclone V GX Start Kit System CD contains the documentation and supporting materials,
including the User Manual, Control Panel, System Builder, referen ce des i g ns an d d evi c e d at ash eets .
User can download this System CD from the web (http://c5g.terasic.com).

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This chapter presents the features and design characteristics of the board.

A photograph of the board is shown in Fig u re 1-2 and Fig u re 1-3. It depicts the layout of the board
and indicates the location of the connectors and key components.

This chapter presents the features and design characteristics of the board

4

Figure 1-2 Development Board (top view)

Figure 1-3 Development Board (bottom view)

5

The board has man y features t hat allow users to i mplement a wi de range o f designed cir cuits, fro m
simple circuits to various multimedia projects.

The following hardware is provided on the board:

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• Cyclone V GX 5CGXFC5C6F27C7N Device

• 77K Programmable Logic Elements

• 4884 Kbits embedded memory

• Six Fractional PLLs

• Two Hard Memory Controllers

• Six 3.125G Transceivers

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• Quad Serial Configuration device – EPCQ256 on FPGA

• On-Board USB Blaster (Normal type B USB connector)

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• LPDDR2 x32 bits data bus

• SRAM x16 bits data bus

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• UART to USB

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• HSMC x 1, including 4-lanes 3.125G transceiver,

• 2x20 GPIO Header

• Arduino header, including analog pins.

• SMA pads, unpopulated.

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• HDMI TX, compatible with DVI v1.0 and HDCP v1.4

6

AAuuddiioo

• 24-bit CODEC, Line-in, line-out, and microphone-in jacks

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• 18 LEDs

• 10 Slide Switches

• 4 Debounced Push Buttons

• 1 CPU reset Push Buttons

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• 12V DC input

7

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Figure 1-4 gives the block diagram of the board. To provide maximum flexibility for the user, all

connections are made through the Cyclone V GX FPGA device. Thus, the user can configure the
FPGA to implement any system design.

Figure 1-4 Board Block Diagram

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Here are the addresses where you can get help if you encounter any problem:

• Terasic Technologies

Taiwan/ 9F, No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, Taiwan 300-70

Email: [e-mail]

Tel.: [phone]

Web: http://c5g.terasic.com

8

Chapter 2

Control Panel

The Cyclone V GX Start board comes with a Control Panel program that allows users to access
various components on the board from a host computer. The host computer communicates with the
board through a USB connection. The program can be used to verify the functionality of
components on the board or be used as a debug tool while developing RTL code.

This chapter first presents some basic functions of the Control Panel, then describes its structur e in
the block diagram form, and finally describes its capabilities.

22..11

CCoonnttrrooll PPaanneell SSeettuup

The Control Panel Software Utility is located in the directory “Tools/ ControlPanel” on the Cyclone
V GX Starter Kit System CD. It's free of installation, just copy the whole folder to your host
computer and launch the control panel by executing the “C5G_ControlPanel.exe”.

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Specific control circuits should be downloaded to your FPGA board before the control panel can
request it to perform required tasks. The program will call Quartus II tools to download the control
circuit to the FPGA board through the USB-Blaster[USB-0] connection.

To activate the Control Panel, perform the following steps:

1. Make sure Quartus II 13.0 or a later version is installed successfully on your PC.

2. Set the RUN/PROG switch to the RUN position.

3. Connect the supplied USB cable to the USB Blaster port, connect the 12V power supply, and
turn the power switch ON.

4. Start the executable C5G_ControlPanel.exe on the host computer. The Control Panel user
interface shown in Figure 2-1 will appear.

5. The C5G_ControlPanel.sof bit stream is loaded automatically as soon as the
C5G_ControlPanel.exe is launched.

6. In case of a disconnetion, click on CONNECT where the .sof will be re-loaded onto the board.

9

Please note that the Control Panel will occupy the USB port until you close that port; you cannot use Quartus II

to download a configuration file into the FPGA until the USB port is closed.

7. The Control Panel is now ready for use; experience it by setting the ON/OFF status for some
LEDs and observing the result on the C5G board.

Figure 2-1 The C5G Control Panel

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The concept of the C5G Control Panel is illustrated in Figure 2-2. The “Control Circuit” that
performs the control functions is implemented in the FPGA board. It communicates with the
Control Panel window, which is active on the host computer, via the USB Blaster link. The
graphical interfac e is used to send commands to the control circuit. It handles all the requests and
performs data transfers between the computer and the Cyclone V Starter Kit board.

Figure 2-2 The C5G Control Panel concept

The C5G Control Panel can be used to light up LEDs, change the values displayed on 7-segment,
monitor buttons/switches status, read/write the SRAM and LPDDR2 Memory, output HDMI-TX
color pattern to VGA monitor, verify functionality of HSMC connector I/Os, communicate with PC
via UART to USB interface, read SD Card specification information. The feature of reading/writing
a word or an entire file from/to the Memory allows the user to develop multimedia applications
(Flash Audio Player, Flash Picture Viewer) without worrying about how to build a Memory
Programmer.

11

22..22

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A simple function of the Control Panel is to allow setting the values displayed on LEDs, 7-segment
displays.

Choosing the LED tab leads to the window in Figu re 2-3. Here, you can directly turn the LE Ds on
or off individually or by clicking “Light All” or “Unlight All”.

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Figure 2-3 Controlling LEDs

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Choosing the 7-SEG t ab leads to the window shown in Fi gure 2-4. From the window, directly use
the left-ri ght arrows to control the 7-SEG patterns on the Cyclone V GX Starter board which are
updated immediately. Note that the dots of the 7-SEGs are not enabled on Cyclone V GX Starter
Board.

Figure 2-4 Controlling 7-SEG display

The ability to set arbitrary values into simple display devices is not needed in typical design
activities. However, it gives users a simple mechanism for verifying that these devices are
functioning correctly in case a malfunction is suspected. Thus, it can be used for troubleshooting
purposes.

13

22..33

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Choosing the Switches tab leads to the window in Fig ure 2-5. The function is designed to monitor
the status of slide switches and push-buttons in real time and show the status in a graphical user
interface. It can be used to verify the functionality of the slide switches and push-buttons.

s

Figure 2-5 Monitoring switches and butto n s

The ability to check the status of push-button and slide switch is not needed in typical design
activities. However, it provides users a simple mechanism to verify if th e buttons and switches are
functioning correctly. Thus, it can be used for troubleshooting purposes.

14

22..44

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The Control Panel can be used to write/read data to/from the SRAM and LPDDR2 chips on the
Cyclone V GX Starter b oard. As an example, we will describe ho w the LPDDR2 may be accessed ;
the same approach is us ed to access t he SRAM. Cli ck on the Memor y tab and select “LPDDR2” t o
reach the window in Figure 2-6.

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Figure 2-6 Access ing the LPDDR2

A 16-bit word can be written into the LPDDR2 by entering the address of the desired location,
specifying the data to be written, and pressing the Write button. Contents of the location can be read
by pressing the Read button. Fig ure 2 -6 depicts the result of writing the hexadecimal value 06CA
into offset address 200, followed by reading the same location.

The Sequential Write function of the Control Panel is used to write the contents of a file into the
LPDDR SDRAM as follows:

1. Specify the starting address in the Address box.

15

2. Specify the number of bytes to be written in the Length box. If the entire file is to be loaded,
then a checkmark may be placed in the File Length box instead of giving the number of bytes.

3. To initiate the writing process, click on the Write a File to Memory button.

4. When the Control Panel responds with the standard Windows dialog box asking for the source
file, specify the desired file in the usual manner.

The Control Panel also supports loading files with a .hex extension. Files with a .hex extension are
ASCII text files that specify memory values using ASCII characters to represent hexadecimal
values. For example, a file containing the line

0123456789ABCDEF

defines eight 8-bit values: 01, 23, 45, 67, 89, AB, CD, EF. These values will be loaded
consecutively into the memory.

The Sequential Read function is used to read the contents of the LPDDR2 and fill them into a file as
follows:

1. Specify the starting address in the Address box.

2. Specify the number of bytes to be copied into the file in the Length box. If the entire contents
of the LPDDR2 are to be copied (which involves all 512 Mbytes), then place a checkmark in
the Entire Memory box.

3. Press Load Memory Content to a File button.

4. When the Control Panel responds with the standard Windows dialog box asking for the
destination file, specify the desired file in the usual manner.

Users can use the similar way to access the SRAM.

16

22..55

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The function is designed to read the identification and specification information of the SD Card.
The 4-bit SD MODE is used to access the SD Card. This function can be used to verify the
functionality of the SD Card Interface. Fo llow the steps below to perform the SD Card exercise:

1. Choosing the SD Card tab leads to the window in Figure 2-7.

2. Insert an SD Card to the Cyclone V GX Starter board, and then press the Read button to read
the SD Card. The SD Card’s identification, specification, and file format information will be
displayed in the control window.

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Figure 2-7 Reading the SD Card Identifica tion and Specification

22..66

From the Control Panel, users are able to view the eight-channel 12-bit analog-to-digital converter
reading. The values shown are the ADC register outputs from all of the eight separate channels. The

C

AADDC

17

voltage shown is the voltage reading from the separate pins on the extension header. Figure 2-8
shows the ADC readings when the ADC tab is chosen.

Figure 2-8 Reading of eight channel ADC

22..77

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The Control Panel allows users to verify the operation of the UART to USB serial communication
interface on the Cyclone V GX Starter Board. The setup is established by connecting a USB cable
from the PC to the USB port where the Control Panel communicates to the terminal emulator
software on the PC, or vice versa. The Receive terminal window on the Co ntrol Panel monitors the
serial communication status. Follow the steps below to initiate the UART communication:

1. Choosing the UART-USB tab leads to the window in Figure 2-9.

2. Plug in an USB cable from PC USB port to the USB to UART port on Cyclone V GX Starter
board.

3. The UART settings are provided below in case a connection from the PC is used:

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18

• Baud Rate: 115200

• Parity Check Bit: None

• Data Bits: 8

• Stop Bits: 1

• Flow Control (CTS/RTS): OFF

4. To begin the communication, enter specific letters followed by clicking Send. During the
communication process, observe the status of the Receive terminal window to verify its
operation.

Figure 2-9 UART to USB Serial Communication

22..88

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C5G Control Panel provides video pattern function that allows users to output color pattern to
HDMI interfaced LCD monitor using the Cyclone V GX Starter board. Follow the steps below to
generate the video pattern function:

Note, do not install HSMC loopback board while using HDMI-TX function because the loopback

board will inference the I2C bus of HDMI.

Choosing the Video tab leads to the window in Figure 2-10.

X

19

Plug a HDMI cable to HDMI connector of the Cyclone V GX Starter board and LCD monitor.
The LCD monitor will display the same color pattern on the control panel window.
Click the drop down menu shown in Figure 2-10 where you can output the selected color

individually.

Figure 2-10 Controlling VGA display

22..99

HHSSMMC

Select the HSMC tab to reach the window shown in Figure 2-11. This function is designed to verify
the functionality of the signals located on the HSMC connector. Before running the HSMC
loopback verification test, follow the instruction noted under the Loopback Installation section and
click on Verify. Please note to turn off the Cyclone V GX Starter board before the HSMC loopback
adapter is installed to prevent any damage to the board.

The HSMC loopback adapter is not provided in the kit package but can be purchased through the
website below: (http://hsmc_loopback.terasic.com)

C

20

Figure 2-11 HSMC loopback verification test performed under Control Panel

22..1100

The C5G Control Panel is based on a Nios II Qsys system instantiated in the Cyclone V GX FPGA
with software running on the on-chip memory. The software part is implemented in C code; the
hardware part is implemented in Verilog HDL code with Qsys builder. The source code is not
available on the C5G System CD.

To run the Control Panel, users should make the configuration according to Section 3.1. Figure

2-12 depicts the structure of the Control Panel. Each input/output device is controlled by the Nios II

Processor instantiated in the FPGA chip. The communication with the PC is done via the USB
Blaster link. The Nios II interprets the commands sent from the PC and performs the corresponding
actions.

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21

Figure 2-12 The block diagram of the C5G control panel

22

Chapter 3

Using the Starter Kit

In this chapter we introduce the important components on the Cyclone V GX Starter Kit.

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The procedure of downloading a circuit from a host computer to the Cyclone V GX Starter Kit
board is described in the tutorial Quartus II Introduction. This tutorial can be found under the
\tutorials folder on the Cyclone V GX Starter Kit System CD. You are encouraged to read the
tutorial first, and treat the information below as a short reference.

The Cyclone V GX Starter Ki t board contains a serial configuration device that stores configuration
data for the Cyclone V GX FPGA. This configuration data is automatically loaded from the
configuration devi ce into th e FPGA when powered on. Using the Quartus II software, it is possible
to reconfigure the FPGA at any time, and it is also possible to change the non-volatile data that is
stored in the serial configuration device. Both types of programming methods are described below.

1. JTAG programming: In this method of programming, named after the IEEE standards Joint
Test Action Group, the configuration bit stream is downloaded directly into the Cyclone GX
FPGA. The FPGA will retain this configuration as long as power is applied to the board; the
configuration information will be lost when the power is turned off.

2. AS programming: In this method, called Active Serial programming, the configuration bit
stream is downloaded into the Altera EPCQ256 serial configuration device. It provides
non-volatile storage of the bit stream, so that the information is retained even when the power
supply to the Cyclone V GX Starter Kit board is turned off. When the board’s power is turned
on, the configuration data in the EPCQ256 device is automatically loaded into the Cyclone V
GX FPGA.

 JTAG Chain on Cyclone V GX Starter Kit board

To use JTAG interface for configuring FPGA device, the JTAG chain on Cyclone V GX Starter Kit
must form a closed loop that allows Quartus II programmer to detect FPGA device. Figure 3-1
illustrates the JTAG chain on Cyclone V GX Starter Kit board. Shorting pin1 and pin2 on JP2 can

23

disable the JTAG signals on HSMC connector that will form a closed JTAG loop chain on Cyclone
V GX Starter Kit board (See Figure 3 -2). Thus, only the on-board FPGA device (Cyclone V GX)
will be detected by the Quartus II programmer. If users want to include another FPGA device or
interface containing FPGA device in the chain via HSMC connector, remove JP2 Jumper (open pin1
and pin2 on JP2) to enable the JTAG signal ports on the HSMC connector.

Figure 3-1 The JTAG chain on Cyclone V GX Starter K it board

Figure 3-2 The JTAG chain configuration header

The sections below describe the steps to perform both JTAG and AS programming. For both
methods the Cyclone V GX Starter Kit board is connected to a host computer via a USB cable.
Using this connection, the board will be identified by the host computer as an Altera USB Blaster
device.

24

 Configuring the FPGA in JTAG Mode

Fig ure 3-3 illustrates the JTAG configuration setup. To download a configuration bit stream into

the Cyclone V GX FPGA, you need to perform the following steps:

• Ensure that power is applied to the Cyclone V GX Starter Kit board

• Configure the JTAG programming circuit by setting the RUN/PROG slide switch (SW11) to the

RUN position (See Figure 3-4)

• Connect the supplied USB cable to the USB Blaster port on the Cyclone V GX Starter Kit board

(See Figure 1-2)

• The FPGA can now be programmed by using the Quartus II Programmer to select a

configuration bit stream file with the .sof filename extension

Figure 3-3 The JTAG configuration scheme

Figure 3-4 The RUN/PROG switch (SW11) is set in JTAG mode

25

Board
Reference

LED Name

Description

D5 12

Illuminates when 12

 Configuring the EPCQ256 in AS Mode

Fig ure 3-5 illustrates the AS configuration setup. To download a configuration bit stream into the

EPCQ256 serial configuration device, you need to perform the following steps:

• Ensure that power is applied to the Cyclone V GX Starter Kit board.

• Connect the supplied USB cable to the USB Blaster port on the Cyclone V GX Starter Kit board

• Configure the JTAG programming circuit by setting the RUN/PROG slide switch (SW11) to the

PROG position.

• The EPCQ256 chip can now be programmed by using the Quartus II Programmer to select a

configuration bit stream file with the .pof filename extension.

• Once the programming operation is finished, set the RUN/PROG slide switch back to the RUN

position and then reset the board by turning the power switch off and back on; this action causes
the new configuration data in the EPCQ256 device to be loaded into the FPGA chip.

Figure 3-5 The AS configuration scheme

 Status LED

• The FPGA development board includes board-specific status LEDs to indicate board status.

Please refer to Table 3-1 for the description of the LED indicator. Please refer to Figure 3-6 for
detailed LED location.

Table 3-1 Status LED

-V Power

-V power is active.

26

D6 3.3

Illuminates when 3.3

D

HSMC_12

Illuminates when

D

HSMC_PSNT_n

Illuminates

D7 ULED

Illuminates when the

-V Power

-V power is active.
24
23

-V Power

HSMC 12-V power is active.

when HSMC Daughter Card is present

on-board USB-Blaster is working

Figure 3-6 Status L ED position

33..22 GGeenneerraall UUsseerr IInnppuutt//OOuuttppuutt

This section describes the user I/O interface to the FPGA.

 User Defined Push-buttons

The board includes four user defined push-buttons that allow users to interact with the Cyclone V
GX device as shown in Figu re 3-7. E ach of these switches is debounced using a Schmitt Trigger
circuit, as indicated in Fi gu re 3 -8. The four outputs called KEY0, KEY1, KEY2, and KEY3 of the
Schmitt Trigger devices are connected directly to the Cyclone V GX FPGA. Each push-button
switch provides a high logic level when it is not pressed, and provides a low logic level when

27

Pushbutton releasedPushbutton depressed

Before

Debouncing

Schmitt Trigger

Debounced

depressed. Since the push-button switches are debounced, they are appropriate for using as clocks
or reset inputs in a circuit.

Ta b l e 3 -2 lists the board referenc es, signal names, and their corresponding Cyclone V GX device

pin numbers.

Figure 3-7 Connections between the push-button and Cyclone V GX FPGA

Figure 3-8 Switch debouncing

28