TEMIC TS80C31X2 Technical data

查询TS80C31X2-LIAB供应商

8-bit CMOS Microcontroller 0-60 MHz

1. Description

TS80C31X2

TEMIC TS80C31X2 is high performance CMOS and
ROMless versions of the 80C51 CMOS single chip 8­bit microcontroller.

The TS80C31X2 retains all features of the TEMIC
TSC80C31 with 128 bytes of internal RAM, a 5-source,
4 priority level interrupt system, an on-chip oscilator
and two timer/counters.

In addition, the TS80C31X2 has a dual data pointer, a
more versatile serial channel that facilitates
multiprocessor communication (EUART) and a X2 speed
improvement mechanism.

2. Features

● 80C31 Compatible

• 8031 pin and instruction compatible

• Four 8-bit I/O ports

• Two 16-bit timer/counters

• 128 bytes scratchpad RAM

● High-Speed Architecture

• 40 MHz @ 5V, 30MHz @ 3V

• X2 Speed Improvement capability (6 clocks/

machine cycle)
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to

60 MHz @ 5V, 40 MHz @ 3V)

● Dual Data Pointer

● Asynchronous port reset

The fully static design of the TS80C31X2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.

The TS80C31X2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the timers, the serial port and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.

● Interrupt Structure with

• 5 Interrupt sources,

• 4 priority level interrupt system

● Full duplex Enhanced UART

• Framing error detection

• Automatic address recognition

● Power Control modes

• Idle mode

• Power-down mode

• Power-off Flag

● Once mode (On-chip Emulation)

● Power supply: 4.5-5.5V, 2.7-5.5V

● Temperature ranges: Commercial (0 to 70

Industrial (-40 to 85oC)

● Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1

(13.9 footprint)

o

C) and

Rev. A - Mar. 19, 1999 1

Preliminary

TS80C31X2

3. Block Diagram

RxD

(1)(1)

TxD

ALE/

XTAL1
XTAL2

PROG

PSEN

EA

RD

WR

(1)
(1)

CPU

RESET

EUART

Timer 0
Timer 1

(1) (1) (1) (1)

RAM
128x8

C51

CORE

INT
Ctrl

T0

T1

INT0

(1): Alternate function of Port 3

IB-bus

INT1

Parallel I/O Ports & Ext. Bus

Port 0

Port 1

P0

P1

Port 2

Port 3

P2

P3

2 Rev. A - Mar. 19, 1999

Preliminary

TS80C31X2

4. SFR Mapping

The Special Function Registers (SFRs) of the TS80C31X2 fall into the following categories:

• C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1

• I/O port registers: P0, P1, P2, P3

• Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1

• Serial I/O port registers: SADDR, SADEN, SBUF, SCON

• Power and clock control registers: PCON

• Interrupt system registers: IE, IP, IPH

• Others: CKCON

Table 1. All SFRs with their address and their reset value

Bit

address-

able

0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

F8h FFh
F0h

E8h EFh
E0h

D8h DFh
D0h

C8h CFh

B

0000 0000

ACC

0000 0000

PSW

0000 0000

Non Bit addressable

F7h

E7h

D7h

C0h C7h

B8h

B0h

A8h

A0h

98h

90h

88h

80h

IP

XXX0 0000

P3

1111 1111

IE

0XX0 0000

P2

1111 1111

SCON

0000 0000

P1

1111 1111

TCON

0000 0000

P0

1111 1111

0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

SADEN

0000 0000

SADDR

0000 0000

SBUF

XXXX XXXX

TMOD

0000 0000

SP

0000 0111

AUXR1

XXXX 0XX0

TL0

0000 0000

DPL

0000 0000

TL1

0000 0000

DPH

0000 0000

TH0

0000 0000

TH1

0000 0000

IPH

XXX0 0000

CKCON

XXXX XXX0

PCON

00X1 0000

BFh

B7h

AFh

A7h

9Fh

97h

8Fh

87h

reserved

Rev. A - Mar. 19, 1999 3

Preliminary

TS80C31X2

5. Pin Configuration

P1.0
P1.1

P1.2
P1.3
P1.4

P1.5

P1.6

P1.7

RST

P3.0/RxD
P3.1/TxD

P3.2/INT0
P3.3/INT1

P3.4/T0
P3.5/T1

P3.6/WR

P3.7/RD

XTAL2
XTAL1

VSS

1

3
4

5

9
10
11

14
15
16
17

2

6
7

8

12
13

18
19

20

PDIL40

24

40

31
30

26

VCC

39

P0.0

38

P0.1

P0.2

37

P0.3

36

P0.4

35

P0.5

34

P0.6

33

P0.7

32

EA
ALE
PSEN

29

P2.7

28

P2.6

27

P2.5
P2.4

25

P2.3
P2.2

23

P2.1

22

21

P2.0

P1.4

P1.3

P1.2

P1.1

P1.0

VSS1/NIC*

VCC

RST

P3.0/RxD

NIC*

P3.1/TxD
P3.2/INT0
P3.3/INT1

P3.4/T0
P3.5/T1

P0.0/AD0

P0.1/AD1

P1.5
P1.6
P1.7

P0.2/AD2

P1.4

7

8
9
10
11

12
13

14
15
16
17

P1.1

P1.3

P1.2

5 4 3 2 1 6

PLCC44

18 19 20 21 22 23 24 25 26 27 28

XTAL2

XTAL1

P3.7/RD

P3.6/WR

P0.3/AD3

P1.0

VSS1/NIC*

VCC

44 43 42 41 40

NIC*

VSS

P2.0/A8

P0.0/AD0

P2.1/A9

P0.2/AD2

P0.1/AD1

P2.2/A10

P2.3/A11

P0.3/AD3

39

38
37
36
35

34

33

32
31
30
29

P2.4/A12

P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC*
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13

P3.2/INT0

*NIC: No Internal Connection

P1.5
P1.6
P1.7
RST

P3.0/RxD

NIC*

P3.1/TxD

P3.3/INT1

P3.4/T0

P3.5/T1

43 42 41 40 3944

1

2

3
4

5

6
7

8
9
10
11

38 37 36 35 34

PQFP44
VQFP44VQFP44

12 13 14 15 16 17 18 19 20 21 22

VSS

NIC*

XTAL1

P3.7/RD

P3.6/WR

XTAL2

P2.0/A8

P2.1/A9

P2.2/A10

33

32
31
30
29

28

27

26
25
24
23

P2.3/A11

P2.4/A12

P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC*
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13

4 Rev. A - Mar. 19, 1999

Preliminary

TS80C31X2

Table 2. Pin Description for 40/44 pin packages

MNEMONIC

V

SS

Vss1 1 39 I Optional Ground: Contact the Sales Office for ground connection.
V

CC

P0.0-P0.7 39-32 43-36 37-30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s

P1.0-P1.7 1-8 2-9 40-44

P2.0-P2.7 21-28 24-31 18-25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2

P3.0-P3.7 10-17 11,

Reset 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running,

ALE 30 33 27 O (I) Address Latch Enable: Output pulse for latching the low byte of the address

PSEN 29 32 26 O Program Store ENable: The read strobe to external program memory. When

EA 31 35 29 I

XTAL1 19 21 15 I

XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier

PIN NUMBER

DIL LCC VQFP 1.4

20 22 16 I Ground: 0V reference

40 44 38 I

1-3

5,

13-19

10 11 5 I RXD (P3.0): Serial input port
11 13 7 O TXD (P3.1): Serial output port
12 14 8 I INT0 (P3.2): External interrupt 0
13 15 9 I INT1 (P3.3): External interrupt 1
14 16 10 I T0 (P3.4): Timer 0 external input
15 17 11 I T1 (P3.5): Timer 1 external input
16 18 12 O WR (P3.6): External data memory write strobe
17 19 13 O RD (P3.7): External data memory read strobe

7-13

TYPE

Power Supply: This is the power supply voltage for normal, idle and power-

down operation

written to them float and can be used as high impedance inputs. Port 0 is also
the multiplexed low-orderaddress and data bus during access to external program
and data memory. In this application, it uses strong internal pull-up when emitting
1s.

I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1

pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 1 pins that are externally pulled low will
source current because of the internal pull-ups.

pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 2 pins that are externally pulled low will
source current because of the internal pull-ups. Port 2 emits the high-order address
byte during fetches from external program memory and during accesses to external
data memory that use 16-bit addresses (MOVX @DPTR).In this application, it
uses strong internal pull-ups emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.

I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3

pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 3 pins that are externally pulled low will
source current because of the internal pull-ups. Port 3 also serves the special
features of the 80C51 family, as listed below.

resets the device. An internal diffused resistor to VSSpermits a power-on reset
using only an external capacitor to V

during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used
for external timing or clocking. Note that one ALE pulse is skipped during each
access to external data memory.

executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access
to external data memory. PSEN is not activated during fetches from internal
program memory.

External Access Enable: EA must be externally held low to enable the device
to fetch code from external program memory locations.

Crystal 1: Input to the inverting oscillator amplifier and input to the internal
clock generator circuits.

NAME AND FUNCTION

CC.

Rev. A - Mar. 19, 1999 5

Preliminary

TS80C31X2

6. TS80C31X2 Enhanced Features

In comparison to the original 80C31, the TS80C31X2 implements some new features, which are:

• The X2 option.

• The Dual Data Pointer.

• The 4 level interrupt priority system.

• The power-off flag.

• The ONCE mode.

• Enhanced UART

6.1 X2 Feature

The TS80C31X2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following
advantages:

● Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.

● Save power consumption while keeping same CPU power (oscillator power saving).

● Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes.

● Increase CPU power by 2 while keeping same crystal frequency.

In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main
clock input of the core (phase generator). This divider may be disabled by software.

6.1.1 Description

The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and
peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed,
the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 1. shows the clock generation block
diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode.
Figure 2. shows the mode switching waveforms.

XTAL1:2

XTAL1

F

XTAL

2

0
1

X2

CKCON reg

Figure 1. Clock Generation Diagram

F

OSC

state machine: 6 clock cycles.
CPU control

6 Rev. A - Mar. 19, 1999

Preliminary

TS80C31X2

XTAL1

XTAL1:2

X2 bit

CPU clock

X2 ModeSTD Mode STD Mode

Figure 2. Mode Switching Waveforms

The X2 bit in the CKCON register (See Table 3.) allows to switch from 12 clock cycles per instruction to 6 clock
cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature
(X2 mode).

CAUTION

In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all peripherals
using clock frequency as time reference (UART, timers) will have their time reference divided by two. For example
a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. UART with
4800 baud rate will have 9600 baud rate.

Rev. A - Mar. 19, 1999 7

Preliminary

TS80C31X2

Table 3. CKCON Register

CKCON - Clock Control Register (8Fh)

7 6 5 4 3 2 1 0

- - - - - - - X2

Bit

Number

7 -

6 -

5 -

4 -

3 -

2 -

1 -

0 X2

Bit

Mnemonic

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

CPU and peripheral clock bit

Reset Value = XXXX XXX0b
Not bit addressable

Description

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

Clear to select 12 clock periods per machine cycle (STD mode, F
Set to select 6 clock periods per machine cycle (X2 mode, F

OSC=FXTAL

OSC=FXTAL

).

/2).

8 Rev. A - Mar. 19, 1999

Preliminary

TS80C31X2

6.2 Dual Data Pointer Register Ddptr

The additional data pointer can be used to speed up code execution and reduce code size in a number of
ways.

The dual DPTR structure is a way by which the chip will specify the address of an external data memory
location. There are two 16-bit DPTR registers that address the external memory, and a single bit called
DPS = AUXR1/bit0 (See Table 5.) that allows the program code to switch between them (Refer to Figure 3).

External Data Memory

07

DPS

AUXR1(A2H)

DPH(83H) DPL(82H)

DPTR1

DPTR0

Figure 3. Use of Dual Pointer

Rev. A - Mar. 19, 1999 9

Preliminary

TS80C31X2

Table 4. AUXR1: Auxiliary Register 1

7 6 5 4 3 2 1 0

- - - - - - - DPS

Bit

Number

7 -

6 -

5 -

4 -

3 -

2 -

1 -

0 DPS

Bit

Mnemonic

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Data Pointer Selection

Reset Value = XXXX XXX0
Not bit addressable

Description

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

Clear to select DPTR0.
Set to select DPTR1.

Application

Software can take advantage of the additional data pointers to both increase speed and reduce code size, for
example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’
pointer and the other one as a "destination" pointer.

10 Rev. A - Mar. 19, 1999

Preliminary

ASSEMBLY LANGUAGE

; Block move using dual data pointers
; Destroys DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6 JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS

TS80C31X2

INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However,
note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it.
In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence
matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1'
on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the
opposite state.

Rev. A - Mar. 19, 1999 11

Preliminary

TS80C31X2

6.3 TS80C31X2 Serial I/O Port

The serial I/O port in the TS80C31X2 is compatible with the serial I/O port in the 80C31.
It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous
Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and
reception can occur simultaneously and at different baud rates

Serial I/O port includes the following enhancements:

● Framing error detection

● Automatic address recognition

6.3.1 Framing Error Detection

Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing
bit error detection feature, set SMOD0 bit in PCON register (See Figure 4).

RITIRB8TB8RENSM2SM1SM0/FE

SCON (98h)

Set FE bit if stop bit is 0 (framing error) (SMOD = 1)
SM0 to UART mode control (SMOD = 0)

PCON (87h)

IDLPDGF0GF1POF-SMOD0SMOD1

To UART framing error control

Figure 4. Framing Error Block Diagram

When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop
bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit
is not found, the Framing Error bit (FE) in SCON register (See Table 5.) bit is set.

12 Rev. A - Mar. 19, 1999

Preliminary