TEMIC TEA1124, TEA1024 Datasheet

TEA1024/ TEA1124

Zero Voltage Switch with Fixed Ramp

Description

The monolithic integrated bipolar circuit, TEA1024/
TEA1124 is a zero voltage switch for triac control in
domestic equipments. It offers not only the control of a
triac in zero crossing mode but also the possibility of
power control. This is why the IC contains a mains

Features

D

Direct supply from the mains

D

Definite IC switching characteristics

D

Very few external components

D

Full wave drive – no dc component in the load circuit

D

Current consumption ≤ 1.5 mA

synchronized ramp generator with 640 ms (1280 ms)
duration (50 Hz). It is suitable for a typical load of 750 W
(1000 W) meeting the Flicker Standard. (values in
brackets relate to TEA1124.)

D

Simple power control

D

Integrated ramp generator

D

Reference voltage variable by external resistance

D

Pulse position optimization

D

Output short circuit protected

Block Diagram

95 10871

1

56 k

W

W

Protection

2

43 k

W

min.

100 k

max.

Ramp generator

TEA 1024 – 640 ms

TEA 1124 – 1280 ms

Comparator

+

–

NC

Package: DIP8

R

390 k

W

Sync. logic Supply

3 8

2

(R

sync

7 4

NC

MT2

MT1

L

V

=

M

230 V ~

N

D

)

1

R

1

amplifier

22 kW/

2 W

Pulse

1N4007

Load

1000 W

C

100 mF

1

16 V

6

5

R

68

TIC

236N

G

W

Figure 1. Typical block diagram – open loop power control

TELEFUNKEN Semiconductors

Rev . A1, 24-May-96

1 (8)

TEA1024/ TEA1124

Power Supply and its Limitations

The voltage limitation contained in the IC allows it to be
powered from mains via series resistance R
fying diode D
The capacitor C

between Pin 6 (+ Pol/ă) and Pin 4 (–VS).

1

smooths the supply voltage

1

and recti–

1

(see figure 1).
An internal temperature-compensated limiting circuit

protects the module from random peaks of voltage on the
mains, and delivers a defined reference voltage during the
negative half-cycle.

Synchronization

Full-Wave Logic

The full-wave logic ensures that only pairs of pulses can
be released, and that these always begin with the positive
dv/dt. The load is thus switched on for a minimum of one
complete mains cycle. This means that the triac receives
a minimum of two driving pulses, so that the unwanted
d.c. component in the load circuit is definitely eliminated.

Pulse Amplifier

The pulse amplifier connected to the output of the full­wave logic circuit, is proof against continuos
short-circuits, and delivers negative output pulses of typ.
75 mA, via an integrated limiting resistance, to Pin 5.

Ramp Generator (Figures 3, 4)

Ramp voltage which is generated in the IC is available not
only at reference Pin 1, but also at the non-inverted input
of the comparator.

The current sink which is controlled by D/A converter
influences the internal reference voltage at Pin 1 specified
by voltage divider. The current sink is turned-off in the
reset state of the D/A converter so that the voltage at Pin 1
is primarily specified via the internal voltage divider
(ramp starting voltage).

Figure 2. Pulse position optimization

The logic function is synchronized by means of a separate
resistance R

connected between Pin 7 and phase

2

(voltage-synchronization). The width of the pulse can be
varied between wide limits by choice of R

. The larger

sync

the value chosen, the wider the output pulse is on Pin 5.
Automatic optimization of the phase of the pulse is
necessary, since the latching current of the triac exceeds
the steady current by a factor of 3.

The phase of the pulse is chosen so that ca. 1/3 of the pulse
width appears before the transition through null and 2/3
after it (see electrical characteristics and figure 2).

In order to avoid phase-clipping after the switch-on the
first third of the first pulse is automatically suppressed.

In the maximum state of the 4 stage (5 stage – TEA1124)
D/A converter, the current sink overtakes the maximum
current, whereby the ramp’s final (end) voltage has
reached. External resistance R

, Ry shown in figure 4 are

x

in position to influence the initial ramp voltage as well as
the ramp amplitude. If the external resistances ratio R

is the same as that of the internal ratio, the ramp

R

y

voltage at the beginning remains maintained (constant),
only the amplitude is compressed.

t

V

1

–1.3 V

2.2 V

–3.8 V

T= 640 ms

(T= 1280 ms)

95 11410

Figure 3. Ramp diagram without external circuit

16 stage ramp

,

x

2 (8)

TELEFUNKEN Semiconductors

Rev . A1, 24-May-96

GND

R

R

–V

TEA1024/ TEA1124

2

Protection

6

50 k

1

150 k
4

W

W

Current sink

Figure 4. Principle diagram – Generation and evaluation of ramp

x

y

S

–

+

D/A converter

A

D

4 stage

ripple counter

3

2

2

2

1

2

0

2

Period
20 ms

(40 ms)

Divider

1:2

(1:4)

7

Sync (50 Hz)

95 11411

Period

1. The time required for one complete cycle of a regular.
repeating signal, function, or series of emends.

2. The tune between two consecutive transients of the
pointer or indicating means of an electrical indicating
instrument in the same disdain the rest position.
Something called periodic fine.

Comparator

The comparison of set value and measured value is
carried out via the two comparator inputs Pin 1 and Pin 2.
Here Pin 2 is the inverting input and has a circuit pro­tecting it against interference spikes. Figure 5 shows the
protective circuit of the comparator. Pin 1 is the non­inverting input.

1

6

GND

R

Z

Ramp

generator

Firing Pulse Width (Figures 6, 7)

It depends on the latching current as well as on the load
current of the used triacs.

IL

[s]

t

p

whereas I

3

+

arcsin

4pf

[A] = Latching current of the triac

L

V

[V]= Mains voltage, effective

M

P[W] = Power load
f[1/s] = Mains frequency

Firing pulse width is specified through the zero cross over
identification which can be influenced by the sync.
resistance.

V

2Ǹsin

R

[W]

sync

+

M

where

[s] = required ignition pulse width

t

p

V

Ǹ

P 2

2

ǒ

w

3

2.5 10

M

Ǔ

t

–0.6

p

–5

–1.4 10

3

T

2

Figure 5. Protective circuit of the comparator

TELEFUNKEN Semiconductors

Rev . A1, 24-May-96

+

–

95 11412

3 (8)