TEMIC e1217D User Manual
查询e1217D供应商
32 kHz Standard Watch CMOS IC
Features
D
32 kHz oscillator
D
1.3 - 1.8 V operating voltage range
D
180 nA typical current consumption
D
Voltage regulator
e1217D
D
Integrated capacitors, mask selectable
D
Mask options for pad designation, motor period and
motor pulse width
D
Low resistance outputs for bipolar stepping motor
D
Motor fast-test function
Pad Configuration
1
2
e1217D
3
4
Figure 1. Chip size 1.06 mm x 1.02 mm
Pad size: 112 mm x 112 mm (pad window 100 x 100)
8
7
6
5
95 9979
General Description
The e1217D is an integrated circuit in CMOS Silicon
Gate Technology for analog watches. It consists of a
32 kHz oscillator, frequency dividers down to 1/64 Hz,
output pulse formers and push-pull motor drivers. For
tuning of the crystal, integrated capacitors are provided
(selectable mask option). Low current consumption and
high oscillator stability are enabled by an on-chip voltage
regulator.
Pin Symbol Function
1, 4 V
5, 6, 8 V
1 to 4 OSCIN/
(7/5) or (7/6) MOT 1/2 Motor drive outputs
1 to 5, 8 RESET Reset input
1 to 5, 8 TEST T est input/output
SS
DD
OSCOUT
Absolute Maximum Ratings
Parameters Symbol Value Unit
Supply voltage V
Input voltage range, all inputs V
Output short circuit duration indefinite
Power dissipation (DIL package) P
Operating ambient temperature range T
Storage temperature range T
Lead temperature during soldering at 2 mm
distance, 10 s
T
SS
IN
tot
amb
stg
sld
(VSS–0.3 V
–0.3 to +5 V
≤ VIN≤ (VDD + 0.3 V) V
)
125 mW
–20 to +70 °C
–40 to +70 °C
260 °C
Negative supply voltage
Positive supply voltage
Oscillator input/output
Absolute maximum ratings define parameter limits
which, if exceeded, may permanently change or damage
the device.
All inputs and outputs on TEMIC circuits are protected
against electrostatic discharges. However, precautions to
TELEFUNKEN Semiconductors
Rev . A1, 08-May-96
minimize the build-up of electrostatic charges during
handling are recommended.
The circuit is protected against supply-voltage reversal
for typically 5 minutes.
1 (4)
e1217D
Functional Description
Voltage Regulator
An integrated voltage regulator provides the oscillator
with a well controlled negative supply voltage V
This improves the stability of the oscillator and keeps current consumption at a minimum.
REG
Oscillator
An oscillator inverter with feedback resistor is provided
for generation of the 32768 Hz clock frequency. A total
capacitance of 24 pF is integrated.This can be selected for
C
OSCOUT
in 2 pF increments via a mask option.
Frequency Divider
A 21 bit binary counter is provided, dividing the oscillator
frequency down to 1/64 Hz. The leading six stages are
connected to V
15 stages are connected to V
and V
DD
, while the remaining
REG
and VSS.
DD
Motor Drive Output
The e1217D contains two push-pull output buffers for
driving bipolar stepping motors. During a motor pulse,
the n-channel device of one buffer and the p-channel device of the other buffer are activated. The p-channel
devices of both buffers are active (figure 3) between two
the pulses.
RESET
A debounced RESET input is provided. Connecting the
RESET input to V
.
frequency divider, thus disabling further motor pulses.
Motor pulses in progress when the reset function is applied are completed. After releasing the RESET pad from
, the next motor pulse appears with a delay of one half
V
DD
motor cycle on the drive output opposed to the former
(figure 4). Due to the debounce circuitry on the RESET
input, V
RESET the input current is limited to 8 nA typically.
must be applied for at least 31.2 ms. During
DD
resets the low order 12 stages of the
DD
Test
A test frequency of 512 Hz is output to this pad which can
be measured with a high resistance probe (R ≥ 10 M
C ≤ 20 pF). This signal can be used for testing and tuning
the oscillator. Connecting TEST to V
changes the motor cycle time from the selected value to
the test cycle time (mask options), while the motor pulse
width remains unchanged (figure 3).
This feature can be used to reduce the amount of time required for testing the mechanical parts of the watch.
for at least 4 ms
DD
W,
Cycle time and pulse width can be chosen via a metalmask option (table 1).
Table 1. Motor options
Cycle time T
Motor pulse width t
Motor test cycle time T
M
M
MIT
= 2, 4, 6, 8, 10, 12, 20, 24, 30, 40, 60, 80, 120 s
= 0.98 to 14.65 ms in increments of 0.98 ms
= 250, 125, 62.5 ms
2 (4)
TELEFUNKEN Semiconductors
Rev . A1, 08-May-96
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