Mod. 0805 2017-01 Rev.6
WL865E4-P
HW User Guide
1VV0301580 Rev. 1 – 2019-04-02
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SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE
NOTICE
While reasonable efforts have been made to assure the accuracy of this document, Telit
assumes no liability resulting from any inaccuracies or omissions in this document, or from
use of the information obtained herein. The information in this document has been carefully
checked and is believed to be reliable. However, no responsibility is assumed for
inaccuracies or omissions. Telit reserves the right to make changes to any products
described herein and reserves the right to revise this document and to make changes from
time to time in content hereof with no obligation to notify any person of revisions or changes.
Telit does not assume any liability arising out of the application or use of any product,
software, or circuit described herein; neither does it convey license under its patent rights
or the rights of others.
It is possible that this publication may contain references to, or information about Telit
products (machines and programs), programming, or services that are not announced in
your country. Such references or information must not be construed to mean that Telit
intends to announce such Telit products, programming, or services in your country.
COPYRIGHTS
This instruction manual and the Telit products described in this instruction manual may be,
include or describe copyrighted Telit material, such as computer programs stored in
semiconductor memories or other media. Laws in the Italy and other countries preserve for
Telit and its licensors certain exclusive rights for copyrighted material, including the
exclusive right to copy, reproduce in any form, distribute and make derivative works of the
copyrighted material. Accordingly, any copyrighted material of Telit and its licensors
contained herein or in the Telit products described in this instruction manual may not be
copied, reproduced, distributed, merged or modified in any manner without the express
written permission of Telit. Furthermore, the purchase of Telit products shall not be deemed
to grant either directly or by implication, estoppel, or otherwise, any license under the
copyrights, patents or patent applications of Telit, as arises by operation of law in the sale
of a product.
COMPUTER SOFTWARE COPYRIGHTS
The Telit and 3rd Party supplied Software (SW) products described in this instruction
manual may include copyrighted Telit and other 3rd Party supplied computer programs
stored in semiconductor memories or other media. Laws in the Italy and other countries
preserve for Telit and other 3rd Party supplied SW certain exclusive rights for copyrighted
computer programs, including the exclusive right to copy or reproduce in any form the
copyrighted computer program. Accordingly, any copyrighted Telit or other 3rd Party
supplied SW computer programs contained in the Telit products described in this instruction
manual may not be copied (reverse engineered) or reproduced in any manner without the
express written permission of Telit or the 3rd Party SW supplier. Furthermore, the purchase
of Telit products shall not be deemed to grant either directly or by implication, estoppel, or
otherwise, any license under the copyrights, patents or patent applications of Telit or other
3rd Party supplied SW, except for the normal non-exclusive, royalty free license to use that
arises by operation of law in the sale of a product.
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USAGE AND DISCLOSURE RESTRICTIONS
I. License Agreements
The software described in this document is the property of Telit and its licensors. It is
furnished by express license agreement only and may be used only in accordance with the
terms of such an agreement.
II. Copyrighted Materials
Software and documentation are copyrighted materials. Making unauthorized copies is
prohibited by law. No part of the software or documentation may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language or
computer language, in any form or by any means, without prior written permission of Telit
III. High Risk Materials
Components, units, or third-party products used in the product described herein are NOT
fault-tolerant and are NOT designed, manufactured, or intended for use as on-line control
equipment in the following hazardous environments requiring fail-safe controls: the
operation of Nuclear Facilities, Aircraft Navigation or Aircraft Communication Systems, Air
Traffic Control, Life Support, or Weapons Systems (High Risk Activities"). Telit and its
supplier(s) specifically disclaim any expressed or implied warranty of fitness for such High
Risk Activities.
IV. Trademarks
TELIT and the Stylized T Logo are registered in Trademark Office. All other product or
service names are the property of their respective owners.
V. Third Party Rights
The software may include Third Party Right software. In this case you agree to comply with
all terms and conditions imposed on you in respect of such separate software. In addition
to Third Party Terms, the disclaimer of warranty and limitation of liability provisions in this
License shall apply to the Third Party Right software.
TELIT HEREBY DISCLAIMS ANY AND ALL WARRANTIES EXPRESS OR IMPLIED
FROM ANY THIRD PARTIES REGARDING ANY SEPARATE FILES, ANY THIRD PARTY
MATERIALS INCLUDED IN THE SOFTWARE, ANY THIRD PARTY MATERIALS FROM
WHICH THE SOFTWARE IS DERIVED (COLLECTIVELY “OTHER CODE”), AND THE
USE OF ANY OR ALL THE OTHER CODE IN CONNECTION WITH THE SOFTWARE,
INCLUDING (WITHOUT LIMITATION) ANY WARRANTIES OF SATISFACTORY
QUALITY OR FITNESS FOR A PARTICULAR PURPOSE.
NO THIRD PARTY LICENSORS OF OTHER CODE SHALL HAVE ANY LIABILITY FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED
AND WHETHER MADE UNDER CONTRACT, TORT OR OTHER LEGAL THEORY,
ARISING IN ANY WAY OUT OF THE USE OR DISTRIBUTION OF THE OTHER CODE
OR THE EXERCISE OF ANY RIGHTS GRANTED UNDER EITHER OR BOTH THIS
LICENSE AND THE LEGAL TERMS APPLICABLE TO ANY SEPARATE FILES, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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APPLICABILITY TABLE (REMOVE UNUSED)
PRODUCTS
WL865E4-P
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Contents
NOTICE 2
COPYRIGHTS ................................................................................................ 2
COMPUTER SOFTWARE COPYRIGHTS ...................................................... 2
USAGE AND DISCLOSURE RESTRICTIONS ............................................... 3
APPLICABILITY TABLE (REMOVE UNUSED) ............................................. 4
CONTENTS .................................................................................................... 5
1. INTRODUCTION .......................................................................... 8
Scope ................................................................ ........................... 8
Audience....................................................................................... 8
Contact Information, Support ........................................................ 8
Text Conventions .......................................................................... 9
Related Documents .................................................................... 10
2. OVERVIEW ................................................................................ 11
3. PINS ALLOCATION ................................................................... 13
Pin-out ........................................................................................ 13
Pads Layout ................................................................................ 17
4. POWER SUPPLY ....................................................................... 18
Power Supply Requirements ....................................................... 18
Power Consumption ................................................................... 18
General Design Rules ................................ ................................. 20
5. DIGITAL SECTION .................................................................... 21
Logic Levels ................................................................................ 21
Power Up/Down Sequence ......................................................... 22
5.2.1. Power-on reset timing ................................................................. 22
Unconditional Shutdown ............................................................. 22
Communication ports .................................................................. 22
5.4.1. High Speed UART ...................................................................... 22
5.4.2. Low Speed UART ................................................................ ....... 23
5.4.3. SDIO ........................................................................................... 23
5.4.4. SPI.............................................................................................. 24
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5.4.5. I2C .............................................................................................. 24
5.4.6. USB ............................................................................................ 24
General purpose I/O ................................................................... 24
ADC / DAC Converter ................................................................. 25
Special Functions ....................................................................... 26
General Digital Interface Recommendations ............................... 26
6. RF SECTION .............................................................................. 27
Bands Variants ........................................................................... 27
6.1.1. WIFI ............................................................................................ 27
6.1.2. BlueTooth ................................................................................... 27
TX Output power ......................................................................... 28
6.2.1. WIFI ............................................................................................ 28
6.2.1.1. 2.4 GHz ...................................................................................... 28
6.2.1.2. 5 GHz ................................................................ ......................... 29
6.2.2. BlueTooth ................................................................................... 30
RX Sensitivity ............................................................................. 30
6.3.1. WIFI ............................................................................................ 30
6.3.1.1. 2.4 GHz ...................................................................................... 30
6.3.1.2. 5 GHz ................................................................ ......................... 31
6.3.2. BlueTooth ................................................................................... 32
WIFI Antenna requirements ........................................................ 32
BlueTooth Antenna requirements ............................................... 32
PCB Design Guidelines .............................................................. 33
6.6.1. PCB General Guidelines ............................................................. 33
6.6.2. RF PCB Guidelines ..................................................................... 34
6.6.3. PCB Guidelines in case of FCC Certification .............................. 36
7. AUDIO SECTION ....................................................................... 37
Electrical Characteristics ............................................................. 37
Codec examples ......................................................................... 37
8. MECHANICAL DESIGN ............................................................. 38
Drawing ...................................................................................... 38
9. APPLICATION PCB DESIGN .................................................... 40
Footprint ..................................................................................... 40
PCB pad design .......................................................................... 40
PCB pad dimensions ................................................................ .. 41
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Stencil ......................................................................................... 41
Solder paste ............................................................................... 41
Solder Reflow ............................................................................. 42
10. PACKAGING ................................................................ .............. 44
Tray ............................................................................................ 44
Moisture sensitivity ..................................................................... 45
11. CONFORMITY ASSESSMENT ISSUES .................................... 46
FCC/IC Regulatory notices ......................................................... 46
12. SAFETY RECOMMENDATIONS................................................ 47
READ CAREFULLY .................................................................... 47
13. ACRONYMS ............................................................................... 48
14. DOCUMENT HISTORY .............................................................. 50
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1. INTRODUCTION
Scope
The aim of this document is the description of some hardware solutions useful for
developing a product with the Telit WL865E4-P module.
Audience
This document is intended for Telit customers, who are integrators, about to implement their
applications using our WL865E4-P modules.
Contact Information, Support
For general contact, technical support services, technical questions and report
documentation errors contact Telit Technical Support at:
• TS-EMEA@telit.com
• TS-AMERICAS@telit.com
• TS-APAC@telit.com
• TS-SRD@telit.com
Alternatively, use:
http://www.telit.com/support
For detailed information about where you can buy the Telit modules or for recommendations
on accessories and components visit:
http://www.telit.com
Our aim is to make this guide as helpful as possible. Keep us informed of your comments
and suggestions for improvements.
Telit appreciates feedback from the users of our information.
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Text Conventions
Danger – This information MUST be followed or catastrophic
equipment failure or bodily injury may occur.
Caution or Warning – Alerts the user to important points about
integrating the module, if these points are not followed, the module and
end user equipment may fail or malfunction.
Tip or Information – Provides advice and suggestions that may be
useful when integrating the module.
All dates are in ISO 8601 format, i.e. 2019-01-08.
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Related Documents
WL865E4-P AT Command Reference Guide
WL865E4-P EVB USER GUIDE
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WL865E4
2. OVERVIEW
The aim of this document is the description of some hardware solutions useful for
developing a product with the Telit WL865E4-P module.
Obviously this document cannot embrace the whole hardware solutions and products that
may be designed. The wrong solutions to be avoided shall be considered as mandatory,
while the suggested hardware configurations shall not be considered mandatory, instead
the information given shall be used as a guide and a starting point for properly developing
your product with the Telit WL865E4-P module. For further hardware details that may not
be explained in this document refer to the Telit WL865E4-P Product Description document
where all the hardware information is reported.
NOTE:
(EN) The integration of the WL865E4-P module within user application
shall be done according to the design rules described in this manual.
(IT) L’integrazione del modulo WL865E4-P all’interno dell’applicazione
dell’utente dovrà rispettare le indicazioni progettuali descritte in questo
manuale.
(DE) Die Integration des WL865E4-P Moduls in ein Gerät muß gemäß
der in diesem Dokument beschriebenen Kunstruktionsregeln erfolgen.
(SL) Integracija WL865E4-P modula v uporabniški aplikaciji bo morala
upoštevati projektna navodila, opisana v tem priročniku.
(SP) La utilización del modulo WL865E4-P debe ser conforme a los
usos para los cuales ha sido deseñado descritos en este manual del
usuario.
(FR) L’intégration du module WL865E4-P dans l’application de
l’utilisateur sera faite selon les règles de conception décrites dans ce
manuel.
(HE)
The information presented in this document is believed to be accurate and reliable.
However, no responsibility is assumed by Telit Communications S.p.A. for its use, nor any
infringement of patents or other rights of third parties which may result from its use. No
WL865E4-P Module Hardware User Guide
1VV0301580 Rev. 1 Page 12 of 52 2019-04-02
license is granted by implication or otherwise under any patent rights of Telit
Communications S.p.A. other than for circuitry embodied in Telit products. This document
is subject to change without notice.
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3. PINS ALLOCATION
Pin-out
The pin out table is shown below, the pins have been grouped for functional areas
Pin
Signal
I/O
Function
Type
Comment
USB HS 2.0 COMMUNICATION PORT
12
VUSB
I
Power Supply for
the internal USB
transceiver.
POWER
VDD_BLE
13
USB_D-
I/O
USB differential
Data -
Used only for
programming/testing
14
USB_D+
I/O
USB differential
Data +
Used only for
programming/testing
High Speed Asynchronous Serial Port (HS-UART0)
23
UART0_CTS
I
Input
VDD_VIO
Max baud rate 3 Mbps
24
UART0_RTS
O
Output
VDD_VIO
Max baud rate 3 Mbps
25
UART0_RXD
I
Serial data input
VDD_VIO
Max baud rate 3 Mbps
26
UART0_TXD
O
Serial data
output
VDD_VIO
Max baud rate 3 Mbps
Low Speed Asynchronous Serial Port (UART1)
27
UART1_RXD
I
Serial data input
VDD_VIO
Max baud rate 115200
bps
28
UART1_TXD
O
Serial data
output
VDD_VIO
Max baud rate 115200
bps
Serial Peripheral Interface (SPI)
53
GPIO_11/SPI_M_CS
I/O
General Purpose
Input/Output
VDD_VIO
SPI Chip Select
(Master) (Active LOW)
54
GPIO_12/SPI_M_CLK
I/O
General Purpose
Input/Output
VDD_VIO
SPI Clock (Master)
55
GPIO_14/SPI_M_MISO
I/O
General Purpose
Input/Output
VDD_VIO
SPI MISO (Master)
56
GPIO_13/SPI_M_MOSI
I/O
General Purpose
Input/Output
VDD_VIO
SPI MOSI (Master)
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Secure Digital Input Output (SDIO)
46
SDIO_CLK/SPI_S_CLK
I/O
SDIO card CLK
signal
VDD_VIO
Slave SPI_S_CLK
(PWM)
47
SDIO_CMD/SPI_S_CS
I/O
SDIO card
Command signal
VDD_VIO
Slave SPI_S_CS
(Active LOW) (PWM)
48
SDIO_D3/SPI_S_MOSI
I/O
SDIO card
DAT[3] signal
VDD_VIO
Slave SPI_S_MOSI
(PWM)
49
SDIO_D2/USB_BOOT
I/O
SDIO card
DAT[2] signal
VDD_VIO
USB BOOT Mode
(Active HIGH) (PWM)
50
SDIO_D1
I/O
SDIO card
DAT[1] signal
VDD_VIO
(PWM)
51
SDIO_D0/SPI_S_MISO
I/O
SDIO card
DAT[0] signal
VDD_VIO
Slave SPI_S_MISO
(PWM)
Inter-Integrated Circuit Interface (I2C)
21
GPIO_06/I2C_SDA
I/O
Data
VDD_VIO
I2C Data (Master)
22
GPIO_07/I2C_SCL
I/O
Clock
VDD_VIO
I2C Clock (Master)
Analog Interface (ADC)
3
GPIO_17/ADC_IN3
I/O
12 BITS 1MHz
VDD_VIO
In ADC mode
VDD_VIO must be
1V8 only
4
GPIO_16/ADC_IN2
I/O
12 BITS 1MHz
VDD_VIO
In ADC mode
VDD_VIO must be
1V8 only
5
GPIO_15/ADC_IN1
I/O 12 BITS 1MHz
VDD_VIO
In ADC mode
VDD_VIO must be
1V8 only
Digital Audio Interface (I2S) Master/Slave
17
I2S_SYNC
I/O
I2S - Frame
Sync or LR
Clock
VDD_VIO
18
I2S_SCK
I/O
I2S - Bit Clock
VDD_VIO
19
I2S_SDO
I/O
I2S - Data
Ouput
VDD_VIO
20
I2S_SDI
I/O
I2S - Data Input
VDD_VIO
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Miscellaneous Fuctions
1
RESET#
I
Hardware
RESET / Power
Disable
VDD_VIO
Active LOW
2
GPIO_02/BT_PRIORITY
I/O
GENERIC IO
VDD_VIO
BT_PRIORITY
15
GPIO_05/DAC_OUT
I/O
GENERIC IO
VDD_VIO
DAC_OUT1
16
GPIO_08/LF_CLK_IN
I/O
GENERIC IO
VDD_VIO
External 32 kHz Clock
Input or floating if not
used.
33
GPIO_03/ WIFI_ACTIVE
I/O
GENERIC IO
VDD_VIO
WIFI_ACTIVE
34
GPIO_04/BT_ACTIVE
I/O
GENERIC IO
VDD_VIO
BT_ACTIVE
43
GPIO_01/WAKEUP
I/O
GENERIC IO
VDD_VIO
WAKEUP
44
GPIO_09/WoW
I/O
GENERIC IO
VDD_VIO
Wake on Wireless
LAN (WoW) (OD)
(PWM)
45
GPIO_10/SW_RESET
I/O
General Purpose
Input/Output
VDD_VIO
Can be
reprogrammed
Input Software
RESET
WPS
Output Watchdog,
etc.Output Watchdog
RF Pads
37
ANT_BLE
I/O
BT 2.4 GHz
RF
50 Ω
40
ANT_WIFI
I/O
WIFI 2.4 GHz
WIFI 5 GHz
RF
50 Ω
Power Supply
6
VDD_WLAN
I
WIFI main power
supply
Power
(3.0 V to 3.6 V)
3.3 V Nominal Power
Supply
9
VDD_VIO
I
Digital
Input/Output
power supply
Power
(1.8 V to 3.6 V)
3.3 V Nominal Power
Supply
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Power Supply (cont…)
11
VDD_BLE
I
Bluetooth main
power supply
Power
(3.0 V to 3.6 V)
3.3 V Nominal Power
Supply
7
GND
-
Ground
Power
10
GND
-
Ground
Power
35
GND
-
Ground
Power
36
GND
-
Ground
Power
38
GND
-
Ground
Power
39
GND
-
Ground
Power
41
GND
-
Ground
Power
42
GND
-
Ground
Power
52
GND
-
Ground
Power
57
GND
-
Ground
Power
58
GND
-
Ground
Power
Table 3 1: WL865E4-P Pinout Table
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Pads Layout
The Figure 3-1 shows the pads layout configuration for the module (top view)
Figure 3-1: Top View Pad Layout
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4. POWER SUPPLY
Power Supply Requirements
Power Supply
Minimum
Typical
Maximum
Absolute Maximum to avoid permanent
damage. At any power supply pin.
-0.3 V
4.0 V
Recommended VDD_BLE, VDD_WLAN,
USB_VDD
3.14 V
3.3 V
3.46 V
Recommended VDD_VIO (see notes)
3.14 V
or
1.71 V
3.3 V
or
1.8 V
3.46 V
or
1.89 V
Table 4-1: Wl865E4-P power supply requirements
Note: The ADC can be used only if VDD_VIO is equal to 1V8.
Power Consumption
Power Consumption
Typical
POWER DOWN
RESET# Low
TBD µA
SUSPEND
TBD µA
HOST OFF
TBD µA
SLEEP
TBD µA
ON, Radio OFF
TBD mA
BLE RX
TBD µA
BLE TX
TBD µA
WIFI RX 2G4
TBD µA
WIFI RX 5G
TBD µA
DTIM=1
TBD µA
DTIM=3
TBD µA
DTIM=5
TBD µA
DTIM=10
TBD µA
Table 4-2: WL865E4-P general power consumption table
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Power Consumption vs TX power at 2.4 GHz
WIFI 2G4 / CH 6
Standard 802.11x
Modulation
Data rates
(Mbps)
RF Output
(dBm)
Current
@3.3V
Unit
b
BPSK
1 Mbps
19
339
mA b QPSK
2 Mbps
19
342
mA
b
CCK
5.5 Mbps
19
327
mA
b
CCK
11 Mbps
19
326
mA g BPSK
6 Mbps
19
332
mA g BPSK
9 Mbps
19
330
mA g QPSK
12 Mbps
19
326
mA
g
QPSK
18 Mbps
18
294
mA
g
16 QAM
24 Mbps
18
286
mA g 16 QAM
36 Mbps
18
276
mA g 64 QAM
48 Mbps
18
266
mA
g
64 QAM
54 Mbps
18
237
mA
n
BPSK
MCS0_20
19
320
mA n QPSK
MCS1_20
19
324
mA n QPSK
MCS2_20
19
309
mA n 16 QAM
MCS3_20
18
285
mA
n
16 QAM
MCS4_20
18
277
mA
n
64 QAM
MCS5_20
17
252
mA n 64 QAM
MCS6_20
17
232
mA n 64 QAM
MCS7_20
17
224
mA
Table 4-3: WL865E4-P TX Table consumption @ 2.4 GHz
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Power Consumption vs TX power at 5 GHz
WIFI 5G / CH 100
Standard 802.11x
Modulation
Data rates
RF Output
(dBm)
Current
@3.3V
Unit
a
BPSK
6 Mbps
16
272
mA a BPSK
9 Mbps
16
269
mA
a
QPSK
12 Mbps
16
269
mA
a
QPSK
18 Mbps
16
267
mA a 16 QAM
24 Mbps
16
269
mA a 16 QAM
36 Mbps
14
230
mA a 64 QAM
48 Mbps
13
218
mA
a
64 QAM
54 Mbps
13
216
mA
n
BPSK
MCS0_20
16
271
mA n QPSK
MCS1_20
16
267
mA n QPSK
MCS2_20
15
253
mA
n
16 QAM
MCS3_20
15
250
mA
n
16 QAM
MCS4_20
14
230
mA n 64 QAM
MCS5_20
14
227
mA n 64 QAM
MCS6_20
13
219
mA n 64 QAM
MCS7_20
13
218
mA
Table 4-4: WL865E4-P TX Table consumption @5GHz
General Design Rules
It is recommended to make provision of at least 10 µF capacitors right next to the
VDD_WLAN and VDD_BLE pins, and 2.2 µF at each of the other power supply pins like
VDD_VIO and VUSB.
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5. DIGITAL SECTION
Logic Levels
Parameter
Min
Max
Input level on any digital pin
-0.3 V
VDD_VIO + 0.3 V
Levels with VDD_VIO = 3.3V
Min
Max
VIH Input high level
2.4 V
3.6 V
VIL Input low level
-0.3 V
0.3 V
VOH Output high level
3.0 V
3.6 V
VOL Output low level
-0.3 V
0.4 V
Levels with VDD_VIO = 3.3V
Typical
IIH Input current
60 µA (Rod is ON)
0.1 µA (Rpd is OFF)
IIL Input current
60 µA (Rod is ON)
0.1 µA (Rpd is OFF)
IOH Output current
5 mA (x4 drive strength)
3.3 mA (x2 drive strength)
2.6 mA (x1 drive strength)
IOL Output current
5 mA (x4 drive strength)
3.3 mA (x2 drive strength)
2.6 mA (x1 drive strength)
Table 5-1: WL865E4-P IO levels
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Power Up/Down Sequence
All Power supplies should be stable for a minimum of 10 µs before RESET# is de-asserted
(that is, is greater than VIL for VDD_VIO). If VDD_VIO = 3.3 V, then VDD_BLE,
VDD_WLAN, and VDD_VIO can share same 3.3 V power.
5.2.1. Power-on reset timing
Figure 5-1: WL865E4-P Power on RESET
Parameter
Description
Min
Max
Unit
TR
Rise time of the power to 90% of final voltage
N/A
25
ms
TS
Minimum time before RESET# is de-asserted
10
N/A
µs
Table 5-2: WL865E4-P Power on Reset Table
Unconditional Shutdown
The RESET# is used for unconditional Hardware RESET.
Connect to the RESET# pin a PU resistor of 10 kΩ to VDD_VIO.
We suggest controlling the RESET# pin in Open Drain configuration.
Communication ports
5.4.1. High Speed UART
A High-speed Universal Asynchronous Receiver/Transmitter (HS-UART0) interfaces with
HW Flow Control, may be configured to serve as either a host interface link or a debug
message console.
By Default HW Flow Control is disable.
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Property
High Speed UART Configuration
Baud rate
115200 bps, no auto-baud rate detection, can be changed by the
host up to 3 Mbps using a special command
Data bits
8 bits
Flow control
CTS/RTS
Parity
None
Stop bits
1
Bit order
LSBit first
Table 5-3: High Speed UART0 Configuration
5.4.2. Low Speed UART
Low-speed Universal Asynchronous Receiver/Transmitter (UART1) interface, which is
configured to serve as a debug port
Property
Low Speed UART Configuration
Baud rate
Up to 115200 bps, no auto-baud rate detection, debug port
Data bits
8 bits
Flow control
None
Parity
None
Stop bits
1
Bit order
LSBit first
Table 5-4: Low Speed UART1 Configuration
5.4.3. SDIO
One SDIO Master/Slave interface:
• Compliant to SDIO v2.0 specification
• Interface clock frequency up to 48 MHz
• Data transfer modes: 4-bit SDIO, 1-bit SDIO, SPI
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5.4.4. SPI
Two general-purpose SPI interfaces. One is configured as dedicated master and one
configured as master or slave pin-mux with SDIO interface pins.
• Interface clock frequency up to 48 MHz
5.4.5. I2C
The I2C Master/Salve interface has weak internal pull-up. If necessary add external ones
of 10 kΩ down to 1 kΩ.
5.4.6. USB
USB 2.0 device interface provides a simplified, high-speed, and scalable manufacturing test
and configuration interface for QCA4020-based systems.
This port is intended only to program the module from scratch or when firmware corrupts,
and it is not intended for normal operation.
VUSB is only 3V3. You can directly connect it to VDD_BLE. The USB plug/unplug detection
is done through the data pins. When USB data is not sensed, the VUSB is internally
disconnected.
General purpose I/O
There are 21 GPIO which are Input / Output configurable pins.
Many can be reprogrammable to have an Alternate Function which are also described here.
GPIO
Alternate Function
Direction
GPIO_01
WAKEUP
Input
GPIO_02
BT_PRIORITY
3 wire PTA, INPUT when slave, OUTPUT when master
Input/Output
GPIO_03
WIFI_ACTIVE
3 wire PTA, OUTPUT when slave, INPUT when master
Input/Output
GPIO_04
BT_ACTIVE
3 wire PTA, INPUT when slave, OUTPUT when master
Input/Output
GPIO_05
DAC_OUT (Digital to Analog Converter)
Output
GPIO_06
I2C_SDA
Input/Output
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GPIO
Alternate Function
Direction
GPIO_07
I2C_SCL
Output
GPIO_08
LF_CLK_IN from an external 32KHz for Low Power Accurancy
Input
GPIO_09
WoW (Wakeup On Wireless)
Input
GPIO_10
SW_RESET , WPS, WHATCH-DOG
Input/Output
GPIO_11
SPI_MASTER_CS
Output
GPIO_12
SPI_MASTER_CLK
Output
GPIO_13
SPI_MASTER_MISO
Input
GPIO_14
SPI_MASTER_MOSI
Output
GPIO_15
ADC_IN1 (Analog to Digital Converter) (VDD_VIO=1V8)
Input
GPIO_16
ADC_IN2 (Analog to Digital Converter) (VDD_VIO=1V8)
Input
GPIO_17
ADC_IN3 (Analog to Digital Converter) (VDD_VIO=1V8)
Input
GPIO_18
JTAG_TCK
Output
GPIO_19
JTAG_TDO
Output
GPIO_20
JTAG_TMS
Output
GPIO_21
JTAG_TDI
Input
Table 5-5: WL865E4-P GPIO Alternate Function
ADC / DAC Converter
GPIO_15, GPIO_16 and GPIO_17 can be reprogrammed to be ADC if VDD_VIO is
powered with 1.8V. Main ADC characteristic are:
• 12-bit ADC up to 1 Msps
• Alternatively 1 differential input, -1.75 V to +1.75 V, common mode 0.875 V.
GPIO_05 can be a DAC_OUT use as output for PWM control and low current variable DC
voltage source.
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Special Functions
Any GPIO can do Interrupt Function and some can be reprogrammed to have dedicated
functions for WIFI and BLE, this are:
• WAKEUP (GPIO_01), input used to wakeup the Processor from Sleep mode.
WL865E4-P has a 3 wire PTA coexistence algorithm between WIFI and BLE.
Packet Traffic Arbiter (PTA) is a dedicated hardware System-on-Chip (SoC) block that
controls access of Wi-Fi and Bluetooth devices to the antenna. It does this through preprogrammed priority of packet transmissions and receptions, controlled through hardware
signaling.
• BT_PRIORITY (GPIO_02), INPUT when slave, OUTPUT when master
• WIFI_ACTIVE (GPIO_03), OUTPUT when slave, INPUT when master
BT_ACTIVE (GPIO_04), INPUT when slave, OUTPUT when master
General Digital Interface Recommendations
If components interfacing Telit component’s digital signals have levels higher than modem’s
I/O interface voltage, then a voltage translator must be used.
Using voltage translator component in your design makes the system ready for working at
full VDD_VIO voltage range, 1V8 to 3V3.
The use of resistor divider and/or emitter follower, as voltage translators, even if not totally
wrong, does not protect the modem against latch-up in case of power-off and furthermore
you cannot guarantee a constant voltage on the divider net.
The use of comparators as voltage shifter in principle are correct but they are less immune
to RF and dependent on a constant VBATT value without ripple.
The use of open collector buffers or bidirectional voltage level translators with unidirectional
signals is in principle correct but they are less immune to RF and dependent on PullUp/Down that could be present at any side of the voltage translator; some have different
power range for both Vcca and Vccb, in some cases you must guarantee Vcca < Vccb, and
their OE should be powered only from Vcca signal. We prefer unidirectional level shifters; if
you anyway decide for bidirectional buffers, then those designed for PU/PD like TXS, NXS,
FXLA and NVT200x are preferable, they work better if strong PU/PD are internally present
like in some of our modems.
We strongly suggest using a dual supply buffer component for unidirectional signals like
UART. Example of this are SN74AVC2T245, SN74AVC4T774 or SN74LVC2T45, for 5 V
signals. They are more immune to RF and are independent on Pull-Up or Pull-Down that
could be present at any side of the voltage translator. Place 33 pF on both power supplies.
The Power bank side connected to the modem should be powered with same VDD_VIO to
prevent latch-up from happening.
When using level shifters, for better testability, prefer the use of those having OE pins. Test
pointing the “EN” lines of the level shifts, along with the addition of the 10 kΩ resistor to
GND or VCC, depending on level shifter used. This will create access points that put shifts
in tristate and can be conveniently used for testing and firmware updates originating from
external serial ports such as PC if needed.
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6. RF SECTION
Bands Variants
6.1.1. WIFI
Supported Frequency Bands
Technology
Frequency Range (GHz)
Channel spacing (MHz)
WIFI 2.4 GHz
2.412 ≤ Fc ≤ 2.484
5
WIFI 5 GHz
5.000 ≤ Fc ≤ 5.925
5
Table 6-1: WL865E4-P supported Frequency Bands for WIFI
6.1.2. BlueTooth
Technology
Frequency Range (GHz)
Channel Number (k)
BLE 5
2.4 ≤ F ≤ 2.4835
Fc=2402 + k × 2 MHz,
where k = 0, ..., 39.
Table 6-2: WL865E4-P supported Frequency Bands for BLE
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TX Output power
6.2.1. WIFI
6.2.1.1. 2.4 GHz
WIFI 2G4 Transmit power with IEEE 802.11 EVM and spectral mask compliance at RF
output Pad at 25 °C
WIFI 2G4 / CH 6
Standard 802.11x
Modulation
Data rates
RF Output
(dBm)
EVM
(dB)
IEEE EVM
(dB)
b
BPSK
1 Mbps
19
-30,4
-14
b
QPSK
2 Mbps
19
-25,6
-14 b CCK
5.5 Mbps
19
-27,5
-14 b CCK
11 Mbps
19
-26,5
-14 g BPSK
6 Mbps
19
-17.0
-5
g
BPSK
9 Mbps
19
-16,9
-8
g
QPSK
12 Mbps
19
-16,5
-10
g
QPSK
18 Mbps
18
-17,4
-13
g
16 QAM
24 Mbps
18
-22,6
-16
g
16 QAM
36 Mbps
18
-21,9
-19
g
64 QAM
48 Mbps
18
-22,8
-22 g 64 QAM
54 Mbps
18
-26,7
-25 n BPSK
MCS0_20
19
-16,5
-5 n QPSK
MCS1_20
19
-15,6
-10
n
QPSK
MCS2_20
19
-16.0
-13
n
16 QAM
MCS3_20
18
-21,4
-16 n 16 QAM
MCS4_20
18
-21,5
-19 n 64 QAM
MCS5_20
17
-23,8
-22
n
64 QAM
MCS6_20
17
-27.0
-25
n
64 QAM
MCS7_20
17
-28,6
-27
Table 6-3: WL865E4-P IEEE 802.11 EVM @2.4GHz
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6.2.1.2. 5 GHz
WIFI 5G Transmit power with IEEE 802.11 EVM and spectral mask compliance at RF output
Pad at 25 °C
WIFI 5G / CH 100
Standard 802.11x
Modulation
Data rates
RF Output
(dBm)
EVM
(dB)
IEEE limit
(dB)
a
BPSK
6 Mbps
16
-18.4
-5
a
BPSK
9 Mbps
16
-18.5
-8
a
QPSK
12 Mbps
16
-17.9
-10
a
QPSK
18 Mbps
16
-18.0
-13 a 16 QAM
24 Mbps
16
-22.8
-16 a 16 QAM
36 Mbps
14
-29.8
-19
a
64 QAM
48 Mbps
13
-31.7
-22
a
64 QAM
54 Mbps
13
-31.8
-25 n BPSK
MCS0_20
16
-17.5
-5 n QPSK
MCS1_20
16
-17.0
-10
n
QPSK
MCS2_20
15
-17.6
-13
n
16 QAM
MCS3_20
15
-25.2
-16 n 16 QAM
MCS4_20
14
-28.7
-19 n 64 QAM
MCS5_20
14
-28.6
-22 n 64 QAM
MCS6_20
13
-30.3
-25
n
64 QAM
MCS7_20
13
-30.5
-27
Table 6-4: WL865E4-P IEEE 802.11 EVM @5GHz
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6.2.2. BlueTooth
BLE Transmit power with at RF output Pad at 25 °C
Packet Type
Channel Number
Output Power (dBm)
LE 1M
1
2.1
LE 2M
1
2.1
Table 6-5: WL865E4-P BLE transmit power
RX Sensitivity
6.3.1. WIFI
6.3.1.1. 2.4 GHz
WIFI 2G4 RX Sensibility Tested at RF output Pad at 25 °C
WIFI 2G4 / CH 6
Standard 802.11x
Modulation
Data rates
Sensibilty
(dBm)
IEEE limit
(dB)
b
BPSK
1 Mbps
-96.5
-80
b
QPSK
2 Mbps
-94.1
-80
b
CCK
5.5 Mbps
-93.7
-76 b CCK
11 Mbps
-90.0
-76 g BPSK
6 Mbps
-94.4
-82
g
BPSK
9 Mbps
-93.0
-81
g
QPSK
12 Mbps
-92.1
-79 g QPSK
18 Mbps
-89.2
-77 g 16 QAM
24 Mbps
-86.3
-74 g 16 QAM
36 Mbps
-82.8
-70
g
64 QAM
48 Mbps
-78.8
-66
g
64 QAM
54 Mbps
-77.2
-65 n BPSK
MCS0_20
-94.3
-82 n QPSK
MCS1_20
-91.4
-79
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n
QPSK
MCS2_20
-89.0
-77
n
16 QAM
MCS3_20
-85.0
-74 n 16 QAM
MCS4_20
-81.5
-70 n 64 QAM
MCS5_20
-77.2
-66 n 64 QAM
MCS6_20
-75.4
-65
n
64 QAM
MCS7_20
-73.8
-64
Table 6-6: WL865E4-P Sensitivity @2.4GHz
6.3.1.2. 5 GHz
WIFI 5G RX Sensibility Tested at RF output Pad at 25 °C
WIFI 5G / CH 100
Standard 802.11x
Modulation
Data rates
Sensibilty
(dBm)
IEEE limit
(dBm)
a
BPSK
6 Mbps
-95.4
-82
a
BPSK
9 Mbps
-94.1
-81 a QPSK
12 Mbps
-93.0
-79 a QPSK
18 Mbps
-90.6
-77 a 16 QAM
24 Mbps
-87.1
-74
a
16 QAM
36 Mbps
-84.0
-70
a
64 QAM
48 Mbps
-80.0
-66 a 64 QAM
54 Mbps
-78.2
-65 n BPSK
MCS0_20
-95.2
-82
n
QPSK
MCS1_20
-92.5
-79
n
QPSK
MCS2_20
-90.2
-77 n 16 QAM
MCS3_20
-85.6
-74 n 16 QAM
MCS4_20
-82.5
-70 n 64 QAM
MCS5_20
-78.2
-66
n
64 QAM
MCS6_20
-76.6
-65
n
64 QAM
MCS7_20
-75.1
-64
Table 6-7: WL865E4-P Sensitivity @5GHz
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6.3.2. BlueTooth
RX Sensisbilty Tested at RF output Pad at 25 °C
Packet Type
Channel Number
RX sensibility (dBm)
LE 1M
1
-97.1
LE 2M
1
-94.3
Table 6-8: WL865E4-P Sensitivity at RF Output
WIFI Antenna requirements
Special care must be taken during the design of the RF section on the application board.
RF performance degradation, and infringements of emission limits,
may arise if the following recommendations are not respected.
A 50Ω antenna is required. Telit’s WL865E4-P interface features an SMA connector for an
external antenna, but other antenna integrated choices are possible, such as a chip or a
printed one. In case an integrated antenna is used, it is recommended to place it at the edge
of the application board.
Since it may be necessary to tune the antenna impedance to 50 Ω, it is recommended to
foresee a PI matching network between the WL865E4-P and the antenna, at least during
first prototyping: if not required, a series 0 Ω resistor can be used, leaving the two shunt
components unpopulated.
In order to be able to reuse Telit’s FCC certification, the antenna on the application board
shall have a gain equal to the one recommended by Telit, or lower.
As external antenna we recommend the T-AT9552 from Antel, a WIRELESS LAN
DUALBAND 2.4-5.8 GHz with SMA M.
It has a Gain of 2.5 dBi at 2400 ÷ 2500 MHz and 4.5 dBi at 4900 ÷ 5925 MHz.
BlueTooth Antenna requirements
Please follow the same raccomandation given for the WIFI antenna.
A separate Application Note will be issue for different antenna options like integrated
ceramic or antenna PCB design.
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PCB Design Guidelines
6.6.1. PCB General Guidelines
The Ground of the PCB or Chip RF antenna is part of antenna when using a monopole,
especially the part that lies in front of the monopole. Leave a wide ground area, without
components and tracks, in front of antenna on all layers. In the inner layers, the width could
be less. 5mm is an optimum value but not always reachable.
If antenna is placed directly on onboard connector, it is important to consider leaving a wide
ground area for it.
The position of the external antenna with respect to other boards is of maximum importance,
since conductive planes close to antenna modify the impedance seen by the antenna and
any board of the system must be RF proof, not only the modem board.
Move components, tracks, vias and connectors away from antenna area to reduce their
coupling with RF signal; you can also bury tracks in the inner layers of a multi-layer PCB.
Since components and PCBs are getting smaller while component’s density
increases,another problem that becomes important is the heat dissipation. For that reason,
we must pay special attention to PCB layup and component placement. We strongly
suggest following these PCB design rule to help not only RF immunity but improving heat
dissipation.
• We suggest to use at least a 6 layers PCB technology.
• Layer2 and Layer4 mainly ground.
• On top Layer1 and bottom Layer6 place mainly ground plane interrupted just by
component pads and RF antenna tracks doing minimum necessary tracks to arrive
to drills connecting to Layer3 and Layer5. This is to avoid ground interruption and
consequently its heat dissipation.
• Use Layer3 and Layer5 only for signals, where power lines are wider tracks
surrounded of ground not to have crosstalk with other signals.
• One layer for horizontal lines only and the other one for vertical lines. Fill remaining
empty space with ground.
• Use many vias to connect all ground planes and areas in all layers with possible
through hole drills.
• Place warmer components, like modem, on PCB side facing up and do not place
anything on top of them, leaving space to the air.
• If it is a closed application, consider opening holes on top and bottom of the cover
for ventilation or use the modem for short time.
The design can be done in 4 layers only if the number of interconnection gives you the
possibility to route them on layer2 and layer3 in a way that power lines and signals lines do
not intersect and the modem do not work continuously so the heat dissipation is not a must.
All the rest suggestion described above must be fulfilling. Any audio, USB, ADC, fast digital
lines must be route avoiding intersection with any other track.
Top and Bottom layers should be mainly a ground plane interrupted just by component’s
pads, vias and RF tracks. Connect all ground areas avoiding isolated island with several
vias. In this way, the signal tracks are more protected from picking up RF due to the
Faraday-Cage effect. Long exposed tracks can easily pick-up RF power and especially in
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case with many RF power sources where high frequency intermodulation harmonics can be
generated. Attention to any exposed tracks, even if short, at our high frequencies, they can
irradiate very efficiently.
All the PCB borders should be ground in ALL layers and fill all the free space in internal
planes with ground. All the ground, either planes or areas, must be well interconnected, with
a fence of GND vias one each 2 mm, to guarantee a strong equipotential node. Avoid
unconnected copper islands and signal or vias on PCB border.
Power tracks should face only ground tracks or planes. Power lines should not run externally
and/or side by side with other signal lines, place ground in between. Power lines should not
have signal lines running or crossing under them, place ground plane area under and above
all its path.
Bypass capacitors must be placed close to the Telit modem’s power input pads. In case of
switching power supply another Bypass low ESR capacitor must be placed close to the
inductor output to reduce the ripple.
Some protection diode must be placed close to the input connector where the power source
is drained.
It is not advisable to route analog or digital audio lines, memory address and data bus, fast
digital signals, clocks, quartz, serial and long signal tracks on an outer layer. It’ll be better
to bury it on an inner layer with a ground plane under and above it to shield the signal from
RF and crosstalk, see figure below.
Figure 6-1: Example of buried lines
6.6.2. RF PCB Guidelines
The WL865E4-P module provides a 50 Ω antenna pad, which has to be routed to the
antenna connector (or the integrated antenna) by means of a transmission line.
Keep as close ad possible to 50 Ω impedance in the RF track including the RF Pad. It is
important to make RF trace equal or wider than the Pad width to avoid step impedance.
The line should be as short as possible, and keep a constant cross section, avoiding stubs,
sharp bends and meanders. Eliminate the right angle on your antenna waveguide design.
It shall be isolated from any other noise source: in particular, trace shall not be crossed by
other lines in adjacent layers. Instead, a continuous ground plane is recommended under
the antenna trace, and a ground via curtain should connect it to the coplanar ground planes.
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The PCB width and size depend on the stackup and on the structure that you’re going to
realize.
As an example of a possible implementation, the details of the antenna trace on the WL865
interface board are described in this section.
A Grounded Coplanar Waveguide (G-CPW) line has been chosen, since this kind of
transmission line ensures good impedance control and can be implemented in an outer
PCB layer as needed in this case. A SMA female connector has been used to feed the line.
The interface board is realized on a FR4, 4-layers PCB. Substrate material is characterized
by relative permittivity εr = 4.6 ± 0.4 @ 1 GHz, TanD= 0.019 ÷ 0.026 @ 1 GHz.
An example of a waveguide having the same width as the RF Pad are shown in figures
below.
Figure 6-2: Coplanar Waveguide dimensioning example
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Please pay attention to cut the GND plane close to the Antenna pad, otherwise you can
change drastically the impedance value.
To give you an idea in Figure 6-3 we are showing the RF track used in our EVB.
Please consider to keep an appropriate clear area from RF PAD to GND in you board.
Figure 6-3: RF Track on EVB
6.6.3. PCB Guidelines in case of FCC Certification
TBD
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7. AUDIO SECTION
Electrical Characteristics
The audio interface is only digital, through the I2S.
The voltage of this interface pins have same electrical characteristics as for digital pins and
are related to the power bank VDD_VIO.
Codec examples
TBD
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8. MECHANICAL DESIGN
Drawing
Figure 8-1: WL865E4-P Top and bottom side mechanical Drawing
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Figure 8-2: WL865E4-P side view
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9. APPLICATION PCB DESIGN
Footprint
Figure 9-1: WL865E4-P recommended footprint
PCB pad design
Non solder mask defined (NSMD) type is recommended for the solder pads on the PCB.
Figure 9-2: SMD and NSMD PAD
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PCB pad dimensions
It is not recommended to place via or micro-via not covered by solder resist in an area of
0.3 mm around the pads unless it carries the same signal of the pad itself (see following
figure).
Figure 9-3: inhibit area for not solder covered vias
Holes in pad are allowed only for blind holes and not for through holes.
Recommendations for PCB pad surfaces:
Finish
Layer thickness [µm]
Properties
Electro-less Ni /
Immersion Au
3 –7 / 0.03 – 0.15
Good solderability
protection,
high shear force values
Table 9-1: PSB Finishing recommendation
The PCB must be able to resist the higher temperatures which are occurring at the leadfree process. This issue should be discussed with the PCB-supplier. Generally, the
wettability of tin-lead solder paste on the described surface plating is better compared to
lead-free solder paste.
It is not necessary to panel the application PCB, however in that case it is suggested to use
milled contours and predrilled board breakouts; scoring or v-cut solutions are not
recommended.
Stencil
Stencil’s apertures layout can be the same of the recommended footprint (1:1), we suggest
a thickness of stencil foil ≥ 120 µm.
Solder paste
Lead free
Solder paste
Sn/Ag/Cu
Table 9-2:Recommended Solder Paste Type
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We recommend using only “no clean” solder paste in order to avoid the cleaning of the
modules after assembly.
Solder Reflow
Recommended solder reflow profile
Figure 9-4: Solder Reflow profile
Profile Feature
Pb-Free Assembly
Average ramp-up rate (TL to TP)
3°C/s max
Preheat
– Temperature Min (Tsmin)
– Temperature Max (Tsmax)
– Time (min to max) (ts)
150°C
200°C
60-180 s
Tsmax to TL
– Ramp-up Rate
3°C/s max
Time maintained above:
– Temperature (TL)
– Time (tL)
217°C
60-150 s
Peak Temperature (Tp)
245 +0/-5°C
Time within 5°C of actual Peak
Temperature (tp)
10-30 s
Ramp-down Rate
6°C/s max.
Time 25°C to Peak Temperature
8 minutes max.
Figure 9-5: Solder Reflow Table
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Tip or Information – All temperatures refer to topside of the package,
measured on the package body surface.
Caution or Warning –WL865E4-P module withstands one reflow
process only.
Warning: The above solder reflow profile represents the typical SAC
reflow limits and does not guarantee adequate adherence of the
module to the customer application throughout the temperature range.
Customer must optimize the reflow profile depending on the overall
system taking into account such factors as thermal mass and warpage.
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10. PACKAGING
Tray
The WL865E4-P modules are packaged on trays of 50 pieces each when small quantities
are required (i.e. for test and evaluation purposes). Trays are not designed to be used in
SMT processes for pick and place handling.
Figure 10-1: WL865E4-P Packaging
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Caution or Warning –These trays can withstand at the maximum
temperature of 65°C.
Moisture sensitivity
The moisture sensitivity level of the Product is “3” according with standard IPC/JEDEC JSTD-020, take care of all the relative requirements for using this kind of components.
Moreover, the customer has to take care of the following conditions:
a) The shelf life of the Product inside of the dry bag is 12 months from the bag seal date,
when stored in a non-condensing atmospheric environment of < 40°C and < 90% RH.
b) Environmental condition during the production: <= 30°C / 60% RH according to
IPC/JEDEC J-STD-033B.
c) The maximum time between the opening of the sealed bag and the reflow process must
be 168 hours if condition b) “IPC/JEDEC J-STD-033B paragraph 5.2” is respected.
d) Baking is required if conditions b) or c) are not respected
e) Baking is required if the humidity indicator inside the bag indicates 10% RH or more.
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11. CONFORMITY ASSESSMENT ISSUES
FCC/IC Regulatory notices
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12. SAFETY RECOMMENDATIONS
READ CAREFULLY
Be sure the use of this product is allowed in the country and in the environment required.
The use of this product may be dangerous and has to be avoided in the following areas:
• Where it can interfere with other electronic devices in environments such as
hospitals, airports, aircrafts, etc.
• Where there is risk of explosion such as gasoline stations, oil refineries, etc. It is the
responsibility of the user to enforce the country regulation and the specific
environment regulation.
Do not disassemble the product; any mark of tampering will compromise the warranty
validity. We recommend following the instructions of the hardware user guides for correct
wiring of the product. The product has to be supplied with a stabilized voltage source and
the wiring has to be conformed to the security and fire prevention regulations. The product
has to be handled with care, avoiding any contact with the pins because electrostatic
discharges may damage the product itself.
The system integrator is responsible for the functioning of the final product; therefore, care
has to be taken to the external components of the module, as well as any project or
installation issue, because the risk of disturbing the GSM network or external devices or
having impact on the security. Should there be any doubt, please refer to the technical
documentation and the regulations in force. Every module has to be equipped with a proper
antenna with specific characteristics. The antenna has to be installed with care in order to
avoid any interference with other electronic devices and has to guarantee a minimum
distance from the body (20 cm). In case this requirement cannot be satisfied, the system
integrator has to assess the final product against the SAR regulation.
The European Community provides some Directives for the electronic equipment
introduced on the market. All of the relevant information is available on the European
Community website:
http://ec.europa.eu/enterprise/sectors/rtte/documents/
The text of the Directive 99/05 regarding telecommunication equipment is available,
while the applicable Directives (Low Voltage and EMC) are available at:
http://ec.europa.eu/enterprise/sectors/electrical/
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13. ACRONYMS
TTSC
Telit Technical Support Centre
USB
Universal Serial Bus
HS
High Speed
UART
Universal Asynchronous Receiver Transmitter
BLE
Bluetooth low energy
SPI
Serial Peripheral Interface
I2C
Inter Integrated Circuit
I2S
Integrated Interchip Sound
ADC
Analog – Digital Converter
DAC
Digital – Analog Converter
I/O
Input Output
GPIO
General Purpose Input Output
MOSI
Master Output – Slave Input
MISO
Master Input – Slave Output
CLK
Clock
CS
Chip Select
PCB
Printed Circuit Board
ESR
Equivalent Series Resistance
LAN
Local Area Network
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14. DOCUMENT HISTORY
Revision
Date
Changes
0
2017-12-15
First issue
1
2019-04-02
General Review of all chapters
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Mod. 0805 2017-01 Rev.6
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