Telit Wireless Solutions JF2 Hardware User's Manual

JF2 Hardware User Guide
1vv0300985 Rev.4 2013-04-09
JF2 Hardware User Guide
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Mod. 0805 2011-07 Rev.2
APPLICABILITY TABLE
PRODUCT
JF2
JF2 Hardware User Guide
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SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE
Notice
While reasonable efforts have been made to assure the accuracy of this document, Telit assumes no liability resulting from any inaccuracies or omissions in this document, or from use of the information obtained herein. The information in this document has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies or omissions. Telit reserves the right to make changes to any products described herein and reserves the right to revise this document and to make changes from time to time in content hereof with no obligation to notify any person of revisions or changes. Telit does not assume any liability arising out of the application or use of any product, software, or circuit described herein; neither does it convey license under its patent rights or the rights of others.
It is possible that this publication may contain references to, or information about Telit products (machines and programs), programming, or services that are not announced in your country. Such references or information must not be construed to mean that Telit intends to announce such Telit products, programming, or services in your country.
Copyrights
This instruction manual and the Telit products described in this instruction manual may be, include or describe copyrighted Telit material, such as computer programs stored in semiconductor memories or other media. Laws in the Italy and other countries preserve for Telit and its licensors certain exclusive rights for copyrighted material, including the exclusive right to copy, reproduce in any form, distribute and make derivative works of the copyrighted material. Accordingly, any copyrighted material of Telit and its licensors contained herein or in the Telit products described in this instruction manual may not be copied, reproduced, distributed, merged or modified in any manner without the express written permission of Telit. Furthermore, the purchase of Telit products shall not be deemed to grant either directly or by implication, estoppel, or otherwise, any license under the copyrights, patents or patent applications of Telit, as arises by operation of law in the sale of a product.
Computer Software Copyrights
The Telit and 3rd Party supplied Software (SW) products described in this instruction manual may include copyrighted Telit and other 3rd Party supplied computer programs stored in semiconductor memories or other media. Laws in the Italy and other countries preserve for Telit and other 3rd Party supplied SW certain exclusive rights for copyrighted computer programs, including the exclusive right to copy or reproduce in any form the copyrighted computer program. Accordingly, any copyrighted Telit or other 3rd Party supplied SW computer programs contained in the Telit products described in this instruction manual may not be copied (reverse engineered) or reproduced in any manner without the express written permission of Telit or the 3rd Party SW supplier. Furthermore, the purchase of Telit products shall not be deemed to grant either directly or by implication, estoppel, or otherwise, any license under the copyrights, patents or patent applications of Telit or other 3rd Party supplied SW, except for the normal non-exclusive, royalty free license to use that arises by operation of law in the sale of a product.
JF2 Hardware User Guide
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Usage and Disclosure Restrictions License Agreements
The software described in this document is the property of Telit and its licensors. It is furnished by express license agreement only and may be used only in accordance with the terms of such an agreement.
Copyrighted Materials
Software and documentation are copyrighted materials. Making unauthorized copies is prohibited by law. No part of the software or documentation may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, without prior written permission of Telit
High Risk Materials
Components, units, or third-party products used in the product described herein are NOT fault-tolerant and are NOT designed, manufactured, or intended for use as on-line control equipment in the following hazardous environments requiring fail-safe controls: the operation of Nuclear Facilities, Aircraft Navigation or Aircraft Communication Systems, Air Traffic Control, Life Support, or Weapons Systems (High Risk Activities"). Telit and its supplier(s) specifically disclaim any expressed or implied warranty of fitness for such High Risk Activities.
Trademarks
TELIT and the Stylized T Logo are registered in Trademark Office. All other product or service names are the property of their respective owners.
Copyright © Telit Communications S.p.A. 2012.
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Contents
1. Introduction ............................................................................................................ 8
1.1. Scope ............................................................................................................................. 8
1.2. Audience ........................................................................................................................ 8
1.3. Contact Information, Support .......................................................................................... 8
1.4. Document Organization .................................................................................................. 9
1.5. Text Conventions ........................................................................................................... 9
1.6. Related Documents ......................................................................................................... 9
2. Powering the JF2 .............................................................................................. 10
2.1. 1.8V Supply Voltage ................................................................................................ 10
2.1.1. Capacitance ................................................................................................................ 10
2.2. Implementing Pseudo Battery Back-up ................................................................ 10
2.3. Understanding ON-OFF and SYSTEM-ON .............................................................. 11
2.3.1. Auto-ON Configuration (GPIO8 Control) ..................................................................... 11
2.4. Reset Design Details .............................................................................................. 13
3. Example Implementations ................................................................................ 14
3.1. Normal Operation Startup and Shutdown ............................................................. 14
3.2. Self-Start Operation ............................................................................................... 14
4. Updating the Firmware: Flash Module (ONLY)................................................... 15
5. Updating Patch Code: EEPROM and ROM modules with Host Memory ............... 16
6. ROM2.2 Features .............................................................................................. 17
6.1. SPI Flash Support ................................................................................................... 17
6.1.1. Hardware Interface .................................................................................................... 17
6.1.2. Supported SPI Flash Chips ......................................................................................... 17
7. Main Serial Interface ......................................................................................... 18
7.1. UART Mode ............................................................................................................. 19
7.2. I2C Mode ................................................................................................................. 19
7.3. SPI Mode ................................................................................................................. 20
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8. MEMS Sensor/EEPROM Interface ...................................................................... 21
9. RF Front End Design ......................................................................................... 22
9.1. RF Signal Requirements ........................................................................................ 22
9.2. GPS Antenna Polarization ...................................................................................... 24
9.3. GPS Antenna Gain ................................................................................................... 24
9.4. System Noise Floor ................................................................................................ 25
9.5. Active versus Passive Antenna ............................................................................... 25
9.6. RF Trace Losses ..................................................................................................... 25
9.7. Implications of the Pre-select SAW Filter ............................................................. 26
9.8. External LNA Gain and Noise Figure ..................................................................... 26
9.9. Powering the External LNA (active antenna) ......................................................... 27
9.10. RF Interference ................................................................................................... 28
9.11. Shielding .............................................................................................................. 28
10. Reference Design .............................................................................................. 29
10.1. Flash, EEPROM, ROM2.0 Reference Design ....................................................... 29
10.1.1. RF ............................................................................................................................ 29
10.1.2. Serial Interface ....................................................................................................... 30
10.1.3. Power Control ......................................................................................................... 30
10.2. ROM2.2 9600bps .................................................................................................. 31
11. Firmware Configuration .................................................................................... 32
11.1. Internal LNA ........................................................................................................ 32
11.2. Low Power Modes ............................................................................................... 32
11.2.1. Full Power............................................................................................................... 32
11.2.2. TricklePowerTM ........................................................................................................ 32
11.2.3. Push-To-Fix ............................................................................................................ 33
11.2.4. Micro Power Mode (MPM)....................................................................................... 33
11.3. Host Serial Interface ........................................................................................... 33
11.3.1. NMEA Protocol Considerations .............................................................................. 33
11.3.2. OSP Considerations ................................................................................................ 33
11.4. MEMS Configuration ........................................................................................... 34
11.5. Motion Dynamics ................................................................................................. 34
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11.5.1. Static Navigation ..................................................................................................... 34
11.5.2. Velocity Dead-Reckoning ........................................................................................ 34
11.5.3. MEMS Static Detection ........................................................................................... 35
11.5.4. MEMS Wake-up ...................................................................................................... 35
11.6. Advanced Features.............................................................................................. 35
11.6.1. CW Jamming Detection .......................................................................................... 35
11.6.2. SBAS ....................................................................................................................... 35
11.6.3. 2-D Acquisition ....................................................................................................... 36
11.6.4. MEMS Compass Heading ........................................................................................ 36
12. Handling and soldering ..................................................................................... 37
12.1. Moisture Sensitivity ............................................................................................. 37
12.2. ESD ...................................................................................................................... 38
12.3. Reflow .................................................................................................................. 38
12.4. Assembly Issues ................................................................................................. 38
13. PCB Layout Details ........................................................................................... 39
14. Document History ............................................................................................. 40
JF2 Hardware User Guide
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1. Introduction
1.1. Scope
The JF2 is an 11mm by 11mm integrated GPS receiver module using SiRFstar IV technology. This document expands upon the data sheet(s) to highlight particular areas to allow the hardware engineer to achieve a successful design implementation.
1.2. Audience
This document is intended for helping customer in the integration of the Telit SE868 GPS module.
1.3. Contact Information, Support
For general contact, technical support, to report documentation errors and to order manuals, contact Telit Technical Support Center (TTSC) at:
TS-EMEA@telit.com TS-NORTHAMERICA@telit.com TS-LATINAMERICA@telit.com TS-APAC@telit.com
Alternatively, use:
http://www.telit.com/en/products/technical-support-center/contact.php
For detailed information about where you can buy the Telit modules or for recommendations on accessories and components visit:
http://www.telit.com
To register for product news and announcements or for product questions contact Telit Technical Support Center (TTSC).
Our aim is to make this guide as helpful as possible. Keep us informed of your comments and suggestions for improvements.
Telit appreciates feedback from the users of our information.
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1.4. Document Organization
This document contains the following chapters (sample):
“Chapter 1: “Introduction” provides a scope for this document, target audience, contact and
support information, and text conventions.
“Chapter 2: “Powering the JF2 gives an overview about power supply. “Chapter 3: “Example Implementations” describes examples on how to implement the JF2. “Chapter 4: “Updating Firmware” describes the SW updating procedure for Flash version. “Chapter 5: “Updating Patch code” describes how to apply patch code to ROM version. “Chapter 6: “ROM2.2 Features describes the new ROM2.2 features. “Chapter 7: “Main Serial Interface” describes the possible serial interfaces of the JF2. “Chapter 8: “MEMS sensor and EEPROM Interface” describes the DR I2C interface. “Chapter 9: “RF Front End Design” describes in details the characteristics of the Front end. “Chapter 10: “Reference Design” gives an overview about the reference design. “Chapter 11: “Firmware configuration” describes the configuration settings. “Chapter 12: “Handling and soldering” describes packaging and soldering of the module. “Chapter 13: “PCB layout details” describes the mechanical design of the module. “Chapter 14: “Document History” describes the history of the present product.
1.5. Text Conventions
Danger – This information MUST be followed or catastrophic equipment failure or bodily injury may occur.
Caution or Warning – Alerts the user to important points about integrating the module, if these points are not followed, the module and end user equipment may fail or malfunction.
Tip or Information – Provides advice and suggestions that may be useful when integrating the module.
All dates are in ISO 8601 format, i.e. YYYY-MM-DD.
1.6. Related Documents
JF2 Product Description, JF2 EVK User Guide,
JF2 Hardware User Guide
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2. Powering the JF2
2.1. 1.8V Supply Voltage
Unlike older GPS receiver modules, the JF2 requires a single always on supply voltage of 1.8 volts. Rather than having a “split” power supply design of main and backup, the JF2 manages all of its power modes internally. The JF2 will normally power up into the lowest power
“hibernate” state upon initial application of power. Upon pulsing the ON-OFF signal, the JF2 will transition to the “operate” state. Pulsing the ON-OFF signal a second time will transition
the JF2 back into the “hibernate” state. The current power state of the JF2 can be determined by monitoring the “SYSTEM-ON”
signal. A logic low indicates the module is in “hibernate”, whereas logic high indicates the
module is in “operate” state.
If the 1.8 volt DC supply is removed from the JF2 (regardless of power state) it will lose current RTC time and will lose the contents of the internal SRAM. To prevent improper startup, once power is removed, keep the power removed for approximately 10 seconds so the internal SRAM contents can clear reliably. The JF2 monitors the 1.8 volt supply and issues an internal hardware reset if the supply drops below 1.7 volts. This reset protects the memory from accidental writes during a power down condition. However, the reset also clears the RTC time and forces the JF2 into a hibernate state. To prevent this, the 1.8 volt supply must be regulated to be within ±50 mV of nominal voltage inclusive of load regulation and power supply noise and ripple. Noise and ripple outside of these limits can affect GPS sensitivity and also risk tripping the internal voltage supervisors, thereby shutting down the JF2 unexpectedly. Regulators with very good load regulation are strongly recommended along with adequate power supply filtering to prevent power supply glitches as the JF2 transitions between power states. The power supply voltage, noise and ripple must be between 1.75V and 1.85V for all frequencies up to 3MHz. Above 3MHz, the noise and ripple component must not exceed ±16mV. To help meet these requirements, a separate LDO for the JF2 is suggested.
2.1.1. Capacitance
Aluminum electrolytic capacitors are not recommended at the input to the JF2 due to their high ESR. Tantalum capacitors are recommended with a minimum value of 10uF in parallel with a 0.1uF ceramic capacitor. Ceramic capacitors alone can be used, but make sure the LDO is stable with such capacitors tied to the output.
2.2. Implementing Pseudo Battery Back-up
As mentioned above, the JF2 cannot tolerate removal of the 1.8 volt supply without losing RTC time and SRAM data. The main supply voltage can be switched to a backup supply external to the JF2 provided the receiver is allowed time to enter the hibernate state. This can be accomplished by monitoring the status of the SYSTEM-ON line, which will be low whenever the JF2 is in the hibernate state. At this point, the main supply can be safely switched over to the backup supply provided the 1.8 volt supply stays within specification. Similarly, the switch back to the main supply must occur prior to placing the JF2 into full power mode.
JF2 Hardware User Guide
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If the product containing the JF2 needs to support abrupt removal of power, then the module will require a cold start reset upon reapplication of power.
2.3. Understanding ON-OFF and SYSTEM-ON
ON-OFF: Input control SYSTEM-ON: Output indicator
The JF2 power is controlled by a state machine. This state machine is clocked by the internal 32 KHz RTC clock, and is controlled by internal signals as well as the ON-OFF and NRESET signals. The SYSTEM-ON signal reflects the power state of the JF2: logic low for hibernate mode, and logic high for full power mode. When power is first applied to the JF2, the internal RTC must start up before the state machine can begin operating. ON-OFF signals applied before the state machine is ready for them will be ignored. The JF2 signals the readiness to accept ON-OFF signals by outputting a pulse on the SYSTEM-ON line after power is first applied. This pulse is only output upon application of power, and is not output when the receiver is in hibernate or full power mode. The ON-OFF signal is normally low. When it transitions high, it should stay high for a time equivalent to a minimum of 3 RTC clock cycles. The signal may then transition low and remain low until the next change in power state is desired. A single OR gate with one input being SYSTEM-ON and the other being an external pulse will allow the module to be turned back on with a suitable pulse, but it will not be possible to use a second pulse as it is blocked with the SYSTEM-ON signal. The only option to place the module in hibernate state is to issue the serial command. If full ON-OFF control is desired along with having SYSTEM-ON auto-start the receiver, then additional logic is needed to detect the first falling edge of SYSTEM-ON and using this detection to gate off the SYSTEM-ON signal to the ON-OFF signal. If GPIO8 is pulled to logic 1, then the ON-OFF input is modified to be just an ON input. It would not be possible to place the JF2 into hibernate by pulsing ON-OFF in this case.
2.3.1. Auto-ON Configuration (GPIO8 Control)
The JF2 powers up directly into the hibernate state. It is possible to have the module automatically transition to the full power state by tying the SYSTEM-ON output to the ON­OFF input. GPIO8 should also be tied high, which changes the ON-OFF signal to just an ON signal. However, this implementation eliminates the possibility of using the ON-OFF signal to change power states and eliminates the SiRFAware™ and Push-to-Fix™ power modes. If the serial command to place the JF2 in hibernate mode is issued, the module will transition to the hibernate state with no way other than removal and reapplication of power (with resulting RTC and SRAM data loss) to force the module to power up. For some users, this may be all that is required if time and data retention are not important during a power down situation.
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VDD 18
ON-OFF
SYSTEM-ON
(clock runs)
Unknown
Unknown
DT
1
DT
2
DT
HIGH
RTC CLK
(INTERNAL)
Figure 1 – Initial Application of Main Power
Timed Parameter
Prior Event/State
Symbol
Min
Typ
Max
Unit
RTC startup time
First power applied
1
0
299
1000
ms
FSM Ready pulse
RTC running 2
10 T
RTC
Min ON-OFF high
HIGH
3
T
RTC
T
RTC
is equivalent to one RTC (32.678KHz) clock cycle.
Table 1 – Power State Timing
The host system can determine if the J-F2 is “ready” as follows
A short pulse on SYSTEM_ON output line indicates to a host that the J-F2 is ready and armed to
accept an ON_OFF pulse.
The host can wait a fixed duration. Wait at minimum 5 seconds before sending an ON_OFF pulse.
Note that Telit recommends monitoring SYSTEM_ON.
The host can issue ON_OFF pulses repeatedly every 100ms and monitor for JF-2 SYSTEM_ON
output to go HIGH. Note that issuing an ON_OFF pulse once the system is running may cause the firmware to initiate the shutdown process
The host can issue ON_OFF repeatedly every one second and wait for serial messages to be output
within the one second. Note that issuing an ON_OFF pulse once the system is running may cause the firmware to initiate the shutdown process
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