Telit Wireless Solutions GS2101M User Manual

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GS2101M Low Power Wi-Fi Module

HW User Guide

1VV0301395 Rev 3.0 – 2017-11-13

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TELIT MAY MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME, WITHOUT NOTICE.

NOTICES LIMITATION OF LIABILITY

While reasonable efforts have been made to assure the accuracy of this document, Telit assumes no liability resulting from any inaccuracies or omissions in this document, or from use of the information obtained herein. The information in this document has been carefully checked and is believed to be reliable. However, no responsibility is assumed for inaccuracies or omissions. Telit reserves the right to make changes to any products described herein and reserves the right to revise this document and to make changes from time to time in the content hereof with no obligation to notify any person of revisions or changes. Telit does not assume any liability arising out of the application or use of any product, software, or circuit described herein; neither does it convey license under its patent rights or the rights of others.

It is possible that this publication may contain references to, or information about Telit products (machines and programs), programming, or services that are not announced in your country. Such references or information must not be construed to mean that Telit intends to announce such Telit products, programming, or services in your country.

Telit assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Telit products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Telit products are not authorized for use as critical components in medical, lifesaving, or life-sustaining applications.

COPYRIGHT

This Telit manual and contents are owned by Telit and/or its licensors and protected by U.S. and international copyright laws, conventions, and treaties. Your right to use this manual is subject to limitations and restrictions imposed by applicable licenses and copyright laws. Unauthorized reproduction, modification, distribution, display or other use of this manual may result in criminal and civil penalties.

This instruction manual and the Telit products described in this instruction manual may be, include or describe copyrighted Telit material, such as computer programs stored in semiconductor memories or other media. Laws in Italy and other countries preserve for Telit and its licensors certain exclusive rights to copyright material, including the exclusive right to copy, reproduce in any form, distribute and make derivative works of the copyrighted material. Accordingly, any copyrighted material of Telit and its licensors contained herein or in the Telit products described in this instruction manual may not be copied, reproduced, distributed, merged or modified in any manner without the express written permission of Telit. Furthermore, the purchase of Telit products shall not be deemed to grant either directly or by implication, estoppel, or otherwise, any license under the copyrights, patents or patent applications of Telit, as arises by operation of law in the sale of a product.

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USAGE AND DISCLOSURE RESTRICTIONS

I. License Agreements

The software described in this document is the property of Telit and its licensors. It is furnished by express license agreement only and may be used only in accordance with the terms of such an agreement.

II. Copyrighted Materials

Software and documentation are copyrighted materials. Making unauthorized copies is prohibited by law. No part of the software or documentation may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, without prior written permission of Telit.

III. High Risk Materials

Components, units, or third-party products used in the product described herein are NOT faulttolerant and are NOT designed, manufactured, or intended for use as on-line control equipment in the following hazardous environments requiring fail-safe controls: the operation of Nuclear Facilities, Aircraft Navigation or Aircraft Communication Systems, Air Traffic Control, Life Support, or Weapons Systems (High Risk Activities). Telit and its supplier(s) specifically disclaim any expressed or implied warranty of fitness for such High-Risk Activities.

IV. Trademarks

Telit, Telit and stylized Logos are registered Trademarks. All other product or service names are the property of their respective owners.

V. Third Party Rights

The software may include Third Party Right software. In this case, you agree to comply with all terms and conditions imposed on you in respect of such separate software. In addition to Third Party Terms, the disclaimer of warranty and limitation of liability provisions in this License shall apply to the Third Party Right software.

TELIT HEREBY DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED FROM ANY THIRD PARTIES REGARDING ANY SEPARATE FILES, ANY THIRD PARTY MATERIALS INCLUDED IN THE SOFTWARE, ANY THIRD PARTY MATERIALS FROM

WHICH THE SOFTWARE IS DERIVED (COLLECTIVELY “OTHER CODE”), AND THE USE

OF ANY OR ALL THE OTHER CODE IN CONNECTION WITH THE SOFTWARE, INCLUDING (WITHOUT LIMITATION) ANY WARRANTIES OF SATISFACTORY QUALITY OR FITNESS FOR A PARTICULAR PURPOSE.

NO THIRD PARTY LICENSORS OF OTHER CODE SHALL HAVE ANY LIABILITY FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND WHETHER MADE UNDER CONTRACT, TORT OR OTHER LEGAL THEORY, ARISING IN ANY WAY OUT OF THE USE OR DISTRIBUTION OF THE OTHER CODE OR THE EXERCISE OF ANY RIGHTS GRANTED UNDER EITHER OR BOTH THIS LICENSE AND THE LEGAL TERMS APPLICABLE TO ANY SEPARATE FILES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

www.Telit.com

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NOTICES… ...................................................................................................... 2

LIMITATION OF LIABILITY ............................................................................. 2

USAGE AND DISCLOSURE RESTRICTIONS ................................................ 3

CONTENTS ...................................................................................................... 4

About This Manual ............................................................................................ 8

1. GS2101M OVERVIEW ................................................................. 17

Product Overview ......................................................................... 17

GS2101M Module Product Features ............................................ 17

2. GS2101M ARCHITECTURE ........................................................ 20

Architecture Description ............................................................... 20

2.1.1. Wireless LAN and System Control Subsystem ............................. 22

2.1.2. On-board Antenna / RF Port / Radio ............................................ 22

2.1.2.1. 802.11 MAC .................................................................................. 22

2.1.2.2. 802.11 PHY ................................................................................... 23

2.1.2.3. RF/Analog .................................................................................... 23

2.1.3. Network Services Subsystem ....................................................... 24

2.1.3.1. APP CPU ...................................................................................... 24

2.1.3.2. Crypto Engine ............................................................................... 24

2.1.4. Memory Subsystem ...................................................................... 24

2.1.4.1. SRAM ........................................................................................... 24

2.1.4.2. ROM ............................................................................................. 24

2.1.4.3. OTP ROM ..................................................................................... 24

2.1.4.4. Flash Interface .............................................................................. 25

2.1.5. Clocks ........................................................................................... 25

2.1.6. Real Time Clock (RTC) Overview ................................................. 25

2.1.6.1. RTC Main Features ...................................................................... 25

2.1.6.2. Real Time Clock Counter .............................................................. 26

2.1.6.3. RTC I/O ........................................................................................ 26

2.1.7. GS2101M Peripherals ................................................................ .. 26

2.1.7.1. SDIO Interface .............................................................................. 26

2.1.7.2. SPI Interface ................................................................................. 27

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2.1.7.3. UART Interface ............................................................................. 27

2.1.7.4. I2C Interface ................................................................................. 27

2.1.7.5. GPIO ............................................................................................ 28

2.1.7.6. Sigma Delta ADC .......................................................................... 28

2.1.7.7. PWM ............................................................................................. 28

2.1.8. System States .............................................................................. 28

2.1.9. Power Supply ............................................................................... 30

3. PIN-OUT AND SIGNAL DESCRIPTION ...................................... 31

GS2101Mxx Device Pin-out ......................................................... 31

3.1.1. GS2101Mxx Module Pins Description .......................................... 32

3.1.2. GS2101M Pin MUX Function ....................................................... 36

3.1.3. GS2101M Program and Code Restore Options ........................... 38

4. ELECTRICAL CHARACTERISTICS ............................................ 39

Absolute Maximum Ratings .......................................................... 39

Operating Conditions .................................................................... 39

I/O DC Specifications ................................................................... 40

4.3.1. I/O Digital Specifications (Tri-State) Pin Types 4mA, 12mA, and 16mA 40

4.3.1.1. I/O Digital Specifications for VDDIO=2.7V to 3.6V ....................... 40

4.3.2. RTC I/O Specifications ................................ ................................. 41

Power Consumption ..................................................................... 42

802.11 Radio Parameters ............................................................. 43

Sigma Delta ADC Parameters ...................................................... 44

5. PACKAGE AND LAYOUT GUIDELINES .................................... 46

GS2101Mxx Recommended PCB Footprint and Dimensions ...... 46

5.1.1. Surface Mount Assembly .............................................................. 49

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FIGURE LIST

Fig. 1 GS2101M Block Diagram ..................................................................................... 21

Fig. 2 GS2101Mxx Always ON Power Supply Connection ............................................. 30

Fig. 3 GS2101Mxx Device Pin-out Diagram (Module Top View) .................................... 31

Fig. 4 GS2101MIx Module Recommended PCB Footprint (in millimeters) ..................... 46

Fig. 5 GS2101MIx Module Dimensions (in millimeters) .................................................. 47

Fig. 6 Reflow Temperature Profile .................................................................................. 49

Fig. 7 Thermocouple Locations ....................................................................................... 51

Fig. 8 Module Moisture Conditions ................................................................................. 52

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TABLE LIST

Tab. 1 Revision history ..................................................................................................... 8

Tab. 2 Document Conventions ....................................................................................... 11

Tab. 3 Documentation Lists ............................................................................................ 13

Tab. 4 GS2101Mxx Ordering Information ....................................................................... 16

Tab. 5 GS2101Mxx Module Pin Signal Description ........................................................ 32

Tab. 6 GS2101M Pin MUX Description .......................................................................... 36

Tab. 7 GS2101M Pin Program and Code Restore ......................................................... 38

Tab. 8 Absolute Maximum Ratings ................................................................................. 39

Tab. 9 Operating Conditions ........................................................................................... 39

Tab. 10 I/O Digital Parameters for VDDIO=2.7V to 3.6V ................................................ 40

Tab. 11 RTC I/O Parameters .......................................................................................... 41

Tab. 12 Power Consumption in Different States ............................................................. 42

Tab. 13 802.11 Radio Parameters - (Typical - Nominal Conditions)............................... 43

Tab. 14 ADC Parameters ................................................................................................ 44

Tab. 15 Recommended Reflow Parameters ................................................................... 49

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About This Manual

This manual describes the GS2101M Low Power module hardware specification. Refer to the following sections:

• Revision History

• Audience

• Standards

• Certifications

• Documentation Conventions

• Text Conventions

• Related Documents

• Documentation Feedback

• Contacting Telit Technical Support

• Guidelines for Packing Components for Shipment

• Accessing the Telit GainSpan Portal

• Ordering Information

Revision History

This version of the Telit GS2101M Low Power Wi-Fi Module contains the following new information listed.

Version

Date

Remarks

May 2016

Initial release.

1.0

July 2017

Updated 802.11 Output Power, RF Frequency Range. Table

13, Page 45.

2.0

October 2017

Updated Output Power in. Table 13, Page 45.

3.0

November 2017

Updated Data rates for 802.11n in 1GS2101M Overview

and 2.1.2.2802.11 PHY

Tab. 1 Revision history

Audience

This manual is designed to help system designers build low power, cost effective, flexible platforms to add Wi-Fi connectivity for embedded device applications using the Telit GS2101M based module.

Standards

The standards that are supported by the Telit modules are IEEE 802.11b/g/n.

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Certifications

GainSpan GS2101M Low Power Wi-Fi Module has Certification Compliance for the following:

1. GS2101M OVERVIEW

This chapter describes the Telit® GS2101M low power module hardware specification overview.

• Product Overview

• GS2101M Module Product Features

Product Overview

The GS2101M based modules provide cost effective, low power, and flexible platform to add Wi-Fi® connectivity for embedded devices for a variety of applications, such as wireless sensors and thermostats. It uses the GS2000 SoC, which combines ARM® Cortex M3-based processors with a 802.11b/g/n Radio, MAC, security, & PHY functions, RTC and SRAM, up to 4 MB FLASH, and on-board and off module certified antenna options. The module provides a Wi-Fi and regulatory certified IEEE 802.11b/g/n radio with concurrent network processing services for variety of applications, while leverage existing 802.11 wireless network infrastructures.

GS2101M Module Product Features

• Family of modules with different antenna options:

• GS2101MIx 18mm (0.71in) x 25 mm (0.98in) x 2.7mm (0.106in) 40-pin

PCB Surface Mount Package. Two SKU’s are:

– GS2101MIP (on-board PCB antenna) – GS2101MIE (external antenna)

• The two SKUs are pin to pin compatible

• Simple API for embedded markets covering a large range of applications

• Fully compliant with IEEE 802.11b/g/n and regulatory domains:

– 802.11n: 1x1 single stream, 20 MHz channels, 400/800ns GI, MCS0-7

data rates of 6.5, 13, 19.5, 26, 39, 52, 58.5, 65 Mbps

– 802.11g: OFDM modulation for data rates of 6, 9, 12, 18, 24, 36, 48,

54 Mbps.

• Wi-Fi Solution:

– Wi-Fi security (802.11i) – WPA™ - Enterprise, Personal – WPA2™ - Enterprise, Personal – Vendor EAP Type(s) – EAP-TTLS/MSCHAPv2, PEAPv0/EAP-MSCHAPv2, PEAPv1/EAP-

GTC, EAP-FAST, EAP-TLS

• Hardware-accelerated high-throughput AES and RC4

encryption/decryption engines for WEP, WPA/WPA2 (AES-CCMP and TKIP).

• Additional dedicated encryption HW engine to support higher layer

encryption such as IPSEC (IPv4 and IPv6), SSL/TLS, HTTPs, PKI, digital certificates, RNG, etc.

• Dual ARM Cortex M3 Processor Platform:

• 1st Cortex M3 processor (WLAN CPU) for WLAN software

– Implements 802.11 b/g/n WLAN protocol services

– 320 KB dedicated SRAM – 512 KB dedicated ROM

• 2

Cortex M3 processor (APP CPU) for networking software

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– Implements networking protocol stacks and user application

software

– 384 KB dedicated SRAM – 512 KB dedicated ROM

• 64KB shared dual ported SRAM for inter-processor communications

• 320KB assignable (under SW control) SRAM

• Support processor clock frequencies for both CPU of up to 120MHz

• Based on Advanced Microprocessor Bus Architecture (AMBA) system

– AMBA Multilayer High-Speed Bus (AHB) – AMBA Peripheral Bus (APB)

• On-module flash controller:

– Manages read/write/program/erase operations to the 4 MB flash

memory device on the module

– Supports higher performance QUAD SPI protocol operations – Active power management

• Interfaces:

• SDIO:

– Compliant to SDIO v2.0 specification – Interface clock frequency up to 40 MHz

NOTICE:

Tested with current test platform up to 33 MHz.

Data transfer modes: 4-bit, 1-bit SDIO, SPI

– Device mode only (slave)

• SPI:

– Two (2) general-purpose SPI interfaces (each configurable

independently as master or slave)

– The SPI pins are muxed with other functions such as GPIO – Supports clock rates of up to 30 MHz (master mode) and up to 10

MHz (slave mode)

– Protocols supported include: Motorola SPI, TI Synchronous Serial

Protocol (SSP) and National Semiconductor Microwire

– Supports SPI mode 0 thru 3 (software configurable)

• UART:

– Two (2) multi-purpose UART interfaces operating in full-duplex mode – 16450/16550 compatible – Optional support for flow control using RTS/CTS signaling for high

data transfer rates

– Standard baud rate from 9600 bps up to 921.6K baud (additional

support for higher non-standard rates using baud rates up to 7.5 MHz)

• GPIOs:

– Up to 16 configurable general purpose I/O

• Single 3.3V supply option

• Three (3) PWM output

• I2C master/slave interface

• Three (3) 16-bit Sigma Delta ADC channels, for sensors and

measurements

• One (1) RTC I/O that can be configured as:

– Alarm input to asynchronously awaken the chip – Support control outputs for sensors

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• Embedded RTC (Real Time Clock) can run directly from battery

• Power supply monitoring capability

• Low-power mode operations:

• Standby, Sleep, and Deep Sleep

• FCC/IC/ETSI/TELEC/Wi-Fi Certification

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2. GS2101M ARCHITECTURE

This chapter describes the Telit® GS2101M Low Power module architecture.

• Architecture Description

Architecture Description

The Telit GS2101M module (see Fig. 1, page 21) is based on a highly integrated GS2000 ultra low power Wi-Fi System-on-Chip (SoC) that contains the following:

• The GS2000 SoC contains two ARM Cortex M3 CPUs, a compatible

802.11 radio, security, on-chip memory, and variety of peripherals in a single package.

– One ARM core is dedicated to Networking Subsystems, and the other

dedicated to Wireless LAN Subsystems.

– The module carries an 802.11/g/n radio with on-board 32KHz &

40MHz crystal circuitries, RF, and on-board antenna or external antenna options.

• On module 4 Mega Byte FLASH device that contains the user embedded

applications and data such as web pages.

• Variety of interfaces are available such as two UART blocks using only

two data lines per port with optional hardware flow controls, two SPI blocks (one SDIO is shared function with one for the SPI interfaces), I2C with Master or slave operation, JTAG port, three 16-bit Sigma-Delta ADCs capable of running at up to 80K samples/Sec., GPIO’s, and LED Drivers/GPIO with 16mA capabilities.

• GS2101Mxx has a VRTC pin that is generally connected to always

available power source such as battery or line power. This provides power to the Real Time Clock (RTC) block on the SoC. The module also has VIN_3V3 power supply input to provide the logic signal level for the I/O pins. The VRTC and VIN_3V3 pins should always be connected to the same power source.

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Fig. 1 GS2101M Block Diagram

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2.1.1. Wireless LAN and System Control Subsystem

The WLAN CPU subsystem consists of the WLAN CPU, its ROM, RAM, 802.11b/g/n MAC/PHY, and peripherals. This CPU is intended primarily to implement the 802.11 MAC protocols. The CPU system has GPIO, Timer, and Watchdog for general use. A UART is provided as a debug interface. A SPI interface is provided for specific application needs. The WLAN CPU can access the RTC registers through an asynchronous AHB bridge.

WLAN CPU has only Flash read access to the on-board flash memory. The WLAN subsystem interacts with the App subsystem through a set of mailboxes and shared dual–port memories.

The CPUs provide debug access through a JTAG/serial port. For GS2101M module, the complete JTAG port is brought out for both CPUs. The CPUs also include code and data trace and watch point logic to assist in-system debugging of SW.

The WLAN subsystem includes an integrated power amplifier. In addition, it contains hardware support for AES-CCMP encryption (for WPA2) and RC4 encryption (for WEP & WPA TKIP) encryption/decryption.

2.1.2. On-board Antenna / RF Port / Radio

The GS2101Mxx modules have fully integrated RF frequency synthesizer, reference clock, and PA. Both TX and RX chain in the module incorporate internal power control loops. The GS2101Mxx modules also incorporate an on-board antenna option or an external antenna connector.

2.1.2.1. 802.11 MAC

The 802.11 MAC implements all time critical functionality of the 802.11b/g/n protocols. It works in conjunction with the MAC SW running on the CPU to implement the complete MAC functionality. It interfaces with the PHY to initiate transmit/receive and CCA. The PHY registers are programmed indirectly through the MAC block. The MAC interfaces to the system bus and uses DMA to fetch transmit packet data and save receive packet data. The MAC SW exchanges packet data with the HW though packet descriptors and pointers.

Key Features

• Compliant to IEEE 802.11 (2012)

• Compliant to IEEE 802.11b/g/n (11n – 2009)

• Long and short preamble generation on frame-by-frame basis for 11b frames

• Transmit rate adaptation

• Transmit power control

• Frame aggregation (AMPDU, AMSDU)

• Block ACK (Immediate, Compressed)

• RTS/CTS, CTS-to-self frame sequences and SIFS

• Client and AP modes support

• Encryption support including: AES-CCMP, legacy WPA-TKIP, legacy WEP ciphers

and key management

• Wi-Fi Protected Setup 2.0 (WPS2.0) including both PIN and push button options

• 802.11e based QoS (including WMM, WMM-PS)

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2.1.2.2. 802.11 PHY

The 802.11 PHY implements all the standard required functionality and Telit specific functionality for 802.11b/g/n protocols. It also implements the Radar detection functionality to support 802.11h. The PHY implements the complete baseband Tx and Rx pipeline. It interfaces with the MAC to perform transmit and receive operations. It interfaces directly to the ADC and DAC. The PHY implements the Transmit power control, receive Automatic Gain Control and other RF control signals to enable transmit and receive. The PHY also computes the CCA for MAC use.

Key Features

• Compliant to 2.4GHz IEEE 802.11b/g/n (11n – 2009)

• Support 802.11g/n OFDM with BPSK, QPSK, 16-QAM and 64-QAM; 802.11b

with BPSK, QPSK and CCK

• Support for following data rates:

– 802.11n (20MHz): MCS0 - 7; 6.5, 13, 19.5, 26, 39, 52, 58.5, 65 Mbps – 802.11g: 6, 9, 12, 18, 24, 36, 48, 54 Mbps – 802.11b: 1, 2, 5.5, 11 Mbps

• Support Full (800ns) & Half (400ns) Guard Interval (GI) modes (SGI and LGI)

• Support Space time block coding (STBC) for receive direction

• Complete front-end radio integration including PA, LNA and RF Switch

2.1.2.3. RF/Analog

The RF/Analog is a single RF transceiver for IEEE 802.11b/g/n (WLAN). The RF Interface block provides the access to the RF and analog control and status to the CPU. This block is accessible only from the WLAN CPU. It implements registers to write static control words. It provides read only register interface to read static status. It generates the dynamic control signals required for TX and RX based on the PHY signals. The AGC look up table to map the gain to RF gain control word is implemented in this block.

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2.1.3. Network Services Subsystem

2.1.3.1. APP CPU

The Network services subsystem consists of an APP CPU which is based on an ARM CORTEX M3 core. It incorporates an AHB interface and a JTAG debug interface. The network RTOS, network stack, and customer application code run on this CPU.

2.1.3.2. Crypto Engine

The Network services subsystem contains a separate hardware crypto engine that provides a flexible framework for accelerating the cryptographic functions for packet processing protocols. The crypto engine has the raw generic interface for cipher and hash/MAC functions such as AES, DES, SHA, and RC4. It also includes two optional engines to provide further offload; the PKA and RNG modules. These provide additional methods for public key acceleration functions and random number generation. The engine includes a DMA engine that allows the engine to perform cryptographic operation on data packets in the system memory without any CPU intervention.

2.1.4. Memory Subsystem

The GS2101M module contains several memory blocks.

2.1.4.1. SRAM

The system memory is built with single port and dual port memories. Most of the memory consists of single port memory. A 64KB dual port memory is used for exchange of data between the two CPU domains. All the memories are connected to the system bus matrix in each CPU subsystem. All masters can access any of the memory within the subsystem.

The APP subsystem has 384KB of dedicated SRAM for program and data use. The WLAN subsystem has 320KB of dedicated SRAM for program and data use.

These memories are divided into banks of 64KB each. The bank structure allows different masters to access different banks simultaneously through the bus matrix without incurring any stall. Code from the external Flash is loaded into the SRAM for execution by each CPU.

In addition, a static shared SRAM is provided. This consists of five 64KB memory blocks. At any time, any of these memory blocks can be assigned to one of the CPU subsystem.

These should be set up by the APP CPU SW at initialization time. The assignment is not intended to change during operation and there is no HW interlock to avoid switching in the middle of a memory transaction. The assignment to the WLAN CPU should be done starting from the highest block number going down to lowest block number. This result in the shared memory appearing as a single bank for each CPU subsystem, independent of the number of blocks assigned. The shared memory is mapped such that the SRAM space is continuous from the dedicated SRAM to shared SRAM.

2.1.4.2. ROM

ROM is provided in each CPU subsystem to provide the boot code and other functional code that are not expected to change regularly. Each CPU has 512KB of ROM

2.1.4.3. OTP ROM

The GS2000 device includes a 64Kbit OTP ROM used for storing MAC ID and calibration information. The APP and WLAN subsystem each contain 32Kbits (4Kbytes) of OTP memory.

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2.1.4.4. Flash Interface

The GS2000 SoC has only internal ROM and RAM for code storage. There is no embedded Flash memory on the SoC. Any ROM patch code and new application code must reside in the on-module Flash device of the GS2101M module. Flash access from the two CPUs are independent. The APP CPU is considered the system Master and the code running on this CPU is required to initialize the overall chip and common interfaces. WLAN CPU access to the Flash is restricted to read DMA. Any write to the Flash from the WLAN CPU must be done through the APP CPU. The operational parameters of the DMA accesses are set by the APP CPU at system startup. The Flash code is transferred to internal RAM before execution.

2.1.5. Clocks

The GS2101M includes four basic clock sources:

• Low power 32KHz clock (see 2.1.6 Real Time Clock (RTC) Overview, page

29)

• 40MHz Xtal Oscillator

• PLL to generate the internal 120MHz (CPU) and 80MHz (PHY) clocks from

the 40MHz Xtal.

• High speed RC oscillator 80MHz

Intermediate modes of operation, in which high speed clocks are active but some modules are inactive, are obtained by gating the clock signal to different subsystems. The clock control blocks within the device are responsible for generation, selection and gating of the clocked used in the module to reduce power consumption in various power states

2.1.6. Real Time Clock (RTC) Overview

To provide global time (and date) to the system, the GS2101Mxx module is equipped with a low-power Real Time Clock (RTC). The RTC is the always on block that manages the Standby state. This block is powered from a supply pin (VRTC) separate from the digital core and may be powered directly from a battery. The RTC implementation supports a voltage range of 1.6V to 3.6V

2.1.6.1. RTC Main Features

• One 48-bit primary RTC counter as the primary reference for all timing events

and standby awake management

• 1 programmable IO pins with specific default behavior. These pins are in the

RTC IO domain.

– Alarm inputs to wake up the GS2101M module from its sleep states

(deep-sleep/standby)

• Startup control counters with HW and SW override registers

• Power-on-reset control with brown-out detector

• RTC registers to hold RTC and wakeup control bits while the core domain is

off

• 1Kbyte latch based memory (1.6-3.6V capable)

• 16KB of SRAM memory, divided into 4 equal blocks (1.2V capable)

• uLDO to supply the SRAM memory

• RTC logic is 1.6-3.6V capable

• 32 KHz RC oscillator

• 32768Hz crystal oscillator

• APB interface for CPU access

• Interrupts to CPU

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The RTC contains a low-power 32.768KHz RC oscillator which provides fast startup at first application of RTC power. It also supports an optional 32.768KHz crystal oscillator which can be substituted for the RC oscillator under software control. In normal operation, the RTC is always powered up.

The standby programmable counter is 48-bits and provides up to 272 years’ worth of standby duration. For the RTC_IO pin, the programmable embedded counter (32-bit) is provided to enable periodic wake-up of the remainder of the external system, and

provide a 1.5 days’ max period. The RTC_IO pin can be configured as input (ALARM) or

output (WAKE UP) pin. The RTC includes a Power-On Reset (POR) circuit, to eliminate the need for an external

component. The RTC contains low-leakage non-volatile (battery-powered) RAM, to enable storage of data that needs to be preserved. It also includes a brown-out detector that can be disabled by SW.

2.1.6.2. Real Time Clock Counter

• The Real Time Counter features:

– 48-bit length (with absolute duration of 272 years). – Low-power design.

• This counter is automatically reset by power-on-reset.

• This counter wraps around (returns to “all-0” once it has reached the

highest possible “all-1” value).

2.1.6.3. RTC I/O

There is one (1) RTC I/O that can be used to control external devices, such as sensors or wake up the module based on external events or devices.

2.1.7. GS2101M Peripherals

2.1.7.1. SDIO Interface

The SDIO interface is a full / high speed SDIO device (slave). The device supports SPI, 1-bit SD and 4-bit SD bus mode. The SDIO block has an AHB interface, which allows the CPU to configure the operational registers residing inside the AHB Slave core. The CIS and CSA area is located inside the internal memory of CPU subsystem. The SDIO Registers (CCCR and FBR) are programmed by both the SD Host (through the SD Bus) and CPU (through the AHB bus) via Operational registers. The SDIO block implements the AHB master to initiate transfers to and from the system memory autonomously.

During the normal initialization and interrogation of the card by the SD Host, the card will identify itself as an SDIO device. The SD Host software will obtain the card information in a

tuple (linked list) format and determine if that card’s I/O function(s) are acceptable to

activate. If the Card is acceptable, it will be allowed to power up fully and start the I/O function(s) built into it.

The SDIO interface implements Function 1 in addition to the default Function 0. All application data transfers are done through the Function 1

The primary features of this interface are

• Meets SDIO card specification version 2.0.

• Conforms to AHB specification.

• Host clock rate variable between 0 and 40 MHz

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NOTICE:

Tested with current test platform up to 33 MHz.

• All SD bus modes supported including SPI, 1 and 4-bit SD.

• Allows card to interrupt host in SPI, 1 and 4 bit SD modes.

• Read and Writes using 4 parallel data lines

• Cyclic Redundancy Check CRC7 for command and CRC16 for data

integrity-CRC checking optional in SPI mode

• Programmable through a standard AHB Slave interface

• Writing of the I/O reset bit in CCCR register generates an active low reset

output synchronized to AHB Clock domain.

• Card responds to Direct read/write (IO52) and Extended read/write (IO53)

transactions.

• Supports Read Wait Control operation.

• Supports Suspend/Resume operation.

2.1.7.2. SPI Interface

The SPI interface is a master slave interface that enables synchronous serial communications with slave or master peripherals having one of the following: Motorola SPI-compatible interface, TI synchronous serial interface or National Semiconductor Microwire interface. In both master and slave configuration, the block performs

parallel-to-serial conversion on data written to an internal 16-bit wide, 8-deep transmit FIFO and serial to parallel conversion on received data, buffering it in a similar 16-wide, 8 deep FIFO. It can generate interrupts to the CPU to request servicing transmit and receive FIFOs and indicate FIFO status and overrun/underrun. The clock bit rate is SW programmable. In master mode, the SPI block in GS2000 can perform up to 30 MHz and in slave mode up to 10 MHz serial clock. Clock rates higher than 20MHz in master mode

or 6.66MHz in slave mode requires activation of the PLL’s 120MHz clock source. The

interface type, data size and interrupt masks are programmable. It supports DMA working in conjunction with the uDMA engine

2.1.7.3. UART Interface

The UART interface implements the standard UART protocol. It is 16450/16550 compatible. It has separate 32 deep transmit and receive FIFOs to reduce CPU interrupts. The interface supports standard asynchronous communication protocol using start, stop and parity bits. These are added and removed automatically by the interface logic. The data size, parity and number of stop bits are programmable. It supports HW based flow control through CTS/RTS signaling. A fractional baud rate generator allows accurate setting of the communication baud rate. It supports DMA working in conjunction with the uDMA engine.

2.1.7.4. I2C Interface

The I2C interface block implements the standard based two wire serial I2C protocol. The interface can support both master and slave modes. It supports multiple masters, high speed transfer (up to 3.4MHz), 7 or 10-bit slave addressing scheme, random and current address transfer. It also supports clock stretching to interface with slower devices. It can generate interrupts to the CPU to indicate specific events such as FIFO full/empty, block complete, no ack error, and arbitration failure.

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2.1.7.5. GPIO

The GPIO block provides programmable inputs and outputs that can be controlled from the CPU SW through an APB interface. Any number of inputs can be configured as an interrupt source. The interrupts can be generated based on the level or the transition of a pin. At reset, all GPIO lines defaults to inputs. Each pin can be configured as input or output from SW control.

2.1.7.6. Sigma Delta ADC

The ADC and DAC are 16-bit sigma-delta converters. There are 3 ADC channels, each having a differential pair for a total of six input pins. The sample rate can be 32KHz to 80KHz. The sigma delta converter ratio is 250. The ADC is a 3-channel converter. Each channel can have an optional pre-amplifier stage. The gain can be set to 0db, 6db, 12db, 18db, or 24db. The delay between the second and third channels of the ADC can be

adjusted under SW control. The digital interface for the ADCs and the DAC are 2’s

complement. ADC channel 0 (only) can alternatively be used as a differential DAC.

2.1.7.7. PWM

The PWM consists of three identical PWM function blocks. The PWM function blocks can be used in two modes of operations:

• Independent PWM function blocks providing output signal with

programmable frequency and duty cycle

• Synchronized PWM function blocks with programmable phase delay

between each PWM output

The PWM has the following features:

• 32-bit AMBA APB interface to access control, and status information

• Three identical PWM function blocks

• Each PWM block can be enabled independently

• All three PWM blocks can be started synchronously or chained with

programmable delay

• Programmable 6-bit prescaler for the input clock (see 2.1.5 Clocks, page

24)

• Programmable frequency and duty cycle using 16-bit resolution in terms

of clock cycles for ON and OFF interval time

• Combined interrupt line with independent masking of interrupts

2.1.8. System States

The system states of the GS2101Mxx system are as follows:

Power OFF: No power source connected to the system.

Standby: In the standby state, the GS2101M is in its lowest power state. In this state

power is on to the VRTC and VIN_3V3 input. The RTC portion of the GS2000 chip is powered from the VRTC pin. In standby state, the 32.768KHz oscillator is running and RTC RAM retains the state (how many banks retain their state is SW configurable). SRAM, CPUs and I/Os are powered off using the internal switches within the device thus reducing overall power consumption. Exit from standby occurs when a pre-specified wakeup time occurs, or when the RTC_IO configured as alarm inputs sees the programmed polarity of signal edge.

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NOTICE :

During first battery plug-in, i.e., when power is applied the first time to the RTC power rail (VRTC), the power detection circuit in the RTC also causes a wakeup request.

System Configuration: When a power-up is requested, the system transitions from the Standby state to the System Configuration state. In this state, the APP CPU is released from reset by the RTC. The WLAN CPU remains in the reset state during System Configuration. The APP CPU then executes the required system configurations, releases the WLAN CPU from reset, and transitions to the Power-ON state. The System Configuration state is also entered on transition from the PowerON state to the Standby state, to complete necessary preparations before shutting off the power to the core system. Power-ON: This is the active state where all system components can be running. The Power-ON state has various sub-states, in which unused parts of the system can be in sleep mode, reducing power consumption. Sleep states are implemented by gating the clock signal off for a specific system component. Additionally, unneeded clock sources can be turned off. For example, receiving data over a slave SPI interface could be done with only the 80MHz RC oscillator active, and the 40MHz crystal and PLL turned off. Sleep: In the Sleep state, the 40MHz crystal and the 80MHz RC oscillator remains running, but it is gated off to one or both CPUs. Each CPU can independently control its own entry into Sleep state. Any enabled interrupt will cause the interrupted CPU to exit from Sleep state, and this will occur within a few clock cycles. Deep Sleep: Deep sleep is entered only when both CPUs agree that the wakeup latency is OK. In Deep Sleep mode, the 40MHz crystal oscillator and 80MHz RC oscillator are turned off to save power, but all power supplies remain turned on. Thus all registers, memory, and I/O pins retain their state. Any enabled interrupt will cause an exit from Deep Sleep state.

EXT_RTC_RESET_n pin: This is an input pin for resetting the entire module, including the RTC section of the device. This pin should not be left floating. An external 10K pull up resistor to VRTC is recommended.

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2.1.9. Power Supply

This section shows various application power supply connections. Following figure shows the GS2101Mxx power supply connection

Fig. 2 GS2101Mxx Always ON Power Supply Connection

Note:

1. Always ON connection connects VRTC and VIN_3V3 together to

a 3.3V power supply.

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3. PIN-OUT AND SIGNAL DESCRIPTION

This chapter describes the Telit® GS2101M Low Power module architecture.

• GS2101Mxx Device Pin-out

GS2101Mxx Device Pin-out

Following figure shows the GS2101Mxx device pin-out diagram

Fig. 3 GS2101Mxx Device Pin-out Diagram (Module Top View)

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3.1.1. GS2101Mxx Module Pins Description

Pins

Name

Voltage Domain

Internal Bias

after

Hardware

Reset

Drive

Strength

(mA)

Signal State

Description

GND

Not Applicable

Analog port

Ground

ADC_SD_0p

VIN_3V3

Not Applicable

Analog port

Sigma Delta ADC differential positive input 0 or Sigma Delta DAC positive output 0

ADC_SD_0n

VIN_3V3

Not Applicable

Analog port

Sigma Delta ADC differential negative input 0 or Sigma Delta DAC negative output 0

ADC_SD_1p

VIN_3V3

Not Applicable

Analog port

Sigma Delta ADC differential positive input 1

ADC_SD_1n

VIN_3V3

Not Applicable

Analog port

Sigma Delta ADC differential negative input 1

ADC_SD_2p

VIN_3V3

Not Applicable

Analog port

Sigma Delta ADC differential positive input 2

ADC_SD_2n

VIN_3V3

Not Applicable

Analog port

Sigma Delta ADC differential negative input 2

GND

Not Applicable

Analog Port

Ground

GND

Not Applicable

Analog Port

Ground

VRTC

Not Applicable

Analog port

Embedded Real Time Clock Power Supply

EXT_RTC_RESET_n

VRTC

None

Digital Input

Device Reset Input

RTC_IO_2 (see Note 2)

VRTC

None

RTC Digital Input/Output

Embedded Real Time Clock Input/Output 2

VPP

(see Note 7)

VPP

Not Applicable

Analog port

Programming Voltage for OTP Memory

GND (see Note 3)

Not Applicable

Analog port

Ground

VIN_3V3

Not Applicable

Analog port

Single Supply Port

Tab. 5 GS2101Mxx Module Pin Signal Description

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Pins

Name

Voltage

Domain

Internal Bias

after

Hardware

Reset

Drive

Strength

(mA)

Signal State

Description

GPIO10/PWM0 (see Note 3)

VIN_3V3

Pull-down

Digital Input/Output

GPIO/Pulse Width Modulator 0

GPIO9/I2C_CLK (see Note 3 and Note 5)

VIN_3V3

Pull-down

Digital Input/Output

GPIO/InterIntegrated Circuit Clock

GPIO8/I2C_DATA (see Note 3 and

Note 5)

VIN_3V3

Pull-down

Digital Input/Output

GPIO/InterIntegrated Circuit Data

GPIO32/SDIO_DA T2/ UART1_TX (see Note 3)

VIN_3V3

Pull-down

Digital Input/Output

GPIO/SDIO_D ATA Bit 2/UART1 Transmitter Output

GPIO33/SDIO_DA T3/ SPI0_CS_n_0 (see Note 3)

VIN_3V3

Pull-up

Digital Input/Output

GPIO/SDIO Data Bit 3/SPI0 Chip Select Input 0 from the HOST (Active Low)

GPIO34/SDIO_CM D/ SPI0_DIN (see Note 3)

VIN_3V3

Pull-down

Digital Input/Output

GPIO/SDIO Command Input/SPI0 Receive Data Input

GPIO35/SDIO_CL K/

SPI0_CLK (see Note 3)

VIN_3V3

Pull-down

Digital Input/Output

GPIO/SDIO Clock/SPI0 Clock Input from the HOST

GPIO36/SDIO_DA T0/

SPI0_DOUT (see Note

3) (see Errata E-1)

VIN_3V3

Pull-down

Digital Input/Output

GPIO/SD IO Data Bit 0/SPI0 Transmit Data Output to the HOST

GPIO37/ SDIO_DAT1_INT

(see Note 3 and Note 8)

VIN_3V3

Pull-down

Digital Input/Output

GPIO/4-bit SDIO DATA Bit 1/SDIO SPI Mode Interrupt

Tab. 5 GS2101Mxx Module Pin Signal Description (Continued)

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Pins

Name

Voltage Domain

Internal Bias after Hardware Reset

Drive Strength (mA)

Signal State

Description

Not Applicable

Not Connected 26

GND

Not Applicable

Analog Port

Ground

GPIO1/UART0_T X (see Note 3)

VIN_3V3

Pull-down

Digital Input/Output

GPIO/UART0 Transmitter Output.

GPIO25/UART0_ RTS (see Note 3 and Note 6)

VIN_3V3

Pull-down

Digital Input/Output

GPIO/UART0 Request to Send Output. This pin is used for Program Select.

GPIO0/UART0_R X (see Note 3)

VIN_3V3

Pull-down

Digital Input Output

GPIO/UART0 Receive Input

GPIO24/UART0_ CTS (see Note 3 and Note 6)

VIN_3V3

Pull-down

Digital Input/Output

GPIO/UART0 Clear to Send Input

GPIO31/PWM2 (see Note 3 and Note 4)

VIN_3V3

Pull-down

Digital Input/Output

GPIO/Puls e Width Modulation Output 2.

This pin is used for Program Mode.

GPIO30/PWM1 (see Note 3)

VIN_3V3

Pull-down

Digital Input/Output

GPIO/Pulse Width Modulation Output 1

GPIO0/UART0_R X (see Note 3)

VIN_3V3

Pull-down

Digital Input Output

GPIO/UART0 Receive Input

GPIO24/UART0_

CTS (see Note 3 and Note 6)

VIN_3V3

Pull-down

Digital Input/Output

GPIO/UART0

Clear to Send

Input

GPIO31/PWM2

(see Note 3 and

Note 4)

VIN_3V3

Pull-down

Digital Input/Output

GPIO/Puls

e Width

Modulation

Output 2.

This pin is used

for Program

Mode.

Tab. 5 GS2101Mxx Module Pin Signal Description (Continued)

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Pins

Name

Voltage Domain

Internal Bias after Hardware Reset

Drive Strength (mA)

Signal State

Description

GPIO30/PWM 1 (see Note 3)

VIN_3V3

Pull-down

Digital Input/Output

GPIO/Pulse Width Modulation

Output 1

GND

N/A

Analog Port

Ground

GPIO28/I2C_ DATA

(see Note 3 and Note 5)

VIN_3V3

Pull-down

Digital Input/Output

GPIO/InterIntegrated Circuit Data

JTAG_TCK

VIN_3V3

Pull-up

Digital Input

JTAG Test Clock

JTAG_TDO

VIN_3V3

Pull-down

Digital Output

JTAG Test Data Out

JTAG_TDI

VIN_3V3

Pull-up

Digital Input

JTAG Test Data In

JTAG_TMS

VIN_3V3

Pull-up

Digital Input

JTAG Test Mode Select

JTAG_TRST_ n

VIN_3V3

Pull-up

Digital Input

JTAG Test Mode Rest (Active Low)

GND

N/A

Analog Port

Ground

Tab. 5 GS2101Mxx Module Pin Signal Description (Continued)

Notes:

1. Recommend 10K external pull up resistor to VRTC.

2. Can be left as no connect.

3. Pins with drive strength 4, 12, and 16 have one pull resistor (either up or down, not both), which is enabled at reset.

4. This pin enables programming of the module. If GPIO31/PWM2 is high during reset or power on, then the GS2101M will wait for Flash download via UART0 or SPI0 interface. Route this pin on the base board so it can be pulled up to VIN_3V3 for programming the module.

5. If I2C interface is used, provide 2K Ohm pull-ups, to VIN_3V3, for I2C_CLK and I2C_DATA.

6. CTS and RTS signals indicate it is clear to send or ready to send when they are LOW. If signals are high, indicates device is not ready.

7. This pin is generally reserved for Telit use, but if a design requires to OTP during production, then design must consider the connection to this pin. Otherwise, it should be left as a No Connect.

8. In the Serial-to-Wi-Fi firmware when using the SPI interface this pin is

the host wake-up signal or the Ready to Send signal.

a. GPIO37 - when using the SPI interface this pin is the host wake-up

signal or the Ready to Send signal.

Errata

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E1. The SPI0_DOUT and SPI1_OUT signals do not disable their drive and become Hi-Z when the associated chip select pin is high. This applies to all pin MUX locations for the SPI_DOUT signals. If there are multiple write only devices on the same SPI bus, then this is not an issue. This only becomes an issue when there are other read/write devices on the same SPI bus. The workaround is to add an external buffer chip, such as 74LVC1G125 between the SPI_DOUT pin and the SPI bus, with the enable connected to the chip select signal.

3.1.2. GS2101M Pin MUX Function

The GS2101M pins have multiple functions that can be selected using MUX function by software. The table below shows the various MUX functions for each pin. Each pin can be independently configured. Table below shows the various mux functions for each pin. All I/O pins are GPIO inputs at reset. For pins that are inputs to functional blocks only one pin may be assigned to any input function. For example, UART1_RX may be assigned to GPIO9 but not to both GPIO9 and GPIO37.

Alternate Functions

Pin#

Pin Name

Internal

Pull

Resistor

Mux3

Mux4

Mux5

Mux7

Comments

GND

adc_sd_0p

adc_sd_0n

adc_sd_1p

adc_sd_1n

adc_sd_2p

adc_sd_2n

GND

VRTC

ext_rtc_reset_n

pull-up (u)

rtc_io_2

u/d

Alarm or

wake up pin

VPP

Programming voltage for OTP memory

GND

VIN_3V3

gpio10/pwm0

pull-down (d)

pwm0

uart1_tx

spi1_clk

clk_rtc

gpio9/i2c_clk

i2c_clk

uart1_rx

spi1_din

i2s_lrclk

gpio8/i2c_data

i2c_data

uart1_tx

spi1_dout

reserved

gpio32/sdio_dat2/u

d 4 sdio_data

wuart_tx

uart1_tx

spi1_cs_n_1

gpio33/sdio_dat3/s pi0_cs_n_0

u 4 sdio_data 3

reserved

uart1_rts

spi0_cs_n_0 21

gpio34/sdio_cmd/s

d 4 sdio_cmd

reserved

usart1_cts

spi0_din

gpio35/sdio_clk/spi 0_clk

d 4 sdio_clk

reserved

i2c_clk

spi0_clk

Note: only 4mA for i2C

Tab. 6 GS2101M Pin MUX Description

Alternate Functions Available

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Pin#

Pin Name

Internal

Pull

Resistor

Mux3

Mux4

Mux5

Mux7

Comments

gpio36/sdio_dat0_d

d 4 sdio_data0

reserved

i2c_data

spi0_dout1

gpio37/sdio_dat1_int

d 4 sdio_data1

wuart_rx

uart1_rx

spi0_cs_n_10

GND

gpio1/uart0_tx

d 4 uart0_tx

wuart_tx

pwm1

spi1_dout

gpio25/uart0_rts

uart0_rts

wuart_rts

spi1_cs_n_7

spi1_clk

gpio0_uart0_rx

d 4 uart0_rx

wuart_rx

pwm2

spi1_din

gpio24/uart0_cts

uart0_cts

wuart_cts

pwm0

spi1_cs_n_0

gpio31/pwm2

pwm2

spi1_dout

uart1_tx

wuart_tx

gpio30/pwm1

pwm1

spi1_din

uart1_rx

wuart_rx

GND

gpio28/i2c_data

i2c_data

spi1_clk

clk_hs_rc

spi1_cs_n_21

jtag_tck

jtag_tdo

jtag_tdi

jtag_tms

jtag_trst_n

GND

Tab. 6 GS2101M Pin MUX Description (Continued)

Note 1: The SPI0_DOUT and SPI1_OUT signals do not disable their drive and become Hi-Z when the associated chip select pin is high. This applies to all pin MUX locations for the SPI_DOUT signals. If there are multiple write only devices on the same SPI bus, then this is not an issue. This only becomes an issue when there are other read/write devices on the same SPI bus. The workaround is to add an external buffer chip, such as 74LVC1G125 between the SPI_DOUT pin and the SPI bus, with the enable connected to the chip select signal.

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3.1.3. GS2101M Program and Code Restore Options

Following table describes the options available for device program mode and code restore capabilities. The respective GPIO pins are sampled at reset by device and depending on the values seen on these pins goes into the appropriate mode. The code for the GS2101M resides on the internal flash of the module and up to two back-up copies could be stored in flash. If a software designer wants to restore the execution code to one of the backup copy, it can be accomplished by asserting the appropriate GPIO pins as shown in the table below during power up or reset.

Boot Control

Program Mode

(GPIO 31)

Program Select/Previous Restore

(GPIO 25)

Interfaces for Program Load

(see Note 1)

Normal boot

Previous Code Restore. Restores the prior code revision by invalidating the present code image. Will NOT invalidate the last remaining image.

Program Mode: UART0 @ 115.2Kbaud; nothing on GPIO15-18; SPI0 on SDIO pins. Note: this

is the default you get if you don’t pull the

Program Select pin high.

Program Mode using: UART0 @921.6Kbaud; SPI0 on GPIO15-18. Note: GPIO15-18 are only available on GS2000 SoC, and not on modules.

Tab. 7 GS2101M Pin Program and Code Restore

Note:

1. In Run Mode, boot ROM leaves all GPIO pins as input with pull resistor enabled until the flash code sets them otherwise. In Program Mode, only the pins required for the Program Mode specified interfaces are set to non-GPIO mode

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4. ELECTRICAL CHARACTERISTICS

This chapter describes the Telit® GS2101M electrical characteristics.

• Absolute Maximum Ratings

• Operating Conditions

• I/O DC Specifications

• Power Consumption

• 802.11 Radio Parameters

• Sigma Delta ADC Parameters

Absolute Maximum Ratings

Conditions beyond as shown in the following table may cause permanent damage to the GS2101Mxx, and must be avoided. Sustained operation, beyond the normal operating conditions, may affect the long-term reliability of the module

Parameter

Symbol

Minimum

Typical

Maximum

Unit

Storage Temperature

-55

+125

RTC Power Supply

VRTC

-0.5

4.0

Single Supply Port

VIN_3V3

-0.5

4.0

OTP Supply

VPP

TBD

Signal Pin Voltage

-0.3

Voltage Domain +0.3

Tab. 8 Absolute Maximum Ratings

Note:

1. Reference domain voltage is the Voltage Domain per section GS2101Mxx Module Pins Description. For limitations on state voltage ranges, please consult section on GS2101Mxx Module Pins Description.

Operating Conditions

Following table lists the operating conditions of the GS2101Mxx module

Parameter

Symbol

Minimum

Typical

Maximum

Unit

Extended

Temperature Range

-40

+85

RTC Power3

VRTC

2.7

3.3

3.6

Single Supply Port GS2101MIx

VIN_3V3

2.7

3.3

3.6

Signal Pin Voltage

0 Voltage Domain

VPP

5.5

5.75

6.0

Tab. 9 Operating Conditions

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Notes:

1. Reference domain voltage is the Voltage Domain per section GS2101Mxx Module Pins Description.

2. The VPP pin should be left floating when not doing OTP programming operations.

3. The VRTC power MUST be the same as the VIN_3V3 power.

I/O DC Specifications

4.3.1. I/O Digital Specifications (Tri-State) Pin Types 4mA, 12mA, and 16mA

The specifications for these I/O’s are given for voltage ranges: 2.7V to 3.6V.

4.3.1.1. I/O Digital Specifications for VDDIO=2.7V to 3.6V

Following table lists the parameters for I/O digital specification for VDDIO 2.7V to 3.6V for Pin Types 4mA, 12mA, and 16mA.

Parameter

Symbol

Minimum

Typical

Maximum

Unit

Note

I/O Supply Voltage

DDIO

2.7

3.3

3.6

Input Low Voltage

-0.3

0.3*V

DDIO

V Input High Voltage

0.7*V

DDIO

Input Leakage Current

μA

Pull up/down disabled

Tri-State Output

Leakage Current

μA

Pull up/down disabled

Pull-Up Resistor

34K

51K

100K

Pull-Down Resistor

35K

51K

100K

Output Low Voltage

0.4

V Output High Voltage

0.8*V

DDIO

Low Level Output Current @ V

max

4 12 16

Pin Type 4mA Pint Type 12mA Pint Type 16mA

High Level Output Current @ V

min

12 16

Pin Type 4mA Pin Type 12mA Pin Type 16mA

Output rise time 10% to 90% load, 30pF

TRLH

3.1

1.8

1.5

4.2

2.4

2.0

7 4

3.4

Pin Type 4mA Pint Type 12mA Pin Type 16mA

Output fall time 90% to 10% load, 30pF

TFHL

3.8

1.8

1.5

5.0

2.5

2.1

4.2

3.5

Pin Type 4mA Pin Type 12mA Pin Type 16mA

Tab. 10 I/O Digital Parameters for VDDIO=2.7V to 3.6V

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4.3.2. RTC I/O Specifications

Following table lists the RTC I/O parameters.

Parameter

Symbol

Minimum

Typical

Maximum

Unit

Note

Supply

VRTC

1.6

3.6

Input

Low

-.03

0.3*V

RTC

Input

High

0.7*V

RTC

VRTC+0.3

Input Leakage

0.1

μA

Pullup

1 μA

Pulldo wn

μA

Output

Low

0.4

IL=1mA or 4mA*

Output

High

VRTC-0.4

IL=1mA or 4mA*

Tab. 11 RTC I/O Parameters

*RTC I/O’s are software selectable as 1mA or 4mA drive strength

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Power Consumption

Following table lists the power consumption for the GS2101Mxx. Typical conditions are:

VIN_3V3=VRTC=3.3V Temp=25oC.

System State

Current (Typical)

Standby (VIN_3V3 ON), Note 4

TBD μA

Deep Sleep (see Notes 1 and 2)

615 μA

WLAN Continuous Transmit (1 Mbps, 15 dBm)

257 mA

WLAN Continuous Receive (1 Mbps)

131 mA

PS-Poll, DTIM=1, 1mS beacon, Note 3

2.80 mA

PS-Poll, DTIM=1, 2mS beacon, Note 3

4.02 mA

PS-Poll, DTIM=3, 1mS beacon, Note 3

1.52 mA

PS-Poll, DTIM=3, 2mS beacon, Note 3

1.90 mA

PS-Poll, DTIM=10, 1mS beacon, Note 3

1.02 μA

PS-Poll, DTIM=10, 2mS beacon, Note 3

1.17 μA

Tab. 12 Power Consumption in Different States

Notes:

1. Depends on firmware version.

2. One Sigma (+200μA).

3. Average current. PS-POLL currents given for both 1mS beacon duration and 2mS beacon. DTIM1, DTIM3, and DTIM10 use deep sleep between beacons.

4. Software currently does not support Standby mode for GS2101M.

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802.11 Radio Parameters

Following table lists the 802.11 Radio parameters. Test conditions are: VIN_3V3=VRTC=3.3V Temp=25oC.

Parameter

Minimum

Typical

Maximum

Unit

Notes

RF Frequency Range

2400

2497

MHz

N/A

Radio bit rate

HT2

Mbps

N/A

Transmit/Receive Specification for GS2101M

Output power (average)

14.5 13 14 14 12 14 14

dBm

11b, 1Mbps 11b,5.5Mbps 11b, 11Mbps 11g, 6Mbps 11g, 18Mbps 11g, 54Mbps 11n, MCS0 11n, MCS3 11n, MCS7

Spectrum Mask

dBr

Meets 802.11 requirement for selected data rates

Receive Sensitivity at antenna port

-90

-84

-86

-71

-86

-67

dBm

11b, 1Mbps, BPSK/DSSS 11b, 11Mbps 11g, 6Mbps 11g, 54Mbps, 64-QAM/OFDM 11n, MSC0 11n, MCS7, 64-QAM/OFDM

Tab. 13 802.11 Radio Parameters - (Typical - Nominal Conditions)

NOTICE: TX output power and RX sensitivity are firmware dependent. All the values provided for these parameters are measured at the antenna port based on 5.2.1 GA firmware.

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Sigma Delta ADC Parameters

Following table lists the Sigma Delta ADC parameters. Test conditions are: VIN_3V3=VRTC=3.3V Temp=25oC.

Parameter

Minimum

Typical

Maximum

Unit

Notes

D/A DC Performance (see Note 1)

Resolution

Bits

Full Scale

2.4 0 V

See Note 2

Output common-mode

VIN_3V3/2

Gain Error

- - +5

See Note 2

Offset - -

+20

D/A Dynamic Performance

Data Rate

32 - 80

KHz

Clock Frequency

8 - 20

MHz

See Note 3

Signal to Noise Ratio

67 - dB

See Note 4

Total

Harmonic

-74

Output load

KΩ

Output load

A/D DC Performance (Preamplifier Gain=0db)

Resolution

Bits

Full Scale

2.0

Input common-

VIN_3V3/2

Gain Error

Offset

+10

LSB

A/D Dynamic Performance (Preamplifier Gain=0db)

Data Rate

KHz

Clock Frequency

8 20

MHz

See Note 3

Signal-toNoise Ratio

80 dB

See Note 4

Total

Harmonic

-85

See Note 4

Input Resistance

100

KΩ

Tab. 14 ADC Parameters

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Notes:

1. The D/A output is fully differential. The Analog power supply is

3.3V +/- 10%.

2. Full scale (FS) can be trimmed in the reference generator. The gain error specified is on top of the reference level error.

3. The master clock frequency is always 250 times higher than the data clock rate.

4. Assumes a -1-dB full scale input and corrected for full scale. Fin can be from 0 to 10KHz. The SNR is met for all master clock frequencies.

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5. PACKAGE AND LAYOUT GUIDELINES

This chapter describes the Telit® GS2101M package and layout guidelines.

• GS2101Mxx Recommended PCB Footprint and Dimensions

GS2101Mxx Recommended PCB Footprint and Dimensions

Fig. 4, page 46 shows the GS2101MIx Module PCB Footprint. Fig. 5, page 47 shows the GS2101MIx Module Dimensions.

Fig. 4 GS2101MIx Module Recommended PCB Footprint (in millimeters)

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Fig. 5 GS2101MIx Module Dimensions (in millimeters)

Notes:

1. All Dimensions are in millimeters (mm).

2. For Boards using PCB Antenna, we recommend:

– Have Only Air on BOTH sides of the antenna. – Hang Antenna over edge of the base board (best) – Or Cut notch in base board under antenna area

– 5mm beyond module edge on both sides is good – Full module width is minimum

– No metal or FR4 encircling antenna area

– Antenna at edge of base board, not interior of base

board

– Nothing conductive near antenna (for example battery,

display, wire)

3. The 3 RF shield mounting holes and 2 test fixture alignment holes (circled in red in Fig. 4, page 44) have exposed metal. These areas must not have metal on the customer board.

4. For best RF performance, we recommend:

– Using the power (PWR) or the GND planes from module

back to the power supply.

– Isolating PWR/GND from high frequency or high current

components. For example, a notch in GND plane to isolate from host µC.

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– Using at least 3 vias when either power or GND change

layers. This applies particularly at the module GND pins and at the VIN_3V3 pins.

– Providing a 10 µF capacitor at the VIN_3V3 pin and using 3

vias both sides of the capacitor.

– Keep high speed signals away from RF areas of the module.

5. For the area under Module, other than an antenna area, we recommend two options:

– No metal of any kind under the module “not on any layer” – Having a full GND plane under module (layer 1 or layer 2)

with no “HOT” vias under module (over 100KHz) and may route signals below GND plane. Also, no metal traces are to be present in the circle, around the shield and alignment holes. This option is best for 2 layer boards. If the GND plane is on layer 1, then use thermal relief pads for the GND pins of the module footprint.

6. If any metal is present on layer 1, then extra thick solder mask under the module is required.

7. In performing SMT or manual soldering of the module to the base board, first align the row of pins from #15 through #26 onto the base board and then match the other two rows.

In addition to the guidelines, note the following suggestions:

1. External Bypass capacitors for all module supplies should be as close as possible to the module pins.

2. Never place the antenna very close to metallic objects.

3. External monopole antennas need a reasonable ground plane area for antenna efficiency.

4. Do not use a metal or metalized plastic for the end product enclosure when using an on-board antenna.

5. If the module is enclosed in a plastic case, have reasonable clearance from the plastic case to the on-board antenna.

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5.1.1. Surface Mount Assembly

The following figure shows the reflow profile. The recommended reflow parameters are summarized in the following table.

Fig. 6 Reflow Temperature Profile

Preheat

Temperature Ramp up rate for (A)

1.5~3.5 oC/s

Pre-heat time (B)

80 to 130 seconds

Pre-heat starting temperature (C1)

125 to 135 oC

Pre-heat ending temperature (C2)

180 to 200 oC

Heating

Peak Temperature range (D)

240 to 250 oC

Melting time4 that is the time over 220 oC (E)

50 to 75 seconds

Cool Down Ramp (F)

>2 oC/s

Tab. 15 Recommended Reflow Parameters

Notes:

1. Perform an adequate test in advance as the reflow temperature profile will vary according to the conditions of the parts and boards, and the specifications of the reflow furnace.

2. Max number of reflow supported are two.

3. Temperature uniformity inside the IR reflow oven must be

tightly controlled and multiple thermocouples should be used. An example of possible thermocouple locations is given in Fig. 7. The locations should also include multiple points inside the module RF shield (for example TC1, TC5, and TC7 in Fig. 7). The temperature profile of all

thermocouples must meet the requirements Tab. 15, page

50.

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4. Pay close attention to “Melting Time over 220ºC”. Sufficient time is necessary to completely melt all solder.

5. Be careful about the rapid temperature rise in the preheat zone as it may cause excessive slumping of the solder paste.

6. If the preheat is insufficient, rather large solder balls tend to be generated. Conversely, if performed excessively, fine balls and large balls will generate in clusters at a time.

7. If the temperature is too low, non-melting tends to be caused in the area with a large heat capacity after re-flow.

8. Be careful about the sudden rise in temperature as it may worsen the slump of solder paste.

9. Be careful about slow cooling as it may cause the positional shift of parts and decline in joining at times.

10. A no clean flux should be used during SMT process.

11. The modules are shipped in sealed trays with the following conditions (see Fig. 8, page 52).

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Fig. 7 Thermocouple Locations

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Fig. 8 Module Moisture Conditions

Page 53

Telit Wireless Solutions GS2101M User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

COPYRIGHT

USAGE AND DISCLOSURE RESTRICTIONS

I. License Agreements

II. Copyrighted Materials

III. High Risk Materials

IV. Trademarks

V. Third Party Rights

CONTENTS

About This Manual

1. GS2101M OVERVIEW

• Product Overview

• GS2101M Module Product Features

2. GS2101M ARCHITECTURE

• Architecture Description

2.1.1. Wireless LAN and System Control Subsystem

2.1.2. On-board Antenna / RF Port / Radio

2.1.2.1. 802.11 MAC

2.1.2.2. 802.11 PHY

2.1.2.3. RF/Analog

2.1.3. Network Services Subsystem

2.1.3.1. APP CPU

2.1.3.2. Crypto Engine

2.1.4. Memory Subsystem

2.1.4.1. SRAM

2.1.4.2. ROM

2.1.4.3. OTP ROM

2.1.4.4. Flash Interface

2.1.5. Clocks

2.1.6. Real Time Clock (RTC) Overview

2.1.6.1. RTC Main Features

2.1.6.2. Real Time Clock Counter

2.1.6.3. RTC I/O

2.1.7. GS2101M Peripherals

2.1.7.1. SDIO Interface

2.1.7.2. SPI Interface

2.1.7.3. UART Interface

2.1.7.4. I2C Interface

2.1.7.5. GPIO

2.1.7.6. Sigma Delta ADC

2.1.7.7. PWM

2.1.8. System States

2.1.9. Power Supply

3. PIN-OUT AND SIGNAL DESCRIPTION

GS2101Mxx Device Pin-out

3.1.1. GS2101Mxx Module Pins Description

3.1.2. GS2101M Pin MUX Function

3.1.3. GS2101M Program and Code Restore Options

4. ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Operating Conditions

I/O DC Specifications

4.3.1. I/O Digital Specifications (Tri-State) Pin Types 4mA, 12mA, and 16mA

4.3.1.1. I/O Digital Specifications for VDDIO=2.7V to 3.6V

4.3.2. RTC I/O Specifications

Power Consumption

802.11 Radio Parameters

Sigma Delta ADC Parameters

5. PACKAGE AND LAYOUT GUIDELINES

GS2101Mxx Recommended PCB Footprint and Dimensions

5.1.1. Surface Mount Assembly