GS2101M Low Power Wi-Fi Module Hardware User Guide
TELIT MAY MAKE CHANGES TO SPECIFICATI ONS AND PRODUCT
DESCRIPTIONS AT ANY TIME, WITHOUT NOTICE.
NOTICES
LIMITATION OF LIABILITY
While reasonable efforts have been made to assure the accuracy of this document, Telit
assumes no liability resulting from any inaccuracies or omissions in this document, or from
use of the information obtained herein. The information in this document has been
carefully checked and is believed to be reliable. However, no responsibility is assumed for
inaccuracies or omissions. Telit reserves the right to make changes to any products
described herein and reserves the right to revise this document and to make changes from
time to time in the content hereof with no obligation to notify any person of revisions or
changes. Telit does not assume any liability arising out of the application or use of any
product, software, or circuit described herein; neither does it convey license under its
patent rights or the rights of others.
It is possible that this publication may contain references to, or information about Telit
products (machines and programs), programming, or services that are not announced in
your country. Such references or information must not be construed to mean that Telit
intends to announce such Telit products, programming, or services in your country.
Telit assumes no liability whatsoever, and disclaims any express or implied warranty,
relating to sale and/or use of Telit products including liability or warranties relating to
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components in medical, lifesaving, or life-sustaining applications.
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This Telit manual and contents are owned by Telit and/or its licensors and protected
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this manual is subject to limitations and restrictions imposed by applicable licenses and
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sale of a product.
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GS2101M Low Power Wi-Fi Module Hardware User Guide
USAGE AND DISCLOSURE RESTRICTIONS
I. License Agreements
The software described in this document is the property of Telit and its licensors. It is
furnished by express license agreement only and may be used only in accordance with
the terms of such an agreement.
II. Copyrighted Materials
Software and documentation are copyrighted materials. Making unauthorized copies is
prohibited by law.
transmitted, transcribed, stored in a retrieval system, or translated into any language or
computer language, in any form or by any means, without prior written permission of Telit.
III. High Risk Materials
Components, units, or third-party products used in the product described herein are NOT
fault-tolerant and are NOT designed, manufactured, or intended for use as on-line control
equipment in the following hazardous environments requiring fail-safe controls: the
operation of Nuclear Facilities, Aircraft Navigation or Aircraft Communication Systems, Air
Traffic Control, Life Support, or Weapons Systems (High Risk Activities). Telit and its
supplier(s) specifically disclaim any expressed or implied warranty of fitness for such HighRisk Activities.
No part of the software or documentation may be reproduced,
IV. Trademarks
Telit, Telit and stylized Logos are registered Trademarks. All other product or service
names are the property of their respective owners.
V. Third Party Rights
The software may include Third Party Right software. In this case, you agree to comply
with all terms and conditions imposed on you in respect of such separate software. In
addition to Third Party Terms, the disclaimer of warranty and limitation of liability provisions
in this License shall apply to the Third Party Right software.
TELIT HEREBY DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED
FROM ANY THIRD PARTIES REGARDING ANY SEPARATE FILES, ANY THIRD
PARTY MATERIALS INCLUDED IN THE SOFTWARE, ANY THIRD PARTY MATERIALS
FROM WHICH THE SOFTWARE IS DERIVED (COLLECTIVELY “OTHER CODE”), AND
THE USE OF ANY OR ALL THE OTHER CODE IN CONNECTION WITH THE
SOFTWARE, INCLUDING (WITHOUT LIMITATION) ANY WARRANTIES OF
SATISFACTORY QUALITY OR FITNESS FOR A PARTICULAR PURPOSE.
NO THIRD PARTY LICENSORS OF OTHER CODE SHALL HAVE ANY LIABILITY FOR
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CONSEQUENTIAL DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS),
HOWEVER CAUSED AND WHETHER MADE UNDER C ONTRACT, TORT OR O THER
LEGAL THEORY, ARISING IN ANY WAY OUT OF THE USE OR DISTRIBUTION OF
THE OTHER CODE OR THE EXERCISE OF ANY RIGHTS GRANTED UNDER EITHER
OR BOTH THIS LICENSE AND THE LEGAL TERMS APPLICABLE TO ANY SEPARATE
FILES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
www.Telit.com
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GS2101M Low Power Wi-Fi Module Hardware User Guide
GS2101M Low Power Wi-Fi Module Hardware User Guide
About this manual
This manual describes the GS2101M Low Power module hardware specification. Refer
to the following sections:
• Revision History
• Audience
• Standards
• Certifications
• Documentation Conventions
• Text Conventions
• Related Documents
• Documentation Feedback
• Contact Information
• Returning Products to Telit
• Guidelines for Packing Components for Shipment
• Accessing the Telit Wi-Fi Portal
• Ordering Information
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GS2101M Low Power Wi-Fi Module Hardware User Guide
FCC, IC,
WPS 2.0
Enterprise, WPA and WPA2 Personal
Revision History
Version DateRemarks
0May 2016Initial release.
1 July 2017
2 October 2017
3 November 2017
4 December 2017 Added details to 2.1.7.6Sigma Delta ADC
5 September 2018 Updated the technical support information.
6 February 2019
7 November 2019
8 April 2020
Updated 802.11 Output Power, RF Frequency Range inTab.
13 802.11 Radio Parameters - (Typical - Nominal Conditions)
Updated Output Power in Tab. 13 802.11 Radio Parameters -
(Typical - Nominal Conditions)
Updated Data rates for 802.11n in GS2101M Overview and
2.1.2.2802.11 PHY
Updated Tab. 5 GS2101Mxx Module Pin Signal Description.
Updated Output Power in Tab. 13 802.11 Radio Parameters -
(Typical - Nominal Conditions)
Added section Conformity Assessment Issues with Anatel
Regulatory Notices.
Updated the Certifications section for CE, ETSI, KCC, and
Anatel Radio regulatory certificates.
Tab. 1 Revision History
Audience
This manual is designed to help system designers build low power, cost effective, flexible
platforms to add Wi-Fi connectivity for embedded device applications using the Telit
GS2101M based module.
Standards
The standards that are supported by the Telit modules are IEEE 802.11b/g/n.
Certifications
GainSpan GS2101M Low Power Wi-Fi Module has Certification Compliance for the
following:
CategoryCertification
Radio Regulatory Certificates
Wi-Fi Alliance Certificates
TELEC, RED, CE, ETSI, KCC and Anatel.
, WMM, WMM-PS, WPA and WPA2
.
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GS2101M Low Power Wi-Fi Module Hardware User Guide
Command
syntax
monospaced
font
This monospaced font represents command strings entered on a
AT XXXX
Gives specific details about a parameter.
UPPERCASE
Variable
parameter
<Data> DATA
Indicates user input. Enter a value according to the descriptions that
follow. Each uppercased token expands into one or more other token.
Lowercase
Keyword
parameter
Indicates keywords. Enter values exactly as sho wn in the command
[ ]
Square
brackets
Enclose optional parameters. Choose none; or sele ct one or m ore an
?
Question mark
[parm1 l parm2 l parm 3]
Conformity Assessment Issues
Anatel Regulatory Notices
HOMOLOGATION:00527-18-02618
Documentation Conventions
This manual uses the following text and syntax conventions:
– Special text fonts represent particular commands, keywords, variables, or
window sessions
– Color text indicates cross-reference hyperlinks to supplemental information
– Command notation indicates commands, subcommands, or command
elements
Following tabledescribes the text conventions used in this manual for software procedures
that are explained using the AT command line interface.
Convention Type Description
command line and sample source code.
Proportional font
description
description.
unlimited number of times each. Do not enter brac kets as parts of any
command.
Used with the square brackets to limit the immediately following token
to one occurrence.
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GS2101M Low Power Wi-Fi Module Hardware User Guide
<ESC>
Escape
sequence
Each escape sequence <ESC> starts with the ASCII character 27(0x1B).
This is equivalent to the Escape Key.
<CR>
Carriage return
< ESC>C
Each command is terminated by a carriage
return.
<LF>
Line feed
Each command is terminated by a line feed.
<CR<LF>
Carriage
return
Line feed
Each response is started with a carriage return and line feed with some
< >
Enclose a numeric range, endpoints inclusive. Do not enter
angle brackets as part of any command.
<SSID>
Separates the variable from explanatory text. Is entered as
part of the command.
=
PROCESSID = <CID>
Allow the repetition of the element that immediately follows it
multiple times. Do not enter as part of the command.
.
dot
(period)
AA:NN can be expanded to 1:01 1:02 1:03
IPv04-style address.
A.B.C.D
IP address
10.0.11.123
IPv6-style address.
X:X::X:X
IPv6 IP address
3ffe:506::1
Where the :: represents all 0x for those address components not
explicitly given.
exceptions.
Angle brackets
Equal sign
Line
End -to-line input
token
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Indicates user input of any string, including spaces. No other
parameters may be entered after input for this token.
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GS2101M Low Power Wi-Fi Module Hardware User Guide
WORD
string of words
Single token
Indicates user input of any contagious string (excluding
spaces).
Singlewordnospaces
Tab. 2 Document Conventions
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GS2101M Low Power Wi-Fi Module Hardware User Guide
This information MUST be
Alerts the user to important points about
Text Conventions
Tip or Information – Provides advice and suggestions that may be
useful when integrating the module.
followed, or catastrophic equipment failure or bodily injury m ay occur.
Caution or Warning –
integrating the module, if these points are not followed, the module
and end user equipment may fail or malfunction.
All dates are in ISO 8601 format, i.e. YYYY-MM-DD.
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GS2101M Low Power Wi-Fi Module Hardware User Guide
1VV0301416
GS2101M Evaluation Board
Provides an easy to follow
1VV0301498
GS2101M Serial-to-Wi-Fi
Provides a complete listing of
series modules.
1VV0301444
GS2K S2W Use Case
Provides references for using
1VV0301509
GS2xxxM Customer Hardware
Hardware Design Guide for
1VV0301499
GS2101M IP-to-Wi-Fi
Provides a complete listing of
Related Documents
The Telit documentation suite listed below, includes the part number, documentation name,
and a description of the document. The documents are available from the Telit Wi-Fi Portal.
For details, refer to Accessing the Telit Wi-Fi Portal
Part Number Document Title Description
Quick Start Guide
Adapter Command Reference
Guide
Reference Guide
Design Guidelines
guide on how to unpack and
setup Telit GS2000 based
module kit for the GS2011M
and GS2100M modules.
AT serial commands, including
configuration examples for
initiating, maintaining, and
evaluating Telit Wi-Fi GS2101M
GainSpan AT commands and
its usage in different scenarios
using different features and
protocols.
GS2000 modules.
1VV0301395 Rev 8.0 Page 14 of 54 2020-04-28
Adapter Command
Reference Guide
Tab. 3 Documentation Lists
AT serial commands, including
configuration examples for
initiating, maintaining, and
evaluation IP-to-Wi-Fi GS2000
based modules.
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GS2101M Low Power Wi-Fi Module Hardware User Guide
Documentation Feedback
We encourage you to provide feedback, comments, and suggestions so that we can
improve the documentation. You can send your comments by logging into Telit,
https://wifi.telit.com/secure/login
information with your comments:
– Document name
– URL or page number
– Hardware release version (if applicable)
– Software release version (if applicable)
. If you are using email, be sure to include the following
Contact Information
For general contact, technical support services, technical questions and to report
documentation errors contact Telit Technical Support at:
TS-SRD@telit.com
We recommend adding “Wi-Fi” in subject of the email. For example, the subject of email
can be “Wi-Fi: Your actual issue or question in brief” like “Wi-Fi: SPI Driver Issue”.
Also, in description of your email, please provide details about the issue, product and
module including software firmware version, module version and type, application being
used, customizations done to application, use case, issue frequency, and ability to
recreate it among other things wherever applicable.
Alternatively, for more Technical Support information or assistance, perform the following
steps:
1. Visit http://www.telit.com
the Telit Wi- Fi Portal.
2. Click Access the Portal Here icon which will direct you to the Telit Wi-Fi portal
https://wifi.telit.com/secure/login
1. Log in with your customer Email and Password.
2. Select the Location.
3. Select Q&A tab.
4. Select Ask a New Question.
5. Enter your technical support question, product information, and a brief description.
, go to Products> Wi-Fi and Blue-tooth, then scroll down to
For detailed information about where you can buy the Telit modules or for
recommendations on accessories and components visit:
http://www.telit.com
Our aim is to make this guide as helpful as possible. Keep us informed of your comments
and suggestions for improvements. Telit appreciates feedback from the users of our
information.
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GS2101M Low Power Wi-Fi Module Hardware User Guide
Returning Products to Telit
If a problem cannot be resolved by Telit technical support, a Return Material Authorization
(RMA) is issued. This number is used to track the returned material at the factory and to
return repaired or new components to the customer as needed.
NOTICE:
Do not return any components to Telit unless you have first obtained an
RMA number. Telit reserves the right to refuse shipments that do not have
an RMA. Refused shipments will be returned to the customer by collecting
freight.
To return a hardware component:
1. Determine the part number and serial number of the component.
2. Obtain an RMA number from Sales/Distributor Representative.
3. Provide the following information in an e-mail or during the telephone call:
– Part number and serial number of components
– Your name, organization name, telephone number, and fax number
– Description of the failure
4. The support representative validates your request and issues an RMA
number for return of the components.
5. Pack the component for shipment.
Guidelines for Packing Components for Shipment
To pack and ship individual components:
– When you return components, make sure they are adequately protected
with packing materials and packed so that the pieces are prevented from
moving around inside the carton.
– Use the original shipping materials if they are available.
– Place individual components in electrostatic bags.
– Write the RMA number on the exterior of the box to ensure proper
tracking.
CAUTION!
Do not stack any of the components.
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GS2101M Low Power Wi-Fi Module Hardware User Guide
Accessing the Telit Wi-Fi Portal
To find the latest version of Telit documentation supporting the Telit product release you
are interested in, you can search the Telit Wi-Fi Portal website by performing the following
steps:
NOTICE:
You must first contact Telit to set up an account and obtain a customer
user name and password before you can access the Telit Wi-Fi Portal.
`
1. Visit http://www.telit.com, go to IoT Products & Solutions > Wi-Fi and Blue-tooth, then scroll down the Telit Wi- Fi Portal.
2. Click Access the Portal Here icon which will direct you to the Telit Wi-Fi
portal https://wifi.telit.com/secure/login
3. Log in using your customer Email and Password.
4. Click the Getting Started tab to view a Quick Start tutorial on how to use
various features within the Telit Wi-Fi Portal.
5. Click the Agreements tab to download and upload the SLA for ADK and
SDK respectively.
6. Click on the Documents tab to search, download, and print product
documentation.
7. Click the Software tab to search and download the latest software
versions.
8. Click the Kits Purchased tab to view customer account history.
9. Click the Legal Documents tab to view Non-Disclosure Agreement
(NDA).
10. Click the Certifications tab to view certifications.
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GS2101M Low Power Wi-Fi Module Hardware User Guide
Ordering
Number
Low power module with on-board PCB antenna
GS2101MIP
1.0
Low power module with external antenna
GS2101MIE
1.0
Ordering Information
To order Telit’s GS2101Mxx low power module contact a Telit Sales/Distributor
Representative. Following table lists the Telit device information.
Device Description
NOTICE:
Modules ship with test code ONLY. Designers must first program the
modules with a released firmware version. Designers should bring out
GPIO31 pin (option to pull this pin to VDDIO during reset or power-on) and
UART0 or SPI0 pins to enable programming of firmware into the module.
For details refer to the Programming the Telit Modules document.
Revision
Tab. 4 GS2101Mxx Ordering Information
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GS2101M Low Power Wi-Fi Module Hardware User Guide
1. GS2101M OVERVIEW
This chapter describes the Telit® GS2101M low power module hardware specification
overview.
• Product Overview
• GS2101M Module Product Features
Product Overview
The GS2101M based modules provide cost effective, low power, and flexible platform to
add Wi-Fi® connectivity for embedded devices for a variety of applications, such as
wireless sensors and thermostats. It uses the GS2000 SoC, which combines ARM®
Cortex M3-based processors with a 802.11b/g/n Radio, MAC, security, & PHY functions,
RTC and SRAM, up to 4 MB FLASH, and on-board and off module certified antenna
options. The module provides a Wi-Fi and regulatory certified IEEE 802.11b/g/n radio with
concurrent network processing services for variety of applications, while leverage existing
802.11 wireless network infrastructures.
GS2101M Module Product Features
• Family of modules with different antenna options:
• GS2101MIx 18mm (0.71in) x 25 mm (0.98in) x 2.7mm (0.106in) 40-pin
– Two (2) multi-purpose UART interfaces operating in full-duplex mode
– 16450/16550 compatible
– Optional support for flow control using RTS/CTS signaling for high
data transfer rates
– Standard baud rate from 9600 bps up to 921.6K baud (additional
support for higher non-standard rates using baud rates up to 7.5 MHz)
•GPIOs:
– Up to 16 configurable general purpose I/O
• Single 3.3V supply option
• Three (3) PWM output
• I2C master/slave interface
• Three (3) 16-bit Sigma Delta ADC channels, for sensors and
measurements
•One (1) RTC I/O that can be configured as:
– Alarm input to asynchronously awaken the chip
– Support control outputs for sensors
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GS2101M Low Power Wi-Fi Module Hardware User Guide
• Embedded RTC (Real Time Clock) can run directly from battery
GS2101M Low Power Wi-Fi Module Hardware User Guide
2. GS2101M ARCHITECTURE
This chapter describes the Telit
® GS2101M Low Power module architecture.
•Architecture Description
Architecture Description
The Telit GS2101M module (see Fig. 1, page 21) is based on a highly integrated GS2000
ultra low power Wi-Fi System-on-Chip (SoC) that contains the following:
•The GS2000 SoC contains two ARM Cortex M3 CPUs, a compatible 802.11
radio, security, on-chip memory, and variety of peripherals in a single
package.
– One ARM core is dedicated to Networking Subsystems, and the other
dedicated to Wireless LAN Subsystems.
– The module carries an 802.11/g/n radio with on-board 32KHz & 40MHz
crystal circuitries, RF, and on-board antenna or external antenna
options.
•On module 4 Mega Byte FLASH device that contains the user embedded
applications and data such as web pages.
•Variety of interfaces are available such as two UART blocks using only two
data lines per port with optional hardware flow controls, two SPI blocks (one
SDIO is shared function with one for the SPI interfaces), I2C with Master or
slave operation, JTAG port, three 16-bit Sigma-Delta ADCs capable of
running at up to 80K samples/Sec., GPIO’s, and LED Drivers/GPIO with
16mA capabilities.
•GS2101Mxx has a VRTC pin that is generally connected to always
available power source such as battery or line power. This provides power
to the Real Time Clock (RTC) block on the SoC. The module also has
VIN_3V3 power supply input to provide the logic signal level for the I/O pins.
The VRTC and VIN_3V3 pins should always be connected to the same
power source.
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GS2101M Low Power Wi-Fi Module Hardware User Guide
Fig. 1 GS2101M Block Diagram
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GS2101M Low Power Wi-Fi Module Hardware User Guide
2.1.1. Wireless LAN and System Control Subsystem
The WLAN CPU subsystem consists of the WLAN CPU, its ROM, RAM, 802.11b/g/n
MAC/PHY, and peripherals. This CPU is intended primarily to implement the 802.11 MAC
protocols. The CPU system has GPIO, Timer, and Watchdog for general use. A UART is
provided as a debug interface. A SPI interface is provided for specific application needs.
The WLAN CPU can access the RTC registers through an asynchronous AHB bridge.
WLAN CPU has only Flash read access to the on-board flash memory. The WLAN
subsystem interacts with the App subsystem through a set of mailboxes and shared dual–
port memories.
The CPUs provide debug access through a JTAG/serial port. For GS2101M module, the
complete JTAG port is brought out for both CPUs. The CPUs also include code and data
trace and watch point logic to assist in-system debugging of SW.
The WLAN subsystem includes an integrated power amplifier. In addition, it contains
hardware support for AES-CCMP encryption (for WPA2) and RC4 encryption (for WEP &
WPA TKIP) encryption/decryption.
2.1.2. On-board Antenna/RF Port/Radio
The GS2101Mxx modules have fully integrated RF frequency synthesizer, reference clock,
and PA. Both TX and RX chain in the module incorporate internal power control loops. The
GS2101Mxx modules also incorporate an on-board antenna option or an external antenna
connector.
2.1.2.1. 802.11 MAC
The 802.11 MAC implements all time critical functionality of the 802.11b/g/n protocols. It
works in conjunction with the MAC SW running on the CPU to implement the complete
MAC functionality. It interfaces with the PHY to initiate transmit/receive and CCA. The
PHY registers are programmed indirectly through the MAC block. The MAC interfaces to
the system bus and uses DMA to fetch transmit packet data and save receive packet data.
The MAC SW exchanges packet data with the HW though packet descriptors and pointers.
Key Features
• Compliant to IEEE 802.11 (2012)
• Compliant to IEEE 802.11b/g/n (11n – 2009)
• Long and short preamble generation on frame-by-frame basis for 11b frames
• Transmit rate adaptation
• Transmit power control
• Frame aggregation (AMPDU, AMSDU)
• Block ACK (Immediate, Compressed)
• RTS/CTS, CTS-to-self frame sequences and SIFS
• Client and AP modes support
• Encryption support including: AES-CCMP, legacy WPA-TKIP, legacy WEP ciphers
and key management
• Wi-Fi Protected Setup 2.0 (WPS2.0) including both PIN and push button options
• 802.11e based QoS (including WMM, WMM-PS)
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GS2101M Low Power Wi-Fi Module Hardware User Guide
2.1.2.2. 802.11 PHY
The 802.11 PHY implements all the standard required functionality and Telit specific
functionality for 802.11b/g/n protocols. It also implements the Radar detection functionality
to support 802.11h. The PHY implements the complete baseband Tx and Rx pipeline. It
interfaces with the MAC to perform transmit and receive operations. It interfaces directly
to the ADC and DAC. The PHY implements the Transmit power control, receive Automatic
Gain Control and other RF control signals to enable transmit and receive. The PHY also
computes the CCA for MAC use.
Key Features
• Compliant to 2.4GHz IEEE 802.11b/g/n (11n – 2009)
• Support 802.11g/n OFDM with BPSK, QPSK, 16-QAM and 64-QAM; 802.11b with
• Support Full (800ns) & Half (400ns) Guard Interval (GI) modes (SGI and LGI)
• Support Space time block coding (STBC) for receive direction
• Complete front-end radio integration including PA, LNA and RF Switch
2.1.2.3. RF/Analog
The RF/Analog is a single RF transceiver for IEEE 802.11b/g/n (WLAN). The RF Interface
block provides the access to the RF and analog control and status to the CPU. This block
is accessible only from the WLAN CPU. It implements registers to write static control words.
It provides read only register interface to read static status. It generates the dynamic control
signals required for TX and RX based on the PHY signals. The AGC look up table to map
the gain to RF gain control word is implemented in this block.
2.1.3. Network Services Subsystem
2.1.3.1. APP CPU
The Network services subsystem consists of an APP CPU which is based on an ARM
CORTEX M3 core. It incorporates an AHB interface and a JTAG debug interface. The
network RTOS, network stack, and customer application code run on this CPU.
2.1.3.2. Crypto Engine
The Network services subsystem contains a separate hardware crypto engine that provides
a flexible framework for accelerating the cryptographic functions for packet processing
protocols. The crypto engine has the raw generic interface for cipher and hash/MAC
functions such as AES, DES, SHA, and RC4. It also includes two optional engines to
provide further offload; the PKA and RNG modules. These provide additional methods for
public key acceleration functions and random number generation. The engine includes a
DMA engine that allows the engine to perform cryptographic operation on data packets in
the system memory without any CPU intervention.
2.1.4. Memory Subsystem
The GS2101M module contains several memory blocks.
2.1.4.1. SRAM
The system memory is built with single port and dual port memories. Most of the memory
consists of single port memory. A 64KB dual port memory is used for exchange of data
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GS2101M Low Power Wi-Fi Module Hardware User Guide
between the two CPU domains. All the memories are connected to the system bus matrix
in each CPU subsystem. All masters can access any of the memory within the subsystem.
The APP subsystem has 384KB of dedicated SRAM for program and data use. The WLAN
subsystem has 320KB of dedicated SRAM for program and data use.
These memories are divided into banks of 64KB each. The bank structure allows different
masters to access different banks simultaneously through the bus matrix without incurring
any stall. Code from the external Flash is loaded into the SRAM for execution by each
CPU.
In addition, a static shared SRAM is provided. This consists of five 64KB memory blocks.
At any time, any of these memory blocks can be assigned to one of the CPU subsystem.
These should be set up by the APP CPU SW at initialization time. The assignment is not
intended to change during operation and there is no HW interlock to avoid switching in the
middle of a memory transaction. The assignment to the WLAN CPU should be done
starting from the highest block number going down to lowest block number. This result in
the shared memory appearing as a single bank for each CPU subsystem, independent of
the number of blocks assigned. The shared memory is mapped such that the SRAM space
is continuous from the dedicated SRAM to shared SRAM.
2.1.4.2. ROM
ROM is provided in each CPU subsystem to provide the boot code and other functional
code that are not expected to change regularly. Each CPU has 512KB of ROM.
2.1.4.3. OTP ROM
The GS2000 device includes a 64Kbit OTP ROM used for storing MAC ID and calibration
information. The APP and WLAN subsystem each contain 32Kbits (4Kbytes) of OTP
memory.
2.1.4.4. Flash Interface
The GS2000 SoC has only internal ROM and RAM for code storage. There is no embedded
Flash memory on the SoC. Any ROM patch code and new application code must reside in
the on-module Flash device of the GS2101M module. Flash access from the two CPUs are
independent. The APP CPU is considered the system Master and the code running on this
CPU is required to initialize the overall chip and common interfaces. WLAN CPU access
to the Flash is restricted to read DMA. Any write to the Flash from the WLAN CPU must be
done through the APP CPU. The operational parameters of the DMA accesses are set by
the APP CPU at system startup. The Flash code is transferred to internal RAM before
execution.
2.1.5. Clocks
The GS2101M includes four basic clock sources:
• Low power 32KHz clock (see 2.1.6 Real Time Clock (RTC) Overview, page 29)
• 40MHz Xtal Oscillator
• PLL to generate the internal 120MHz (CPU) and 80MHz (PHY) clocks from
the 40MHz Xtal.
•High speed RC oscillator 80MHz
Intermediate modes of operation, in which high speed clocks are active but some modules
are inactive, are obtained by gating the clock signal to different subsystems. The clock
control blocks within the device are responsible for generation, selection and gating of the
clocked used in the module to reduce power consumption in various power states
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GS2101M Low Power Wi-Fi Module Hardware User Guide
2.1.6. Real Time Clock (RTC) Overview
To provide global time (and date) to the system, the GS2101Mxx module is equipped with
a low-power Real Time Clock (RTC). The RTC is the always on block that manages the
Standby state. This block is powered from a supply pin (VRTC) separate from the digital
core and may be powered directly from a battery. The RTC implementation supports a
voltage range of 1.6V to 3.6V
2.1.6.1. RTC Main Features
•One 48-bit primary RTC counter as the primary reference for all timing events
and standby awake management
•1 programmable IO pins with specific default behavior. These pins are in the
RTC IO domain.
– Alarm inputs to wake up the GS2101M module from its sleep states (deep-
sleep/standby)
• Startup control counters with HW and SW override registers
• Power-on-reset control with brown-out detector
• RTC registers to hold RTC and wakeup control bits while the core domain is
off
• 1Kbyte latch-based memory (1.6-3.6V capable)
• 16KB of SRAM memory, divided into 4 equal blocks (1.2V capable)
• uLDO to supply the SRAM memory
• RTC logic is 1.6-3.6V capable
• 32 KHz RC oscillator
• 32768Hz crystal oscillator
• APB interface for CPU access
• Interrupts to CPU
The RTC contains a low-power 32.768KHz RC oscillator which provides fast startup at
first application of RTC power. It also supports an optional 32.768KHz crystal oscillator
which can be substituted for the RC oscillator under software control. In normal operation,
the RTC is always powered up.
The standby programmable counter is 48-bits and provides up to 272 years’ worth of
standby duration. For the RTC_IO pin, the programmable embedded counter (32-bit) is
provided to enable periodic wake-up of the remainder of the external system and provide
a 1.5 days’ max period. The RTC_IO pin can be configured as input (ALARM) or output
(WAKE UP) pin.
The RTC includes a Power-On Reset (POR) circuit, to eliminate the need for an external
component. The RTC contains low-leakage non-volatile (battery-powered) RAM, to enable
storage of data that needs to be preserved. It also includes a brown-out detector that can
be disabled by SW.
• This counter is automatically reset by power-on-reset.
• This counter wraps around (returns to “all-0” once it has reached the
highest possible “all-1” value).
2.1.6.3. RTC I/O
There is one (1) RTC I/O that can be used to control external devices, such as sensors or
wake up the module based on external events or devices.
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GS2101M Low Power Wi-Fi Module Hardware User Guide
2.1.7. GS2101M Peripherals
2.1.7.1. SDIO Interface
The SDIO interface is a full / high speed SDIO device (slave). The device supports SPI,
1-bit SD and 4-bit SD bus mode. The SDIO block has an AHB interface, which allows the
CPU to configure the operational registers residing inside the AHB Slave core. The CIS
and CSA area is located inside the internal memory of CPU subsystem. The SDIO
Registers (CCCR and FBR) are programmed by both the SD Host (through the SD Bus)
and CPU (through the AHB bus) via Operational registers. The SDIO block implements
the AHB master to initiate transfers to and from the system memory autonomously.
During the normal initialization and interrogation of the card by the SD Host, the card will
identify itself as an SDIO device. The SD Host software will obtain the card information in a
tuple (linked list) format and determine if that card’s I/O function(s) are acceptable to
activate. If the Card is acceptable, it will be allowed to power up fully and start the I/O
function(s) built into it.
The SDIO interface implements Function 1 in addition to the default Function 0. All
application data transfers are done through the Function 1
The primary features of this interface are
• Meets SDIO card specification version 2.0.
• Conforms to AHB specification.
• Host clock rate variable between 0 and 40 MHz
NOTICE:
Tested with current test platform up to 33 MHz
• All SD bus modes supported including SPI, 1 and 4-bit SD.
• Allows card to interrupt host in SPI, 1 and 4-bit SD modes.
• Read and Writes using 4 parallel data lines
• Cyclic Redundancy Check CRC7 for command and CRC16 for data
integrity-CRC checking optional in SPI mode
• Programmable through a standard AHB Slave interface
• Writing of the I/O reset bit in CCCR register generates an active low reset
output synchronized to AHB Clock domain.
•Card responds to Direct read/write (IO52) and Extended read/write (IO53)
transactions.
• Supports Read Wait Control operation.
• Supports Suspend/Resume operation.
2.1.7.2. SPI Interface
The SPI interface is a master slave interface that enables synchronous serial
communications with slave or master peripherals having one of the following: Motorola
SPI-compatible interface, TI synchronous serial interface or National Semiconductor
Microwire interface. In both master and slave configuration, the block performs
parallel-to-serial conversion on data written to an internal 16-bit wide, 8-deep transmit
FIFO and serial to parallel conversion on received data, buffering it in a similar 16-wide, 8
deep FIFO. It can generate interrupts to the CPU to request servicing transmit and receive
FIFOs and indicate FIFO status and overrun/underrun. The clock bit rate is SW
programmable. In master mode, the SPI block in GS2000 can perform up to 30 MHz and
in slave mode up to 10 MHz serial clock. Clock rates higher than 20MHz in master mode
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GS2101M Low Power Wi-Fi Module Hardware User Guide
or 6.66MHz in slave mode requires activation of the PLL’s 120MHz clock source. The
interface type, data size and interrupt masks are programmable. It supports DMA working
in conjunction with the uDMA engine
2.1.7.3. UART Interface
The UART interface implements the standard UART protocol. It is 16450/16550
compatible. It has separate 32 deep transmit and receive FIFOs to reduce CPU interrupts.
The interface supports standard asynchronous communication protocol using start, stop
and parity bits. These are added and removed automatically by the interface logic. The data
size, parity and number of stop bits are programmable. It supports HW based flow control
through CTS/RTS signaling. A fractional baud rate generator allows accurate setting of the
communication baud rate. It supports DMA working in conjunction with the uDMA engine.
2.1.7.4. I2C Interface
The I2C interface block implements the standard based two wire serial I2C protocol. The
interface can support both master and slave modes. It supports multiple masters, high
speed transfer (up to 3.4MHz), 7 or 10-bit slave addressing scheme, random and current
address transfer. It also supports clock stretching to interface with slower devices. It can
generate interrupts to the CPU to
indicate specific events such as FIFO full/empty, block
complete, no ack error, and arbitration failure.
2.1.7.5. GPIO
The GPIO block provides programmable inputs and outputs that can be controlled from the
CPU SW through an APB interface. Any number of inputs can be configured as an interrupt
source. The interrupts can be generated based on the level or the transition of a pin. At reset,
all GPIO lines defaults to inputs. Each pin can be configured as input or output from SW
control.
2.1.7.6. Sigma Delta ADC
The ADC and DAC are 16-bit sigma-delta converters. There are 3 ADC channels, each
having a
differential pair for a total of six input pins. The sample rate can be 32KHz to
80KHz. The sigma delta converter ratio is 250. The ADC is a 3-channel converter. Each
channel can have an optional pre-amplifier stage. The gain can be set to 0db, 6db, 12db,
18db, or 24db. The delay between the second and third channels of the ADC can be
adjusted under SW control. The digital interface for the ADCs and the DAC are 2’s
complement. ADC channel 0 (only) can alternatively be used as a differential DAC.
All the 3 ADC channels can be used at once. For a single ended input (Ex: temperature
sensor) – ground the negative input, the sigma delta is 2Vdpp (volts differential peak to
peak) comes to 1V full scale. So, the input has to be scaled downed below 1V. Also, the
Programmable Gain Amplifier needs to be set to 0db or 6db, and NOT the higher settings.
SD-ADC are continuous sampling device, they use digital filters which work on multiple
samples. For a DC measurement - start the device, wait until its fully stabilized, samp le
the output and then put it OFF. The stabilizing time depends on the programming sample
rate
For single measurement use SD-ADC at its highest sample rate(80KHz) with a quick
return value, the input clock of SD-ADC is 250 * 80KHz, or 20MHz. It is recommended to
use HS_RC oscillator as a source to the NCO, and set the step value to 0x 01000000, that
is 26-bit NCO divided by 4. With a sampling rate of 80KHz, the delay before fetching the
data is 100uS. Lowering the sampling rate leads to a proportionately longer delay, so
before considering a valid data - read and discard 8 samples of it.
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GS2101M Low Power Wi-Fi Module Hardware User Guide
2.1.7.7. PWM
The PWM consists of three identical PWM function blocks. The PWM function blocks can
be used in two modes of operations:
•Independent PWM function blocks providing output signal with
programmable frequency and duty cycle
•Synchronized PWM function blocks with programmable phase delay
between each PWM output
The PWM has the following features:
• 32-bit AMBA APB interface to access control, and status information
• Three identical PWM function blocks
• Each PWM block can be enabled independently
• All three PWM blocks can be started synchronously or chained with
programmable delay
•Programmable 6-bit prescaler for the input clock (see 2.1.5Clocks, page
24)
•Programmable frequency and duty cycle using 16-bit resolution in terms of
clock cycles for ON and OFF interval time
•Combined interrupt line with independent masking of interrupts
2.1.8. System States
The system states of the GS2101Mxx system are as follows:
Power OFF: No power source connected to the system.
Standby: In the standby state, the GS2101M is in its lowest power state. In this state
power is on to the VRTC and VIN_3V3 input. The RTC portion of the GS2000 chip is
powered from the VRTC pin. In standby state, the 32.768KHz oscillator is running and
RTC RAM retains the state (how many banks retain their state is SW configurable).
SRAM, CPUs and I/Os are powered off using the internal switches within the device
thus reducing overall power consumption. Exit from standby occurs when a prespecified wakeup time occurs, or when the RTC_IO configured as alarm inputs sees
the programmed polarity of signal edge.
NOTICE:
During first battery plug-in, i.e., when power is applied the first time to the
RTC power rail (VRTC), the power detection circuit in the RTC also
causes a wakeup request.
System Configuration: When a power-up is requested, the system transitions from the
Standby state to the System Configuration state. In this state, the APP CPU is released
from reset by the RTC. The WLAN CPU remains in the reset state during System
Configuration. The APP CPU then executes the required system configurations,
releases the WLAN CPU from reset, and transitions to the Power-ON state. The
System Configuration state is also entered on transition from the Power-ON state to
the Standby state, to complete necessary preparations before shutting off the power
to the core system.
Power-ON: This is the active state where all system components can be running . The
Power-ON state has various sub-states, in which unused parts of the system can be
in sleep mode, reducing power consumption. Sleep s tates are im plement ed by gat ing
the clock signal off for a specific system component. Additionally, unneeded clock
sources can be turned off. For example, receiving data over a slave SPI interface
could be done with only the 80MHz RC oscillator active, and the 40MHz crystal and
PLL turned off.
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GS2101M Low Power Wi-Fi Module Hardware User Guide
Sleep: In the Sleep state, the 40MHz crystal and the 80MHz RC oscillator remains
running, but it is gated off to one or both CPUs. Each CPU can independently control
its own entry into Sleep state. Any enabled interrupt will cause the interru pted CPU t o
exit from Sleep state, and this will occur within a few c l ock cycles.
Deep Sleep: Deep sleep is entered only when both CPUs agree that the wakeup latency
is OK. In Deep Sleep mode, the 40MHz crystal oscillator and 80MHz RC oscillator are
turned off to save power, but all power supplies remain turned on. Thus, all registers,
memory, and I/O pins retain their state. Any enabled interrupt will cause an exit from
Deep Sleep state.
EXT_RTC_RESET_n pin: This is an input pin for resetting the entire module,
including the RTC section of the device. This pin should not be left floating. An
external 10K pull up resistor to VRTC is recommended.
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GS2101M Low Power Wi-Fi Module Hardware User Guide
2.1.9. Power Supply
This section shows various application power supply connections. Following figure shows
the GS2101Mxx power supply connection.
Fig. 2 GS2101Mxx Always ON Power Supply Connection
Note:
1. Always ON connection connects VRTC and VIN_3V3 together to
a 3.3V power supply.
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GS2101M Low Power Wi-Fi Module Hardware User Guide
3. PIN-OUT AND SIGNAL DESCRIPTION
This chapter describes the Telit® GS2101M Low Power module architecture.
•GS2101Mxx Device Pin-out
GS2101Mxx Device Pin-out
Following figureshows the GS2101Mxx device pin-out diagram
Fig. 3 GS2101Mxx Device Pin-out Diagram (Module Top View)
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GS2101M Low Power Wi-Fi Module Hardware User Guide
Internal
Reset
Signal State
1
GND
0V
Not
Analog port
Ground
2
ADC_SD_0p
Analog port
Sigma Delta ADC
Delta DAC positive
output 0
3
ADC_SD_0n
Analog port
Sigma Delta ADC
differential negative
Delta DAC negative
output 0
4 ADC_SD_1p
Analog port
Sigma Delta ADC
input 1
5 ADC_SD_1n
Analog port
Sigma Delta ADC
differential negative
input 1
6 ADC_SD_2p
Analog port
Sigma Delta ADC
input 2
7 ADC_SD_2n
Analog port
Sigma Delta ADC
differential negative
input 2
8
GND
0V
Not
Analog Port
Ground
9
GND
0V
Not
Analog Port
Ground
10 VRTC
Analog port
Embedded Real
Supply
11
EXT_RTC_RESET_n
VRTC
None
Digital Input
Device Reset Input
12
RTC_IO_2
RTC Digital
Input/Output 2
13
VPP
Analog port
Memory
14
GND (see Note 3)
0V
Not
4
Analog port
Ground
15
VIN_3V3
VIN_3V3
Not
Analog port
Single Supply Port
3.1.1. GS2101Mxx Module Pins Description
Pins Name
Voltage
Domain
VIN_3V3Not
VIN_3V3Not
VIN_3V3Not
VIN_3V3 Not
VIN_3V3 Not
Bias after
Hardware
Applicable
Applicable
Applicable
Applicable
Applicable
Applicable
Drive
Strength
(mA)
Description
differential positive
input 0 or Sigma
input 0 or Sigma
differential positive
differential positive
(see Note 2)
(see Note 7)
VIN_3V3Not
Applicable
Applicable
Applicable
VRTCNot
Applicable
VRTCNone1
VPPNot
Applicable
Applicable
Input/Output
Time Clock Power
Embedded Real
Time Clock
Programming
Voltage for OTP
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Applicable
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GS2101M Low Power Wi-Fi Module Hardware User Guide
Internal
Reset
Signal State
16
GPIO10/PWM0 (see
VIN_3V3
Pull-down
4
Digital
Input/Output
GPIO/Pulse Width
Modulator 0
17
GPIO9/I2C_CLK
5)
VIN_3V3
Pull-down
12
Digital
Input/Output
GPIO/InterIntegrated Circuit
Clock
18
GPIO8/I2C_DATA
5)
GPIO/Inter-
19
GPIO32/SDIO_DAT2/
GPIO/SDIO_DATA
Transmitter Output
20
GPIO33/SDIO_DAT3/
4
GPIO/SDIO Data
(Active Low)
21
GPIO/SDIO
Input
22
GPIO35/SDIO_CLK/
23
GPIO36/SDIO_DAT0/
(see Errata E-1)
24
GPIO37/
Interrupt
25
NC
Not
Applicable
26
GND
0V
Not
Applicable
Analog Port
27
GPIO1/UART0_TX
VIN_3V3
Pull-down
Digital
Input/Output
28
GPIO25/UART0_RTS
VIN_3V3
Pull
Digital
Input/Output
Select.
Pins Name
Note 3)
(see Note 3 and Note
(see Note 3 and Note
UART1_TX
(see Note 3)
SPI0_CS_n_0
(see Note 3)
GPIO34/SDIO_CMD/
SPI0_DIN
(see Note 3)
Voltage
Domain
VIN_3V3 Pull-down 12
VIN_3V3 Pull-down 4
VIN_3V3 Pull-up
VIN_3V3 Pull-down 4
Bias after
Hardware
Strength
Drive
(mA)
Digital
Input/Output
Digital
Input/Output
Digital
Input/Output
Digital
Input/Output
Description
Integrated Circuit
Data
Bit
2/UART1
Bit 3/SPI0 Chip
Select Input 0
from the HOST
Command
Input/SPI0
Receive Data
SPI0_CLK
(see Note 3)
SPI0_DOUT
(see Note 3)
SDIO_DAT1_INT
(see Note 3 and Note
8)
(see Note 3)
(see Note 3 and Note
6)
VIN_3V3 Pull-down 4
VIN_3V3 Pull-down 4
VIN_3V3 Pull-down 4
4
-down
12
Digital
Input/Output
Digital
Input/Output
Digital
Input/Output
GPIO/SDIO
Clock/SPI0 Clock
Input from the
GPIO/SDIO Data
Bit 0/SPI0 Transmit
Data Output to the
HOST
GPIO/4-bit SDIO
DATA Bit
1/SDIO SPI Mode
Not Connected
Ground
GPIO/UART0
Transmitter Output.
GPIO/UART0
Request to Send
Output. This pin is
used for Program
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GS2101M Low Power Wi-Fi Module Hardware User Guide
Internal
Reset
Signal State
29
GPIO0/UART0_RX
VIN_3V3
Pull-down
Digital Input
Output
30
GPIO24/UART0_CTS
(see
6)
VIN_3V3
Pull-down
Digital
Input/Output
31
16
Digital
Input/Output
GPIO/Pulse Width
32
GPIO30/PWM1
VIN_3V3
Pull-down
16
Digital
Input/Output
GPIO/Pulse Width
33
GND
0V
N/A
Analog Port
Ground
34
GPIO28/I2C_DATA
(see
5)
VIN_3V3
Pull-down
12
Digital
Input/Output
GPIO/InterData
35
JTAG_TCK
VIN_3V3
Pull-up
Digital Input
JTAG Test
36
JTAG_TDO
VIN_3V3
Pull-down
Digital Output
JTAG Test
37
JTAG_TDI
VIN_3V3
Pull-up
Digital Input
JTAG Test Data In
38
JTAG_TMS
VIN_3V3
Pull-up
Digital Input
JTAG Test Mode
39
JTAG_TRST_n
VIN_3V3
Pull-up
Digital Input
JTAG Test Mode
40
GND
0V
N/A
Analog Port
Ground
Pins Name
(see Note 3)
GPIO31/PWM2
Note 3 and Note
(see Note 3 and Note
4)
(seeNote 3)
Note 3 and Note
Voltage
Domain
VIN_3V3 Pull-down
Bias after
Hardware
Drive
Strength
(mA)
4
12
Description
GPIO/UART0
Receive Input
GPIO/UART0
Clear to Send Input
Modulation Output
2.
This pin is used for
Program Mode.
Modulation
Output 1
Integrated Circuit
Clock
Data Out
Select
Rest (Active Low)
Tab. 5 GS2101Mxx Module Pin Signal Description
Notes:
1. Recommend 10K external pull up resistor to VRTC.
2. Can be left as no connect.
3. Pins with drive strength 4, 12, and 16 have one pull resistor (either up
or down, not both), which is enabled at reset.
4. This pin enables programming of the module. If GPIO31/PWM2 is high
during reset or power on, then the GS2101M will wait f or F lash
download via UART0 or SPI0 interface. Route this pin on the base
board so it can be pulled up to VIN_3V3 for programmi ng the module.
2
5. If I
C interface is used, provide 2K Ohm pull-ups, to VIN_3V3, for
I2C_CLK and I2C_DATA.
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GS2101M Low Power Wi-Fi Module Hardware User Guide
Pin#
Pin Name
Internal
mA
Mux3
Mux4
Mux5
Mux7
Comments
1
2
adc_sd_0p
3
adc_sd_0n
4
5
adc_sd_1n
6
adc_sd_2p
7
8
GND
9
GND
10
11
ext_rtc_reset_n
pull-up (u)
12
u/d
Alarm or
13
VPP
Programming
14
15
VIN_3V3
16
pull
pwm0
spi1_clk
17
d
i2c_clk
spi1_din
6. CTS and RTS signals indicate it is clear to send or ready to send when
they are LOW. If signals are high, indicates device i s not ready.
7. This pin is generally reserved for Telit use, but if a design requires to
OTP during production, then design must consider the connection to
this pin. Otherwise, it should be left as a No Connect.
8. In the Serial-to-Wi-Fi firmware when using the SPI interface this pin is
the host wake-up signal or the Ready to Send signal.
a. GPIO37 - when using the SPI interface this pin is the host w ake-up
signal or the Ready to Send signal.
Errata
E1. The SPI0_DOUT and SPI1_OUT signals do not disable their drive and become Hi-Z
when the associated chip select pin is high. This applies to all pin MUX locations for the
SPI_DOUT signals. If there are multiple write only devices on the same SPI bus, then this
is not an issue. This only becomes an issue when there are other read/write devices on
the same SPI bus. The workaround is to add an external buffer chip, such as 74LVC1G125
between the SPI_DOUT pin and the SPI bus, with the enable connected to the chip select
signal.
3.1.2. GS2101M Pin MUX Function
The GS2101M pins have multiple functions that can be selected using MUX function by
software. The table below shows the various MUX functions for each pin. Each pin can be
independently configured. Table below shows the various mux functions for each pin. All
I/O pins are GPIO inputs at reset. For pins that are inputs to functional blocks only one pin
may be assigned to any input function. For example, UART1_RX may be assigned to
GPIO9 but not to both GPIO9 and GPIO37.
Alternate Functions Available
Pull
Resistor
GND
adc_sd_1p
adc_sd_2n
VRTC
rtc_io_2
GND
gpio10/pwm0gpio9/i2c_clk
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1
-down (d)4
12
uart1_tx
uart1_rx
wake up pin
voltage for
OTP memory
clk_rtc
i2s_lrclk
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GS2101M Low Power Wi-Fi Module Hardware User Guide
18
d
i2c_data
spi1_dout
1
19
gpio32/sdio_dat2/u
d4sdio_data
wuart_tx
uart1_tx
spi1_cs_n_12
20
u
uart1_rts
21
gpio34/sdio_cmd/s
d4sdio_cmd
reserved
usart1_cts
spi0_din
22
gpio35/sdio_clk/spi
d4sdio_clk
reserved
i2c_clk
spi0_clk
Note: only
23
gpio36/sdio_dat0_d
d 4 sdio_data
reserved
i2c_data
24
d
uart1_rx
25
NC 26
27
gpio1/uart0_tx
d 4 uart0_tx
wuart_tx
pwm1
spi1_dout1
28
gpio25/uart0_rts
d
12
uart0_rts
wuart_rts
spi1_cs_n_
spi1_clk
29
d
pwm2
30
gpio24/uart0_cts
d
12
uart0_cts
wuart_cts
pwm0
spi1_cs_n_0
31
d
uart1_tx
32
gpio30/pwm1
d
16
pwm1
spi1_din
uart1_rx
wuart_rx
33
GND
34
d
clk_hs_rc
35
jtag_tck
36
37
jtag_tdi
38
jtag_tms
39
40
GND
gpio8/i2c_data
gpio33/sdio_dat3/s
pi0_cs_n_0
0_clk
out
gpio37/sdio_dat1_i
nt
GND
gpio0_uart0_rx
gpio31/pwm2
gpio28/i2c_data
12
4sdio_data3reserved
0
4 sdio_data1 wuart_rx
4 uart0_rx wuart_rx
16 pwm2 spi1_dout
12 i2c_data spi1_clk
uart1_tx
reserved
spi0_cs_n_0
spi0_dout1
spi0_cs_n_10
spi1_din
wuart_tx
spi1_cs_n_21
4mA for i2C
jtag_tdo
jtag_trst_n
Tab. 6 GS2101M Pin MUX Description
Note 1:
The SPI0_DOUT and SPI1_OUT signals do not disable their drive and
become Hi-Z when the associated chip select pin is high. This applies to all
pin MUX locations for the SPI_DOUT signals. If t here are mult iple write o nly
devices on the same SPI bus, then this is not an issue. This only becomes
an issue when there are other read/write device s on t he sam e SP I bus. T he
workaround is to add an external buffer chi p, such as 74LVC1G125 betwe en
the SPI_DOUT pin and the SPI bus, with the enable connected to the chip
select signal.
1VV0301395 Rev 8.0 Page 38 of 54 2020-04-28
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GS2101M Low Power Wi-Fi Module Hardware User Guide
(GPIO 25)
0
0
Normal boot
0
Previous Code Restore. Restores the prior
1
Program Mode: UART0 @ 115.2Kbaud;
1
Program Mode using: UART0
3.1.3. GS2101M Program and Code Restore Options
Following table describes the options available for device program mode and code restore
capabilities. The respective GPIO pins are sampled at reset by device and depending on
the values seen on these pins goes into the appropriate mode. The code for the G S2101M
resides on the internal flash of the module and up to two back-up copies could be stored
in flash. If a software designer wants to restore the execution code to one of the backup
copy, it can be accomplished by asserting the appropriate GPIO pins as shown in the table
below during power up or reset.
Boot
Control
(see Note 1)
Program
Mode
Program
Select/Previous
Restore
Interfaces for Program Load
(GPIO 31)
1
code revision by invalidating the present
code image. Will NOT invalidate the last
remaining image.
0
nothing on
GPIO15-18; SPI0 on SDIO pins. Note: this
is the default you get if you don’t pull the
Program Select pin high.
1
@921.6Kbaud; SPI0 on GPIO15-18. Note:
GPIO15-18 are only available on GS2000
SoC, and not on modules.
Tab. 7 GS2101M Pin Program and Code Restore
Note:
1. In Run Mode, boot ROM leaves all GPIO pins as input with pull resistor
enabled until the flash code set s them otherwise. In Pro gram Mode, only
the pins required for the Program Mode specified interfaces are set to
non-GPIO mode.
1VV0301395 Rev 8.0 Page 39 of 54 2020-04-28
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GS2101M Low Power Wi-Fi Module Hardware User Guide
Storage Temperature
T
ST
-55
+125
RTC Power Supply
VRTC
-0.5
4.0
V
Single Supply Port
VIN_3V3
-0.5
4.0
V
OTP Supply
VPP
TBD
V
Signal Pin Voltage
1
VI
-0.3
Voltage Domain +0.3
V
Symbol
Minimum
Unit
Extended
Temperature Range
T
-
RTC Power3
VRTC
2.7
3.3
3.6
V
Single Supply Port
GS2101MIx
VIN_3V3
2.7
Signal Pin Voltage
1
VI 0
VPP
2
VPP
5.5
4. ELECTRICAL CHARACTERISTICS
This chapter describes the Telit
® GS2101M electrical characteristics.
• Absolute Maximum Ratings
• Operating Conditions
• I/O DC Specifications
• Power Consumption
• 802.11 Radio Parameters
• Sigma Delta ADC Parameters
Absolute Maximum Ratings
Conditions beyond as shown in the following table may cause permanent damage to the
GS2101Mxx and must be avoided. Sustained operation, beyond the normal operating
conditions, may affect the long-term reliability of the module
ParameterSymbolMinimumTypical
Tab. 8 Absolute Maximum Ratings
MaximumUnit
o
Note:
1. Reference domain voltage is the Voltage Domain per section
GS2101Mxx Module Pins Description. For limitations on state
voltage ranges, please consult section on GS2101Mxx Module
Pins Description.
Operating Conditions
Following table lists the operating conditions of the GS2101Mxx module
Parameter
A
Notes:
1. Reference domain voltage is the Voltage Domain per section
GS2101Mxx Module Pins Description.
40
3.33.6 V
TypicalMaximum
5.756.0 V
Tab. 9 Operating Conditions
+85
Voltage Domain V
o
C
1VV0301395 Rev 8.0 Page 40 of 54 2020-04-28
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GS2101M Low Power Wi-Fi Module Hardware User Guide
I/O Supply Voltage
DDIO
2.7
3.3
3.6
V
Input Low Voltage
IL
-0.3
0.3*V
V Input High Voltage
IH
0.7*V
V
V
Pull up/down
Tri-State Output
Pull up/down
Pull-Up Resistor
R
u
34K
51K
100K
Ω
Pull-Down Resistor
d
35K
51K
100K
Ω
Output Low Voltage
OL
0.4
V Output High Voltage
OH
0.8*V
V
4
Pin Type 4mA
4
Pin Type 4mA
3.1
4.2
7
Pin Type 4mA
3.8
5.0
8
Pin Type 4mA
2. The VPP pin should be left floating when not doing OTP
programming operations.
3. The VRTC power MUST be the same as the VIN_3V3 power.
I/O DC Specifications
4.3.1. I/O Digital Specifications (Tri-State) Pin Types 4mA, 12mA, and 16mA
The specifications for these I/O’s are given for voltage ranges: 2.7V to 3.6V.
4.3.1.1. I/O Digital Specifications for VDDIO=2.7V to 3.6V
Following table lists the parameters for I/O digital specification for VDDIO 2.7V to 3.6V for
Pin Types 4mA, 12mA, and 16mA.
ParameterSymbolMinimumTypicalMaximumUnitNote
V
V
V
DDIO
DDIO
DDIO
Input Leakage Current
Leakage Current
Low Level Output
Current @ V
OL
max
High Level Output
Current @ V
OH
min
Output rise time 10% to
90% load, 30pF
I
I
OZ
R
V
V
I
OL
I
OH
t
TRLH
L
DDIO
12
10
10
16
12
16
1.8
1.5
2.4
2.0
4
3.4
μA
μA
mA
mA
ns
disabled
disabled
Pint Type 12mA
Pint Type 16mA
Pin Type 12mA
Pin Type 16mA
Pint Type 12mA
Pin Type 16mA
Output fall time 90% to
10% load, 30pF
1VV0301395 Rev 8.0 Page 41 of 54 2020-04-28
t
TFHL
1.8
1.5
2.5
2.1
4.2
3.5
ns
Pin Type 12mA
Pin Type 16mA
Tab. 10 I/O Digital Parameters for VDDIO=2.7V to 3.6V
Page 42
GS2101M Low Power Wi-Fi Module Hardware User Guide
Supply
VRTC
1.6
3.6
V
Input
Low
Input
High
Input
Leakage
Pullup
I
PU
1μA
Pulldo
Output
Low
IL=1mA or
4mA*
Output
High
IL=1mA or
4mA*
4.3.2. RTC I/O Specifications
Followingtable lists the RTC I/O parameters.
ParameterSymbolMinimumTypicalMaximumUnitNote
wn
V
V
V
V
I
IL
IH
I
L
PU
OL
OH
1
0.3*V
VRTC+0.3V
-.03
0.7*V
RTC
VRTC-0.4
RTC
0.1
V
μA
μA
0.4V
V
Tab. 11 RTC I/O Parameters
*RTC I/O’s are software selectable as 1mA or 4mA drive strength
1VV0301395 Rev 8.0 Page 42 of 54 2020-04-28
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GS2101M Low Power Wi-Fi Module Hardware User Guide
System
Standby (VIN_3V3 ON), Note 4
TBD μA
Deep Sleep (see Notes 1 and 2)
615 μA
WLAN Continuous Transmit (1 Mbps, 15 dBm)
257 mA
WLAN Continuous Receive (1 Mbps)
131 mA
PS-Poll, DTIM=1, 1mS beacon, Note 3
2.80 mA
PS-Poll, DTIM=1, 2mS beacon, Note 3
4.02 mA
PS-Poll, DTIM=3, 1mS beacon, Note 3
1.52 mA
PS-Poll, DTIM=3, 2mS beacon, Note 3
1.90 mA
PS
1.02 μA
PS
1.17 μA
Power Consumption
Followingtablelists the power consumption for the GS2101Mxx. Typical conditions are:
o
VIN_3V3=VRTC=3.3V Temp=25
State
C.
Current (Typical)
1
-Poll, DTIM=10, 1mS beacon, Note 3
-Poll, DTIM=10, 2mS beacon, Note 3
Tab. 12 Power Consumption in Different States
Notes:
1. Depends on firmware version.
2. One Sigma (+200μA).
3. Average current. PS-POLL currents given for both 1mS beacon
duration and 2mS beacon. DTIM1, DTIM3, and DTIM10 use deep
sleep between beacons.
4. Software currently does not support Standby mode for GS2101M.
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GS2101M Low Power Wi-Fi Module Hardware User Guide
RF Frequency Range
2400
2497
MHz
N/A
Transmit/Receive Specification for GS2101M
14
4.5
11b, 1Mbps
11n, MCS7
Meets 802.11 requirement for
-90
-67
11b, 1Mbps, BPSK/DSSS
11n, MCS7, 64-QAM/OFDM
802.11 Radio Parameters
Following table lists the 802.11 Radio parameters. Test conditions are:
o
VIN_3V3=VRTC=3.3V Temp=25
ParameterMinimum TypicalMaximum UnitNotes
C.
Radio bit rate1
Output power
(average)
Spectrum Mask
Receive Sensitivity at
antenna port
13.5
12
13
13
9
12.5
13
-84
-86
-71
-86
HT2
MbpsN/A
11b,5.5Mbps
11b, 11Mbps
11g, 6Mbps
dBm
11g, 18Mbps
11g, 54Mbps
11n, MCS0
11n, MCS3
dBr
selected data rates
11b, 11Mbps
11g, 6Mbps
dBm
11g, 54Mbps, 64-QAM/OFDM
11n, MSC0
Tab. 13 802.11 Radio Parameters - (Typical - Nominal Conditions)
NOTICE:
TX output power and RX sensitivity are firmware dependent. All the values
provided for these parameters are measured at the antenna port based on
5.2.1 GA firmware.
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GS2101M Low Power Wi-Fi Module Hardware User Guide
Minimum
Notes
D/A DC Performance (see Note 1)
Resolution
-
16
-
Bits
Full Scale
2.40V
See Note 2
Output
Gain Error
--+5
%
See Note 2
Offset--
+20
mV
D/A Dynamic Performance
Data Rate
32-80
KHz
Clock
Frequency
8-20
MHz
See Note 3
Signal to
See Note 4
Total
Output load
10
KΩ
Output load
30
pF
A/D DC Performance (Preamplifier Gain=0db)
Resolution
16
Bits
Full Scale
2.0
V
Input
Gain Error
+3
%
Offset
+10
LSB
A/D Dynamic Performance (Preamplifier Gain=0db)
Data Rate
32
80
KHz
Clock
8 20
MHz
See Note 3
Signal-to-
See Note 4
Total
See Note 4
Input
100
KΩ
Sigma Delta ADC Parameters
Following table lists the Sigma Delta ADC parameters. Test conditions are:
o
VIN_3V3=VRTC=3.3V Temp=25
C.
Parameter
common-mode
Noise Ratio
Harmonic
TypicalMaximumUnit
VIN_3V3/2
67-dB
--74
dB
common-
VIN_3V3/2
Frequency
Noise Ratio
Harmonic
80
-85
Resistance
Tab. 14 ADC Parameters
1VV0301395 Rev 8.0 Page 45 of 54 2020-04-28
dB
dB
Page 46
GS2101M Low Power Wi-Fi Module Hardware User Guide
Notes:
1. The D/A output is fully differential. The Analog power supply is
3.3V +/- 10%.
2. Full scale (FS) can be trimmed in the reference generator. The
gain error specified is on top of the reference level error.
3. The master clock frequency is always 250 times higher than the
data clock rate.
4. Assumes a -1-dB full scale input and corrected for full scale. Fin
can be from 0 to 10KHz. The SNR is met for all master clock
frequencies.
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GS2101M Low Power Wi-Fi Module Hardware User Guide
5. PACKAGE AND LAYOUT GUIDELINES
This chapter describes the Telit® GS2101M package and layout guidelines.
•GS2101Mxx Recommended PCB Footprint and Dimensions
GS2101Mxx Recommended PCB Footprint and Dimensions
Fig. 4, page 46 shows the GS2101MIx Module PCB Footprint.
Fig. 5, page 47 shows the GS2101MIx Module Dimensions.
Fig. 4 GS2101MIx Module Recommended PCB Footprint (in millimeters)
1VV0301395 Rev 8.0 Page 47 of 54 2020-04-28
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GS2101M Low Power Wi-Fi Module Hardware User Guide
Fig. 5 GS2101MIx Module Dimensions (in millimeters)
Notes:
1. All Dimensions are in millimeters (mm).
2. For Boards using PCB Antenna, we recommend:
– Have Only Air on BOTH sides of the antenna.
– Hang Antenna over edge of the base board (best)
– Or Cut notch in base board under antenna area
– 5mm beyond module edge on both sides is good
– Full module width is minimum
– No metal or FR4 encircling antenna area
– Antenna at edge of base board, not interior of base board
– Nothing conductive near antenna (for example battery,
display, wire)
3. The 3 RF shield mounting holes and 2 test fixture alignment holes
(circled in red in Fig. 4, page 44) have exposed metal. These
areas must not have metal on the customer board.
4. For best RF performance, we recommend:
– Using the power (PWR) or the GND planes from module back
to the power supply.
– Isolating PWR/GND from high frequency or high current
components. For example, a notch in GND plane to isolate
from host µC.
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GS2101M Low Power Wi-Fi Module Hardware User Guide
– Using at least 3 vias when either power or GND change
layers. This applies particularly at the module GND pins and
at the VIN_3V3 pins.
– Providing a 10 µF capacitor at the VIN_3V3 pin and using 3
vias both sides of the capacitor.
– Keep high speed signals away from RF areas of the module.
5. For the area under Module, other than an antenna area, we
recommend two options:
– No metal of any kind under the module “not on any layer”
– Having a full GND plane under m odule (layer 1 or layer 2) with
no “HOT” vias under module (over 100KHz) and may route
signals below GND plane. Also, no metal traces are to be
present in the circle, around the shield and alignment holes.
This option is best for 2-layer boards. If the GND plane is on
layer 1, then use thermal relief pads for the GND pins of the
module footprint.
6. If any metal is present on layer 1, then extra thick solder mask
under the module is required.
7. In performing SMT or manual soldering of the module to the base
board, first align the row of pins from #15 through #26 onto the
base board and then match the other two rows.
In addition to the guidelines, note the following suggestions:
1. External Bypass capacitors for all module supplies should be as
close as possible to the module pins.
2. Never place the antenna very close to metallic objects.
3. External monopole antennas need a reasonable ground plane
area for antenna efficiency.
4. Do not use a metal or metalized plastic for the end product
enclosure when using an on-board antenna.
5. If the module is enclosed in a plastic case, have reasonable
clearance from the plastic case to the on-board antenna.
1VV0301395 Rev 8.0 Page 49 of 54 2020-04-28
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GS2101M Low Power Wi-Fi Module Hardware User Guide
Temperature Ramp up rate for (A)
2
1.5~3.5 oC/s
Pre-heat time (B)
3
80 to 130 seconds
Pre-heat starting temperature (C1)
125 to 135 oC
Pre-heat ending temperature (C2)
180 to 200 oC
Peak Temperature range (D)
240 to 250 oC
Melting time4 that is the time over 220 oC (E)
50 to 75 seconds
Cool Down Ramp (F)
>2 oC/s
5.1.1. Surface Mount Assembly
The following figure shows the reflow profile. The recommended reflow parameters are
summarized in the following table.
Fig. 6 Reflow Temperature Profile
Preheat
Heating
Tab. 15 Recommended Reflow Parameters
Notes:
1. Perform an adequate test in advance as the reflow temperature
profile will vary according to the conditions of the parts and
boards, and the specifications of the reflow furnace.
2. Max number of reflow supported are two.
3. Temperature uniformity inside the IR reflow oven must be tightly
controlled, and multiple thermocouples should be used. An
example of possible thermocouple locations is given in Fig. 7. The
locations should also include multiple points inside the modul e RF
shield (for example TC1, TC5, and TC7 inFig. 7). The
temperature profile of all thermocouples must meet the
requirements Tab. 15, page 50.
5
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GS2101M Low Power Wi-Fi Module Hardware User Guide
4. Pay close attention to “Melting Time over 220ºC”. Sufficient time
is necessary to completely melt all solder.
5. Be careful about the rapid temperature rise in the preheat zone
as it may cause excessive slumping of the solder paste.
6. If the preheat is insufficient, rather large solder balls tend to be
generated. Conversely, if performed excessively, fine balls and
large balls will generate in clusters at a time.
7. If the temperature is too low, non-melting tends to be caused in
the area with a large heat capacity after re-flow.
8. Be careful about the sudden rise in temperature as it may worsen
the slump of solder paste.
9. Be careful about slow cooling as it may cause the positional shift
of parts and decline in joining at times.
10. A no clean flux should be used during SMT process.
11. The modules are shipped in sealed trays with the following
conditions (seeFig. 8, page 52).
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GS2101M Low Power Wi-Fi Module Hardware User Guide
Fig. 7 Thermocouple Locations
1VV0301395 Rev 8.0 Page 52 of 54 2020-04-28
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GS2101M Low Power Wi-Fi Module Hardware User Guide
Fig. 8 Module Moisture Conditions
1VV0301395 Rev 8.0 Page 53 of 54 2020-04-28
Page 54
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