Teledyne QPHY-LPDDR2 User Manual

QPHY-LPDDR2

LP-DDR2 Serial Data

Operator’s Manual

Revision B – July, 2011

Relating to the Following Release Versions:

• Software Option Rev. 6.5

• LPDDR2 Script Rev. 1.0

• Style Sheet Rev. 1.2

LeCroy Corporation

700 Chestnut Ridge Road Chestnut Ridge, NY 10977–6499 Tel: (845) 578 6020, Fax: (845) 578 5985

Internet: www.lecroy.com

LeCroy, ActiveDSO, WaveLink, JitterTrack, WavePro, WaveMaster, WaveSurfer, WaveExpert, WaveRunner and WaveJet are registered trademarks of LeCroy Corporation. Other product or brand names are trademarks or requested trademarks of their respective holders. Information in this publication supersedes all earlier versions. Specifications subject to change without notice.

Manufactured under an ISO 9000 Registered Quality Management System

Visit www.lecroy.com to view the certificate.

Document Number: 919701 Rev B

This electronic product is subject to disposal and recycling regulations that vary by country and region. Many countries prohibit the disposal of waste electronic equipment in standard waste receptacles.

For more information about proper disposal and recycling of your LeCroy product, please visit

www.lecroy.com/recycle.

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QPHY-LPDDR2 Software Option

Table of Contents

INTRODUCTION TO QPHY-LPDDR2 ....................................................................................... 7

Required equipment ................................................................................................................................................... 7

SIGNALS MEASURED .............................................................................................................. 7

CK, CK# Input ............................................................................................................................................................ 7

DQ Input/Output ......................................................................................................................................................... 7

DQS, DQS# Input/Output ........................................................................................................................................... 7

ADD/CTRL ................................................................................................................................................................. 7

BASIC FUNCTIONALITY .......................................................................................................... 7

Burst Read ................................................................................................................................................................. 8

Burst Write .................................................................................................................................................................. 9

USING QUALIPHY LPDDR2 ................................................................................................... 10

QUALIPHY COMPLIANCE TEST PLATFORM ....................................................................... 11

Oscilloscope Option Key Installation ........................................................................................................................ 13

Typical (Recommended) Configuration .................................................................................................................... 13

Remote (Network) Configuration ............................................................................................................................. 13

Oscilloscope Selection ............................................................................................................................................. 13

Accessing the QPHY-LPDDR2 Software using QualiPHY ....................................................................................... 14

Customizing QualiPHY ............................................................................................................................................. 17

QPHY-LPDDR2 Operation ....................................................................................................................................... 20

LPDDR2 MEASUREMENT PREPARATION ........................................................................... 21

Differential Probe Deskew Procedure using TF-DSQ .............................................................................................. 21

Differential Probe Deskew Procedure on Zi oscilloscopes using PCF200 .............................................................. 21

PCF200 Fixture Overview ................................................................................................................................. 23

Probe Connection to PCF200 ........................................................................................................................... 23

Probe Calibration Menu .................................................................................................................................... 24

Probe ............................................................................................................................................................................. 25

Full Calibration Button .................................................................................................................................................... 25

Gain & Offset.................................................................................................................................................................. 25

Skew .............................................................................................................................................................................. 26

Clear .............................................................................................................................................................................. 26

Calibration Source .......................................................................................................................................................... 26

Calibration Skew Reference ........................................................................................................................................... 26

Recall Calibration ........................................................................................................................................................... 26

Advanced Mode Checkbox ............................................................................................................................................ 26

Advanced Mode Probe Calibration Menu ......................................................................................................... 26

Gain/Offset Only ............................................................................................................................................................. 28

Deskew Only .................................................................................................................................................................. 28

The Advanced Menu ......................................................................................................................................... 28

Rise Time Skew Correction ............................................................................................................................................ 28

Differential (or Single-Ended) Probe Selection ............................................................................................................... 29

Deskew All (or Common Skew)...................................................................................................................................... 29

Common Mode Voltage Selection .................................................................................................................................. 29

Advanced Probe Calibration ............................................................................................................................. 29

D620 Probe Calibration Procedure ................................................................................................................... 29

QPHY-LPDDR2 TEST CONFIGURATIONS ............................................................................ 31

1) Clock tests LPDDR2-667 (1 Probe) ..................................................................................................................... 31

2) CKdiff-DQse-DQSdiff 667 (3 probes) ................................................................................................................... 31

3) 4 Probe tests ........................................................................................................................................................ 32

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D2) Demo of Eye Diagram (Debug) ......................................................................................................................... 34

D3) Demo of All tests ............................................................................................................................................... 34

D4) Demo of All CKdiff-DQSdiff-DQse tests ............................................................................................................ 34

QPHY-LPDDR2 VARIABLES .................................................................................................. 35

General Variables ..................................................................................................................................................... 35

DUT Speed Grade in MT/s ............................................................................................................................... 35

DQ Signal Name ............................................................................................................................................... 35

DQS Signal Name............................................................................................................................................. 35

Clock Signal Name ........................................................................................................................................... 35

DUT Power Supply VDDQ ................................................................................................................................ 35

Script Settings .......................................................................................................................................................... 35

Save Acquired Waveforms ............................................................................................................................... 35

Silent mode control ........................................................................................................................................... 35

Stop On Test to review results .......................................................................................................................... 35

Waveform Path ................................................................................................................................................. 35

Demo Settings .......................................................................................................................................................... 35

Use Stored Waveforms ..................................................................................................................................... 35

Recalled Waveform File Index (5 digits) ........................................................................................................... 35

Define format used to set trace names ............................................................................................................. 36

Use Stored Trace for Speed Grade .................................................................................................................. 36

Advanced Settings ................................................................................................................................................... 36

Clock Period per Screen Division ..................................................................................................................... 36

Number of cycles for Clock test ........................................................................................................................ 36

Max. Number Of Samples Per Clock Period .................................................................................................... 36

Configuration Specific Variables............................................................................................................................... 36

XX Channel Gain .............................................................................................................................................. 36

XX Channel Index ............................................................................................................................................. 36

XX Channel Invert ............................................................................................................................................. 36

XX Channel Offset ............................................................................................................................................ 36

Select Signal Under Test if many ..................................................................................................................... 37

QPHY-LPDDR2 LIMIT SETS ................................................................................................... 38

LPDDR2-466 ............................................................................................................................................................ 38

LPDDR2-533 ............................................................................................................................................................ 38

LPDDR2-667 ............................................................................................................................................................ 38

LPDDR2-800 ............................................................................................................................................................ 38

LPDDR2-933 ............................................................................................................................................................ 38

LPDDR2-1066 .......................................................................................................................................................... 38

QPHY-LPDDR2 TESTS ........................................................................................................... 38

Clock Tests ............................................................................................................................................................... 38

tCK(avg), Average Clock Period ................................................................................................................................ 38

tCK(abs), Absolute Clock Period ................................................................................................................................ 38

tCH(avg), Average High Pulse Width ......................................................................................................................... 39

tCL(avg), Average Low Pulse Width .......................................................................................................................... 39

tCH(abs), Absolute High Pulse Width ........................................................................................................................ 39

tCL(abs), Absolute Low Pulse Width .......................................................................................................................... 39

tJIT(duty), Half Period Jitter ....................................................................................................................................... 40

tJIT(per), Clock Period Jitter ...................................................................................................................................... 40

tJIT(cc), Cycle to Cycle Period Jitter .......................................................................................................................... 40

tERR(n per), Cumulative Error ................................................................................................................................... 40

Eye Diagram ............................................................................................................................................................ 41

Write Burst (Inputs) .................................................................................................................................................... 41

Read Burst (Outputs) ................................................................................................................................................. 41

Electrical Tests ......................................................................................................................................................... 41

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QPHY-LPDDR2 Software Option

Slew Rate .......................................................................................................................................................... 41

Logic Levels ................................................................................................................................................................... 41

VIH(ac), maximum AC input logic high ....................................................................................................................... 41

VIH(dc), minimum DC input logic high ....................................................................................................................... 42

VIL(ac), maximum AC input logic low ......................................................................................................................... 42

VIL(dc), minimum DC input logic low ......................................................................................................................... 42

VSWING(MAX), input signal maximum peak to peak swing ...................................................................................... 42

AC Over/Undershoot ...................................................................................................................................................... 42

AC Overshoot, Maximum peak amplitude .................................................................................................................. 42

AC Overshoot, Maximum overshoot area above VDDQ ............................................................................................ 42

AC Undershoot, Maximum peak amplitude ................................................................................................................ 43

Tests Requiring Single Ended Probing of Differential Signal ........................................... Error! Bookmark not defined.

Timing Tests ............................................................................................................................................................. 43

Read Bursts ...................................................................................................................................................... 43

tDQSQ, DQS-DQ Skew for DQS and Associated DQ Signals ....................................................................................... 43

tQHS, DQ hold skew factor ............................................................................................................................................ 44

tQH, DQ/DQS Output Hold Time From DQS.................................................................................................................. 44

tDQSCK, DQS Output Access Time from CK/CK # ....................................................................................................... 44

tHZ(DQ), DQ High Impedance Time From CK/CK# ....................................................................................................... 45

tLZ(DQ), DQ Low-Impedance Time from CK/CK# ......................................................................................................... 45

tLZ(DQS), DQS Low-Impedance Time from CK/CK# ..................................................................................................... 45

tRPRE, Read Preamble ................................................................................................................................................. 45

tRPST, Read Postamble ................................................................................................................................................ 45

Write Bursts ...................................................................................................................................................... 46

tDQSS, DQS latching rising transitions to associated CK edge ..................................................................................... 46

tDQSH, DQS Input High Pulse Width ............................................................................................................................. 46

tDQSL, DQS Input Low Pulse Width .............................................................................................................................. 46

tDSS, DQS Falling Edge to CK Setup Time ................................................................................................................... 47

tDSH, DQS Falling Edge Hold Time from CK ................................................................................................................ 47

tWPRE, Write Preamble ................................................................................................................................................. 47

tWPST, Write Postamble ............................................................................................................................................... 47

tDS(base), DQ and DM Input Setup Time ...................................................................................................................... 47

tDH(base), DQ and DM Input Hold Time ........................................................................................................................ 47

tIS(base) - Address and Control Input Setup Time ......................................................................................................... 48

tIH(base) - Address and Control Input Hold Time .......................................................................................................... 49

TABLE OF FIGURES

Figure 1. Data output (read) timing [JESD209-2D figure 23] .................................................................. 8

Figure 2. Burst read followed by burst write [JESD209-2D figure 32] ................................................... 8

Figure 3. Data input (write) timing [JESD209-2D figure 40] .................................................................... 9

Figure 4. Burst write: WL = 1, BL = 4 [JESD209-2D figure 41] ................................................................ 9

Figure 5. Burst write followed by burst read [JESD209-2D-2E figure 44] ........................................... 10

Figure 6. Report menu in QualiPHY General Setup ............................................................................... 11

Figure 7. The Test Report includes a summary table with links to the detailed test results ............. 12

Figure 8. QualiPHY main menu and compliance test Standard selection menu ................................ 15

Figure 9. QualiPHY configuration selection menu ................................................................................ 16

Figure 10. QualiPHY test item selection menu ....................................................................................... 18

Figure 11. Variable Setup and Limits Manager windows ...................................................................... 19

Figure 12. Start button .............................................................................................................................. 20

Figure 13. Example of pop-up connection diagram and dialog box .................................................... 20

Figure 14. PCF200 Deskew Fixture ......................................................................................................... 23

Figure 15. Differential probe properly connected to the fixture (Solder-In configuration) ............... 24

Figure 16. Accessing the probe calibration menu ................................................................................. 24

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Figure 17. Basic Probes Calibration menu ............................................................................................. 25

Figure 18. Advanced Mode Probe Calibration menu ............................................................................. 27

Figure 19. Probes Calibration menu Advanced tab ............................................................................... 28

Figure 20. Data output (read) timing [JESD209-2D figure 23] .............................................................. 39

Figure 21. Differential Input Slew Rate Definitions [JESD209-2D figure 111] ..................................... 41

Figure 22. Differential signal levels [JESD209-2D figure 110] .............................................................. 43

Figure 23. Data output (read) timing [JESD208-2B figure 23] .............................................................. 44

Figure 24. Burst read operation [JESD209-2D figure 25] ...................................................................... 44

Figure 25. Data input (write) timing [JESD209-2D figure 40] ................................................................ 46

Figure 26. Slew Rate [JESD209-2D figure 124] ...................................................................................... 48

Figure 27. Command Input Setup and hold timing [JESD209-2D figure 22] ....................................... 49

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QPHY-LPDDR2 Software Option

INTRODUCTION TO QPHY-LPDDR2

QPHY-LPDDR2 is an automated test package performing all of the real time oscilloscope tests for Double Data Rate in accordance with JEDEC Standard No. 209-2B. The software can be run on the LeCroy SDA/DDA/WavePro 740Zi and 760Zi, all SDA/DDA/WaveMaster 8Zi, and WaveRunner 625Zi and WaveRunner 640Zi oscilloscopes.

Required equipment

• SDA/DDA/WavePro 740/760Zi or SDA/DDA/WaveMaster 8Zi or WaveRunner 640Zi/625Zi oscilloscope

• Four D620 Probes with WL-Plink Prolink probe body

• Alternatively, D610 probes may be used if the voltage swing of the signal is within +/- 2.5Vp-p.

• TF-DSQ Probe Deskew and Calibration Fixture (not needed if using a Zi oscilloscope)

SIGNALS MEASURED

The compliance test requires probing the following signals (# is the negative polarity of the differential signal):

CK, CK# Input

Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the

crossing of the positive edge of CK and negative edge of CK#. Output (read) data is referenced to the crossings of CK and CK# (both directions of crossing).

DQ Input/Output

Data Input/Output: Bi-directional data bus.

DQS, DQS# Input/Output

Data Strobe: output with read data, input with write data. This signal is in phase with read data and 90

degrees out of phase with write data.

ADD/CTRL

In addition to the Clock, Data and Strobe signals, address and control signals can also be measured. Bank Address (BA0 – BA2), Chip Select (CS), Command Inputs (RAS, CAS and WE), Clock Enable (CKE) and On Die Termination (ODT) can all be specified as the signal under test.

BASIC FUNCTIONALITY

The functionality is extracted from JEDEC Standard No. 209-2B.

Read and write accesses to the LPDDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a burst length of four or eight or sixteen in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command.

Prior to normal operation, the LPDDR2 SDRAM must be initialized.

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Burst Read

The Burst Read command is initiated by having CS_n LOW, CA0 HIGH, CA1 LOW and CA2 HIGH at the rising edge of the clock. The command address bus inputs, CA5r-CA6r and CA1f-CA9f, determine the starting column address for the burst. The Read Latency (RL) is defined from the rising edge of the clock on which the Read Command is issued to the rising edge of the clock from which the tDQSCK delay is measured. The first valid datum is available RL * tCK + tDQSCK + tDQSQ after the rising edge of the clock where the Read Command is issued. The data strobe output is driven LOW tRPRE before the first rising valid strobe edge. The first bit of the burst is synchronized with the first rising edge of the data strobe. Each subsequent data-out appears on each DQ pin edge aligned with the data strobe. The RL is programmed in the mode registers.

Figure 1. Data output (read) timing [JESD209-2D figure 23]

Figure 2. Burst read followed by burst write [JESD209-2D figure 32]

The minimum time from the burst read command to the burst write command is defined by the Read Latency (RL) and the Burst Length (BL). Minimum read to write latency is RL + RU(tDQSCKmax/tCK) +

QPHY-LPDDR2-OM-G Rev B

QPHY-LPDDR2 Software Option

BL/2 + 1 - WL clock cycles. Note that if a read burst is truncated with a Burst Terminate (BST) command, the effective burst length of the truncated read burst should be used as “BL” to calculate the minimum read to write delay.

Burst Write

The Burst Write command is initiated by having CS_n LOW, CA0 HIGH, CA1 LOW and CA2 LOW at the rising edge of the clock. The command address bus inputs, CA5r-CA6r and CA1f-CA9f, determine the starting column address for the burst. The Write Latency (WL) is defined from the rising edge of the clock on which the Write Command is issued to the rising edge of the clock from which the tDQSS delay is measured. The first valid datum shall be driven WL * tCK + tDQSS from the rising edge of the clock from which the Write command is issued. The data strobe signal (DQS) should be driven LOW tWPRE prior to the data input. The data bits of the burst cycle must be applied to the DQ pins tDS prior to the respective edge of the DQS and held valid until tDH after that edge. The burst data are sampled on successive edges of the DQS until the burst length is completed, which is 4, 8, or 16 bit burst.

Figure 3. Data input (write) timing [JESD209-2D figure 40]

Figure 4. Burst write: WL = 1, BL = 4 [JESD209-2D figure 41]

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Figure 5. Burst write followed by burst read [JESD209-2D-2E figure 44]

USING QUALIPHY LPDDR2

QualiPHY LPDDR2 guides the user, step-by-step, through each of the source tests described in JEDEC Standard No. 209-2B. To do this, the user must setup a test session.

Users choose test configurations to run. There are several pre-loaded test configurations including:

• 1) Clock tests LPDDR2-667 (1 Probe)

• 2) CKdiff-DQse-DQSdiff 667 Write Burst (3 probes)

• 3) CKdiff-DQse-DQSdiff 667 Read Burst (3 probes)

• 4) Eye Diagram (3 Probes Debug)

• 5) Addr/Cmd tests (4 Probes)

• D3) Demo of All tests

The pre-loaded configurations provide quick and easy ways to begin compliance testing. You can create your own custom configurations (see the Customizing QualiPHY topic for details).

The variables are pre-loaded with the standard settings for compliance testing; however, the user may choose to create their own configuration with the variables set as desired.

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QPHY-LPDDR2 Software Option

QUALIPHY COMPLIANCE TEST PLATFORM

QualiPHY is LeCroy’s compliance test framework which leads the user through the compliance tests. QualiPHY displays connection diagrams to ensure tests run properly, automates the oscilloscope setup, and generates complete, detailed reports.

The QualiPHY software application automates the test and report generation.

Figure 6. Report menu in QualiPHY General Setup

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See the QualiPHY Operator’s Manual for more information on how to use the QualiPHY framework.

Figure 7. The Test Report includes a summary table with links to the detailed test results

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QPHY-LPDDR2 Software Option

Oscilloscope Option Key Installation

An option key must be purchased to enable the QPHY-LPDDR2 option. Call LeCroy Customer Support to place an order and receive the code.

Enter the key and enable the purchased option as follows:

1. From the oscilloscope menu select Utilities  Utilities Setup

2. Select the Options tab and click the Add Key button.

3. Enter the Key Code using the on-screen keyboard.

4. Restart the oscilloscope to activate the option after installation.

Typical (Recommended) Configuration

QualiPHY software can be executed from the oscilloscope or a host computer. The first step is to install QualiPHY. Please refer to the QualiPHY Operator’s Manual for installation instructions.

LeCroy recommends running QualiPHY on an oscilloscope equipped with Dual Monitor Display capability (Option DMD-1 for oscilloscopes where this is not standard). This allows the waveform and measurements to be shown on the oscilloscope LCD display while the QualiPHY application and test results are displayed on a second monitor.

By default, the oscilloscope appears as a local host when QualiPHY is executed in the oscilloscope. Follow the steps under Oscilloscope Selection (as follows) and check that the IP address is 127.0.0.1.

Remote (Network) Configuration

It is also possible to install and run QualiPHY on a host computer, controlling the oscilloscope with a Network/LAN Connection.

The oscilloscope must already be configured, and an IP address (fixed or network-assigned) must already be established.

Oscilloscope Selection

Set up the oscilloscope using QualiPHY over a LAN (Local Area Network) by doing the following:

1. Make sure the host computer is connected to the same LAN as the oscilloscope. If unsure, contact your system administrator.

2. From the oscilloscope menu, select Utilities  Utilities Setup

3. Select the Remote tab.

4. Verify the oscilloscope has an IP address and the control is set to TCP/IP.

5. Run QualiPHY in the host computer and click the General Setup button.

6. Select the Connection tab.

7. Enter the IP address from step 4 (previous).

8. Click the Close button.

QualiPHY is now ready to control the oscilloscope.

QPHY-LPDDR2-OM-G Rev B

QualiPHY tests the oscilloscope connection after clicking the Start button. The system prompts you if there is a connection problem. QualiPHY’s Scope Selector function can also be used to verify the connection. Please refer to the QualiPHY Operator’s Manual for explanations on how to use Scope Selector and other QualiPHY functions.

Accessing the QPHY-LPDDR2 Software using QualiPHY

This topic provides a basic overview of QualiPHY’s capabilities. Please refer to the QualiPHY Operator’s Manual for detailed information.

Access the QPHY-LPDDR2 software using the following steps:

1. Wait for the oscilloscope to start and have its main application running.

2. Launch QualiPHY from the Analysis menu if installed on the oscilloscope or from the desktop icon if installed on a host computer.

3. From the QualiPHY main window (as follows), select Standard, then LPDDR2 from the pop-up menu (if not already selected). If you check the Pause on Failure box (circled) QualiPHY prompts to retry the test in the case of a failure.

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QPHY-LPDDR2 Software Option

Figure 8. QualiPHY main menu and compliance test Standard selection menu

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Teledyne QPHY-LPDDR2 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual