Teledyne QPHY-DDR4 User Manual
QPHY-DDR4
Operator’s Manual
Revision A – June, 2014
Relating to the Following Release
Versions:
• Software Version Rev. 7.4
• DDR4 Script Rev. 7.4
• Style Sheet Rev. 1.2
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© 2014 by Teledyne LeCroy . All rights reserved.
Teledyne LeCroy and other product or brand names are trademarks or requested trademarks of their
respective holders. Information in this publication supersedes all earlier versions. Specifications are
subject to change without notice.
924291 Rev A
June 2014
QPHY-DDR4 Software Option
TABLE OF CONTENTS
Introduction to Qualiphy DDR4 ................................................................................................ 6
Required Equipment ..................................................................................................................................... 6
Using Qualiphy DDR4 ............................................................................................................... 7
QualiPHY Compliance Test Platform ....................................................................................... 8
Oscilloscope Option Key Installation ........................................................................................................... 10
Typical (Recommended) Configuration ....................................................................................................... 10
Remote (Network) Configuration ................................................................................................................ 10
Oscilloscope Selection ................................................................................................................................ 10
Accessing the QPHY-DDR4 Software using QualiPHY .............................................................................. 11
Customizing QualiPHY ................................................................................................................................ 13
Creating Custom Configurations ................................................................................................................. 14
QPHY-DDR4 OPERATION ......................................................................................................................... 16
QPHY-DDR4 Measurement Preparation ................................................................................ 17
Deskewing the Probes ................................................................................................................................ 17
Connecting the Probes ................................................................................................................................ 19
Read (R) and Write (W) Burst Requirements ............................................................................................. 19
Initial Signal Checking ................................................................................................................................. 21
QPHY-DDR4 Test Configurations .......................................................................................... 23
QPHY-DDR4 Variables ............................................................................................................ 24
QPHY-DDR4 LIM IT SETS ........................................................................................................ 28
QPHY-DDR4 Test Descriptions .............................................................................................. 29
Clock Tests (Ck Diff) .................................................................................................................................... 29
Eye Diagram Tests (CKdiff-DQSdiff-DQse) ................................................................................................. 38
Write Bursts (Inputs) - DQ and DQS Eyes .......................................................................................... 38
DQ Input Compliance Mask ................................................................................................................. 39
VIHL_AC, DQ AC Input Swing Pk-Pk .................................................................................................. 40
Read Bursts (Outputs) - DQ and DQS Eyes ....................................................................................... 41
VOHL_AC, DQ AC Output Swing Pk -Pk ............................................................................................. 42
Electrical Tests (CKdiff-DQSdiff-DQse) ....................................................................................................... 43
SRIN_dIVW, Input Slew Rate .............................................................................................................. 43
tDVAC, Time Above AC Level ............................................................................................................. 47
AC Overshoot/Undershoot ................................................................................................................... 48
SRQ, Output Slew Rate ....................................................................................................................... 51
Timing Tests (CKdiff-DQSdiff-DQse) ........................................................................................................... 53
tDQSQ_total, DQS to DQ Skew .......................................................................................................... 53
tQSH/tQSL, DQS Output High/Low Time ............................................................................................ 55
tQH_total, DQ Output Hold Time ......................................................................................................... 56
tDQSCK, CK to DQS Skew ................................................................................................................. 57
tHZ/tLZ, High/Low Impedance Time .................................................................................................... 59
tRPRE/tRPST, Read Pre/Postamble Time .......................................................................................... 61
tDQSS, CK to DQS Skew .................................................................................................................... 62
tDQSH/tDQSL, DQS Input High/Low Pulse Width .............................................................................. 64
tDIPW, DQ Input Pulse Width .............................................................................................................. 65
tDSS/tDSH, DQS to CK Setup/Hold Time ........................................................................................... 66
Tdqs/Tdqh, DQ to DQS Setup/Hold Time ........................................................................................... 68
tWPRE/tWPST, Write Pre/Postamble Time ........................................................................................ 69
Appendix A: File name conventions for saved waveforms .................................................. 71
Appendix B: Common WaRning Messages .......................................................................... 72
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TABLE OF FIGURES
Figure 1 - Report menu in QualiPHY General Setup................................................................................ 8
Figure 2 - The Test Report includes a summary table with links to the detailed test results ............. 9
Figure 3 - QualiPHY main menu and compliance test Standard selection menu ............................... 11
Figure 4 - QualiPHY configuration selection menu ............................................................................... 12
Figure 5 - QualiPHY test item selection menu ....................................................................................... 13
Figure 6 - Variable Setup and Limits Manager windows ....................................................................... 15
Figure 7 - Start button ............................................................................................................................... 16
Figure 8 - Example of pop-up connection diagram and dial og b ox .................................................... 16
Figure 9 – Overview of QPHY-DDR4 Probe Setups ............................................................................... 19
Figure 10 – Memtest86+ ........................................................................................................................... 20
Figure 11 – Verification of CK signal ....................................................................................................... 21
Figure 12 – Verification of Idle Levels ..................................................................................................... 22
Figure 13 – Example of Auto Levels Reported During Test .................................................................. 27
Figure 14 - Oscilloscope Configuration after tCK, tCH, tCL and tJIT(duty) Tests .............................. 30
Figure 15 - tCK, tCH, tCL and tJIT(duty) Results ................................................................................... 31
Figure 16 - Oscilloscope Configuration after tJIT(per)_total and tJIT(per)_dj Tests .......................... 32
Figure 17 - tJIT(per)_total and tJIT(per)_dj Results ............................................................................... 33
Figure 18 - Oscilloscope Configuration after tJIT(cc)_total and tJIT(cc)_dj Tests ............................. 34
Figure 19 - tJIT(cc)_total and tJIT(cc)_dj Results .................................................................................. 34
Figure 20 - Oscilloscope Configuration after tERR(2per), tERR (3per), tERR (4per), and tERR (5per)
Tests .................................................................................................................................................... 35
Figure 21 - tERR(2per), tERR (3per), tERR (4per), and tERR (5per) Results ....................................... 36
Figure 22 - Oscilloscope Configuration after Write Bursts (Inputs) – DQ and DQS Eyes ................. 38
Figure 23 - Oscilloscope Configuration after DQ Input Compliance Mask Test ................................. 39
Figure 24 - DQ Input Compliance Mask Results .................................................................................... 40
Figure 25 - Oscilloscope Configuration after VIHL_AC Test ................................................................ 40
Figure 26 – VIHL_AC Results ................................................................................................................... 40
Figure 27 - Oscilloscope Configuration after Read Bursts (Outputs) Test ......................................... 41
Figure 28 - Oscilloscope Configuration after DQ Read Eye Test ......................................................... 42
Figure 29 - Oscilloscope Configuration after SRIN_dIVW_R Test ....................................................... 44
Figure 30 – SRIN_dIVW Test Results ...................................................................................................... 44
Figure 31 - Oscilloscope Configuration after Slew_R Test ................................................................... 45
Figure 32 – SRIN_dIVW Test Results ...................................................................................................... 46
Figure 33 - Oscilloscope Configuration after the tDVAC Test .............................................................. 47
Figure 34 - tDVAC Results ........................................................................................................................ 47
Figure 35 - Oscilloscope Configuration after Overshoot Peak Amplitude Test .................................. 48
Figure 36 – Overshoot/Undershoot Results ........................................................................................... 49
Figure 37 - Oscilloscope Configuration after the Overshoot Area Test .............................................. 50
Figure 38 – Overshoot/Undershoot Results ........................................................................................... 51
Figure 39 - Oscilloscope Configuration after the SRQ test .................................................................. 52
Figure 40 - SRQ Results ........................................................................................................................... 52
Figure 41 - Oscilloscope Configuration after the tDQSQ_total test ..................................................... 54
Figure 42 – tDQSQ_total Results ............................................................................................................. 54
Figure 43 - Oscilloscope Configuration after the tQSH test ................................................................. 55
Figure 44 – tQSH/tQSL Results ................................................................................................................ 55
Figure 45 - Oscilloscope Configuration after the tQH_toal test ........................................................... 56
Figure 46 – tQH_total Results .................................................................................................................. 56
Figure 47 - Oscilloscope Configuration after the tDQSCK test ............................................................ 57
Figure 48 – tDQSCK Results .................................................................................................................... 58
Figure 49 - Oscilloscope Configuration after the tLZ(DQ) test ............................................................. 59
Figure 50 – tHZ/tLZ Results ...................................................................................................................... 60
Figure 51 - Oscilloscope Configuration after the tRPRE test ............................................................... 61
Figure 52 – tRPRE/tRPST Results ........................................................................................................... 61
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QPHY-DDR4 Software Option
Figure 53 - Oscilloscope Configuration after the tDQSS test ............................................................... 62
Figure 54 – tDQSS Results ....................................................................................................................... 63
Figure 55 - Oscilloscope Configuration after the tDQSH test .............................................................. 64
Figure 56 – tDQSH/tDQSL Results .......................................................................................................... 64
Figure 57 - Oscilloscope Configuration after the tDIPW test ............................................................... 65
Figure 58 – tDIPW Results ........................................................................................................................ 66
Figure 59 - Oscilloscope Configuration after the tDSS test ................................................................. 66
Figure 60 – tDSS/tDSH Results ................................................................................................................ 67
Figure 61 - Oscilloscope Configuration after the Tdqs test ................................................................. 68
Figure 62 – Tdqs/Tdqh Results ................................................................................................................ 68
Figure 63 - Oscilloscope Configuration after the tWPST test .............................................................. 69
Figure 64 – tWPRE/tWPST Re sults.......................................................................................................... 70
Figure 65 – File Name Convention Summary ......................................................................................... 71
Figure 66 – Clock Speed Grade Warning ................................................................................................ 72
Figure 67 – R/W Burst Detection Warning .............................................................................................. 72
Figure 68 – DUT Name Warning ............................................................................................................... 73
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Introduction to Qualiphy DDR4
QPHY-DDR4 is an automated test package performing all of the real time oscilloscope in accordance
with JEDEC Standard No. JESD79-4. The standard is available on jedec.org.
The software can be run on any Teledyne LeCroy Zi Series oscillosc ope wit h at lea s t 8 GHz
bandwidth. The oscilloscope must also be equipped with the QPHY-DDR4 and SD AIII opt ions.
Required Equipment
• Real time Teledyne LeCroy Oscillosc ope with at least 8 GHz bandwidth. The minimum
recommended bandwidth for DDR4 is 13 GHz.
• QPHY-DDR4 (available on firmware 7.4.0.3 or later) and SDA III options
Note: SDAIII is included on all SDA and DDA oscilloscope models
o The VirtualProbe option is required to perform de-embedding
• A minimum of three Dxx30-PS differential probes (a fourth probe is required for some probe
setups)
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QPHY-DDR4 Software Option
Using Qualiphy DDR4
QualiPHY DDR4 guides the user, step-by-step, through each of the tests in conformance with the
JEDEC DDR4 specification: JESD79-4. To do this, the user must set up a test session.
Before beginning testing, users choose the test configuration they wish to run. There are seven preloaded test configurations. They are:
• 1) Clock tests DDR4-1600 (1 Probe)
• 2) Ckdiff-DQSdiff-DQse DDR4-1600 Write (3 Probes)
• 3) Ckdiff-DQSdiff-DQse DDR4-1600 Read (3 Probes)
• 4) Eye Diagram DDR4-1600 (3 Probes)
• 5) ADD/CTRL tests DDR4-1600 (4 Probes)
• 6) Pre/Postamble test DDR4-1600 (3 Probes)
• D1) Demo of All tests
These pre-loaded configurations provide quick and easy ways to begin DDR4 testing (see the QPHYDDR4 Test Configurations section for details on eac h c onf igurati on). The configurations are separated by
the signals which need to be probed in order to run each configuration. If the user does not want to run
any of these configurations, they can create their own custom configuration (see the Creating Custom
Configurations section for details).
The pre-loaded configurations are set up to run all of the tests required for compliance. If this is not what
the user wants, the variables can be modified (see the QPHY-DDR4 Variables section of this manual).
The variables are pre-loaded with the standard settings for compliance testing; however, the user may
choose to create their own configuration with the variables set as desired.
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QualiPHY Compliance Test Platform
QualiPHY is Teledyne LeCroy’s compliance test framework which leads the user through the
compliance tests. QualiPHY displays connection diagrams to ensure tests run properly, automates the
oscilloscope setup, and generates complete, detailed reports.
The QualiPHY software application automates the test and report generation.
Figure 1 - Report menu in QualiPHY Ge n eral Setup
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QPHY-DDR4 Software Option
Figure 2 - The Test Report includes a summary table with links to the detailed test results
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Oscilloscope Option Key Installation
The required option k eys must be purchased to en able the QPHY-DDR4 compliance tests. If you do not
have the required option keys already call Teledyne LeCroy Customer Support to place an order and
receive the codes.
Enter the key and enable the purchased option as follows:
1. From the oscilloscope menu select Utilities Utilities Setup...
2. Select the Options tab and click the Add Key button.
3. Enter the Key Code using the on-screen keyboard.
4. Restart the oscilloscope to activate the option after installation.
Typical (Recommended) Configuration
QualiPHY software can be executed from the oscilloscope or a host computer. The first step is to install
QualiPHY. Please refer to the QualiPHY Operator’s Manual for installation instructions.
Teledyne LeCroy recommends running Qu aliPHY on an oscillosc ope equipped with Dual Monitor Dis play
capability (Option DMD-1 for oscilloscopes where this is not standard). This allows the waveform and
measurements to be shown on the oscilloscope LCD display while the QualiPHY application and test
results are displayed on a second monitor.
By default, the oscilloscope appears as a local host when QualiPHY is executed in the oscilloscope.
Follow the steps under O sc illo scop e Selection (as follows) and check that the IP address is 127.0.0.1.
Remote (Network) Configuration
It is also possible to install and run QualiPHY on a host computer, controlling the oscilloscope with a
Network/LAN Connection.
The oscilloscope must already be configured, and an IP address (fixed or network-assigned) must already
be established.
Oscilloscope Selection
Set up the oscilloscope using QualiPHY over a LAN (Local Area Network) by doing the following:
1. ... Make sure the host computer is connected to the same LAN as the oscilloscope. If
unsure, contact your system administrator.
2. ... From the oscilloscope menu, select Utilities Utilities Setup...
3. ... Select the Remote tab.
4. ... Verify the oscilloscope has an IP address and the control is set to TCP/IP.
5. ... Run QualiPHY in the host computer and click the General Setup button.
6. ... Select the Connection tab.
7. ... Enter the IP address from step 4 (previous).
8. ... Click the Close button.
QualiPHY is now ready to control the oscilloscope.
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QPHY-DDR4 Software Option
QualiPHY tests the oscilloscope connection after clicking the Start button. The system prompts you if
there is a connection problem. QualiPHY’s Scope Selector function can also be used to verify the
connection. Please refer to the QualiPHY Operator’s Manual for explanations on how to use Scope
Selector and other QualiPHY functions.
Accessing the QPHY-DDR4 Software using QualiPHY
This topic provides a basic overview of QualiPHY’s capabilities. Please refer to the QualiPHY Operator’s
Manual for detailed information.
Access the QPHY-DDR4 software using the following steps:
1. Wait for the oscilloscope to start and have its main application running.
2. Launch QualiPHY from the Analysis menu if installed on the oscillos cope or from the desktop
icon if installed on a host computer.
3. From the QualiPHY main window (as follows), select Standard, then DDR DDR4 from the
pop-up menu (if not alread y selected) . If you check the Pause on Failure box (circled) QualiPH Y
prompts to retry the measure whenever a test fails.
Figure 3 - QualiPHY main menu and compliance test Standard selection menu
4. Click the Configuration button in the QualiPHY main menu:
5. Select a configuration from the pop-up menu:
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Figure 4 - QualiPHY configuration selection menu
6. Click Start.
7. Follow the pop-up windo w pr ompts.
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QPHY-DDR4 Software Option
Customizing QualiPHY
The predefined conf igurations in t he Configuration sc reen can not be m odified. Ho wever, you can create
your own test confi gurations by copying one of the s tandard t est c onf ig ur at ions a nd making modifications.
A description of the test is also shown in the description field when selected.
Figure 5 - QualiPHY test item selection menu
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Creating Custom Configurations
Beginning with any of the pre-loaded configurations,
1. Click on the Test Selector tab to change what tests you would like to be included in your new
configuration.
2. Click on the Variable Setup tab to change the variables for your new configuration.
3. Click on the Limits tab to change which limit set should be used for your new configuration
• See QualiPHY Manual for more information
4. Once a change has been made to any of these sections, the Save As button becomes clickable
on the bottom of the dialog.
5. Clicking the Save As button will prompt you for a new configuration name and desc ription.
Note: If a Custom Configuration was used for the procedure, the Save button will also become
clickable on the bottom of the dialog. Clicking this button will update the current configuration
with new changes.
6. Once a custom configuration is defined, script variables and the test limits can be changed by
using the Variable Setup and Limits Manager from the Edit/View Configuration window.
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Figure 6 - Variable Setup and Limits Manager windows
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QPHY-DDR4 OPERATION
After pressing Start in the QualiPHY menu, the softwar e instructs how to set up the test using pop-up
connection diagrams and dialog boxes. QualiPHY also instructs how to properly configure the Device
Under T est (DUT) to change test signal modes (when necessary).
Figure 7 - Start button
Figure 8 - Example of pop-up connection diagram and dialog b ox
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QPHY-DDR4 Software Option
QPHY-DDR4 Measurement Preparation
Deskewing the Probes
For DDR measurements it is crucial to make sure the probes are properly deskewed before running
QPHY-DDR4 to ensure proper signal timing. Ideally, when deskewing the same settings should be used
as when QualiPHY is acquiring the signals for analysis. This will ensure that the channels are deskewed
using the same setup as when running conformance tests. Deskew values are saved and stored by
QPHY at the beginning of each run.
Required Equipment
• PCF200 (included with D1330-PS)
• Square-Pin (SP) tip (included with D1330-PS)
• 50 Ω terminator
Note: Alternatively an LPA-K-A adapter and a SMA cable could be used
Methodology
Before beginning the procedure the oscilloscope should be warmed for at least 20 minutes.
1.) Connect the PCF200 to the oscilloscope’s fast edge output. The PCF 200 fixture has two different
signal paths that can be used, depending on the type of probe tip being used for the
measurement. The upper signal path is for deskewing Solder-In (SI), Quick-Connect (QC) and
Adjustable Tip (AT) probe tips and the lower circuit is for Square-Pin (SP) probe tips. Depending
upon which probe tip is being used the appropriate signal path should be connected to the fast
edge output. For ease of connectivity it is recommended that SP tip is used. As long as the same
tip is used to deskew each probe it does not matter which style of probe tip is used.
2.) Probes are connected electrically in a single-ended arrangement using their designated area on
the fixture. The positive side of the probe must be connected to the signal trace (in between the
two white strips), while the negative side is connected to the ground plane (outside of the white
strips). The positive polarity is indicated on the tip of the probe by a plus sign. In order to minimize
reflections a 50 Ω terminator shall be applied to the end of the signal path in use. If a 50 Ω
terminator is not available a SMA cable can be used to terminate the PCF200 to one of the
oscilloscope’s outputs.
3.) Set the oscilloscope trigger source to “fast edge”, set the trigger type to “edge”, set the trigger
level to 50%, and set the oscilloscope timebase delay to zero. It is recommended that the
oscilloscope be bandwidth limited to the same setting which QualiPHY uses. For DDR4 the
bandwidth limit is set to 13 GHz.
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Once everything is properly set up the oscilloscope display should look similar to the figure below. If there
was no propagation delay due to the probe, and no internal oscilloscope channel propagation delay, the
50% trigger level would be in the middle of the oscilloscope grid.
The channel’s deskew value shall be adjusted so that the 50% rising edge point is centered in time, as
shown below. From the channel setup dialog, enable Sinx/x interpolation and set the averaging to 50
sweeps. To adjust the deskew value, touch the Deskew entry once to highlight it yellow, then use the
Adjust control knob to modify the value. Starting with a timebase of approximately 10 ns/div, adjust the
deskew value to move the rising edge of the trace to the center of the display. Now, decrease the
timebase to around 20 ps/div and adjust the deskew value so that the 50% rising edge point is centered in
time. This process shall be repeated for each probe using the same probe tip.
When QualiPHY is started the deskew values from each channel dialog are saved and stored by QPHY at
the beginning of each run. However, at the end of the testing these values will be erased. By saving a
panel setup it is possible to refer to the deskew values after testing has completed.
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QPHY-DDR4 Software Option
Connecting the Probes
Determining Signals to Access
The required signals to probe depend up on which tests are being run in QPHY-DDR4. The tests are
broken up into different “Probe Setups” to allow the user to easily see which signals are required for a
particular test. You can view each of the probe setups in the Test Selector tab.
Figure 9 – Overview of QPHY-DDR4 Probe Setups
Best Places to Probe
The DDR4 specification is defined at the balls of the DRAM so the probes should be placed as close to
the DRAM as possible in order to closely follow the specification. This is important to minimize reflections
on the signals. However, in some situations it can make sense to place the probes as close to the
controller as possible. For example, if the user is a controller designer and is only interested in verifying
the performance of the controller. It should be noted that some of the limits may not be applicable in this
scenario.
One of the most desirable locations for probing is at the back side of the vias. This will generally result in
good signal integrity; however, these may not always be accessible. Another alternative is to use an
interposer such as the ones available from Nexus Technologies. No matter where the probes are placed it
is essential to ensure that the probing points are equidistant from the DRAM. This will ensure that there is
no additional skew introduced for timing measurements.
Read (R) and Write (W) Burst Requirements
R/W Burst Detection
QPHY-DDR4 separates R and W burst depending upon the skew between the data (DQ) and strobe
(DQS) signals. For a W burst QPHY expects to see that the DQ and DQS signals are approximately a
quarter cycle out of phase. For a R burst QPHY expects to that the DQ and DQS signals are in phase.
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R/W Burst Generation
QPHY-DDR4 recommends to have a minimum of 10 R and 10 W bursts during each acquisition but for
greater statistical significance it is encouraged to have more. Programs which can communicate with the
DRAM and controller are widely available online. One example is Memtest86+ which is available for
download from memtest.org. When using Memtest it is recommended to use test mode 7, which will
randomly generate both R and W bursts. Additionally a custom program can be used to stimulate the
DUT.
Figure 10 – Memtest86+
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QPHY-DDR4 Software Option
Initial Signal Checking
Before running QPHY-DDR4 the user should have a quick look at their signals to verify that they make
sense. This section covers some of the basic things which should be verified by the operator before
running QPHY-DDR4.
Expected Channels
By default QPHY-DDR4 expects to see the clock (CK) on CH1, DQS on CH2 and DQ on CH3. This is
what is shown in the connection diagram. The Channel Index variable can always be used to modify any
of these channels.
Signal Amplitude
For best results it is recommended that the signals take up 80% of the grid. In order to adjust the
amplitude of each signal use the Channel Gain variable. The user can determine what the optimal gain
settings are before running QPHY-DDR4 to ensure the best results.
Clock Frequency
By using the frequency parameter on the oscilloscope the user can verify that the DDR system is running
at the transfer rate which the user expects (Transfer Rate =Frequency * 2). This will also help in the limit
selection. The user should also do a quick visual inspection to ensure that the signal does not have any
non-monotonic edges due to reflections.
Figure 11 – Verification of CK signal
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Presence of R/W Burst
The operator should do a quick check to make sure their device is outputting the expected bursts. As a
general rule of thumb, during a R burst DQ and DQS should be in phase and during a W burst DQ and
DQS should be a quarter cycle out of phase. Additionally, the signal amplitude can be used to determine
the presence of R and W bursts. If probing at the memory R bursts will have a larger amplitude than W
bursts.
Check Idle Levels
Before running QPHY-DDR4 the operator should do a quick validation of the signal idle levels. If the
signal idle levels are off this will have an impact on the R/W burst detection, electrical, and timing
measurements. DQS should have an idle level of ~ 0 mV. DQ should have an idle level slightly less than
1.2 V.
Figure 12 – Verification of Idle Levels
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