Teledyne QPHY-DDR3 User Manual

QPHY-DDR3

DDR3 Serial Data

Operator’s Manual

917717 Revision C – July 2011

Relating to the Following Release
Versions:

• Software Option Rev. 6.1

• DDR3 Script Rev. 1.1

• Style Sheet Rev. 1.2

LeCroy Corporation
700 Chestnut Ridge Road
Chestnut Ridge, NY, 10977-6499
Tel: [phone], Fax: [phone]

Internet: www.lecroy.com
© 2009 by LeCroy Corporation. All rights reserved.

LeCroy and other product or brand names are trademarks or requested trademarks of their respective
holders. Information in this publication supersedes all earlier versions. Specifications are subject to
change without notice.

917717 Rev C

QPHY-DDR3 Software Option

TABLE OF CONTENTS

INTRODUCTION TO QPHY-DDR3 ............................................................................................ 7

Required equipment ................................................................................................................................................... 7

SIGNALS MEASURED .............................................................................................................. 7

CK, CK# Input ............................................................................................................................................................ 7

DQ Input/Output ......................................................................................................................................................... 7

DQS, DQS# Input/Output ........................................................................................................................................... 7

CS# Input ................................................................................................................................................................... 7

BASIC FUNCTIONALITY .......................................................................................................... 8

READ Burst Operation ............................................................................................................................................. 14

WRITE Burst Operation ........................................................................................................................................... 15

USING QUALIPHY DDR3 ........................................................................................................ 16

QUALIPHY COMPLIANCE TEST PLATFORM ....................................................................... 16

Oscilloscope Option Key Installation ........................................................................................................................ 19

Typical (Recommended) Configuration .................................................................................................................... 19

Remote (Network) Configuration ............................................................................................................................. 19

Oscilloscope Selection ............................................................................................................................................. 19

Accessing the QPHY-DDR3 Software using QualiPHY ........................................................................................... 20

Customizing QualiPHY ............................................................................................................................................. 23

QPHY-DDR3 Operation............................................................................................................................................ 25

DDR3 MEASUREMENT PREPARATION ................................................................................. 8

Deskewing the Probes ............................................................................................................................................... 8

Differential Probe Deskew Procedure using TF-DSQ on non-Zi oscilloscopes ......................................................... 8

Differential Probe Deskew Procedure on Zi oscilloscopes using PCF200 ................................................................ 8

PCF200 Fixture Overview ................................................................................................................................... 8

Probe Connection to PCF200 ............................................................................................................................. 9

Probe Calibration Menu .................................................................................................................................... 10

Probe Calibration Procedure ............................................................................................................................ 11

QPHY-DDR3 TEST CONFIGURATIONS ................................................................................ 26

1) Clock tests DDR3-1333 (1 Probe) ....................................................................................................................... 26

2) CKdiff-DQse-DQSdiff 1333 Write Burst (3 Probes) ............................................................................................. 26

3) CKdiff-DQse-DQSdiff 1333 Read Burst (3 Probes) ............................................................................................. 28

4) Eye Diagram (3 Probes Debug) ........................................................................................................................... 28

5) Eye Diagram with CS Enabled (4 Probes Debug) ............................................................................................... 28

6) CKDiff-DQse-DQS-ADD/CTRLse (4 Probes Debug) .......................................................................................... 28

7) CKdiff-DQse-DQSp-DQsn (4 probes test, each DQS signal probed single ended) ............................................ 29

8) CKp-CKn-DQse-DQSdiff (4 probe test, each CK signal is probed single ended) ............................................... 29

9) Vref tests .............................................................................................................................................................. 29

D1) Demo of All Tests ............................................................................................................................................... 29

QPHY-DDR3 VARIABLES ...................................................................................................... 29

General Variables ..................................................................................................................................................... 29

DUT Speed Grade in MT/s ............................................................................................................................... 29

DQ Signal Name ............................................................................................................................................... 30

DQS Signal Name............................................................................................................................................. 30

Clock Signal Name ........................................................................................................................................... 30

DUT Power Supply VDDQ ................................................................................................................................ 30

4th Probe Names ...................................................................................................................................................... 30

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Chip Select Signal Name .................................................................................................................................. 30

Script Settings .......................................................................................................................................................... 30

Save Acquired Waveforms ............................................................................................................................... 30

Silent mode control ........................................................................................................................................... 30

Stop On Test to review results .......................................................................................................................... 30

Use Chip Select (require one more probe) ....................................................................................................... 30

Waveform Path ................................................................................................................................................. 30

Latency Setting ........................................................................................................................................................ 30

Overall Read Latency ....................................................................................................................................... 30

Overall Write Latency ....................................................................................................................................... 31

Demo Settings .......................................................................................................................................................... 31

Use Stored Waveforms ..................................................................................................................................... 31

Recalled Waveform File Index (5 digits) ........................................................................................................... 31

Define format used to set trace names ............................................................................................................. 31

Use Stored Trace for Speed Grade .................................................................................................................. 31

Advanced Settings ................................................................................................................................................... 32

Clock Period per Screen Division ..................................................................................................................... 32

Number of cycles for Clock test ........................................................................................................................ 32

Max. Number Of Samples Per Clock Period .................................................................................................... 32

Configuration Specific Variables............................................................................................................................... 32

XX Channel Gain .............................................................................................................................................. 32

XX Channel Index ............................................................................................................................................. 32

XX Channel Invert ............................................................................................................................................. 32

XX Channel Offset ............................................................................................................................................ 32

Speed Bin Paramters ............................................................................................................................................... 32

CAS Latency ..................................................................................................................................................... 32

CAS Write Latency............................................................................................................................................ 33

Speed Bin ......................................................................................................................................................... 33

QPHY-DDR3 LIMIT SETS ....................................................................................................... 34

DDR3-800 ................................................................................................................................................................ 34

DDR3-1066 .............................................................................................................................................................. 34

DDR3-1333 .............................................................................................................................................................. 34

DDR3-1600 .............................................................................................................................................................. 34

QPHY-DDR3 TESTS ................................................................................................................ 34

Clock Test s ............................................................................................................................................................... 34

tCK(avg), Average Clock Period ................................................................................................................................ 34

tCK(abs), Absolute Clock Period ................................................................................................................................ 34

tCH(avg), Average High Pulse Width ......................................................................................................................... 34

tCL(avg), Average Low Pulse Width .......................................................................................................................... 35

tCH(abs), Absolute High Pulse Width ........................................................................................................................ 35

tCL(abs), Absolute Low Pulse Width .......................................................................................................................... 35

tJIT(duty), Half Period Jitter ....................................................................................................................................... 35

tJIT(per), Clock Period Jitter ...................................................................................................................................... 35

tJIT(cc), Cycle to Cycle Period Jitter .......................................................................................................................... 35

tERR(n per), Cumulative Error ................................................................................................................................... 36

Eye Diagram ............................................................................................................................................................ 36

Write Burst (Inputs) .................................................................................................................................................... 36

Read Burst (Outputs) ................................................................................................................................................. 36

Electrical Tests ......................................................................................................................................................... 36

Write Bursts (Inputs) ......................................................................................................................................... 36

Slew (Input Slewrate) ..................................................................................................................................................... 36

SlewR and SlewF ....................................................................................................................................................... 36

Logic Levels ................................................................................................................................................................... 37

VIH(ac), maximum AC input logic high ....................................................................................................................... 37

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VIH(dc), minimu m DC input lo gic high ....................................................................................................................... 37

VIL(ac), maximum AC input logic low ......................................................................................................................... 38

VIL(dc), minimum DC input logic low ......................................................................................................................... 38

Read Bursts (Outputs) ...................................................................................................................................... 38

SRQ (Output Slew Rate) ................................................................................................................................................ 38

SRQr and SRQf ......................................................................................................................................................... 38

Timing Tests ............................................................................................................................................................. 38

Read Bursts ...................................................................................................................................................... 38

tDQSQ, DQS-DQ Skew for DQS and Associated DQ Signals ....................................................................................... 38

tQH, DQ/DQS Output Hold Time From DQS.................................................................................................................. 39

tDQSCK, DQS Output Access Time from CK/CK # ....................................................................................................... 39

Write Bursts ...................................................................................................................................................... 41

tDQSS, DQS latching rising transitions to associated CK edge ..................................................................................... 41

tDQSH, DQS Input High Pulse Width ............................................................................................................................. 41

tDQSL, DQS Input Low Pulse Width .............................................................................................................................. 41

tDSS, DQS Falling Edge to CK Setup Time ..................................................................................................... 42

tDSH, DQS Falling Edge Hold Time from CK ................................................................................................... 42

tDS(base), DQ and DM Input Setup Time ........................................................................................................ 42

tDH(base), DQ and DM Input Hold Time .......................................................................................................... 42

Four Probe tests measurements using ADDR/CTL ................................................................................................. 42

tIS /tIH (base) - Address and Control Input Setup Time (Hold Time) ............................................................... 42

tIPW, Control and Address Input pulse width for each input ............................................................................ 43

VIX(ac), AC Differential Input Cross Point Voltage ........................................................................................... 44

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FIGURES

Figure 1. READ Burst Operation RL = 5 (AL = 0, CL = 5, BL8) [JESD79-3D Figure 25] ...................... 14

Figure 2. READ Burst Operation RL = 9 (AL = 4, CL = 5, BL8) [JESD79-3D Figure 26] ...................... 14

Figure 3. Write Timing Definition and Parameters [JESD79-3D Figure 43] ......................................... 15

Figure 4. Report menu in QualiPHY General Setup ............................................................................... 17

Figure 5. The Test Report includes a summary table with links to the detailed test results ............. 18

Figure 6. QualiPHY main menu and compliance test Standard selection menu ................................ 21

Figure 7. QualiPHY configur ation selection menu ................................................................................ 22

Figure 8. QualiPHY test item selection menu ......................................................................................... 23

Figure 9. Variable Setup and Limits Manager windows ........................................................................ 24

Figure 10. Start button .............................................................................................................................. 25

Figure 11. Example of pop-up connection diagram and dialog box .................................................... 25

Figure 12. PCF200 Deskew Fixture ........................................................................................................... 9

Figure 13. Differential probe properly connected to the fixture (Solder-In configuration) ............... 10

Figure 14. Accessing the probe calibration menu ................................................................................. 11

Figure 15. Basic Probes Calibration menu ............................................................................................. 11

Figure 16. Ad van ced Mode Probe Calibration menu ...................................... Error! Bookmark not defined.

Figure 17. Probes Calibration menu Advanced tab ........................................ Error! Bookmark not defined.

Figure 18. AC input test signal waveform [JESD79-3D figure 94] ........................................................ 37

Figure 19 - Data output (read ) timing [JESD79-3D figure 27] ............................................................... 39

Figure 20. Burst read operation [JESD79-3D figure 28] ........................................................................ 40

Figure 21. Burst write operation [JESD79-3D figure 43] ....................................................................... 41

Figure 22. Data input (write) timing [JESD79-3D figure 43] .................................................................. 41

Figure 23: tIS illustration (Figure 111 from JESD79-3E) ........................................................................ 43

Figure 24: Vref table (Table 23 from JESD79-3E) ................................................................................... 44

6 917717 Rev C

QPHY-DDR3 Software Option

INTRODUCTION TO QPHY-DDR3

QPHY-DDR3 is an automated test package performing all of the real time oscilloscope tests for Double
Data Rate in accordance with JEDEC Standard No. JESD79-3D.

The software can be run on the LeCroy SDA/DDA/WavePro 740Zi and 760Zi and all
SDA/DDA/WaveMaster 8Zi oscilloscopes.

Required equipment

• SDA/DDA/WavePro 740/760Zi or SDA/DDA/WaveMaster 8Zi oscilloscope.

• Four D620 Probes with WL-PLink ProLink probe body.

• Alternatively, D610 probes may be used if the voltage swing of the signal is within +/- 2.5Vp-p.

• TF-DSQ Probe Deskew and Calibration Fixture (not needed if using a Zi model oscilloscope).

SIGNALS MEASURED

The compliance test requires probing the following signals (# refers to the negative polarity of the
differential signal):

CK, CK# Input

Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the

crossing of the positive edge of CK and negative edge of CK#. Output (read) data is referenced to the
crossings of CK and CK# (both directions of crossing).

DQ Input/Output

Data Input/Output: Bi-directional data bus.

DQS, DQS# Input/Output

Data Str o b e: output with read data, input w ith write data. This signal is in phase with read data. The data

strobes DQS is paired with complementary signal DQS# to provide differential pair signaling to the system
during both reads and writes.

CS# Input

Chip Select: used only in m ulti-ranked systems. This is where 2 DIMM modules would be communicated

to on the same DDR3 bus. This signal is used to differentiate between the signals that were meant for
the DIMM the customer is measuring versus the signals that were meant for the other DIMM in the
system. Depending on the read and write latency of the system, the chip select signal is present on the
bus several clock cycles earlier than the actual read or write burst that is corresponds to. Be sure to set
the Overall Read Latency and Overall Write Latency variables when using the chip select signal.

917717 Rev C 7

DDR3 MEASUREMENT PREPARATION

Before starting any test or data acquisition, the oscilloscope must be warmed for at least 20 minutes.
Calibration is automatic under software control and no manual calibration is required. The procedure
should be run again if the temperature of the oscilloscope changes by more than a few degrees.

Deskewing the Probes

Deskewing the probes is a mandatory requirement for running QPHY. Given the unknown
conditions posed by individual customer setups, it is required that the customer check the signal
Deskew manually once before giving a thumbs-up on the lane skew and proceeding with the
QPHY test. Having a skew on the signal will cause tests to generate erroneous failures or mask
conditions that could be problematic.

Differential Probe Deskew Procedure using TF-DSQ on non-Zi oscilloscopes

Follow the procedure described in the TF-DSQ Probe Deskew and Calibration Fixture manual. Deskew all
four channels with their respective probe, using external trigger (AUX IN) as reference signal.

You can get more information on TF-DSQ using the oscilloscope Help menu and searching for Probe
Calibration. There is also a section on Desk ew Theory of Operatio n.

Differential Probe Deskew Procedure on Zi oscilloscopes using PCF200

Use the PCF200 Characterization Fixture provided as a standard accessory with the WaveLink series
probes. This fixture determines the effect of probe input loading on the circuit under test and the probe
response to the signal being measured, using the A T, ST, Dx10, and Dx20 modules with SI, or SP, or QC
(QC for WL-PLink only) interconnect leads.

PCF200 Fix tu re Overview

Major components of the PCF200 fixture are shown in the following figure:

• SMA male connector Fast Edge input.

• SMA female connector output to AUX IN for 50-ohm termination.

• Clip for connection of Solder-In probes.

• 2-pins header for connection of Square-Pin probes.

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QPHY-DDR3 Software Option

Figure 1. PCF200 Deskew Fixture

A SMA male to BNC male 50-ohm cable is required to perform the calibration.
System assembly is accomplished in the following steps:

1. Connect the BNC end of the 50 ohm cable to the oscilloscope AUX IN input.

2. Connect the SMA end of the 50 ohm cable to the SMA female connector on the PCF200 fixture.

On oscilloscope models with a dedicated Fast Edge SMA output,

3a. Connect the PCF200 SMA male connector to the oscilloscope Fast Edge SMA output.

Skip to the next section.
On oscilloscope models without a dedicated Fast Edge SMA output,

3b. Using an BNC to female SMA adapter, connect the PCF200 SMA male connect to the

oscilloscope AUX OUT output.

4. Under Utilities → Utilities Setup, select Fast Edge from within the Aux Output tab.

Probe Connection to PCF200

The PCF200 provides multiple probe connectors for various kinds of probes. There are 2 circuits
depending on the type of probes to calibrate:

• The upper circuit is for Solder-In (SI) and Quick-Connect (QC) probes. This circuit can also be
used for AT probes using the designated area to apply the probe tips.

• The lower circuit is for Square-Pin (SP) probes.

Probes are connected electrically in a single-ended arrangement: the positive (+) side of the probe must
be connected to the signal trace, while the negative (-) side is connected to the ground plane. The
positive polarity marking is located on the tip end of the probe in white as a plus sign.

917717 Rev C 9

Figure 2. Differential probe properly connected to the fixture (Solder-In configuration)

Probe Calibration Menu

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QPHY-DDR3 Software Option

The probe calibration menu can be accessed from the Vertical drop-down menu or from the channel
dialog:

Figure 3. A ccessing the probe calibration menu

Figure 4. Basic Probes Calibration menu

The information in the probe calibration menu is organized such that each row represents the information
for a given channel, and each column represents the calibration information or control for that channel.

Probe Calibration P ro c e dure

Depending on the compliance test that is to be performed, probes must connect with certain channels.
This is especially important when probes of different models are used simultaneously. The connection
setup for a particular test can be found in the pop-up dialog box after pressing the start button in Qualiphy.
Should probes be calibrated on the wrong channel, this procedure must be rerun.

Complete the following to properly deskew each probe.

1. Connect probes to their respective channel.

2. Select FastEdge for Cal Source.

3. Select EXT for for Cal Skew Ref.

The following is to be performed separately with each probe.

917717 Rev C 11

1. Connect the probe to the PCF200 Fixture.

2. Press the Deskew Only button in the appropriate row representing the channel to be deskewed.

Now you are ready to probe the circuit and perform your measurements. If power is interrupted during
your measurements, reboot the oscilloscope and manually recall your settings.

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QPHY-DDR3 Software Option

BASIC FUNCTIONALITY

The functionality is extracted from JEDEC Standard No. JESD79-3D, section 3.
The DDR3 SDRAM is a high-speed dynamic random-access memory internally configured as an eight-

bank DRAM. The DDR3 SDRAM uses an 8n prefetch architecture to achieve high-speed operation. The
8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write operation for the DDR3 SDRAM consists of a single 8n-bit wide, four
clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data
transfers at the I/O pins.

Read and write operation to the DDR3 SDRAM are burst oriented, start at a selected location, and
continue for a burst length of eight or a “chopped” burst of four in a programmed sequence. Operation
begins with the registration of an Active command, which is then followed by a Read or Write command.
The address bits registered coincident with the Active command are used to select the bank and row to
be activated
(BA0-BA2 select the bank; A0-A15 select the row; refer to “DDR3 SDRAM Addressing” on page 15 for
specific requirements). The address bits registered coincident with the Read or Write command are used
to select the starting column location for the burst operation, determine if the auto precharge command is
to be issued (via A10), and select BC4 or BL8 mode on the fly (via A12) if enabled in the mode register.

Prior to normal operation, the DDR3 SDRAM must be powered up and initialized in a predefined manner.

917717 Rev C 13

READ Burst Operation

During a READ or WRITE command, DDR3 supports BC4 and BL8 on the fly using address A12 during
the READ or WRITE (AUTO PRECHARGE can be enabled or disabled).

• A12 = 0, BC4 (BC4 = burst chop, tCCD = 4).

• A12 = 1, BL8.

• A12 is used only for burst length control, not as a column address.

Figure 5. READ Burst Operation RL = 5 (AL = 0, CL = 5, BL8) [JESD79-3D Figure 25]

Figure 6. READ Burst Operation RL = 9 (AL = 4, CL = 5, BL8) [JESD79-3D Figure 26]

14 917717 Rev C