Teledyne QPHY-DDR2 User Manual
QPHY-DDR2
DDR2 Serial Data
Operator’s Manual
Revision A – July, 2009
Relating to the Following Release Versions:
Software Option Rev. 5.9
DDR2 Script Rev. 1.0
Style Sheet Rev. 1.2
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Document Number: 916905 Rev A
2 QPHY-DDR2-OM-E Rev A
QPHY-DDR2 Software Option
Table of Contents
INTRODUCTION TO QPHY-DDR2 ............................................................................................ 7
Required equipment ................................................................................................................................................... 7
SIGNALS MEASURED .............................................................................................................. 7
CK, CK# Input ............................................................................................................................................................ 7
DQ Input/Output ......................................................................................................................................................... 7
DQS, DQS# Input/Output ........................................................................................................................................... 7
ADD/CTRL ................................................................................................................................................................. 7
BASIC FUNCTIONALITY .......................................................................................................... 7
Burst Read ................................................................................................................................................................. 8
Burst Write .................................................................................................................................................................. 9
USING QUALIPHY DDR2 ........................................................................................................ 10
QUALIPHY COMPLIANCE TEST PLATFORM ....................................................................... 11
Oscilloscope Option Key Installation ........................................................................................................................ 13
Typical (Recommended) Configuration .................................................................................................................... 13
Remote (Network) Configuration ............................................................................................................................. 13
Oscilloscope Selection ............................................................................................................................................. 13
Accessing the QPHY-DDR2 Software using QualiPHY ........................................................................................... 14
Customizing QualiPHY ............................................................................................................................................. 16
QPHY-DDR2 Operation............................................................................................................................................ 18
DDR2 MEASUREMENT PREPARATION ............................................................................... 19
Differential Probe Deskew Procedure using TF-DSQ .............................................................................................. 19
Differential Probe Deskew Procedure on Zi oscilloscopes using PCF200 .............................................................. 19
PCF200 Fixture Overview ................................................................................................................................. 21
Probe Connection to PCF200 ........................................................................................................................... 21
Probe Calibration Menu .................................................................................................................................... 22
Probe ............................................................................................................................................................................. 23
Full Calibration Button .................................................................................................................................................... 23
Gain & Offset.................................................................................................................................................................. 23
Skew ................................ ................................................................ .............................................................................. 24
Clear .............................................................................................................................................................................. 24
Calibration Source .......................................................................................................................................................... 24
Calibration Skew Reference ........................................................................................................................................... 24
Recall Calibration ........................................................................................................................................................... 24
Advanced Mode Checkbox ............................................................................................................................................ 24
Advanced Mode Probe Calibration Menu ......................................................................................................... 24
Gain/Offset Only ............................................................................................................................................................. 25
Deskew Only .................................................................................................................................................................. 25
The Advanced Menu ......................................................................................................................................... 25
Rise Time Skew Correction ............................................................................................................................................ 25
Differential (or Single-Ended) Probe Selection ............................................................................................................... 26
Deskew All (or Common Skew)...................................................................................................................................... 26
Common Mode Voltage Selection .................................................................................................................................. 26
Advanced Probe Calibration ............................................................................................................................. 26
D620 Probe Calibration Procedure ................................................................................................................... 26
QPHY-DDR2 TEST CONFIGURATIONS ................................................................................ 27
1) Clock tests DDR2-667 (1 Probe) ......................................................................................................................... 27
2) CKdiff-DQse-DQSdiff 667 Write Burst (3 probes) ................................................................................................ 27
3) CKdiff-DQse-DQSdiff 667 Read Burst (3 probes) ............................................................................................... 28
4) Eye Diagram (3 Probes Debug) ........................................................................................................................... 28
5) All tests that require 4 Probes .............................................................................................................................. 28
QPHY-DDR2-OM-E Rev A 3
D1) Demo of All Clock tests ..................................................................................................................................... 29
D2) Demo of Eye Diagram (Debug) ......................................................................................................................... 30
D3) Demo of All tests ............................................................................................................................................... 30
D4) Demo of All CKdiff-DQSdiff-DQse tests ............................................................................................................ 30
QPHY-DDR2 VARIABLES ...................................................................................................... 31
General Variables ..................................................................................................................................................... 31
DUT Speed Grade in MT/s ............................................................................................................................... 31
DQ Signal Name ............................................................................................................................................... 31
DQS Signal Name ............................................................................................................................................. 31
Clock Signal Name ........................................................................................................................................... 31
DUT Power Supply VDDQ ................................................................................................................................ 31
4th Probe Names ...................................................................................................................................................... 31
DQSp Signal Name ........................................................................................................................................... 31
DQSn Signal Name ........................................................................................................................................... 31
ADD/CTRL signal name.................................................................................................................................... 31
Clock Positive Signal Name .............................................................................................................................. 31
Clock Negative Signal Name ............................................................................................................................ 31
DM Signal Name ............................................................................................................................................... 31
Script Settings .......................................................................................................................................................... 31
Save Acquired Waveforms ............................................................................................................................... 31
Silent mode control ........................................................................................................................................... 32
Stop On Test to review results .......................................................................................................................... 32
Waveform Path ................................................................................................................................................. 32
Demo Settings .......................................................................................................................................................... 32
Use Stored Waveforms ..................................................................................................................................... 32
Recalled Waveform File Index (5 digits) ........................................................................................................... 32
Define format used to set trace names ............................................................................................................. 32
Use Stored Trace for Speed Grade .................................................................................................................. 32
Advanced Settings ................................................................................................................................................... 32
Clock Period per Screen Division ..................................................................................................................... 32
Number of cycles for Clock test ........................................................................................................................ 32
Max. Number Of Samples Per Clock Period .................................................................................................... 32
Configuration Specific Variables ............................................................................................................................... 33
XX Channel Gain .............................................................................................................................................. 33
XX Channel Index ............................................................................................................................................. 33
XX Channel Invert ............................................................................................................................................. 33
XX Channel Offset ............................................................................................................................................ 33
Select Signal Under Test if many ..................................................................................................................... 33
Previously measured tHP in seconds ............................................................................................................... 33
Max Overshoot Peak Amplitude ....................................................................................................................... 33
QPHY-DDR2 LIMIT SETS ....................................................................................................... 34
DDR2-400 ................................................................................................................................................................ 34
DDR2-533 ................................................................................................................................................................ 34
DDR2-667 ................................................................................................................................................................ 34
DDR2-800 ................................................................................................................................................................ 34
DDR2-1066 .............................................................................................................................................................. 34
QPHY-DDR2 TESTS ................................................................................................ ............... 34
Clock Tests ............................................................................................................................................................... 34
tCK(avg), Average Clock Period ................................................................................................................................. 34
tCK(abs), Absolute Clock Period ................................................................................................................................ 34
tCH(avg), Average High Pulse Width ......................................................................................................................... 35
tCL(avg), Average Low Pulse Width ........................................................................................................................... 35
tCH(abs), Absolute High Pulse Width ......................................................................................................................... 35
4 QPHY-DDR2-OM-E Rev A
QPHY-DDR2 Software Option
tCL(abs), Absolute Low Pulse Width .......................................................................................................................... 35
tJIT(duty), Half Period Jitter ....................................................................................................................................... 35
tJIT(per), Clock Period Jitter ...................................................................................................................................... 36
tJIT(cc), Cycle to Cycle Period Jitter .......................................................................................................................... 36
tERR(n per), Cumulative Error ................................................................................................................................... 36
Eye Diagram ............................................................................................................................................................ 37
Write Burst (Inputs) .................................................................................................................................................... 37
Read Burst (Outputs) ................................................................ ................................ ................................................. 37
Electrical Tests ......................................................................................................................................................... 37
Write Bursts (Inputs) ......................................................................................................................................... 37
Slew (Input Slewrate) ..................................................................................................................................................... 37
SlewR and SlewF ....................................................................................................................................................... 37
Logic Levels ................................................................................................................................................................... 37
VIH(ac), maximum AC input logic high ....................................................................................................................... 37
VIH(dc), minimum DC input logic high ....................................................................................................................... 38
VIL(ac), maximum AC input logic low ......................................................................................................................... 38
VIL(dc), minimum DC input logic low ......................................................................................................................... 38
VSWING(MAX), input signal maximum peak to peak swing ...................................................................................... 38
AC Over/Undershoot ...................................................................................................................................................... 38
AC Overshoot, Maximum peak amplitude .................................................................................................................. 38
AC Overshoot, Maximum overshoot area above VDDQ ............................................................................................ 38
AC Undershoot, Maximum peak amplitude ................................................................................................................ 38
AC Undershoot, Maximum overshoot area above VDDQ .......................................................................................... 39
Tests Requiring Single Ended Probing of Differential Signal ......................................................................................... 39
VID(ac), AC Differential Input Voltage ........................................................................................................................ 39
VIX(ac), AC Differential Input Cross Point Voltage..................................................................................................... 39
Read Bursts (Outputs) ...................................................................................................................................... 39
Sout (Output Slew Rate) ................................................................................................................................................ 39
SoutR and SoutF ........................................................................................................................................................ 39
tSLMR ........................................................................................................................................................................ 39
Tests Requiring Single Ended Probing of Differential Signal ......................................................................................... 40
VOX(ac) , AC Differential Output Cross Point Voltage ............................................................................................... 40
Timing Tests ............................................................................................................................................................. 40
Read Bursts ...................................................................................................................................................... 40
tDQSQ, DQS-DQ Skew for DQS and Associated DQ Signals ....................................................................................... 40
tHP, CK half pulse width ................................................................................................................................................ 41
tQHS, DQ hold skew factor ............................................................................................................................................ 41
tQH, DQ/DQS Output Hold Time From DQS.................................................................................................................. 41
tDQSCK, DQS Output Access Time from CK/CK # ....................................................................................................... 41
tAC, DQ Output Access Time from CK/CK# .................................................................................................................. 41
tHZ(DQ), DQ High Impedance Time From CK/CK# ....................................................................................................... 42
tLZ(DQ), DQ Low-Impedance Time from CK/CK# ......................................................................................................... 42
tLZ(DQS), DQS Low-Impedance Time from CK/CK# ..................................................................................................... 42
tRPRE, Read Preamble ................................................................................................................................................. 42
tRPST, Read Postamble ................................................................................................................................................ 42
Write Bursts ...................................................................................................................................................... 43
tDQSS, DQS latching rising transitions to associated CK edge ..................................................................................... 43
tDQSH, DQS Input High Pulse Width ............................................................................................................................. 43
tDQSL, DQS Input Low Pulse Width .............................................................................................................................. 43
tDSS, DQS Falling Edge to CK Setup Time ................................................................................................................... 43
tDSH, DQS Falling Edge Hold Time from CK ................................................................................................................ 43
tWPRE, Write Preamble ................................................................................................................................................. 44
tWPST, Write Postamble ............................................................................................................................................... 44
tDS(base), DQ and DM Input Setup Time ...................................................................................................................... 44
tDH(base), DQ and DM Input Hold Time ........................................................................................................................ 44
tDS1(base), DQ and DM input setup time (single-ended strobe) ................................................................................... 45
tDH1(base), DQ and DM input hold time (single-ended strobe) ..................................................................................... 45
tIS(base) - Address and Control Input Setup Time ......................................................................................................... 46
tIH(base) - Address and Control Input Hold Time .......................................................................................................... 47
QPHY-DDR2-OM-E Rev A 5
TABLE OF FIGURES
Figure 1. Data output (read) timing [JESD79-2E figure 32] .................................................................................. 8
Figure 2. Burst read followed by burst write [JESD79-2E figure 35] .................................................................. 8
Figure 3. Data input (write) timing [JESD79-2E figure 38] ................................................................................... 9
Figure 4. Burst write operation [JESD79-2E figure 39] ........................................................................................ 9
Figure 5. Burst write followed by burst read [JESD79-2E figure 41] ................................................................ 10
Figure 6. Report menu in QualiPHY General Setup ............................................................................................ 11
Figure 7. The Test Report includes a summary table with links to the detailed test results .......................... 12
Figure 8. QualiPHY main menu and compliance test Standard selection menu ............................................. 14
Figure 9. QualiPHY configuration selection menu ............................................................................................. 15
Figure 10. QualiPHY test item selection menu .................................................................................................... 16
Figure 11. Variable Setup and Limits Manager windows ................................................................................... 17
Figure 12. Start button ........................................................................................................................................... 18
Figure 13. Example of pop-up connection diagram and dialog box ................................................................. 18
Figure 14. PCF200 Deskew Fixture ...................................................................................................................... 21
Figure 15. Differential probe properly connected to the fixture (Solder-In configuration) ............................ 22
Figure 16. Accessing the probe calibration menu .............................................................................................. 22
Figure 17. Basic Probes Calibration menu .......................................................................................................... 23
Figure 18. Advanced Mode Probe Calibration menu .......................................................................................... 24
Figure 19. Probes Calibration menu Advanced tab ............................................................................................ 25
Figure 24. Data output (read) timing [JESD79-2E figure 32] .............................................................................. 35
Figure 25. AC input test signal waveform [JESD79-2E figure 73] ..................................................................... 37
Figure 26. Differential signal levels [JESD79-2E figure 74] ............................................................................... 39
Figure 27. Differential signal levels [JESD79-2E figure 74] ............................................................................... 40
Figure 28. Data output (read) timing [JESD79-2E figure 32] .............................................................................. 40
Figure 29. Burst read operation [JESD79-2E figure 33] ..................................................................................... 41
Figure 30. Burst write operation [JESD79-2E figure 39] .................................................................................... 43
Figure 31. Data input (write) timing [JESD79-2E figure 38] ............................................................................... 43
Figure 32. Data input (write) timing [JESD79-2E figure 38] ............................................................................... 45
Figure 33. Differential input waveform timing - tDS and tDH [JESD79-2E figure 98] ...................................... 45
Figure 34. Single-ended input waveform timing - tDS1 and tDH1 ..................................................................... 46
Figure 35. Differential input waveform timing - tIS and tIH [JESD79-2E figure 99] ......................................... 47
6 QPHY-DDR2-OM-E Rev A
QPHY-DDR2 Software Option
INTRODUCTION TO QPHY-DDR2
QPHY-DDR2 is an automated test package performing all of the real time oscilloscope tests for Double Data Rate
in accordance with JEDEC Standard No. 79-2E. The software can be run on the LeCroy SDA/DDA/WavePro
740Zi and 760Zi and all SDA/DDA/WaveMaster 8Zi oscilloscopes.
Required equipment
SDA/DDA/WavePro 740/760Zi or SDA/DDA/WaveMaster 8Zi oscilloscope
Four D620 Probes with WL-Plink Prolink probe body
Alternatively, D610 probes may be used if the voltage swing of the signal is within +/- 2.5Vp-p.
TF-DSQ Probe Deskew and Calibration Fixture (not needed if using a Zi oscilloscope)
SIGNALS MEASURED
The compliance test requires probing the following signals (# is the negative polarity of the differential signal):
CK, CK# Input
Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing
of the positive edge of CK and negative edge of CK#. Output (read) data is referenced to the crossings of CK and
CK# (both directions of crossing).
DQ Input/Output
Data Input/Output: Bi-directional data bus.
DQS, DQS# Input/Output
Data Strobe: output with read data, input with write data. This signal is in phase with read data and 90 degrees
out of phase with write data. The data strobes DQS may be used in single ended mode or paired with optional
complementary signal DQS# to provide differential pair signaling to the system during both reads and writes.
ADD/CTRL
In addition to the Clock, Data and Strobe signals, address and control signals can also be measured. Bank
Address (BA0 – BA2), Chip Select (CS), Command Inputs (RAS, CAS and WE), Clock Enable (CKE) and On Die
Termination (ODT) can all be specified as the signal under test.
BASIC FUNCTIONALITY
The functionality is extracted from JEDEC Standard No. 79-2E section 3.
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and
continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an
Active command, which is then followed by a Read or Write command.
Prior to normal operation, the DDR2 SDRAM must be initialized.
QPHY-DDR2-OM-E Rev A 7
Burst Read
The Burst Read command is initiated by having CS# and CAS# LOW while holding RAS# and WE# HIGH at the
rising edge of the clock. The address inputs determine the starting column address for the burst. The data strobe
output (DQS) is driven LOW one clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the
burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ
pin in phase with the DQS signal in a source synchronous manner.
Figure 1. Data output (read) timing [JESD79-2E figure 32]
Figure 2. Burst read followed by burst write [JESD79-2E figure 35]
The minimum time from the burst read command to the burst write command is defined by a read-to-write-turnaround-time, which is 4 clocks in case of BL = 4 operation, 6 clocks in case of BL = 8 operation.
8 QPHY-DDR2-OM-E Rev A
QPHY-DDR2 Software Option
Burst Write
The Burst Write command is initiated by having CS#, CAS# and WE# LOW while holding RAS# HIGH at the rising
edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a
read latency (RL) minus one and is equal to (AL + CL -1); and is the number of clocks of delay that are required
from the time the write command is registered to the clock edge associated to the first DQS strobe. A data strobe
signal (DQS) should be driven LOW (preamble) nominally half clock prior to the [first rising edge]. The first data bit
of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The
tDQSS specification must be satisfied for each positive DQS transition to its associated clock edge during write
cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is
completed, which is 4 or 8 bit burst.
Figure 3. Data input (write) timing [JESD79-2E figure 38]
Figure 4. Burst write operation [JESD79-2E figure 39]
QPHY-DDR2-OM-E Rev A 9
Figure 5. Burst write followed by burst read [JESD79-2E figure 41]
USING QUALIPHY DDR2
QualiPHY DDR2 guides the user, step-by-step, through each of the source tests described in JEDEC Standard
No. 79-2E. To do this, the user must setup a test session.
Users choose test configurations to run. There are several pre-loaded test configurations including:
1) Clock tests DDR2-667 (1 Probe)
2) CKdiff-DQse-DQSdiff 667 Write Burst (3 probes)
3) CKdiff-DQse-DQSdiff 667 Read Burst (3 probes)
4) Eye Diagram (3 Probes Debug)
5) All tests that require 4 Probes
D1) Demo of All Clock tests
D2) Demo of Eye Diagram (Debug)
D3) Demo of All tests
D4) Demo of All Ck-diff-DQSdiff-DQse tests
The pre-loaded configurations provide quick and easy ways to begin compliance testing. You can create your own
custom configurations (see the Customizing QualiPHY topic for details).
The variables are pre-loaded with the standard settings for compliance testing; however, the user may choose to
create their own configuration with the variables set as desired.
10 QPHY-DDR2-OM-E Rev A
QPHY-DDR2 Software Option
QUALIPHY COMPLIANCE TEST PLATFORM
QualiPHY is LeCroy’s compliance test framework which leads the user through the compliance tests. QualiPHY
displays connection diagrams to ensure tests run properly, automates the oscilloscope setup, and generates
complete, detailed reports.
The QualiPHY software application automates the test and report generation.
Figure 6. Report menu in QualiPHY General Setup
QPHY-DDR2-OM-E Rev A 11
See the QualiPHY Operator’s Manual for more information on how to use the QualiPHY framework.
Figure 7. The Test Report includes a summary table with links to the detailed test results
12 QPHY-DDR2-OM-E Rev A
QPHY-DDR2 Software Option
Oscilloscope Option Key Installation
An option key must be purchased to enable the QPHY-DDR2 option. Call LeCroy Customer Support to place an
order and receive the code.
Enter the key and enable the purchased option as follows:
1. From the oscilloscope menu select Utilities Utilities Setup
2. Select the Options tab and click the Add Key button.
3. Enter the Key Code using the on-screen keyboard.
4. Restart the oscilloscope to activate the option after installation.
Typical (Recommended) Configuration
QualiPHY software can be executed from the oscilloscope or a host computer. The first step is to install QualiPHY.
Please refer to the QualiPHY Operator’s Manual for installation instructions.
LeCroy recommends running QualiPHY on an oscilloscope equipped with Dual Monitor Display capability (Option
DMD-1 for oscilloscopes where this is not standard). This allows the waveform and measurements to be shown
on the oscilloscope LCD display while the QualiPHY application and test results are displayed on a second
monitor.
By default, the oscilloscope appears as a local host when QualiPHY is executed in the oscilloscope. Follow the
steps under Oscilloscope Selection (as follows) and check that the IP address is 127.0.0.1.
Remote (Network) Configuration
It is also possible to install and run QualiPHY on a host computer, controlling the oscilloscope with a Network/LAN
Connection.
The oscilloscope must already be configured, and an IP address (fixed or network-assigned) must already be
established.
Oscilloscope Selection
Set up the oscilloscope using QualiPHY over a LAN (Local Area Network) by doing the following:
1. Make sure the host computer is connected to the same LAN as the oscilloscope. If unsure, contact your
system administrator.
2. From the oscilloscope menu, select Utilities Utilities Setup
3. Select the Remote tab.
4. Verify the oscilloscope has an IP address and the control is set to TCP/IP.
5. Run QualiPHY in the host computer and click the General Setup button.
6. Select the Connection tab.
7. Enter the IP address from step 4 (previous).
8. Click the Close button.
QualiPHY is now ready to control the oscilloscope.
QPHY-DDR2-OM-E Rev A 13
QualiPHY tests the oscilloscope connection after clicking the Start button. The system prompts you if there is a
connection problem. QualiPHY’s Scope Selector function can also be used to verify the connection. Please refer
to the QualiPHY Operator’s Manual for explanations on how to use Scope Selector and other QualiPHY
functions.
Accessing the QPHY-DDR2 Software using QualiPHY
This topic provides a basic overview of QualiPHY’s capabilities. Please refer to the QualiPHY Operator’s Manual
for detailed information.
Access the QPHY-DDR2 software using the following steps:
1. Wait for the oscilloscope to start and have its main application running.
2. Launch QualiPHY from the Analysis menu if installed on the oscilloscope or from the desktop icon if installed
on a host computer.
3. From the QualiPHY main window (as follows), select Standard, then DDR2 from the pop-up menu (if not
already selected). If you check the Pause on Failure box (circled) QualiPHY prompts to retry the test in the
case of a failure.
Figure 8. QualiPHY main menu and compliance test Standard selection menu
14 QPHY-DDR2-OM-E Rev A
4. Click the Configuration button in the QualiPHY main menu:
5. Select a configuration from the pop-up menu:
QPHY-DDR2 Software Option
Figure 9. QualiPHY configuration selection menu
6. Click Start.
7. Follow the pop-up window prompts.
QPHY-DDR2-OM-E Rev A 15
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