PERSONAL COMPUTER DATA ACQUISITION A/D CONVERTER
1
TC835
FEATURES
■ Upgrade of Pin-Compatible TC7135, ICL7135,
MAX7135 and SI7135
■ Guaranteed 200 kHz Operation
■ Single 5V Operation With TC7660
■ Multiplexed BCD Data Output
■ UART and Microprocessor Interface
■ Control Outputs for Auto-Ranging
■ Input Sensitivity ............................................ 100 µV
■ No Sample and Hold Required
APPLICATIONS
■ Personal Computer Data Acquisition
■ Scales, Panel Meters, Process Controls
■ HP-IL Bus Instrumentation
ORDERING INFORMATION
Temperature
Part No. Package Range
TC835CBU 64-Pin PQFP 0°C to +70°C
TC835CKW 44-Pin PQFP 0°C to +70°C
TC835CPI 28-Pin Plastic DIP 0°C to +70°C
NOTE: Tape and reel available for 44-pin PQFP packages.
TYPICAL APPLICATION
GENERAL DESCRIPTION
The TC835 is a low-power, 4-1/2 digit (0.005% resolution), BCD analog-to-digital converter (ADC) that has been
characterized for 200 kHz clock rate operation. The five
conversions per second rate is nearly twice as fast as the
ICL7135 or TC7135. The TC835 (like the TC7135) does
not use the external diode-resistor roll-over error compensation circuits required by the ICL7135.
The multiplexed BCD data output is perfect for interfacing to personal computers. The low-cost, greater than 14bit high-resolution, and 100 µV sensitivity makes the TC835
exceptionally cost-effective.
Microprocessor-based data acquisition systems are
supported by the BUSY and STROBE outputs, along with
the RUN/HOLD input of the TC835. The overrange, underrange, busy, and run/hold control functions and multiplexed
BCD data outputs make the TC835 the ideal converter for
µP-based scales and measurement systems and intelligent
panel meters.*
The TC835 interfaces with full-function LCD and LED
display decoder/drivers. The UNDERRANGE and
OVERRANGE outputs may be used to implement an autoranging scheme or special display functions.
*See Application Notes 16 and 17 for microprocessor interface techniques.
2
3
4
5
ADDRESS BUS
CONTROL
DATA BUS
PA0
PA1
PA2
PB0 PB3PB2PB1
6522
-VIA-
PA3
PA4
PA5
PA6
PA7
CA1
CA2
GAIN SELECTION
PB5
PB4
CHANNEL SELECTION
TELCOM SEMICONDUCTOR, INC.
+
5V
+
REF CAP
V
1B
1Y
2B
2Y
3Y
3B
SEL
1A
157
2A
3A
POL
OR
UR
D5
B8
B4
B2
B1
D1
D2
D3
D4
STB
R/H
f
IN
TC835
COMMON
f
IN
BUF
+
INPUT
–
INPUT
ANALOG
DGND
–
AZ
INT
V
R
5V
GAIN: 10, 20, 50, 100
REF
VOLTAGE
10
14
8
LH0084
16
–+
15V 15V
11
DG529
+
3
D
A
9
D
–
B
WR
15
A1A
EN
0
DIFFERENTIAL
MULTIPLEXER
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
6
7
8
TC835-8 11/5/96
3-65
TC835
PERSONAL COMPUTER
DA TA ACQUISITION A/D CONVERTER
ABSOLUTE MAXIMUM RATINGS* (Note 1)
Positive Supply Voltage ............................................. +6V
Negative Supply Voltage............................................ - 9V
Analog Input Voltage (Pin 9 or 10) ........ V+ to V– (Note 2)
Reference Input Voltage (Pin 2).......................... V+ to V
Clock Input Voltage ............................................. 0V to V
Operating Temperature Range ....................0°C to +70°C
Storage Temperature Range ................– 65°C to +150°C
Lead Temperature (Soldering, 10 sec) .................+300°C
ELECTRICAL CHARACTERISTICS:
TA = +25°C, f
Package Power Dissipation (TA ≤ 70°C)
28-Pin Plastic DIP.............................................1.14W
44-Pin PQFP ....................................................1.00W
64-Pin PFP .......................................................1.14W
*Static-sensitive device. Unused devices must be stored in conductive
–
material. Protect devices from static discharge and static fields. Stresses
+
above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
= 200 kHz, V+ = +5V, V– = – 5V, unless otherwise specified.
CLOCK
Symbol Parameter Test Conditions Min Typ Max Unit
Analog
Display Reading With Notes 3 and 4 –0.0000 ±0.0000 +0.0000 Display
Zero Volt Input Reading
TC
Z
TC
FS
NL Nonlinearity Error Note 7 — 0.5 1 Count
DNL Differential Linearity Error Note 7 — 0.01 — LSB
±FSE ± Full-Scale Symmetry –VIN = +V
I
IN
e
N
Digital
I
IL
I
IH
V
OL
V
OH
f
CLK
Power Supply
+
V
–
V
+
I
–
I
PD Power Dissipation f
NOTES: 1. Functional operation is not implied.
Zero Reading VIN = 0V — 0.5 2 µV/°C
Temperature Coefficient Note 5
Full-Scale VIN = 2V — — 5 ppm/°C
Temperature Coefficient Notes 5 and 6
Display Reading in VIN = V
REF
+0.9996 +0.9998 +1.0000 Display
Ratiometric Operation Note 3 Reading
IN
— 0.5 1 Count
Error (Roll-Over Error) Note 8
Input Leakage Current Note 4 — 1 10 pA
Noise
Peak-to-Peak Value Not Exceeded 95% of Time
—15—µV
P-P
Input Low Current VIN = 0V — 10 100 µA
Input High Current VIN = +5V — 0.08 10 µA
Output Low Voltage IOL = 1.6 mA — 0.2 0.4 V
Output High Voltage
B
, B2, B4, B8, D1–D
1
Busy, Polarity, Overrange, I
IOH = 1 mA 2.4 4.4 5 V
5
= 10 µA 4.9 4.99 5 V
OH
Underrange, Strobe
Clock Frequency Note 10 0 200 1200 kHz
Positive Supply Voltage 4 5 6 V
Negative Supply Voltage – 3 – 5 – 8 V
Positive Supply Current f
Negative Supply Current f
2. Limit input current to under 100 µA if input voltages exceed supply
voltage.
3. Full-scale voltage = 2V.
4. VIN = 0V.
5. 0°C ≤ TA ≤ +70°C.
6. External reference temperature coefficient less than 0.01 ppm/°C.
= 0 Hz — 1 3 mA
CLK
= 0 Hz — 0.7 3 mA
CLK
= 0 Hz — 8.5 30 mW
CLK
7. – 2V ≤ VIN ≤ +2V. Error of reading from best fit straight
line.
8. |VIN| = 1.9959.
9. Test circuit shown in Figure 1.
10. Specification related to clock frequency range over which
the TC835 correctly performs its various functions.
Increased errors result at higher operating frequencies.
3-66
TELCOM SEMICONDUCTOR, INC.
PERSONAL COMPUTER
DA TA ACQUISITION A/D CONVERTER
PIN CONFIGURATIONS
1
TC835
2
V
REF IN
ANALOG
COM
INT OUT
AZ IN
BUFF OUT
–
C
REF
+
C
REF
–
INPUT
+
INPUT
V
(MSD) D5
(LSB) B1
B2
–
1
2
3
4
5
6
7
8
9
10
+
11
12
13
14
TC835CPI
NC
NC
NC
NC
NC
NC
OVERRANGE
UNDERRANGE
SUB
REF IN
ANALOG COM
NC
NC
NC
NC
NOTES:
UNDERRANGE
28
OVERRANGE
27
26
STROBE
RUN/HOLD
25
24
DIGTAL GND
23
POLARITY
CLOCK IN
22
21
BUSY
20
D1 (LSD)
19
D2
18
D3
17
D4
16
B8 (MSD)
B4
15
NC
NC
STROBE
RUN/HOLD
NC
NC
63
64
1
2
3
4
5
6
7
8
9
10
V–
11
12
13
14
15
16
17 18
NC
1. NC = No internal connection.
2. Pins 9, 25, 40 and 56 are connected to the die substrate.
The potential at these pins is approximately V+. No
external connections should be made.
61 60 59 58
62
19 20 21 22
NC
AZ IN
INT OUT
DGND
TC835CBU
NOTES 1 & 2
23
NC
OUT
BUFF
BUF CAP–
57 56
24 25 26
NC
INT OUT
AZ IN
BUFF OUT
REF CAP–
REF CAP+
–INPUT
+INPUT
V+
NC
NC
POL
SUB
CLK IN
55 54
NC
SUB
BUF CAP+
1
2
3
4
5
6
7
8
9
10
11
BUSY
27 28
NC
NCNCNC
44 43 42 41 39 3840
ANALOG COM
REF INV–URORSTROBENCNC
TC835CKW
12 13 14 15 17 18
NC
NC
NC
D1
D2
53
51
52
29 30
NC
–INPUT
+INPUT
(MSD) D5
NC
50 49
31
32
NC
16
B2
(LSB) B1
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V+
NC
NC
NC
D3
D4
B3
B4
B2
SUB
B1
D5
NC
NC
NC
NC
NC
B4
(MSB) B8
37 36 35 34
19 20 21 22
D4
D3
NC
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
RUN/HOLD
DGND
POLARITY
CLK IN
BUSY
D1 (LSD)
D2
NC
NC
3
4
5
6
7
8
TELCOM SEMICONDUCTOR, INC.
3-67
TC835
PERSONAL COMPUTER
DA TA ACQUISITION A/D CONVERTER
SET V
REF
V
IN
REF
100 kΩ
ANALOG GND
0.47
µF
SIGNAL
INPUT
+
5V
LOGIC
INPUT
= 1V
100 kΩ
100
kΩ
0.1 µF
–5V
1
–
V
2
REF IN
3
ANALOG
COMMON
4
1 µF
INT OUT
5
AZ IN
6
BUFF OUT
7
C
8
C
9
–
10
+
11
V
12
D5 (MSD)
13
B1 (LSB)
14
B2
–
REF
+
REF
INPUT
INPUT
+
1 µF
Figure 1. Test Circuit
+
V
UNDERRANGE
OVERRANGE
STROBE
RUN/HOLD
DIGTAL GND
POLARITY
CLOCK IN
BUSY
(LSD) D1
TC835
(MSB) B8
28
27
26
25
24
23
22
21
20
19
D2
18
D3
17
D4
16
15
B4
BUFFER
CLOCK
INPUT
120 kHz
+
IN
REF
IN
ANALOG
COM
–
IN
+
IN
REF
IN
ANALOG
COM
–
IN
SW
SW
SW
SW
SW
SW
SW
SW
ANALOG
SW
C
REF
SW
INPUT BUFFER
+
RI
–
RI
SW
1
+
–
SWIZSW
SW
Z
R
Z
INT
C
INT
C
SZ
–
+
INTEGRATOR
SWITCH OPEN
SWITCH CLOSED
COMPARATOR
+
–
TO
DIGITAL
SECTION
I
–
SW
RI
R
Z
+
SW
RI
I
Figure 3B. System Zero Phase
ANALOG
SW
C
REF
SW
INPUT BUFFER
+
RI
–
RI
SW
1
+
–
SWIZSW
SW
Z
R
Z
INT
C
INT
C
SZ
–
+
INTEGRATOR
SWITCH OPEN
SWITCH CLOSED
COMPARATOR
+
–
TO
DIGITAL
SECTION
I
–
SW
RI
R
Z
+
SW
RI
I
+
REF
ANALOG
COM
–
3-68
Figure 2. Digital Logic Input Figure 3C. Input Signal Integration Phase
REF
SW
+
RI
–
RI
ANALOG
INPUT BUFFER
+
–
SWIZSW
SW
1
SW
C
R
Z
Z
INT
INT
C
SZ
–
+
INTEGRATOR
SWITCH OPEN
SWITCH CLOSED
COMPARATOR
+
–
TO
DIGITAL
SECTION
ANALOG
SW
C
REF
SW
INPUT BUFFER
+
RI
–
RI
SW
1
+
–
SWIZSW
SW
Z
R
INT
Z
C
INT
C
SZ
–
+
INTEGRATOR
COMPARATOR
+
–
TO
DIGITAL
SECTION
SW
I
IN
–
SW
RI
SW
R
IN
SW
Z
+
SW
RI
SW
I
IN
Figure 3A. Analog Circuit Function Diagram
+
IN
REF
IN
ANALOG
COM
–
IN
SW
I
–
SW
SW
RI
C
R
+
SW
RI
I
SW
SW
Z
SW
Figure 3D. Reference Voltage Integration Cycle
TELCOM SEMICONDUCTOR, INC.
PERSONAL COMPUTER
DA TA ACQUISITION A/D CONVERTER
1
TC835
ANALOG
SW
C
REF
SW
INPUT BUFFER
+
RI
–
RI
SW
1
+
–
SWIZSW
SW
Z
R
INT
Z
C
INT
C
SZ
–
+
INTEGRATOR
SWITCH OPEN
SWITCH CLOSED
COMPARATOR
+
–
TO
DIGITAL
SECTION
+
IN
REF
IN
ANALOG
COM
–
IN
SW
SW
I
–
SW
RI
SW
R
Z
+
SW
RI
SW
I
Figure 3E. Integrator Output Zero Phase
GENERAL THEORY OF OPERATION
(All Pin Designations Refer to 28-Pin DIP)
Dual-Slope Conversion Principles
The TC835 is a dual-slope, integrating analog-to-digital
converter. An understanding of the dual-slope conversion
technique will aid in following the detailed TC835 operational theory.
The conventional dual-slope converter measurement
cycle has two distinct phases:
(1) Input signal integration
(2) Reference voltage integration (deintegration)
The input signal being converted is integrated for a fixed
time period. Time is measured by counting clock pulses. An
opposite polarity constant reference voltage is then integrated until the integrator output voltage returns to zero. The
reference integration time is directly proportional to the input
signal.
In a simple dual-slope converter, a complete conversion
requires the integrator output to "ramp-up" and "rampdown."
A simple mathematical equation relates the input signal,
reference voltage, and integration time:
t
1 VR t
RC RC
where:
VR = Reference voltage
tSI = Signal integration time (fixed)
tRI = Reference voltage integration time (variable).
For a constant VIN:
VIN = V
SI
VIN(t) dt =
∫
0
t
RI
.
R
]
[
t
SI
RI ,
The dual-slope converter accuracy is unrelated to the
integrating resistor and capacitor values, as long as they are
stable during a measurement cycle. An inherent benefit is
noise immunity. Noise spikes are integrated, or averaged, to
zero during the integration periods. Integrating ADCs are
immune to the large conversion errors that plague successive approximation converters in high-noise environments.
(See Figure 4.)
TC835 Operational Theory
The TC835 incorporates a system zero phase and
integrator output voltage zero phase to the normal twophase dual-slope measurement cycle. Reduced system
errors, fewer calibration steps, and a shorter overrange
recovery time result.
The TC835 measurement cycle contains four phases:
(1) System zero
(2) Analog input signal integration
(3) Reference voltage integration
(4) Integrator output zero
Internal analog gate status for each phase is shown in
Table 1.
ANALOG
INPUT
SIGNAL
REF
VOLTAGE
OUTPUT
INTEGRATOR
FIXED
SIGNAL
INTEGRATE
TIME
INTEGRATOR
–
+
SWITCH
DRIVER
PHASE
CONTROL
POLARITY CONTROL
DISPLAY
V
IN
V
IN
VARIABLE
REFERENCE
INTEGRATE
TIME
Figure 4. Basic Dual-Slope Converter
COMPARATOR
–
+
'
V
FULL SCALE
1/2 V
'
CONTROL
LOGIC
COUNTER
FULL SCALE
CLOCK
2
3
4
5
6
7
8
TELCOM SEMICONDUCTOR, INC.
3-69
TC835
Table 1. Internal Analog Gate Status
PERSONAL COMPUTER
DA TA ACQUISITION A/D CONVERTER
Conversion Reference
Cycle Phase SW
System Zero Closed Closed Closed 3B
Input Signal Closed 3C
Integration
Reference Voltage Closed* Closed 3D
Integration
Integrator Closed Closed 3E
Output Zero
*NOTE: Assumes a positive polarity input signal. SWRI would be closed for a negative input signal.
SW
I
System Zero (Figure 3B)
During this phase, errors due to buffer, integrator, and
comparator offset voltages are compensated for by charging CAZ (auto-zero capacitor) with a compensating error
voltage. With a zero input voltage the integrator output will
remain at zero.
The external input signal is disconnected from the
internal circuitry by opening the two SWI switches. The
internal input points connect to ANALOG COMMON. The
reference capacitor charges to the reference voltage potential through SWR. A feedback loop, closed around the
integrator and comparator, charges the CAZ capacitor with a
voltage to compensate for buffer amplifier, integrator, and
comparator offset voltages.
Analog Input Signal Integration (Figure 3C)
The TC835 integrates the differential voltage between
the +INPUT and –INPUT pins. The differential voltage must
be within the device common-mode range; - 1V from either
supply rail, typically.
The input signal polarity is determined at the end of this
phase.
Internal Analog Gate Status
+
RI
–
SW
–
RI
SW
Z
Analog Section Functional Description
(In Reference to the 28-Pin Plastic Package)
Differential Inputs
(+INPUT, Pin 10 and –INPUT, Pin 9)
input amplifier common-mode range. The input amplifier
common-mode range extends from 0.5V below the positive
supply to 1V above the negative supply. Within this common-mode voltage range, an 86 dB common-mode rejection ratio is typical.
voltage. The integrator output must not be allowed to saturate. A worst-case condition exists, for example, when a
large positive common-mode voltage with a near full-scale
negative differential input voltage is applied. The negative
input signal drives the integrator positive when most of its
swing has been used up by the positive common-mode
voltage. For these critical applications the integrator swing
can be reduced to less than the recommended 4V full-scale
swing, with some loss of accuracy. The integrator output can
swing within 0.3V of either supply without loss of linearity.
SW
R
SW
1
SW
IZ
Schematic
The TC835 operates with differential voltages within the
The integrator output also follows the common-mode
Reference Voltage Integration (Figure 3D)
The previously-charged reference capacitor is connected with the proper polarity to ramp the integrator output
back to zero. The digital reading displayed is:
Reading = 10,000 .
Differential Input
V
REF
][
Integrator Output Zero (Figure 3E)
This phase guarantees the integrator output is at 0V
when the system zero phase is entered and that the true
system offset voltages are compensated for. This phase
normally lasts 100 to 200 clock cycles. If an overrange
condition exists, the phase is extended to 6200 clock cycles.
3-70
ANALOG COMMON Input (Pin 3)
ANALOG COMMON is used as the –INPUT return
during auto-zero and deintegrate. If –INPUT is different from
ANALOG COMMON, a common-mode voltage exists in the
system. This signal is rejected by the excellent CMRR of the
converter. In most applications, –INPUT will be set at a fixed,
known voltage (power supply common, for instance). In this
application, ANALOG COMMON should be tied to the same
point, thus removing the common-mode voltage from the
converter. The reference voltage is referenced to ANALOG
COMMON.
REFERENCE Voltage Input (REF IN, Pin 2)
The REF IN input must be a positive voltage with respect
to ANALOG COMMON. Two reference voltage circuits are
shown in Figure 5.
TELCOM SEMICONDUCTOR, INC.
,
PERSONAL COMPUTER
DA TA ACQUISITION A/D CONVERTER
1
TC835
+
V
+
V
REF
IN
6.8V
ZENER
TC835
I
–
V
6.8 kΩΩ
TC04
1.25V REF
ANALOG
GROUND
Z
+
V
ANALOG
COMMON
+
V
REF
IN
TC835
ANALOG
COMMON
Figure 5. Using an External Reference
20
k
Digital Section Functional Description
The major digital subsystems within the TC835 are
illustrated in Figure 6, with timing relationships shown in
Figure 7. The multiplexed BCD output data can be displayed
on LCD or LED display with the TC7211A (LCD)
4-digit display driver.
The digital section is best described through a discussion of the control signals and data outputs.
RUN/HOLD Input (Pin 25)
When left open, this pin assumes a logic "1" level. With
a R/H = 1, the TC835 performs conversions continuously,
with a new measurement cycle beginning every 40,002
clock pulses.
When R/H changes to a logic "0," the measurement
cycle in progress will be completed, and data held and
displayed as long as the logic "0" condition exists.
A positive pulse (>300nsec) at R/H initiates a new
measurement cycle. The measurement cycle in progress
when R/H initially assumed the logic "0" state must be
completed before the positive pulse can be recognized as a
single conversion run command.
POLARITY
FROM
ANALOG
SECTION
POLARITY
FF
ZERO
CROSS
DETECT
24 22 25 27 28 26 21
DIGITAL
CLOCKINRUN/
GND
Figure 6. Digital Section Functional Diagram
INTEGRATOR
OUTPUT
BUSY
OVERRANGE
WHEN
APPLICABLE
UNDERRANGE
WHEN
APPLICABLE
DIGIT SCAN
STROBE
DIGIT SCAN
FOR
OVERRANGE
D5 D4 D3 D2 D1
MSB DIGIT DRIVE SIGNAL LSB
MULTIPLEXER
LATCH LATCH LATCH LATCH LATCH
COUNTERS
CONTROL LOGIC
OVER–
HOLD
SYSTEM
ZERO
10,001
COUNTS
FULL MEASUREMENT CYCLE
EXPANDED SCALE
100
COUNTS
*
D5
D4
Figure 7. Timing Diagrams for Outputs
RANGE
SIGNAL
INTE
10,000
COUNTS
(FIXED)
40,002 COUNTS
BELOW
AUTO ZERO
D3
D2
D1
RANGE
REFERENCE
INTEGRATE
20,001
COUNTS (MAX)
*
SIGNAL
INTEGRATE
STROBE BUSYUNDER–
D5
D4
D3
D2
D1
FIRST D5 OF SYSTEM ZERO
AND REFERENCE INTEGRATE
ONE COUNT LONGER.
OUTPUT
REFERENCE
INTEGRATE
*
DATA
13 B1
14 B2
15 B4
16 B8
2
3
4
5
6
7
8
TELCOM SEMICONDUCTOR, INC.
3-71
TC835
PERSONAL COMPUTER
DA TA ACQUISITION A/D CONVERTER
The new measurement cycle begins with a 10,001count auto-zero phase. At the end of this phase the busy
signal goes high.
STROBE Output (Pin 26)
During the measurement cycle, the STROBE control
line is pulsed low five times. The five low pulses occur in the
center of the digit drive signals (D1, D2, D3, D5, Figure 8).
D5 (MSD) goes high for 201 counts when the measurement cycles end. In the center of the D5 pulse, 101 clock
pulses after the end of the measurement cycle, the first
STROBE occurs for one-half clock pulse. After the D5 digit
strobe, D4 goes high for 200 clock pulses. The STROBE
goes low 100 clock pulses after D4 goes high. This continues
through the D1 digit drive pulse.
The digit drive signals will continue to permit display
scanning. STROBE pulses are not repeated until a new
measurement is completed. The digit drive signals will not
continue if the previous signal resulted in an overrange
condition.
The active low STROBE pulses aid BCD data transfer to
UARTs, processors and external latches. (See Application
Note 16.)
BUSY Output (Pin 21)
At the beginning of the signal-integration phase, BUSY
goes high and remains high until the first clock pulse after the
integrator zero crossing. BUSY returns to the logic "0" state
after the measurement cycle ends in an overrange condition. The internal display latches are loaded during the first
clock pulse after BUSY, and are latched at the clock pulse
end. The BUSY signal does not go high at the beginning of
the measurement cycle, which starts with the auto-zero
cycle.
OVERRANGE Output (Pin 27)
If the input signal causes the reference voltage integration time to exceed 20,000 clock pulses, the OVERRANGE
output is set to a logic "1." The overrange output register is
set when BUSY goes low, and is reset at the beginning of the
next reference-integration phase.
TC835
OUTPUTS
BUSY
B1–B8
STROBE
D5
D4
D3
D2
D1
Figure 8. Strobe Signal Pulses Low Five Times per Conversion
END OF CONVERSION
*
D3
DATAD2DATA
200
COUNTS
COUNTS
200
COUNTS
COUNTS
D4
DATA
200
D5 (MSD)
DATA
201
COUNTS
*
DELAY BETWEEN BUSY GOING LOW AND FIRST STROBE
PULSE IS DEPENDENT ON ANALOG INPUT.
200
D1 (LSD)
DATAD5DATA
NOTE ABSENCE
OF STROBE
200
COUNTS
200
COUNTS
The polarity bit is valid even for a zero reading. Signals
less than the converter's LSB will have the signal polarity
determined correctly. This is useful in null applications.
DIGIT Drive Outputs (Pins 12, 17, 18, 19 and 20)
Digit drive signals are positive-going signals. The scan
sequence is D5 to D1. All positive pulses are 200 clock pulses
wide, except D5, which is 201 clock pulses wide.
All five digits are scanned continuously, unless an
overrange condition occurs. In an overrange condition, all
digit drives are held low from the final STROBE pulse until
the beginning of the next reference-integrate phase. The
scanning sequence is then repeated. This provides a blinking visual display indication.
UNDERRANGE Output (Pin 28)
If the output count is 9% of full scale or less (≤1800
counts), the underrange register bit is set at the end of
BUSY. The bit is set low at the next signal-integration phase.
POLARITY Output (Pin 23)
A positive input is registered by a logic "1" polarity signal.
The polarity bit is valid at the beginning of reference integrate and remains valid until determined during the next
conversion.
3-72
BCD Data Outputs (Pins 13, 14, 15 and 16)
The binary coded decimal (BCD) bits B8, B4, B2, B1, are
positive-true logic signals. The data bits become active
simultaneously with the digit drive signals. In an overrange
condition, all data bits are at a logic "0" state.
TELCOM SEMICONDUCTOR, INC.
PERSONAL COMPUTER
DA TA ACQUISITION A/D CONVERTER
1
TC835
APPLICATIONS INFORMATION
Component Value Selection
The integrating resistor is determined by the full-scale
input voltage and the output current of the buffer used to
charge the integrator capacitor. Both the buffer amplifier and
the integrator have a class A output stage, with 100 µA of
quiescent current. A 20 µA drive current gives negligible
linearity errors. Values of 5 µA to 40 µA give good results.
The exact value of an integrating resistor for a 20 µA current
is easily calculated.
R
Integrating Capacitor
The product of integrating resistor and capacitor should
be selected to give the maximum voltage swing that ensures
the tolerance buildup will not saturate the integrator swing
(approximately 0.3V from either supply). For ±5V supplies
and ANALOG COMMON tied to supply ground, a ±3.5V to
±4V full-scale integrator swing is adequate. A 0.10 µF to 0.47
µF is recommended. In general, the value of C
C
A very important characteristic of the integrating capacitor is that it has low dielectric absorption to prevent rollover
or ratiometric errors. A good test for dielectric absorption is
to use the capacitor with the input tied to the reference. This
ratiometric condition should read half-scale 0.9999, any
deviation is probably due to dielectric absorption. Polypropylene capacitors give undetectable errors at reasonable
cost. Polystyrene and polycarbonate capacitors may also be
used in less critical applications.
Auto-Zero and Reference Capacitors
The size of the auto-zero capacitor has some influence
on the noise of the system. A large capacitor reduces the
noise. The reference capacitor should be large enough such
that stray capacitance to ground from its nodes is negligible.
The dielectric absorption of the reference capacitor and
auto-zero capacitor are only important at power-on, or when
the circuit is recovering from an overload. Smaller or cheaper
capacitors can be used if accurate readings are not required
for the first few seconds of recovery.
full-scale voltage
=
INT
INT
=
=
20 µA
[10,000 × clock period] × I
Integrator output voltage swing
(10,000) (clock period) (20 µA)
Integrator output voltage swing
INT
is given by:
INT
The stability of the reference voltage is a major factor in
the overall absolute accuracy of the converter. For this
reason, it is recommended that a high-quality reference be
used where high-accuracy absolute measurements are
being made. Suitable references are:
Part Type Manufacturer
TC04A TelCom Semiconductor
TC9491 TelCom Semiconductor
Conversion Timing
Line Frequency Rejection
A signal integration period at a multiple of the 60 Hz line
frequency will maximize 60 Hz "line noise" rejection.
A 200 kHz clock frequency will reject 60 Hz and 400 Hz
noise. This corresponds to five readings per second.
Conversion Rate vs Clock Frequency
Oscillator Frequency Conversion Rate
(kHz) (Conv/Sec)
100 2.5
120 3
200 5
300 7.5
400 10
800 20
1200 30
Oscillator Frequency
(kHz) 60 Hz 50 Hz 400 Hz
50.000 • • •
53.333 — — •
66.667 • — •
80.000 — — •
83.333 — • •
100.000 • • •
125.000 — • •
133.333 — — •
166.667 — — •
200.000 • — •
250.000 — • •
The conversion rate is easily calculated:
Line Frequency Rejection
2
3
4
5
6
7
Reference Voltage
The analog input required to generate a full-scale output
is VIN = 2 V
TELCOM SEMICONDUCTOR, INC.
REF
.
Conversion Rate
(Readings 1/sec) =
Clock Frequency (Hz)
4000
8
3-73
TC835
PERSONAL COMPUTER
DA TA ACQUISITION A/D CONVERTER
Power Supplies and Grounds
Power Supplies
The TC835 is designed to work from ±5V supplies. For
single +5V operation, a TC7660 can provide a – 5V supply.
Grounding
Systems should use separate digital and analog ground
systems to avoid loss of accuracy.
Displays and Driver Circuits
TelCom Semiconductor manufactures two display decoder/driver circuits to interface the TC835 to an LCD or LED
display. Each drive has 28 outputs for driving four 7-segment
digit displays.
Device Package Description
TC7211AIPL 40-Pin Epoxy 4-Digit LCD Driver/Decoder
Several sources exist for LCD and LED display:
Display
Manufacturer Address Type
Hewlett Packard 640 Page Mill Rd. LED
Components Palo Alto, CA 94304
Litronix, Inc. 19000 Homestead Rd. LED
Cupertino, CA 94010
AND 720 Palomar Ave. LCD and
Sunnyvale, CA 94086 LED
Epson America, Inc. 3415 Kanhi Kawa St. LCD
Torrance, CA 90505
High-Speed Operation
The maximum conversion rate of most dual-slope A/D
converters is limited by the frequency response of the
comparator. The comparator in this circuit follows the integrator ramp with a 3 µsec delay, and at a clock frequency of
200 kHz (5 µsec period), half of the first reference integrate
clock period is lost in delay. This means that the meter
reading will change from 0 to 1 with a 50 µV input, 1 to 2 with
150 µV, 2 to 3 at 250 µV, etc. This transition at midpoint is
considered desirable by most users; however, if the clock
frequency is increased appreciably above 200 kHz, the
instrument will flash "1" on noise peaks even when the input
is shorted.
For many dedicated applications where the input signal
is always of one polarity, the delay of the comparator need
not be a limitation. Since the nonlinearity and noise do not
increase substantially with frequency, clock rates of up to
~1 MHz may be used. For a fixed clock frequency, the extra
count or counts caused by comparator delay will be a
constant and can be subtracted out digitally.
The clock frequency may be extended above 200 kHz
without this error, however, by using a low-value resistor in
series with the integrating capacitor. The effect of the
resistor is to introduce a small pedestal voltage on to the
integrator output at the beginning of the reference integrate
phase. By careful selection of the ratio between this resistor
and the integrating resistor (a few tens of ohms in the
recommended circuit), the comparator delay can be compensated and the maximum clock frequency extended by
approximately a factor of 3. At higher frequencies, ringing
and second-order breaks will cause significant nonlinearities
in the first few counts of the instrument.
The minimum clock frequency is established by leakage
on the auto-zero and reference capacitors. With most devices, measurement cycles as long as 10 seconds give no
measurable leakage error.
The clock used should be free from significant phase or
frequency jitter. Several suitable low-cost oscillators are
shown in the applications section. The multiplexed output
means that if the display takes significant current from the
logic supply, the clock should have good PSRR.
Zero-Crossing Flip-Flop
The flip-flop interrogates the data once every clock
pulse after the transients of the previous clock pulse and
half-clock pulse have died down. False zero-crossings caused
by clock pulses are not recognized. Of course, the flip-flop
delays the true zero-crossing by up to one count in every
instance, and if a correction were not made, the display
would always be one count too high. Therefore, the counter
is disabled for one clock pulse at the beginning of the
reference integrate (deintegrate) phase. This one-count
delay compensates for the delay of the zero-crossing flipflop, and allows the correct number to be latched into the
display. Similarly, a one-count delay at the beginning of
auto-zero gives an overload display of 0000 instead of 0001.
No delay occurs during signal integrate, so that true ratiometric
readings result.
3-74
TELCOM SEMICONDUCTOR, INC.
PERSONAL COMPUTER
+5V
V
OUT
390 pF
30 kΩ
7
8
2
3
16 kΩ
0.22 µF
16 kΩ
4
1 kΩ
1
+5V
V
OUT
2
3
1
4
7
6
R2
100 kΩ
R2
100 kΩ
R3
50 kΩ
C2
10 pF
R4
2 kΩ
C1
0.1 µF
–
+
LM311
–
+
LM311
56 kΩ
DA TA ACQUISITION A/D CONVERTER
TYPICAL APPLICATIONS DIAGRAMS
1
TC835
0.33µF
200 kHz
+
ANALOG
INPUT
–
100 kΩ
1 µF
100 kΩ
4-1/2 Digit ADC With Multiplexed Common Anode LED Display
20 19 18 17 12
D1 D2 D3 D4 D5
4
INT OUT
5
1 µF
6
22
10
9
3
AZ IN
BUFF
OUT
f
IN
+INPUT
–INPUT
ANALOG
COMMON
–
V
21
–5V
100 kΩ
REF
IN
TC835
C
C
6.8 kΩ
TC04
POL
–
REF
+
REF
4.7 kΩ
23
7
1 µF
8
16
B8
15
B4
14
B2
13
B1
+
V
11
BLANK MSD ON ZERO
bc
6
D
2
C
1
B
7
A
7777
5
RBI
7447
X7
9–15
+5V
2
3
16
+5V
4
RC Oscillator Circuit
R
2
C
GATES ARE 74C04
1. fO = , RP =
2 C(0.41 RP + 0.7 R1)
a. If R1 = R2 = R1, f ≅ 0.55/RC
b. If R2 >> R1, f ≅ 0.45/R1C
c. If R2 << R1, f ≅ 0.72/R1C
2. Examples:
1
a. f = 120 kHz, C = 420 pF
R1 = R2 ≈ 10.9 kΩ
b. f = 120 kHz, C = 420 pF, R2 = 50 kΩ
R1 = 8.93 kΩ
c. f = 120 kHz, C = 220 pF, R2 = 5 kΩ
R1 = 27.3 kΩ
TELCOM SEMICONDUCTOR, INC.
Comparator Clock Circuits
R
1
f
O
5
6
R1 R
2
R1 + R
2
7
8
3-75
TC835
TC04
28
27
26
25
24
23
22
21
9
8
7
6
5
4
3
2
1
REF IN
ANALOG
GND
INT
OUT
AZ IN
BUFF
OUT
C
REF
+5V
–5V
6.8V
UR
DGND
POLARITY
OR
STROBE
RUN/HOLD
CLK IN
BUSY
1
2
3
4
5
6
7
8
9
SET V
REF
= 1V
1.22V
100
kΩ
ANALOG
GND
0.33 µF
100 kΩ
1 µF
47
kΩ
150Ω
+5V
150Ω
10
11
12
13
14
15
16
17
18
+5V
CD4513
BE
1 µF
20
19
18
17
16
15
–INPUT
+INPUT
V
+
D5 (MSD)
B1 (LSB)
B2
(LSD) D1
D2
D3
D4
B4
(MSB) B8
10
11
12
13
14
100
kΩ
SIG
IN
+
–
0.1
µF
+5V
f
OSC
= 200 kHz
+
C
REF
–
V
–
TC835
TC7660
11
1
+5V
8
23
(–5V)
V
+
V
–
24
10 µF
5
4
10 µF
+
+
TC835
TYPICAL APPLICATIONS DIAGRAMS
4-1/2 Digit ADC with Multiplexed Common Cathode LED Display
PERSONAL COMPUTER
DA TA ACQUISITION A/D CONVERTER
3-76
200 kHz
+
ANALOG
–
100 kΩ
INPUT
0.33 µF
100 kΩ
1 µF
4
5
6
22
10
9
3
–5V
1
–
V
INT OUT
AZ IN
BUFF OUT
f
IN
+INPUT
–INPUT
ANALOG
COMMON
REF
IN
2
100 kΩ
TC835
23
POL
STROBE
OR
20
D1
19
D2
18
D3
17
D4
16
B8
15
B4
14
B2
13
B1
12
D5
26
27
+
V
6.8 kΩ
TC04
+5V
1/2 CD4030
+5V
1/4 CD4030
CD4081
CD4071
+5V
1/4 CD4081
4-1/2 DIGIT LCD
1/4 CD4030
D
Q
1/2
CD4013
CLK
RS
31
32
33
34
30
29
28
27
5
BP
D1
D2
D3
D4
TC7211A
B3
B2
B1
B0
SEGMENT
DRIVE
+
V
GND
1
35
Negative Supply Voltage Generator
TELCOM SEMICONDUCTOR, INC.
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