Datasheet TC820CPL, TC820CLW, TC820CKW Datasheet (TelCom Semiconductor)

3-3/4 DIGIT A/D CONVERTER WITH FREQUENCY
COUNTER AND LOGIC PROBE

FEATURES

■ Multiple Analog Measurement System

— Digit A/D Converter
— Frequency Counter
— Logic Probe

■ Low Noise A/D Converter:

— Differential Inputs, (1pA Bias Current)
— On-Chip 50PPM/°C Voltage Reference

■ Frequency Counter:

— 4Mhz Maximum Input Frequency
— Auto-ranging Over Four Decade Range

■ Logic Probe:

— Two LCD Annunciators
— Buzzer Driver

■ 3-3/4 Digit Display with Overrange Indicator

■ LCD Display Driver with Built-in Contrast Control

■ Data Hold Input for Comparison Measurements

■ Low Battery Detect with LCD Annunciator

■ Underrange and Overrange Outputs

■ On-Chip Buzzer Driver with Control Input

■ 44-Pin Plastic Flat Pack or PLCC or 40-Pin Plastic

DIP Packages

FUNCTIONAL BLOCK DIAGRAM

LOGIC HIGH
LOGIC LOW

OVERRANGE PKHOLD LOW BATT

GENERAL DESCRIPTION

The TC820 is a 3-3/4 digit, multi-measurement system
especially suited for use in portable instruments. It inte­grates a dual slope A/D converter, auto-ranging frequency
counter and logic probe into a single 44-pin surface mount
or 40-pin through hole package. The TC820 operates from
a single 9V input voltage (battery) and features a built-in
battery low flag. Function and decimal point selection are
accomplished with simple logic inputs designed for direct
connection to an external microcontroller or rotary switch.

Ease of use, low power operation and high functional
integration make the TC820 desirable in a variety of analog
measurement applications.

ORDERING INFORMATION

Part No. Resolution Package Range

TC820CKW 3-3/4 Digits 44-Pin Plastic 0°C to +70°C

TC820CLW 3-3/4 Digits 44-Pin Plastic 0°C to +70°C

TC820CPL 3-3/4 Digits 40-Pin Plastic DIP 0°C to +70°C

TRIPLEX LCD

Quad Flat Package

Leadless Chip
Carrier

1

TC820

2

3

4

Temperature

5

LOW DRIFT VOLTAGE

DIFFERENTIAL

UNDERRANGE

EOC

OVERRANGE

ANALOG

INPUT

FULL-SCALE

SELECT

FREQUENCY

INPUT

LOGIC

PROBE

INPUT

REFERENCE

3-3/4 DIGIT

A/D CONVERTER

ANALOG GND

AUTORANGING

FREQUENCY

COUNTER

LOGIC

PROBE

DIGITAL GROUND

TELCOM SEMICONDUCTOR, INC.

CLOCK

OSCILLATOR

TC820

TO LCD
AND BUZZER

TRIPLE LCD

DRIVERS

PEAK HOLD

COMPARATOR

LOW

BATTERY

DETECT

PEAK
HOLD

ANNUNCIATOR DRIVE

DECIMAL
DRIVERS

BUZZER

FUNCTION

SELECT

+

9V

POINT

DRIVER

VOLTS
FREQUENCY
LOGIC

DECIMAL
POINT
SELECT

BUZZER
CONTROL

FUNCTION
SELECT

6

7

8

TC820-10 10/17/96

3-149

TC820

3-3/4 DIGIT A/D CONVERTER WITH

FREQUENCY AND LOGIC PROBE

GENERAL DESCRIPTION

The TC820 is a 3-3/4 digit measurement system com­bining an integrating analog-to-digital converter, frequency
counter, and logic level tester in a single package. The
TC820 supersedes the TC7106 in new designs by improv­ing performance and reducing system cost. The TC820
adds features that are difficult, expensive, or impossible to
provide with older A/D converters (see the competitive
evaluation). The high level of integration permits TC820­based instruments to deliver higher performance and more
features, while actually reducing parts count. Fabricated in
low-power CMOS, the TC820 directly drives a 3-3/4 digit
(3999 maximum) LCD.

With a maximum range of 3999 counts, the TC820
provides 10 times greater resolution in the 200mV to 400mV
range than traditional 3-1/2 digit meters. An auto-zero cycle
guarantees a zero reading with a 0V input. CMOS process­ing reduces analog input bias current to only 1pA. Rollover
error (the difference in readings for equal magnitude but
opposite polarity input signals) is less than ±1 count. Differ­ential reference inputs permit ratiometric measurements for
ohms or bridge transducer applications.

The TC820's frequency counter option simplifies design
of an instrument well-suited to both analog and digital
troubleshooting: voltage, current, and resistance measure­ments, plus precise frequency measurements to 4MHz
(higher frequencies can be measured with an external
prescaler), and a simple logic probe. The frequency counter
will automatically adjust its range to match the input fre­quency, over a four-decade range.

Two logic level measurement inputs permit a TC820­based meter to function as a logic probe. When combined
with external level shifters, the TC820 will display logic levels
on the LCD and also turn on a piezoelectric buzzer when the
measured logic level is low.

Other TC820 features simplify instrument design and
reduce parts count. On-chip decimal point drivers are in­cluded, as is a low battery detection annunciator. A piezo­electric buzzer can be controlled with an external switch or
by the logic probe inputs. Two oscillator options are pro­vided: A crystal can be used if high accuracy frequency
measurements are desired, or a simple RC option can be
used for low-end instruments.

A "peak reading hold" input allows the TC820 to retain
the highest A/D or frequency reading. This feature is useful
in measuring motor starting current, maximum tempera­ture, and similar applications.

A family of instruments can be created with the TC820.
No additional design effort is required to create instruments
with 3-3/4 digit resolution.

The TC820 operates from a single 9V battery, with
typical power of 10 mW. Packages include a 40-pin plastic
DIP, 44-pin plastic flat package, and 44-pin PLCC.

COMPETITIVE EVALUATION

Features Comparison TC820 7106

3-3/4 Digit Resolution Yes No
Auto-Ranging Frequency Counter Yes No
Logic Probe Yes No
Decimal Point Drive Yes No
Peak Reading Hold Yes No

(Frequency or Voltage)
Display Hold Yes No
Simple 10:1 Range Change Yes No
Buzzer Drive Yes No
Low Battery Detection Yes No

With Annunciator
Overrange Detection Yes No

With Annunciator
Low Drift Reference Yes No
Underrange/Overrange Yes No

Logic Output
Input Overload Display "OL" "1"
LCD Annunciator Driver Yes No
LCD Drive Type Triplexed Direct
LCD Pin Connections 15 24
LCD Elements 36 23

3-150

TELCOM SEMICONDUCTOR, INC.

3-3/4 DIGIT A/D CONVERTER WITH
FREQUENCY AND LOGIC PROBE

1

TC820

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage (VDD to GND) .....................................15V

Analog Input Voltage (Either Input) (Note 1) ....VDD to V

Reference Input Voltage (Either Input).............VDD to V

Digital Inputs ............................................... VDD to DGND

V

............................................. VDD to (DGND – 0.3V)

DISP

Package Power Dissipation (TA ≤ 70°C) (Note 2)

40-Pin Plastic DIP.............................................1.23W

44-Pin PLCC.....................................................1.23W

44-Pin Plastic Flat Package..............................1.00W

Operating Temperature Range

"C" Devices............................................ 0°C to +70°C

"E" Devices .......................................– 40°C to +85°C

Storage Temperature Range ................– 65°C to +150°C

Lead Temperature (Soldering, 10 sec) ................... 300°C

ELECTRICAL CHARACTERISTICS: V

Symbol Parameter Test Conditions Min Typ Max Units

Zero Input Reading VIN = 0V – 000 ±000 +000 Digital

RE Roll-Over Error VIN = ±390mV – 1 ±0.2 +1 Counts

NL Nonlinearity (Maximum Full-Scale = 400mV – 1 ±0.2 +1 Count

CMRR Common-Mode Rejection V

VCMR Common-Mode Voltage Input High, Input Low V

e

N

I

IN

V

COM

V

CTC

TC

ZS

TC

FS

I

S

Deviation From Best
Straight Line Fit)

Ratiometric Reading VIN = V

Ratio Full-Scale = 400mV

Range
Noise (P-P Value Not VIN = 0V — 15 — µV

Exceeded 95% of Time) Full-Scale = 400mV
Input Leakage Current VIN = 0V

Analog Common Voltage 25 kΩ Between Common and V

Common Voltage 25 kΩ Between Common and V
Temperature Coefficient 0°C ≤ TA ≤ +70°C — 35 50 ppm/°C

Zero Reading Drift VIN = 0V

Scale Factor VIN = 399mV
Temperature Coefficient 0°C ≤ T

Supply Current VIN = 0V — 1 1.5 mA
Peak-to-Peak Backplane V

Drive Voltage V

Full Scale = 400 mV Reading

Full-Scale = 400mV

(VFS = 200 mV)

T
0°C ≤ T
– 40°C ≤ TA ≤ +85°C — 100 —

(VSS – V

– 40°C ≤ TA ≤ +85°C—50—

0°C ≤ T
– 40°C ≤ TA ≤ +85°C1

– 40°C ≤ TA ≤ +85°C—5—
Ext Ref = 0 ppm/°C

= 9V, TA = 25°C, unless otherwise specified.

S

, TC820 1999 1999/2000 2000 Digital

REF

= ±1V, VIN = 0V — 50 — µV/V

CM

= 25°C—110pA

A

≤ +70°C—20—

A

) 3.15 3.3 3.45 V

COM

≤ +70°C — 0.2 — µV/°C

A

≤ +70°C — 1 5 ppm/°C

A

= 9V 4.25 4.7 5.3 V

S

= DGND

DISP

*Static-sensitive devices. Unused devices should be stored in conductive
material to protect against static discharge and static fields. Stresses above
those listed under Absolute Maximum Ratings may cause permanent
damage to the device. These are stress ratings only, and functional

SS

operation of the device at these or any other conditions above those

SS

indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.

NOTES: 1. Input voltages may exceed the supply voltages provided that

input current is limited to ±100µA. Current above this value
may result in invalid display readings but will not destroy the
device if limited to ±1mA.

2. Dissipation ratings assume device is mounted with all leads
soldered to printed circuit board.

+ 1.5 — VDD– 1 V

SS

DD

DD

2

3

4

5

6

7

8

TELCOM SEMICONDUCTOR, INC.

3-151

3-3/4 A/D CONVERTER WITH

FREQUENCY COUNTER

AND LOGIC PROBE

TC820

ELECTRICAL CHARACTERISTICS (Cont.)

Symbol Parameter Test Conditions Min Typ Max Units

Buzzer Frequency f
Counter Timebase Period f
Low Battery Flag Voltage V

V

IL

V

IH

V

OL

Input Low Voltage — — DGND + 1.5 V
Input High Voltage V
Output Low Voltage, IL = 50µA — — DGND + 0.4 V

UR, OR Outputs

V

OL

Output High Voltage, IL = 50µAV
UR, OR Outputs

Control Pin VIN = V
Pull-Down Current

PIN DESCRIPTION

= 40kHz — 5 — kHz

OSC

= 40kHz — 1 — Second

OSC

DD

to V

SS

DD

6.7 7 7.3 V

– 1.5 — — V

DD

– 1.5 — — V

DD

—5 —µA

Pin No. Pin No.
(40-Pin (44-Pin Flat

Package) Package) Symbol Description

1 40 L-E4 LCD segment driver for L ("logic LOW"), polarity, and "e" segment of most

significant digit (MSD).
2 41 AGD4 LCD segment drive for "a," "g," and "d" segments of MSD.
3 42 BC4P3 LCD segment drive for "b" and "c" segments of MSD and decimal point 3.
4 43 HFE3 LCD segment drive for H ("logic HIGH"), and "f" and "e" segments of third LSD.
5 44 AGD3 LCD segment drive for "a," "g," and "d" segments of third LSD.
6 1 BC3P2 LCD segment drive for "b" and "c" segments of third LSD and decimal point 2.
7 2 OFE2 LCD segment drive for "overrange," and "f" and "e" segments of second LSD.
8 3 AGD2 LCD segment drive for "a," "g," and "d" segments of second LSD.
9 4 BC2P1 LCD segment drive for "b " and "c" segments of second LSD and decimal point 1.

10 5 PKFE1 LCD segment drive for "hold peak reading," and "f" and "e" segments of LSD.
11 6 AGD1 LCD segment drive for "a," "g," and "d" segments of LSD.
12 7 BC1BT LCD segment drive for "b" and "c" segments of LSD and "low battery."
13 8 BP3 LCD backplane #3.
14 9 BP2 LCD backplane #2.
15 10 BP1 LCD backplane #1.
—11V

DISP

16 12 DGND Internal logic digital ground, the logic "0" level. Nominally 4.7V below VDD.
17 13 ANNUNC Square-wave output at the backplane frequency, synchronized to BP1. ANNUNC

18 14 LOGIC Logic mode control input. When connected to V

19 15 RANGE/ Dual-purpose input. In range mode, when connected to VDD, the integration time

FREQ will be 200 counts instead of 2000 counts and the LCD will display the analog input

Sets peak LCD drive signal: V

PEAK

= (V

DD

) –V

DISP

. V

may also be used to

DISP

compensate for temperature variation of LCD crystal threshold voltage.

can be used to control display annunciators. Connecting an LCD segment to

ANNUNC turns it on; connecting it to its backplane turns it off.

, the converter is in logic mode.

DD

The LCD displays "OL" and the decimal point inputs control the HIGH and LOW

annunciators. When the "low" annunciator is on, the buzzer will also be on. When

unconnected or connected to DGND, the TC820 is in the voltage/frequency

measurement mode. This pin has a 5µA internal pull-down to DGND.

divided by 10. (See text for limitation withTC820.) In frequency mode, this pin is the

frequency input. A digital signal applied to this pin will be measured with a 1-second

time base. There is an internal 5µA pull-down to DGND.

3-152

TELCOM SEMICONDUCTOR, INC.

3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE

PIN DESCRIPTION

1

TC820

Pin No. Pin No.
(40-Pin (44-Pin Flat

Package) Package) Symbol Description

20 16 DP0/LO Dual-purpose input. Decimal point select input for voltage measurements. In logic

mode, connecting this pin to VDD will turn on the "low" LCD segment. There is an
internal 5µA pull-down to DGND in volts mode only. Decimal point logic:

DP1 DP0 Decimal Point Selected

0 0 None
0 1 DP1
1 0 DP2
1 1 DP3

21 17 DP1/HI Dual-purpose input. Decimal point select input for voltage measurements. In logic

mode, connecting this pin to V

internal 5µA pull-down to DGND in volts mode only.
22 18 BUZOUT Buzzer output. Audio frequency, 5kHz, output which drives a piezoelectric buzzer.
23 19 BUZIN Buzzer control input. Connecting BUZIN to V

logically ORed (internally) with the "logic level low" input. There is an internal 5µA

pull-down to DGND.
24 20 FREQ/ Voltage or frequency measurement select input. When unconnected, or connected

VOLTS to DGND, the A/D converter function is active. When connected to V

frequency counter function is active. This pin has an internal 5µA pull-down

to DGND.
25 21 PKHOLD Peak hold input. When connected to V

if a new conversion value is greater than the preceding value. Thus, the peak

reading will be stored and held indefinitely. When unconnected, or connected to

DGND, the converter will operate normally. This pin has an internal 5µA pull-down

to DGND.

22 UR Underrange output. This output will be HIGH when the digital reading is 380 counts

or less.

23 OR Overrange output. This output will be HIGH when the analog signal input is greater

than full scale. The LCD will display "OL" when the input is overranged.
26 24 V
27 25 COM Analog circuit ground reference point. Nominally 3.3V below VDD.
28 26 C
29 27 C
30 28 V
31 29 V
32 30 V
33 31 V
34 32 V
35 33 C
36 34 V

35 EOC/ Bidirectional pin. Pulses low (i.e., from V

37 36 OSC1 Crystal oscillator (input) connection.
38 37 OSC2 Crystal oscillator (output) connection.
39 38 OSC3 RC oscillator connection.
40 39 V

SS

+
REF

–
REF

+
REF

–
REF

–
IN

+
IN

BUFF

AZ

INT

HOLD conversion. If connected to VDD, conversions will continue, but the display is not

DD

Negative supply connection. Connect to negative terminal of 9V battery.

Positive connection for reference capacitor.

Negative connection for reference capacitor.

High differential reference input connection.

Low differential reference input connection.

Low analog input signal connection.

High analog input signal connection.

Buffer output. Connect to integration resistor.

Auto-zero capacitor connection.

Integrator output. Connect to integration capacitor.

updated.

Positive power supply connection, typically 9V.

will turn on the "high" LCD segment. There is an

DD

turns the buzzer on. BUZIN is

DD

, the

DD

, the converter will only update the display

DD

to DGND) at the end of each

DD

2

3

4

5

6

7

8

TELCOM SEMICONDUCTOR, INC.

3-153

TC820

PIN CONFIGURATIONS

3-3/4 A/D CONVERTER WITH

FREQUENCY COUNTER

AND LOGIC PROBE

SEGMENTS L-E4

SEGMENTS AGD4

SEGMENTS BC4P3

SEGMENTS HFE3

SEGMENTS AGD3

SEGMENTS BC3P2

SEGMENTS OFE2

SEGMENTS AGD2

SEGMENTS BCP1

SEGMENTS PKFE1

SEGMENTS AGD1

SEGMENTS BC1BT

BP3
BP2
BP1

DGND

ANNUNC

LOGIC

RANGE/FREQ

DP0/LO

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

TC820CPL

V

40

OSC3

39
38

OSC2
OSC1

37

V

36

C

35

V

34

V

33

V

32

V

31

V

30

C

29

28

C
COM

27

V

26
25

PK HOLD

24

FREQ/VOLTS

23

BUZ IN

22

BUZ OUT

21

DP1/HI

DD

INT
AZ

BUFF

+
IN
–
IN

–
REF

+
REF
–
REF

+
REF

SS

BC3P2

OFE2

AGD2

BC2P1
PKFE1

AGD1

BP1BT

BP3

BP2
BP1

V

DISP

BC3P2

OFE2

AGD2

BCP2P1

PKFE1

AGD1

BP1BT

BP3
BP2

BP1

V

DISP

AGD3

HFE3

BC4P3

6543 1442

7
8
9

10

11

12

13

18 19 20 21 23 24

DGND

AGD4

TC820CLW

LOGIC

ANNUNC

RANGE/FREQ

AGD3

BC4P3

HFE3

44 43 42 41 39 3840

1
2
3
4

5
6

7
8

9
10
11

12 13 14 15 17 18

AGD4

TC820CKW

L-E4

22

DP0/LO

L–E4

16

DD

V

DP1/HI

DD

V

OSC3

BUZ OUT

OSC3

OSC242OSC141EOC/HOLD

43

25 26 27 28

40

INT

V

UR

BUZ IN

PK HOLD

FREQ/VOLTS

INT

V

OSC1

OSC2

37 36 35

19 20 21 22

EOC/HOLD

34

39
38
37
36
35
34
33
3214
3115
3016
2917

33
32
31
30
29
28
27
26
25
24
23

C

AZ

V

BUFF

+

V

IN

–

V

IN

–

V

REF

+

V

REF

–

C

REF

+

C

REF

COM

V

SS

OR

C

AZ

V

BUFF

+

V

IN

–

V

IN

–

V

REF

+

V

REF

–

C

REF

+

C

REF

COM

V

SS

OR

3-154

DGND

LOGIC

ANNUNC

UR

DP1/HI

DP0/LO

RANGE/FREQ

BUZ IN

BUZ OUT

PK HOLD

FREQ/VOLTS

TELCOM SEMICONDUCTOR, INC.

3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE

FUNCTIONAL BLOCK DIAGRAM

1

TC820

2

C

V

V

+

V

REF
–

V

REF

COMMON

V

DD

V

SS

+
REF

+
IN

–
IN

–

C

REFVBUFF

C

V

AZ

INT

LOW

BATT

DETECT

A/D CONTROL

UNDERRANGE
OVERRANGE

RANGE/FREQ

TO LCD

DEINT

RANGE

INPUT

EOC

÷2

TC820

OSC3OSC2OSC1

BUZ IN

LOGIC
LOW

÷8

FREQUENCY COUNTER INPUT
A/D COUNTER SELECT

RANGE

SEL

B
A

LOW BATT

A/D COUNTER

(3999 COUNTS)

COMPARATOR
A > B

DISPLAY

LATCH

LOGIC

TRIPLEX

DRIVERS

LOW

15

BUZZER
DRIVER

RANGE/
FREQ

FREQ/
VOLTS

LOGIC

DP0/LO
DP1/HI

3

4

5

DGND

UR OR

EOC/

HOLD

PEAK
HOLD

ANNUNC

V

DISP

SEG0 • • • BP3

6

7

8

TELCOM SEMICONDUCTOR, INC.

3-155

TC820

3-3/4 A/D CONVERTER WITH

FREQUENCY COUNTER

AND LOGIC PROBE

V

IN

GND

FREQ

LOGIC

V

DD

DGND

S1a

S1b

S1c

V

DD

S1d

S1e

SWITCH

TO

S1a

100kΩ

CHANGE

RANGE

DP3

S2

NO DP

TO SWITCH
S2

0.01µF

DP2

DP1

COM

V

DD

24

18

33

32
16

19

20

21

LOGIC HIGH

LOGIC LOW

FREQ/
VOLTS

LOGIC

+

V

IN
–

V

IN

DGND

RANGE/FREQ

DP0/LO

DP1/HI

OSC1 OSC2 OSC3VBUFFCAZVINT

37 38 39 34 35

OVERRANGE PKHOLD LOW BATT

L-E4

HFE3

40kHz

22M

AGD4

BC4P3

Ω

470
kΩ

AGD3

BC3P2

NC

OFE2

AGD2

TC820

BC2P1

100
kΩ

10 11 12 13 14 15 17987654321

AGD1

PK FE1

BP3

BC1BT

0.47
µF

BP2

36

0.2
µF

BP1

C

NC

+
REF

+

V

REF

ANNUNC

–

V

REF

COM

V

DD

V

SS

BUZ OUT

BUZ IN

PK HOLD

–

C

REF

28 29

0.1
µF

V

DD

22kΩ

2kΩ

30

= 200mV

V

+

–

DGND

REF

9V

PIEZO
BUZZER

DGND

+

1µF

31
27

40

26

22

23

25

NOTE:

Pin numbers are for
40-pin package.

V

DD

V

DD

V

DD

Figure 1. Typical Operating Circuit

GENERAL THEORY OF OPERATION
Dual-Slope Conversion Principles

The TC820 analog-to-digital converter operates on the
principle of dual-slope integration. An understanding of the
dual-slope conversion technique will aid the user in follow­ing the detailed TC820 theory of operation following this
section. A conventional dual-slope converter measurement
cycle has two distinct phases:

(1) Input Signal Integration

(2) Reference Voltage Integration (Deintegration)

Referring to Figure 2, the unknown input signal to be
converted is integrated from zero for a fixed time period
(t

), measured by counting clock pulses. A constant

INT

reference voltage of the opposite polarity is then integrated
until the integrator output voltage returns to zero. The
reference integration (deintegration) time (T
directly proportional to the unknown input voltage (VIN).

In a simple dual-slope converter, a complete conver­sion requires the integrator output to "ramp-up" from zero
and "ramp-down" back to zero. A simple mathematical
equation relates the input signal, reference voltage, and
integration time:

DEINT

) is then

ANALOG

INPUT

SIGNAL

REF

VOLTAGE

OUTPUT

INTEGRATOR

FIXED

SIGNAL

INTEGRATE

TIME

C

INTEGRATOR

R

–

+

SWITCH

DRIVER

PHASE
CONTROL

COMPARATOR

–

+

CONTROL

LOGIC

POLARITY CONTROL

DISPLAY

V
V

VARIABLE
REFERENCE
INTEGRATE
TIME

=

V

IN

=

1.2 V

IN

FULL SCALE

FULL SCALE

COUNTER

Figure 2. Basic Dual-Slope Converter

CLOCK

3-156

TELCOM SEMICONDUCTOR, INC.

3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE

1

TC820

t

1

R

INT CINT

where: V

For a constant t

integrating resistor and capacitor values as long as they are
stable during a measurement cycle. An inherent benefit of
the dual-slope technique is noise immunity. Noise spikes
are integrated or averaged to zero during the integration
periods, making integrating ADCs immune to the large
conversion errors that plague successive approximation
converters in high-noise environments. Interfering signals,
with frequency components at multiples of the averaging
(integrating) period, will be attenuated (Figure 3). Integrating
ADCs commonly operate with the signal integration period
set to a multiple of the 50/60Hz power line period.

REF

t

INT

t

DEINT

VIN = V

Accuracy in a dual-slope converter is unrelated to the

REF

30

T = MEASUREMENT

20

10

INT

0

t

INT

VIN (t) dt =

∫

= Reference voltage
= Integration time
= Deintegration time

:

INT

t

DEINT

3

PERIOD

V

REF tDEINT

R

INT CINT

comparator) are removed from the conversion. A true digital
zero reading is assured without any external adjustments.

A complete conversion consists of four distinct phases:
(1) Zero Integrator Output

(2) Auto-Zero
(3) Signal Integrate
(4) Reference Deintegrate

Zero Integrator Output Phase

This phase guarantees that the integrator output is at 0V
before the system zero phase is entered, ensuring that the
true system offset voltages will be compensated for even
after an overrange conversion. The duration of this phase is
500 counts plus the unused deintegrate counts.

Auto-Zero Phase

During the auto-zero phase, the differential input signal
is disconnected from the measurement circuit by opening
internal analog switches, and the internal nodes are shorted
to Analog Common (0V
tion. Additional analog switches close a feedback loop
around the integrator and comparator to permit comparator
offset voltage error compensation. A voltage established on
CAZ then compensates for internal device offset voltages
during the measurement cycle. The auto-zero phase re­sidual is typically 10µV to 15µV. The auto-zero duration is
1500 counts.

Signal Integration Phase

Upon completion of the auto-zero phase, the auto-zero
loop is opened and the internal differential inputs connect to

+

V

and V

IN

for a fixed time period, which is 2000 counts (4000 clock
periods). The externally-set clock frequency is divided by
two before clocking the internal counters. The integration
time period is:

–

. The differential input signal is then integrated

IN

) to establish a zero input condi-

REF

2

3

4

5

6

NORMAL MODE REJECTION (dB)

0

0.1/T 1/T 10/T
INPUT FREQUENCY

Figure 3. Normal-Mode Rejection of Dual-Slope Converter

Analog Section

In addition to the basic integrate and deintegrate dual­slope phases discussed above, the TC820 design incorpo­rates a "zero integrator output" phase and an "auto-zero"
phase. These additional phases ensure that the integrator
starts at 0V (even after a severe overrange conversion), and
that all offset voltage errors (buffer amplifier, integrator and

TELCOM SEMICONDUCTOR, INC.

INT

=

4000

f

OSC

3-157

t

The differential input voltage must be within the device's
common-mode range when the converter and measured
system share the same power supply common (ground). If
the converter and measured system do not share the same
power supply common, as in battery-powered applications,

–

V

should be tied to analog common.

IN

Polarity is determined at the end of signal integration
phase. The sign bit is a "true polarity" indication in that
signals less than 1 LSB are correctly determined. This
allows precision null detection that is limited only by device
noise and auto-zero residual offsets.

7

8

TC820

3-3/4 A/D CONVERTER WITH

FREQUENCY COUNTER

AND LOGIC PROBE

Reference Integrate (Deintegrate) Phase

The reference capacitor, which was charged during the
auto-zero phase, is connected to the input of the integrating
amplifier. The internal sign logic ensures the polarity of the
reference voltage is always connected in the phase opposite
to that of the input voltage. This causes the integrator to
ramp back to zero at a constant rate determined by the
reference potential.

The amount of time required (T

) for the integrating

DEINT

amplifier to reach zero is directly proportional to the ampli­tude of the voltage that was put on the integrating capacitor
(V

) during the integration phase:

INT

R

t

DEINT

INT CINT VINT

=

V

REF

The digital reading displayed by the TC820 is:

+

Digital Count = 2000

V

IN

V

– V

REF

–

IN

System Timing

The oscillator frequency is divided by 2 prior to clocking
the internal decade counters. The four-phase measurement
cycle takes a total of 8000 (4000) counts or 16000 clock
pulses. The 8000 count phase is independent of input signal
magnitude or polarity.

Each phase of the measurement cycle has the following
length:

Conversion Phase Counts

1) Auto-Zero: 1500

2) Signal Integrate:

3) Reference Integrate: 1 to 4001

4) Integrator Output Zero: 499 to 4499

NOTES: 1. This time period is fixed. The integration period for the

2. Times shown are the RANGE/FREQ at logic low (normal

1,2

TC820 is:
t

INT (TC820)

where f

operation). When RANGE/FREQ is logic high, signal
integrate times are 200 counts. See "10:1 Range Change"
section.

4000

= = 2000 counts

f

OSC

is the clock oscillator frequency.

OSC

2000

Input Overrange

When the analog input is greater than full scale, the LCD
will display "OL" and the "OVERRANGE" LCD annunciator
will be on.

Peak Reading Hold

The TC820 provides the capability of holding the highest

(or peak) reading. Connecting the PK HOLD input to V

DD

enables the peak hold feature. At the end of each conversion
the contents of the TC820 counter is compared to the
contents of the display register. If the new reading is higher
than the reading being displayed, the higher reading is
transferred to the display register. A "higher" reading is
defined as the reading with the higher absolute value.

The peak reading is held in the display register so the
reading will not "droop" or slowly decay with time. The held
reading will be retained until a higher reading occurs, the PK
HOLD input is disconnected from VDD, or power is removed.

The peak signal to be measured must be present during
the TC820 signal integrate period. The TC820 does not
perform transient peak detection of the analog input signal.
However, in many cases, such as measuring temperature or
electric motor starting current, the TC820 "acquisition time"
will not be a limitation. If true peak detection is required, a
simple circuit will suffice. See the applications section for
details.

The peak reading function is also available when the
TC820 is in the frequency counter mode. The counter auto­ranging feature is disabled when peak reading hold is
selected.

10:1 Range Change

The analog input full-scale range can be changed with
the RANGE/FREQ input. Normally, RANGE/FREQ is held
low by an internal pulldown. Connecting this pin to V

+

will

S

increase the full-scale voltage by a factor of 10. No external
component changes are required.

The RANGE/FREQ input operates by changing the
integrate period. When RANGE/FREQ is connected to VDD,
the signal integration phase of the conversion is reduced by
a factor of 10 (i.e., from 2000 counts to 200 counts).

For the TC820, the 10:1 range change will result in ±4V
full scale. This full-scale range will exceed the common­mode range of the input buffer when operating from a 9V
battery. If range changing is required for the TC820, a higher
supply voltage can be provided or the input voltage can be
divided by 2 externally.

Frequency Counter

In addition to serving as an analog-to-digital converter,
the TC820 internal counter can also function as a frequency
counter (Figure 4). In the counter mode, pulses at the
RANGE/FREQ input will be counted and displayed.

The frequency counter derives its time base from the
clock oscillator. The counter time base is:

f

t

COUNT

=

OSC

40,000

3-158

TELCOM SEMICONDUCTOR, INC.

3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE

1

TC820

Thus, the counter will operate with a 1-second time base
when a 40 kHz oscillator is used. The frequency counter
accuracy is determined by the oscillator accuracy. For
accurate frequency measurements, a crystal oscillator is
recommended.

The frequency counter will automatically select the
proper range. Auto-range operation extends over four
decades, from 3.999 kHz to 3.999 MHz. Decimal points are
set automatically in the frequency mode (Figure 5).

The logic switching levels of the RANGE/FREQ input
are CMOS levels. For best counter operation, an external
buffer is recommended. See the applications section for
details.

Logic Probe

The TC820 can also function as a simple logic probe
(Figure 6). This mode is selected when the LOGIC input is
high. Two dual-purpose pins, which normally control the
decimal points, are used as logic inputs. Connecting either
input to a logic high level will turn on the corresponding LCD
annunciator. When the "low" annunciator is on the buzzer
will be on. As with the frequency counter input, external level
shifters/buffers are recommended for the logic probe inputs.

When the logic probe function is selected while FREQ/
VOLTS is low (A/D mode), the ADC will remain in the auto­zero mode. The LCD will read "OL" and all decimal points will
be off (Figure 7).

If the logic probe is active while FREQ/VOLTS is high
(counter mode), the frequency counter will continue to
operate. The display will read "OL" but the decimal points will
be visible. If the logic probe input is also connected to the
RANGE/FREQ input, bringing the LOGIC input low will
immediately display the frequency at the logic probe input.

Analog Pin Functional Description

+

Differential Signal Inputs (V

The TC820 is designed with true differential inputs, and
accepts input signals within the input stage common-mode
voltage (VCM) range. The typical range is VDD –1V to V
+1.5V. Common-mode voltages are removed from the sys­tem when the TC820 operates from a battery or floating
power source (isolated from measured system) and VSS is
connected to analog common. (See Figure 8.)

LCD

IN

), (V

–

)

IN

SS

2

3

4

5

OF A/D CONVERTER

CLOCK

OSCILLATOR

FREQ/

VOLTS

RANGE/

FREQ

TELCOM SEMICONDUCTOR, INC.

A/D CONVERTER/FREQUENCY

COUNTER SELECT

FREQUENCY
INPUT

÷2

÷20,000

PROGRAMMABLE

DIVIDER

( ÷1, 10, 100, 1000)

FROM INTEGRATOR

A/D CONVERTER

FREQUENCY COUNTER

TC820

Figure 4. TC820 Counter Operation

COMPARATOR

TO DECIMAL

POINT DRIVERS

AUTO-RANGE

CONTROL

DATA LATCH, PEAK

HOLD REGISTER,

LCD DECODER/DRIVERS

ENABLE

3-3/4 DIGIT COUNTER

COUNT OVERFLOW

UNDERRANGE

DETECT

OVERRANGE

DETECT

6

7

8

3-159

TC820

Figure 5. TC820 Auto-Range Decimal Point Selection

DP3 DP2 DP1

f

IN

0Hz – 3999Hz

4kHz – 39.99kHz

40kHz – 399.9kHz

≥

400kHz

vs Frequency Counter Input

DECIMAL POINT

DP3
DP2
DP1

NONE

3-3/4 A/D CONVERTER WITH

FREQUENCY COUNTER

AND LOGIC PROBE

In systems where common-mode voltages exist, the
86dB common-mode rejection ratio minimizes error. Com­mon-mode voltages do, however, affect the integrator out­put level. A worst-case condition exists if a large, positive
VCM exists in conjunction with a full-scale, negative differen­tial signal. The negative signal drives the integrator output
positive along with VCM (Figure 9). For such applications, the
integrator output swing can be reduced below the recom­mended 2V full-scale swing. The integrator output will swing
within 0.3V of VDD or VDD without increased linearity error.

Reference (VDD, VSS)

The TC820 reference, like the analog signal input, has
true differential inputs. In addition, the reference voltage can
be generated anywhere within the power supply voltage of
the converter. The differential reference inputs permit
ratiometric measurements and simplify interfacing with sen­sors, such as load cells and temperature sensors.

LOGIC

PROBE

INPUT

EXTERNAL
LOGIC LEVEL
DETECTION
AND PULSE
STRETCHING

CMOS
LOGIC
LEVELS

V

DD

DP0/LO

DP1/HI

LOGIC

HIGH

LOW

LCD

DRIVERS

LCD

TC820

DISABLE A/D CONVERTER

TO
BUZZER

3-160

NC

Figure 6. Logic Probe Simplified Schematic

TELCOM SEMICONDUCTOR, INC.

3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE

HIGH

LOW

"HIGH" ANNUNCIATOR WILL BE ON WHEN DP1/HI =

*

LOGIC HIGH
"LOW" ANNUNCIATOR AND BUZZER WILL BE ON

**

WHEN DP0/LO = LOGIC HIGH

To prevent roll-over-type errors from being induced by
large common-mode voltages, C
pared to stray node capacitance. A 0.1µF capacitor is
typical.

The TC820 offers a significantly improved analog
common temperature coefficient, providing a very stable
voltage suitable for use as a voltage reference. The
temperature coefficient of analog common is typically
35ppm/°C.

*

**

Figure 7. LCD During Logic Probe Operation

should be large com-

REF

TC820

Analog Common

The analog common pin is set at a voltage potential
approximately 3.3V below VDD. This potential is guaranteed
to be between 3.15V and 3.45V below VDD. Analog common
is tied internally to an N-channel FET capable of sinking
3mA. This FET will hold the common line at 3.3V below V
should an external load attempt to pull the common line
toward VDD. Analog common source current is limited to
12µA, and is therefore easily pulled to a more negative
voltage (i.e., below VDD – 3.3V).

The TC820 connects the internal V
analog common during the auto-zero cycle. During the
reference integrate phase, V
common. If V
a common-mode voltage exists. This is rejected by the
converter's 86dB common-mode rejection ratio. In battery­powered applications, analog common and V
connected, removing common-mode voltage concerns. In
systems where V
or to a given voltage, analog common should be connected

–

to V

.

IN

The analog common pin serves to set the analog section
reference or common point. The TC820 is specifically
designed to operate from a battery or in any measurement

–

is not externally connected to analog common,

IN

–

is connected to the power supply ground

IN

–
IN

+
IN

is connected to analog

and V

–

IN

–
IN

are usually

DD

inputs to

1

2

3

4

+V–

V
POWER
SOURCE

SEGMENT
DRIVE

BP1

V

MEASURED

SYSTEM

+

V

–

V

Figure 8. Common-Mode Voltage Removed in Battery Operation With V

GND

GND

BUFCAZ

+

V

IN

–

V

IN

ANALOG
COMMON

V

–

REF

V

INT

BP2

OSC1

TC820

V

+

REF

V

DD

+

9V

OSC2

V

SS

OSC3

LCD

BP3

NC

–

= Analog Common

IN

5

6

7

TELCOM SEMICONDUCTOR, INC.

8

3-161

TC820

3-3/4 A/D CONVERTER WITH

FREQUENCY COUNTER

AND LOGIC PROBE

C

–

+

INTEGRATOR

[

4000
f

OSC

Þ VIN)

I

V

I

INPUT

+

V

IN

–

V

CM

Figure 9. Common-Mode Voltage Reduces Available

BUFFER

+

–

T

V

=

I

RI C

Where:

T

= Integration Time =

I

C

= Integration Capacitor

I

R

= Integration Resistor

I

Integrator Swing (V

I

I

R

V

[

CMVIN

I

–

COM

system where input signals are not referenced (float)
with respect to the TC820 power source. The analog common
potential of VDD – 3.3V gives a 7V end-of-battery-life voltage.
The analog common potential has a voltage coefficient of

0.001%/%.

With a sufficiently high total supply voltage (VDD – V

SS

> 7V), analog common is a very stable potential with excellent
temperature stability (typically 35ppm/°C). This potential
can be used to generate the TC820 reference voltage. An
external voltage reference will be unnecessary in most
cases, because of the 35ppm/°C temperature coefficient.
See the applications section for details.

Function Control Input Pin Functional Description

FREQ/VOLTS

This input determines whether the TC820 is in the
analog-to-digital conversion mode or in the frequency counter
mode. When FREQ/VOLTS is connected to VDD, the TC820
will measure frequency at the RANGE/FREQ input. When
unconnected, or connected to DGND, the TC820 will oper­ate as an analog-to-digital converter. This input has an
internal 5µA pull-down to DGND.

LOGIC

The LOGIC input is used to activate the logic probe
function. When connected to VDD, the TC820 will enter the
logic probe mode. The LCD will show "OL" and all decimal
points will be off. The decimal point inputs directly control
"high" and "low" display annunciators. When LOGIC is
unconnected, or connected to DGND, the TC820 will per­form analog-to-digital or frequency measurements as se­lected by the FREQ/VOLTS input. The LOGIC input has an
internal 5 µA pull-down to DGND.

RANGE/FREQ

The function of this dual-purpose pin is determined by
the FREQ/VOLTS input. When FREQ/VOLTS is connected
to VDD, RANGE/FREQ is the input for the frequency counter
function. Pulses at this input are counted with a time base
equal to f

/40,000. Since this input has CMOS input levels

OSC

(VDD - 1.5V and DGND +1.5V), an external buffer is recom­mended.

When the TC820 analog-to-digital converter function is
selected, connecting RANGE/FREQ to VDD will divide the
integration time by 10. Therefore, the RANGE/FREQ input
can be used to perform a 10:1 range change without
changing external components.

The TC820 operating modes are selected with the
function control inputs. The control input truth table is shown
in Table I. The high logic threshold is ≥ VDD - 1.5V and the
low logic level is ≤ DGND +1.5V.

Table I. TC820 Control Input Truth Table

Logic Input

FREQ/ RANGE/ TC820

VOLTS FREQ LOGIC Function

X X 1 Logic Probe
0 0 0 A/D Converter,

V

FULL SCALE

0 1 0 A/D Converter,

V

FULL SCALE

1 Frequency 0 Frequency Counter

Counter Input

NOTES: 1. Logic "0" = DGND

3-162

2. Logic "1" = V

DD

= 2 3V

= 20 3V

REF

REF

DP0/LO, DP1/HI

The function of these dual-purpose pins is determined
by the LOGIC input. When the TC820 is in the analog-to­digital converter mode, these inputs control the LCD decimal
points. The decimal point truth table is shown in Table II.
These inputs have internal 5µA pull-downs to DGND when
the voltage/frequency measurement mode is active.

Table II. TC820 Decimal Point Truth Table
Decimal Point Inputs

DP1 DP0 LCD

0 0 3999
0 1 399.9
1 0 39.99
1 1 3.999

TELCOM SEMICONDUCTOR, INC.

3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE

Connecting the LOGIC input to VDD places the TC820
in the logic probe mode. In this mode, the DP0/LO and DP1/
HI inputs control the LCD "low" and "high" annunciators
directly. When DP1/HI is connected to VDD, the "high"
annunciator will turn on. When DP0/LO is connected to VDD,
the "low" annunciator and the buzzer will turn on. The
internal pull-downs on these pins are disabled when the
logic probe function is selected.

These inputs have CMOS logic switching thresholds.
For optimum performance as a logic probe, external level
shifters are recommended. See the applications section for
details.

BUZ IN

This input controls the TC820 on-chip buzzer driver.
Connecting BUZ IN to VDD will turn the buzzer on. There is
an external pull-down to DGND. BUZ IN can be used with
external circuitry to provide additional functions, such as a
fast, audible continuity indication.

Additional Features

The TC820 is available in 40-pin and 44-pin packages.
Several additional features are available in the 44-pin pack­age.

EOC/HOLD

EOC/HOLD is a dual-purpose, bidirectional pin. As an
output, this pin goes low for 10 clock cycles at the end of each
conversion. This pulse latches the conversion data into the
display driver section of the TC820.

EOC/HOLD can be used to hold (or "freeze") the dis­play. Connecting this pin to VDD inhibits the display update
process. Conversions will continue, but the display will not
change. EOC/HOLD will hold the display reading for either
analog-to-digital or frequency measurements.

The input/output structure of the EOC/HOLD pin is
shown in Figure 10. The output drive current is only a few
microAmps, so EOC/HOLD can easily be overdriven by an
open-collector logic gate, as well as a FET, bipolar transis­tor, or mechanical switch. When used as an output, EOC/
HOLD will have a slow rise and fall time due to the limited
output current drive. A CMOS Schmitt trigger buffer is
recommended.

TC820

EOC/HOLD

Overrange (OR), Underrange (UR)

The OR output will be high when the analog input signal
is greater than full scale (3999 counts). The UR output will
be high when the display reading is 380 counts or less.

The OR and UR outputs can be used to provide an auto­ranging meter function. By logically ANDing these outputs
with the inverted EOC/HOLD output, a single pulse will be
generated each time an underranged or overranged conver­sion occurs (Figure 11).

EOC/HOLD

TC820

Figure 11. Generating Underrange and Overrange Pulses

V

DISP

The V
age. In the 40-pin package, V
DGND, providing a typical LCD drive voltage of 5V
44-pin package includes a separate V
tions requiring a variable or temperature-compensated LCD
drive voltage. See the applications information for sug­gested circuits.

4

500 k

Ω

≈

TC820

Figure 10. EOC/HOLD Pin Schematic

*

UR

OR

74HC132

*

input sets the peak-to-peak LCD drive volt-

DISP

DISP

*

*

is connected internally to

DISP

DISPLAY
UPDATE

EOC

. The

P-P

input for applica-

1

2

3

4

5

6

7

TELCOM SEMICONDUCTOR, INC.

8

3-163

TC820

V

DD

V

SS

V

+

REF

V

–

REF

TC820

3.5V to 6V

TC7660

TC04

V

IN

V

IN

+

–

+

–

V

IN

10µF

3

4

2

8

5

10µF

+

+

+

COM

3-3/4 A/D CONVERTER WITH

FREQUENCY COUNTER

AND LOGIC PROBE

V

DISP

The V
age. In the 40-pin package, V
DGND, providing a typical LCD drive voltage of 5 V
44-pin package includes a separate V

input sets the peak-to-peak LCD drive volt-

DISP

is connected internally to

DISP

input for applica-

DISP

P-P

. The

tions requiring a variable or temperature-compensated LCD
drive voltage. See the applications information for sug­gested circuits.

APPLICATIONS INFORMATION
Power Supplies

The TC820 is designed to operate from a single power
supply such as a 9V battery (Figure 12). The converter will
operate over a range of 7V to 15V. For battery operation,
analog common (COM) provides a common-mode bias
voltage (see analog common discussion in the theory of
operation section). However, measurements cannot be
referenced to battery ground. To do so will exceed the
negative common-mode voltage limit.

V

DD

Digital Ground (DGND)

Digital ground is generated from an internal zener diode
(Figure 14). The voltage between VDD and DGND is the
internal supply voltage for the digital section of the TC820.
DGND will sink a minimum of 3mA.

DGND establishes the low logic level reference for the
TC820 mode select inputs, and for the frequency and logic
probe inputs. The DGND pin can be used as the negative
supply for external logic gates, such as the logic probe
buffers. To ensure correct counter operation at high fre­quency, connect a 1µF capacitor from DGND to VDD.

DGND also provides the drive voltage for the LCD. The
TC820 40-pin package internally connects the LCD V

DISP

pin to DGND, and provides an LCD drive voltage of about
5V

. In the 44-pin package, connecting the V

P-P

DISP

pin to

DGND will provide a 5V LCD drive voltage.

Digital Input Logic Levels

Logic levels for the TC820 digital inputs are referenced
to VDD and DGND. The high-level threshold is VDD– 1.5V
and the low logic level is DGND +1.5V. In most cases,
digital inputs will be connected directly to VDD with a
mechanical switch. CMOS gates can also be used to
control the logic inputs, as shown in the logic probe inputs
section.

+

V

REF

+

9V

–

Figure 12. Powering the TC820 From a Single 9V Battery

A battery with voltage between 3.5V and 7V can be used

3-164

to power the TC820, when used with a voltage doubler, as
shown in Figure 13. The voltage doubler uses the TC7660
and two external capacitors. With this configuration mea­surements can be referenced either to Analog Common or
to battery ground.

–

V

REF

COM

+

V

IN

–

V

IN

V

SS

TC820

+

V

IN

–

Figure 13. Powering the TC820 From a Low-Voltage Battery

TELCOM SEMICONDUCTOR, INC.

3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE

V

DD

5V

3.2V
COM

DGND

V

SS

12µA

–
+

TC820

N

LOGIC

SECTION

P

N

Figure 14. DGND and COM Outputs

Clock Oscillator

The TC820 oscillator can be controlled with either a
crystal or with an inexpensive resistor-capacitor combina­tion. The crystal circuit, shown in Figure 15, is recommended
when high accuracy is required in the frequency counter
mode. The 40kHz crystal is a standard frequency for ultra­sonic alarms, and will provide a 1-second time base for the
counter or 2.5 analog-to-digital conversions per second.
Consult the crystal manufacturer for detailed applications
information.

Where low cost is important, the R-C circuit of Figure 16
can be used. The frequency of this circuit will be approxi­mately:

=

0.3

RC

f

OSC

TC820

5pF

37 38 39

Figure 16. R-C Oscillator Circuit

Typical values are R = 10kΩ and C = 68pF. The resistor
value should be ≥100kΩ. For accurate frequency measure­ment, an R-C oscillator frequency of 40kHz is required.

10pF

110kΩ

System Timing

All system timing is derived from the clock oscillator. The
clock oscillator is divided by 2 prior to clocking the A/D
counters. The clock is also divided by 8 to drive the buzzer,
by 240 to generate the LCD backplane frequency, and by
40,000 for the frequency counter time base. A simplified
diagram of the system clock is shown in Figure 17.

Component Value Selection

Auto Zero Capacitor — C

The value of the auto-zero capacitor (CAZ) has some
influence on system noise. A 0.47µF capacitor is recom­mended; a low dielectric absorption capacitor (Mylar) is
required.

AZ

TC820

75pF

1

2

3

4

5

6

5 pF

37

40kHz

22 M

Ω

Figure 15. Suggested Crystal Oscillator Circuit

TELCOM SEMICONDUCTOR, INC.

10pF

38 39

Ω

470k

TC820

Reference Voltage Capacitor — C

The reference voltage capacitor used to ramp the inte­grator output voltage back to zero during the reference
integrate cycle is stored on C
typical. A good quality, low leakage capacitor (such as
Mylar) should be used.

Integrating Capacitor — C

C

should be selected to maximize integrator output

INT

voltage swing without causing output saturation. Analog
common will normally supply the differential voltage
reference. For this case, a ±2V integrator output swing is
optimum when the analog input is near full scale. For 2.5
readings/second (f
value is suggested. If a different oscillator frequency is used,
C

must be changed in inverse proportion to maintain the

INT

OSC

INT

= 40kHz) and VFS = 400mV, a 0.22µF

REF

. A 0.1µF capacitor is

REF

3-165

7

8

TC820

3-3/4 A/D CONVERTER WITH

FREQUENCY COUNTER

AND LOGIC PROBE

OSCILLATOR

COMPONENTS

OSCILLATOR

COMPONENTS

R/C

XTAL

OSC1 OSC2 OSC3

TC820

A/D

COUNTER

BUZZER

LCD

BACKPLANE

DRIVER

COUNTER

TIME BASE

Figure 17. System Clock Generation

÷

÷

÷

240

÷

40,000

2

8

nominal ±2V integrator swing. An exact expression for C
is:

C

INT

where: f

4000 V

=

V

INT RINT fOSC

= Clock frequency

OSC

FS

VFS= Full-scale input voltage
R

= Integrating resistor

INT

V

= Desired full-scale integrator output swing

INT

Reference Voltage Selection

A full-scale reading (4000 counts for TC820) requires

the input signal be twice the reference voltage.

Table III. Reference Voltage Selection

Full-Scale
Input Voltage
(VFS) (Note 1) V

200mV Note 2 –

400mV 200mV 10 µV

1V 500mV 250µV
2V 1V 500µV

(Notes 3, 4)

NOTES: 1. TC820 in A/D converter mode, RANGE/FREQ = logic low.

2. Not recommended.

3. VFS > 2V may exceed the input common mode range.
See "10:1 Range Change" section.

4. Full-scale voltage values are not limited to the values
shown. For example, TC820 VFS can be any value from
400mV to 2V.

In some applications, a scale factor other than unity may
exist between a transducer output voltage and the required
digital reading. Assume, for example, that a pressure trans­ducer output is 800mV for 4000 lb/in2. Rather than dividing
the input voltage by two, the reference voltage should be set
to 400mV. This permits the transducer input to be used
directly.

The internal voltage reference potential available at

INT

analog common will normally be used to supply the
converter's reference voltage. This potential is stable when­ever the supply potential is greater than approximately 7V.
The low-battery detection circuit and analog common oper­ate from the same internal reference. This ensures that the
low-battery annunciator will turn on at the time the internal
reference begins to lose regulation.

The TC820 can also operate with an external reference.
Figure 18 shows internal and external reference applica­tions.

REF

Resolution

C

must have low dielectric absorption to minimize

INT

roll-over error. A polypropylene capacitor is recommended.

Integrating Resistor — R

INT

The input buffer amplifier and integrator are designed
with class A output stages. The integrator and buffer can
supply 40µA drive currents with negligible linearity errors.
R

is chosen to remain in the output stage linear drive

INT

region but not so large that printed circuit board leakage
currents induce errors. For a 400mV full scale, R

should

INT

be about 100kΩ.

3-166

Ratiometric Resistance Measurements

The TC820 true differential input and differential refer­ence make ratiometric readings possible. In ratiometric
operation, an unknown resistance is measured with respect
to a known standard resistance. No accurately defined
reference voltage is needed.

The unknown resistance is put in series with a known
standard and a current is passed through the pair (Fig­ure 19). The voltage developed across the unknown is
applied to the input and voltages across the known resistor

TELCOM SEMICONDUCTOR, INC.

3-3/4 A/D CONVERTER WITH

TC820

+

DGND

FREQUENCY

INPUT

GND

DGND

74HC14

RANGE/FREQ

FREQ/VOLTS

V

DD

1µF

+9V

FREQUENCY COUNTER
AND LOGIC PROBE

9V

+

DD

2kΩ

+

V

REF

–

V

REF

22kΩ

V

V

DD

SS

+

2kΩ

V

REF

V

REF

–

V

REF

ANALOG

COMMON

SET V = 1/2 V

REF FULL SCALE

(a) Internal Reference (b) External Reference

V

TC820TC820

COMMON

+

V

1

TC820

2

TC04A

1.2V
REF

3

Figure 18. Reference Voltage Connections

V

DD

+

V

R

STANDARD

R

UNKNOWN

Figure 19. Low Parts Count Ratiometric Resistance Measurement

REF

–

V

REF

+

V

IN

TC820

–

V

IN

ANALOG
COMMON

LCD

applied to the reference input. If the unknown equals the
standard, the input voltage will equal the reference voltage
and the display will read 2000. The displayed reading can be
determined from the following expression:

R

Displayed reading = 3 2000

The display will overrange for values of R

3 R

STANDARD

.

UNKNOWN

R

STANDARD

UNKNOWN

≥ 2

Figure 20. Frequency Counter External Buffer

Logic Probe Inputs

The DP0/LO and DP1/HI inputs provide the logic probe
inputs when the LOGIC input is high. Driving either DP0/LO
or DP1/HI to a logic high will turn on the appropriate LCD
annunciator. When DP0/LO is high, the buzzer will be on.

To provide a "single input" logic probe function, external
buffers should be used. A simple circuit is shown in Figure

21. This circuit will turn the appropriate annunciator on for
high and low level inputs.

If carefully controlled logic thresholds are required, a
window comparator can be used. Figure 22 shows a typical
circuit. This circuit will turn on the high or low annunciators
when the logic thresholds are exceeded, but the resistors
connected from DP0/LO and DP1/HI to DGND will turn both
annunciators off when the logic probe is unconnected.

The TC820 logic inputs are not latched internally, so
pulses of short duration will usually be difficult or impossible
to see. To display short pulses properly, the input pulse
should be "stretched." The circuit of Figure 22 shows cap-

+9V

TC820

4

5

6

Buffering the FREQ Input

input is low, the TC820 will count pulses at the RANGE/
FREQ input. The time base will be f
with a 40kHz clock. The signal to be measured should swing
from VDD to DGND. The RANGE/FREQ input has CMOS
input levels without hysteresis. For best results, especially
with low-frequency sine-wave inputs, an external buffer with
hysteresis should be added. A typical circuit is shown in
Figure 20.

When the FREQ/VOLTS input is high and the LOGIC

TELCOM SEMICONDUCTOR, INC.

/40,000, or 1 second

OSC

LOGIC

PROBE

INPUT

V

DD

LOGIC

**

74HC14

*

Figure 21. Simple External Logic Probe Buffer

DP1/HI
DP0/LO

DGND

7

8

3-167

TC820

V

DD

TC820

+

–

V

SS

V

+

IN

PK HOLD

0V

0.01µF

OFFSET
NULL

1N4148

+9V

10kΩ

V

IN

TL061

+9V

R1

V

H

–

1N4148

1M

Ω

LOGIC

PROBE

INPUT

1M

Ω

NOTE: Select R1, R2, R3 for desired logic thresholds.

R2

R3

+

–

1N4148

V

L

+

V

DD

LOGIC

DP1/HI

TC820

DP0/LO

DGND

3-3/4 A/D CONVERTER WITH

FREQUENCY COUNTER

AND LOGIC PROBE

Figure 22. Window Comparator Logic Probe

acitors added across the input pull-down resistors to stretch
the input pulse and permit viewing short-duration input
pulses.

External Peak Detection

depending on the displays values. Figure 25 shows a set of
waveforms for the a, g, d outputs of one digit for several
combinations of "on" segments.

Table IV. LCD Backplane and Segment Assignments

Figure 23. External Peak Detector

The TC820 will hold the highest A/D conversion or
frequency reading indefinitely when the PK HOLD input is
connected to VDD. However, the analog peak input must be
present during the A/D converter's signal integrate period.
For slowly changing signals, such as temperature, the peak
reading will be properly converted and held.

If rapidly changing analog signals must be held, an
external peak detector should be added. An inexpensive
circuit can be made from an op amp and a few discrete
components, as shown in Figure 23. The droop rate of the
external peak detector should be adjusted so that the held
voltage will not decay below the desired accuracy level
during the converter's 400msec conversion time.

Liquid Crystal Display (LCD)

The TC820 drives a triplex (multiplexed 3:1) LCD with
three backplanes. The LCD can include decimal points,
polarity sign, and annunciators for overrange, peak hold,
high and low logic levels, and low battery. Table IV shows the
assignment of the display segments to the backplanes and
segment drive lines. The backplane drive frequency is
obtained by dividing the oscillator frequency by 240.

Backplane waveforms are shown in Figure 24. These
appear on outputs BP1, BP2, and BP3. They remain the
same regardless of the segments being driven.

Other display output lines have waveforms that vary

3-168

40-Pin DIP Flat Pkg Display

Pin No. Pin No. Pin No. BP1 BP2 BP3

1 40 3 LOW "—" E4
2 41 4 A4 G4 D4
3 42 5 B4 C4 DP3
4 43 6 HIGH F3 E3
5 44 7 A3 G3 D3
6 1 8 B3 C3 DP2
7 2 9 OVER F2 E2
8 3 10 A2 G2 D2

9 4 11 B2 C2 DP1
10 5 12 PEAK F1 E1
11 6 13 A1 G1 D1
12 7 14 B1 C1 BATT
13 8 2,16* — — BP3
14 9 1 — BP2 —
15 10 15 BP1 — —

*Connect both pins 2 and 16 of LCD to TC820 BP3 output.

44-Pin LCD

TELCOM SEMICONDUCTOR, INC.

3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE

BP1

BP2

BP3

Figure 24. Backplane Waveforms

SEGMENT

LINE

ALL OFF

a SEGMENT

ON

d, g OFF

a, g ON

d OFF

ALL ON

Figure 25. Typical Display Output Waveforms

V

DD

V

H

V

L

V

DISP

V

DD

V

H

V

L

V

DISP

V

DD

V

H

V

L

V

DISP

V

DD

V

H

V

L

V

DISP

TC820

LCD Source

Although most users will design their own custom LCD,
a standard display for the TC820 (Figure 26), Part No. ST­1355-M1, is available from:

Crystaloid (USA) Crystaloid (Europe)

Crystaloid Electronics Rep France

P.O. Box 628 102, rue des Nouvelles

5282 Hudson Dr. F92150 Suresnes

Hudson, OH 44238 France

Phone: [phone] Phone: [phone]

Fax: [phone] Fax: [phone]

Annunciator Output

The annunciator output is a square wave running
at the backplane frequency (for example, 167Hz when
f

= 40kHz). The peak-to-peak amplitude is equal to (V

OSC

– V
annunciator output turns it on; connecting it to its backplane
turns it off.

LCD Drive Voltage (V

V
internally connected to DGND, providing a typical LCD drive
voltage of 5V

LCDs require that the drive levels vary with temperature to
maintain good viewing angle and display contrast. In this
case, the TC820 44-pin package provides a pin connection
for V
adjusted to give a temperature compensation of about
10mV/°C between VDD and V
and V
cannot exceed 0.3V below GND.

). Connecting an annunciator of the LCD to the

DISP

)

DISP

The peak-to-peak LCD drive voltage is equal to (VDD –

). In the 40-pin dual-in-line package (DIP), V

DISP

.

P-P

For applications with a wide temperature range, some

. Figure 27 shows TC820 circuits that can be

DISP

. The diode between GND

DISP

should have a low turn-on voltage because V

DISP

DISP

DD

is

DISP

1

2

3

4

5

6

HIGH

OVER PEAK

LOW

PIN 1

Figure 26. Typical TC820 LCD

TELCOM SEMICONDUCTOR, INC.

BATT

Crystal Source

Two sources of the 40 kHz crystal are:

Statek Corp. SPK Electronics

512 N. Main St. 2F-1, No. 312, Sec. 4,

Orange, CA 92668 Jen Ai Rd

Phone: [phone] Taipei, Taiwan R.O.C.

Fax: [phone] Phone: [phone]

Part #: CX-1V-40.0 Fax: [phone]

Part#: QRT-38-40.0kHz

7

8

3-169

TC820

3-3/4 A/D CONVERTER WITH

FREQUENCY COUNTER

AND LOGIC PROBE

1N4148

5kΩ

75kΩ

39kΩ

TL071

+

V

200kΩ

–

+

1N5817 1N5817

11

12

Figure 27. Temperature-Compensating Circuits

39

20kΩ

TC820

V

DISP

DGND

24

–

V

NOTE: Pin numbers shown are for 44-pin flat package.

39kΩ

18k Ω

2N2222

11

12

TC820

V

DISP

DGND

+

V

39

24

–

V

3-170

TELCOM SEMICONDUCTOR, INC.