TelCom Semiconductor Inc TC4405EOA, TC4405CPA, TC4405COA, TC4404MJA, TC4404EPA Datasheet

1.5A DUAL OPEN-DRAIN MOSFET DRIVERS

FEATURES

GENERAL DESCRIPTION

1

TC4404
TC4405

2

■ Independently-Programmable Rise and Fall Times

■ Low Output Impedance ................................ 7Ω Typ

■ High Speed tR, tF....... <30 nsec with 1000 pF Load

■ Short Delay Times ....................................< 30 nsec

■ Wide Operating Range ..........................4.5V to 18V

■ Latch-Up Protected ......... Will Withstand >500 mA

Reverse Current (Either Polarity)

■ Input Withstands Negative Swings Up to –5V

APPLICATIONS

■ Motor Controls

■ Driving Bipolar Transistors

■ Driver for Nonoverlapping Totem Poles

■ Reach-Up/Reach-Down Driver

ORDERING INFORMATION

Part No. Package Temperature

Range

TC4404COA 8-Pin SOIC 0°C to +70°C
TC4404CPA 8-Pin PDIP 0°C to +70°C
TC4404EOA 8-Pin SOIC – 40°C to +85°C
TC4404EPA 8-Pin PDIP – 40°C to +85°C
TC4404MJA 8-Pin CerDIP – 55°C to +125°C

TC4405COA 8-Pin SOIC 0°C to +70°C
TC4405CPA 8-Pin PDIP 0°C to +70°C
TC4405EOA 8-Pin SOIC – 40°C to +85°C
TC4405EPA 8-Pin PDIP – 40°C to +85°C
TC4405MJA 8-Pin CerDIP – 55°C to +125°C

FUNCTIONAL BLOCK DIAGRAM

The TC4404 and TC4405 are CMOS buffer-drivers
constructed with complementary MOS outputs, where the
drains of the totem-pole output have been left separated so
that individual connections can be made to the pull-up and
pull-down sections of the output. This allows the insertion
of drain-current-limiting resistors in the pull-up and/or pull­down sections, allowing the user to define the rates of rise
and fall for a capacitive load; or a reduced output swing, if
driving a resistive load, or to limit base current, when
driving a bipolar transistor. Minimum rise and fall times,
with no resistors, will be less than 30 nsec for a 1000-pF
load. There is no upper limit.

For driving MOSFETs in motor-control applications,
where slow-ON/fast-OFF operation is desired, these de­vices are superior to the previously-used technique of add­ing a diode-resistor combination between the driver output
and the MOSFET, because they allow accurate control of
turn-ON, while maintaining fast turn-OFF and maximum
noise immunity for an OFF device.

When used to drive bipolar transistors, these drivers
maintain the high speeds common to other TelCom driv­ers. They allow insertion of a base current-limiting resistor,
while providing a separate half-output for fast turn-OFF. By
proper positioning of the resistor, either npn or pnp transis­tors can be driven.

For driving many loads in low-power regimes, these
drivers, because they eliminate shoot-through currents in
the output stage, require significantly less power at higher
frequencies, and can be helpful in meeting low-power
budgets.

Because neither drain in an output is dependent on
the other, these devices can also be used as open-drain
buffer/drivers where both drains are available in one device,

1

V

DD

3

4

5

6

2 (3)

INPUT

4.7V

4

GND

TELCOM SEMICONDUCTOR, INC.

EFFECTIVE

INPUT

C 12 pF

300 mV

TC4404

INVERTING

TC4405

NONINVERTING

A (B)

8 (6)

7 (5)

PULL UP

PULL DOWN

7

8

TC4404/5-6 10/21/96

4-219

TC4404
TC4405

1.5A DUAL OPEN-DRAIN
MOSFET DRIVERS

thus minimizing chip count. Unused open drains should be
retur ned to the supply rail that their device sources are
connected to (pull-downs to ground, pull-ups to VDD), to
prevent static damage. In addition, in situations where
timing resistors or other means of limiting crossover currents
are used, like drains may be paralleled for greater current
carrying capacity.

These devices are built to operate in the most de­manding electrical environments. They will not latch up
under any conditions within their power and voltage rat­ings; they are not subject to damage when up to 5V of
noise spiking of either polarity occurs on their ground pin;
and they can accept, without damage or logic upset, up to
1/2 amp of reverse current (of either polarity) being forced
back into their outputs. All terminals are fully protected
against up to 2 kV of electrostatic discharge.

ABSOLUTE MAXIMUM RATINGS

Supply Voltage ......................................................... +22V

Maximum Chip Temperature................................. +150°C

Storage Temperature Range ................– 65°C to +150°C

Package Thermal Resistance

CerDIP R
CerDIP R
PDIP R
PDIP R
SOIC R
SOIC R

............................................... 150°C/W

θJ-A

................................................. 55°C/W

θJ-C

.................................................. 125°C/W

θJ-A

.................................................... 45°C/W

θJ-C

.................................................. 155°C/W

θJ-A

.................................................... 45°C/W

θJ-C

Operating Temperature Range

C Version...............................................0°C to +70°C

E Version ..........................................– 40°C to +85°C

M Version .......................................– 55°C to +125°C

Package Power Dissipation (TA ≤ 70°C)

Plastic .............................................................730mW

CerDP.............................................................800mW

SOIC...............................................................470mW

*Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.

Lead Temperature (Soldering, 10 sec) .................+300°C

ELECTRICAL CHARACTERISTICS:

Specifications measured at TA = +25°C with 4.5V ≤ VDD ≤ 18V, unless otherwise specified.

Symbol Parameter Test Conditions Min Typ Max Unit
Input

V

IH

V

IL

I

IN

Logic 1 High Input Voltage 2.4 — — V
Logic 0 Low Input Voltage — — 0.8 V
Input Current – 0V ≤ V

IN

≤ V

DD

– 1 — 1 µA

Output

V

OH

V

OL

R

O

I

PK

I

DC

I

R

High Output Voltage V
Low Output Voltage — — 0.025 V
Output Resistance I
Peak Output Current (Any Drain)
Continuous Output Current (Any Drain)
Latch-Up Protection (Any Drain)

Withstand Reverse Current

= 1 0 mA, VDD = 18V; Any Drain — 7 10 Ω

OUT

Duty cycle < 2%, t ≤ 300µsec — 1.5 — A

Duty cycle < 2%, t ≤ 300µsec > 500 — — mA

– 0.025 — — V

DD

— — 100 mA

Switching Time (Note 1)

t

R

t

F

t

D1

t

D2

Rise Time Figure 1, CL = 1000 pF — 25 30 nsec
Fall Time Figure 1, CL = 1000 pF — 25 30 nsec
Delay Time Figure 1, CL = 1000 pF — 15 30 nsec
Delay Time Figure 1, CL = 1000 pF — 32 50 nsec

Power Supply

I

S

NOTE: 1. Switching times guaranteed by design.

Power Supply Current VIN = 3V (Both Inputs) — — 4.5 mA

VIN = 0V (Both Inputs) — — 0.4

4-220

TELCOM SEMICONDUCTOR, INC.