TelCom TC7109, TC7109A User Manual
查询TC7109供应商
12-BIT µP-COMP ATIBLE ANALOG-TO-DIGITAL CONVERTERS
1
TC7109
TC7109A
FEATURES
■ Zero-Integrator Cycle for Fast Recovery From
Input Overloads
■ Eliminates Cross -Talk in Multiplexed Systems
■ 12-Bit Plus Sign Integrating A/D Converter With
Overrange Indication
■ Sign Magnitude Coding Format
■ True Differential Signal Input and Differential
Reference Input
■ Low Noise............................................ 15 µV
P-P
Typ
■ Input Current .............................................. 1 pA Typ
■ No Zero Adjustment Needed
■ TTL-Compatible, Byte-Organized Tri-State
Outputs
■ UART Handshake Mode for Simple Serial Data
Transmission
ORDERING INFORMATION
PART CODE TC7109X
A or blank*
Package Temperature
Code Package Range
CKW 44-Pin PQFP 0°C to +70°C
CLW 44-Pin PLCC 0°C to +70°C
CPL 40-Pin Plastic DIP 0°C to +70°C
IJL 40-Pin CerDIP –25°C to +85°C
* The "A" version has a higher I
on the digital lines.
OUT
GENERAL DESCRIPTION
The TC7109A is a 12-bit plus sign, CMOS low-power
analog-to-digital converter (ADC). Only eight passive components and a crystal are required to form a complete
dual-slope integrating ADC.
The improved VOH source current TC7109A has features that make it an attractive per-channel alternative to
analog multiplexing for many data acquisition applications. These features include typical input bias current of
1pA drift of less than 1µV/°C, input noise typically 15µV
and auto-zero. True differential input and reference allow
measurement of bridge-type transducers such as load
cells, strain gauges, and temperature transducers.
The TC7109A provides a versatile digital interface. In
the direct mode, chip select and HIGH/LOW byte enables
control parallel bus interface. In the handshake mode, the
TC7109A will operate with industry-standard UARTs in
controlling serial data transmission — ideal for remote
data logging. Control and monitoring of conversion timing
is provided by the RUN/HOLD input and STATUS output.
For applications requiring more resolution, see the
TC500, 15-bit plus sign ADC data sheet.
The TC7109A has improved overrange recovery performance and higher output drive capability than the original TC7109. All new (or existing) designs should specify
the TC7109A wherever possible.
P-P
2
3
,
4
5
FUNCTIONAL BLOCK DIAGRAM
C
REF
REF
REF
+
IN
+
CAP
37 36
AZZIAZ
INT
35
INPUT
COMMON
INPUT
HI
33
INT
34
LO
DE
(–)DE(+)
AZ
DE
DE
(+)
(–)
AZ
DE (±)
ZI
29
28 40
–
REF
V
OUT
TELCOM SEMICONDUCTOR, INC.
HIGH-ORDER
R
REF
IN
ZI
INT
REF
–
–
CAP
3839
BUFFER
–
+
ZI
TC7109A
10 µA
–
+
6.2V
C
AZBUFF
3130
INTEGRATOR
–
+
AZ
ANALOG
SECTION
+
V
AZ
32
TO
C
INT
INT
COMPARATOR
COMP OUT
AZ
INT
DE (±)
ZI
COMP
OUT
BYTE OUTPUTS
B12B11B10B9B8B7B6B5B4B3B2B
POL
OR
TEST
17 3 4 5 6 7 8 9 10 11 12 13 14
16 THREE-STATE OUTPUTS
CONVERSION
CONTROL
LOGIC
226222324
OSC
STATUS
RUN/
HOLD
14 LATCHES
12-BIT COUNTER
LATCH
OSCILLATOR
AND CLOCK
CIRCUITRY
OSC
OSC
SEL
IN
OUT
LOW-ORDER
BYTE OUTPUTS
CLOCK
HANDSHAKE
21
25
BUF
MODE
OSC
OUT
15 16
LOGIC
1
27
SEND
1
GND
18
LBEN
19
HBEN
20
CE/LOAD
TC7109/A-7 11/6/96
6
7
8
3-91
TC7109
TC7109A
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
ABSOLUTE MAXIMUM RATINGS*
Positive Supply Voltage (GND to V+) ..................... +6.2V
Negative Supply voltage (GND to V–) ....................... –9V
Analog Input Voltage (Low to High) (Note 1).......V+ to V
Reference Input Voltage (Low to High (Note 1) ..V+ to V
Digital Input Voltage (Pins 2–27) (Note 2)..... GND –0.3V
Power Dissipation, TA < 70°C, (Note 3)
CerDIP............................................................. 2.29W
Plastic DIP....................................................... 1.23W
PLCC ............................................................... 1.23W
PQFP............................................................... 1.00W
Operating Temperature Range
Plastic Package (C)...............................0°C to +70°C
Ceramic Package (I)....................... – 25°C to +85°C
(M) ................... – 55°C to +125°C
Storage Temperature Range ............... – 65°C to +150°C
Lead Temperature (Soldering, 10 sec) .................+300°C
ELECTRICAL CHARACTERISTICS: All parameters with V
*Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional
–
operation of the device at these or any other conditions above those
–
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
NOTES: 1. Input voltages may exceed supply voltages if input current is
limited to ±100 µA.
2. Connecting any digital inputs or outputs to voltages greater
than V+ or less than GND may cause destructive device latchup. Therefore, it is recommended that inputs from sources
other than the same power supply should not be applied to
the TC7109A before its power supply is established. In
multiple supply systems, the supply to the device should be
activated first.
3. This limit refers to that of the package and will not occur during
normal operation.
+
= +5V, V– = –5V, GND = 0V, TA = +25°C,
unless otherwise indicated.
Symbol Parameter Test Conditions Min Typ Max Unit
Analog
Overload Recovery Time — 0 1 Measurement
(TC7109A) Cycle
Zero Input Reading V
Ratio Metric Reading V
NL Nonlinearity (Max Deviation Full Scale = 409.6 mV to –1 ±0.2 +1 Count
From Best Straight Line Fit) 2.048V Over Full Operating
Roll-Over Error (Difference in Full Scale = 409.6 mV to –1 ±0.02 +1 Count
Reading for Equal Positive and 2.048V Over Full Operating
Negative Inputs Near (Full Scale) Temperature Range
CMRR Input Common-Mode V
Rejection Ratio Full Scale = 409.6 mV
V
CMR
Common-Mode Voltage Input High, Input Low, V–+1.5 — V+–1 V
Range and Common Pins
e
N
Noise (P-P Value Not VIN = 0V — 15 — µV
Exceeded 95% of Time) Full Scale = 409.6 mV
I
IN
TC
TC
ZS
FS
Leakage Current at Input VIN, All Packages: +25°C—110pA
Zero Reading Drift VIN = 0V — 0.2 1 µV/°C
Scale-Factor VIN = 408.9 mV = >7770
Temperature Coefficient Reading, Ext Ref = 0 ppm/°C
+
I
Supply Current VIN = 0V, Crystal Oscillator — 700 1500 µA
(V+ to GND) 3.58 MHz Test Circuit
I
S
Supply Current (V+ to V–) Pins 2–21, 25, 26, 27, 29 Open — 700 1500 µA
= 0V – 00008±00008+00008Octal Reading
IN
Full Scale = 409.6 mV
= V
IN
REF
V
= 204.8 mV 4000
REF
3777
3777840008Octal Reading
8
8
Temperature Range
±1V, VIN = 0V — 50 — µV/V
CM
C Device: 0°C ≤ T
I Device: –25°C ≤ T
≤ +70°C 20 100 pA
A
≤ +85°C 100 250 pA
A
M Device: –55°C ≤ TA ≤ +125°C25nA
8
—15µV/°C
3-92
TELCOM SEMICONDUCTOR, INC.
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGIT AL CONVERTERS
ELECTRICAL CHARACTERISTICS (Cont.)
1
TC7109
TC7109A
Symbol Parameter Test Conditions Min Typ Max Unit
V
REF
TC
REF
Digital
V
OH
V
OL
V
IH
V
IL
t
W
Ref Out Voltage Referenced to V+, 25 kΩ – 2.4 – 2.8 – 3.2 V
Between V+ and Ref Out
Ref Out Temperature 25 kΩ Between V+ and Ref Out — 80 — ppm/°C
Coefficient 0°C ≤ TA ≤ +70°C
Output High Voltage TC7109: I
TC7109A: I
Pins 3–16, 18, 19, 20
Output Low Voltage I
Output Leakage Current Pins 3–16 High Impedance — ±0.01 ±1 µA
Control I/O Pins 18, 19, 20 V
Pull-Up Current Mode Input at GND
Control I/O Loading HBEN, Pin 19; LBEN, Pin 18 — — 50 pF
Input High Voltage Pins 18–21, 26, 27 2.5 — — V
Input Low Voltage Pins 18-21, 26, 27 — — 1 V
Input Pull-Up Current Pins 26, 27; V
Input Pull-Down Current Pin 21; V
Oscillator Output Current, High V
Oscillator Output Current, Low V
Buffered Oscillator Output V
Current, High
Buffered Oscillator Output V
Current, Low
Mode Input Pulse Width 60 — — nsec
= 1.6 mA — 0.2 0.4 V
OUT
Referenced to GND
Referenced to GND
Pins 17, 24; V
= 2.5V — 1 — mA
OUT
= 2.5V — 1.5 — mA
OUT
= 2.5V — 2 — mA
OUT
= 2.5V — 5 — mA
OUT
= 100 µA 3.5 4.3 — V
OUT
= 700 µA
OUT
= V+–3V — 5 — µA
OUT
= V+–3V — 5 — µA
OUT
= V+–3V 25 µA
OUT
= GND = +3V — 1 — µA
OUT
2
3
4
5
HANDLING PRECAUTIONS: These devices are CMOS and must be handled correctly to prevent damage. Package
and store only in conductive foam, anti-static tubes, or other conducting material. Use proper anti-static handling
procedures. Do not connect in circuits under "power-on" conditions, as high transients may cause permanent
damage.
TELCOM SEMICONDUCTOR, INC.
6
7
8
3-93
TC7109
TC7109A
PIN CONFIGURATIONS
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
+
+
–
–
+
–
–
+
12
B
44 43 42 41 39 3840
B
1
11
B
2
10
B
3
9
B
4
8
B
5
7
6
NC
B
7
6
B
5
B
4
B
3
B
2
12 13 14 15 17 18
1
B
OR
TEST
POL
LBEN
STATUS
TC7109ACKW
TC7109CKW
HBEN
GND
(PQFP)
16
CE/LOAD
NC
NC
+
V
MODE
REF CAP
REF CAP
REF IN
37 36 35 34
19
20 21 22
OSC IN
OSC SEL
OSC OUT
STATUS
CE/LOAD
REF IN
33
32
31
30
29
28
27
268
259
2410
2311
BUFF
OSC OUT
GND
POL
OR
B
12
B
11
B
10
B
B
B
B
B
B
B
B
B
TEST
LBEN
HBEN
IN HI
IN LO
COMMON
INT
AZ
NC
BUFF
REF OUT
–
V
SEND
RUN/HOLD
1
2
3
4
5
6
7
9
8
9
8
7
10
6
11
12
5
13
4
14
3
2
15
1
16
17
18
19
20
B
B
10
B
B
B
NC
B
B
B
B
B
TC7109A
TC7109
(CPL, IJL,
MJL)
(PDIP)
(CerDIP)
12
OR
B
6543 1442
7
11
8
9
9
10
8
11
7
12
13
6
5
4
3
2
18 19 20 21 23 24
1
B
TEST
+
40
V
39
REF IN
38
REF CAP
37
REF CAP
36
REF IN
35
IN HI
IN LO
34
33
COMMON
32
INT
31
AZ
30
BUFF
REF OUT
29
–
28
V
27
SEND
26
RUN/HOLD
25
BUFF OSC OUT
24
OSC SEL
23
OSC OUT
22
OSC IN
21
MODE
STATUS
POL
TC7109ACLW
TC7109CLW
LBEN
HBEN
–
–
+
+
GND
(PLCC)
22
CE/LOAD
NC
NC
+
V
MODE
REF CAP
REF CAP
REF IN
43 42 41 40
25
26 27 28
OSC IN
OSC SEL
OSC OUT
REF IN
39
38
37
36
35
34
33
3214
3115
3016
2917
BUFF
OSC OUT
IN HI
IN LO
COMMON
INT
AZ
NC
BUFF
REF OUT
–
V
SEND
RUN/HOLD
3-94
NC = NO INTERNAL CONNECTION
TELCOM SEMICONDUCTOR, INC.
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGIT AL CONVERTERS
TC7109/A PIN DESCRIPTION
1
TC7109
TC7109A
40-Pin PDIP
Pin Number Symbol Description
1 GND Digital ground, 0V, ground return for all digital logic.
2 STATUS Output HIGH during integrate and deintegrate until data is latched. Output LOW
when analog section is in auto-zero or zero-integrator configuration.
3 POL Polarity — High for positive input.
4 OR Overrange — High if overranged.
5B12Bit 12 (Most Significant Bit)
6B11Bit 11
7B10Bit 10
8B
9B
10 B
11 B
12 B
13 B
14 B
15 B
16 B
17 TEST Input High — Normal operation. Input LOW — Forces all bit outputs HIGH.
18 Low-Byte Enable — With MODE (Pin 21) LOW, and CE/LOAD (Pin 20) LOW,
19 High-Byte Enable — With MODE (Pin 21) LOW, and CE/LOAD (Pin 20) LOW,
20 Chip Enable/Load — With MODE (Pin 21) LOW, CE/LOAD serves as a master
21 MODE Input LOW — Direct output mode where CE/LOAD (Pin 20), HBEN (Pin 19), and
22 OSC IN Oscillator Input
23 OSC OUT Oscillator Output
24 OSC SEL Oscillator Select — Input HIGH configures OSC IN, OSC OUT, BUF OSC OUT as
25 BUF OSC OUT Buffered Oscillator Output
26 Input HIGH — Conversions continuously performed every 8192 clock pulses.
9
8
7
6
5
4
3
2
1
LBEN
HBEN
CE/LOAD
RUN/HOLD
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 (Least Significant Bit)
Note: This input is used for test purposes only.
taking this pin LOW activates low-order byte outputs, B1–B8. With MODE (Pin 21)
HIGH, this pin serves as low-byte flag output used in handshake mode. See
Figures 7, 8, and 9.
taking this pin LOW activates high-order byte outputs, B9–B12, POL, OR. With
MODE (Pin 21) HIGH, this pin serves as high-byte flag output used in handshake
mode. See Figures 7, 8, and 9.
output enable. When HIGH, B1–B12, POL, OR outputs are disabled. When
MODE (Pin 21) is HIGH, a load strobe is used in handshake mode. See Figure 7,
8, and 9.
LBEN (Pin 18) act as inputs directly controlling byte outputs.
Input Pulsed HIGH — Causes immediate entry into handshake mode and output
of data as in Figure 9.
Input HIGH — Enables CE/LOAD (Pin 20), HBEN (Pin 19), and LBEN (Pin 18)
as outputs, handshake mode will be entered and data output as in Figures 7 and
8 at conversions completion.
RC oscillator — clock will be same phase and duty cycle as BUF OSC OUT. Input
LOW configures OSC IN, OSC OUT for crystal oscillator — clock frequency will
be 1/58 of frequency at BUF OSC OUT.
Input LOW — Conversion in progress completed; converter will stop in auto-zero
seven counts before integrate.
All Three-State Data Bits
2
3
4
5
6
7
8
TELCOM SEMICONDUCTOR, INC.
3-95
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
TC7109
TC7109A
TC7109/A PIN DESCRIPTION (Cont.)
40-Pin PDIP
Pin Number Symbol Description
27 SEND Input — Used in handshake mode to indicate ability of an external device to
accept data.
Connect to V+ if not used.
28 V
29 REF OUT Reference Voltage Output — Nominally 2.8V down from V+ (Pin 40).
30 BUFFER Buffer Amplifier Output
31 AUTO-ZERO Auto-Zero Node — Inside foil of CAZ.
32 INTEGRATOR Integrator Output — Outside foil of C
33 COMMON Analog Common — System is auto-zeroed to COMMON.
34 INPUT LOW Differential Input Low Side
35 INPUT HIGH Differential Input High Side
36 REF IN + Differential Reference Input Positive
37 REF CAP + Reference Capacitor Positive
38 REF CAP – Reference Capacitor Negative
39 REF IN – Differential Reference Input Negative
40 V
NOTE: All digital levels are positive true.
–
+
Analog Negative Supply — Nominally –5V with respect to GND (Pin 1).
.
INT
Positive Supply Voltage — Nominally +5V with respect to GND (Pin 1).
+5V
GND
+5V
5–12
GND
SERIAL
INPUT
SERIAL
OUTPUT
1
V
2
OSC CONTROL
3
GND
4
RRD
RBR1–8
13
14
15
16
20
25
CMOS UART
PE
FE
OE
SFD
RR1
TRO
6403
*
Q11
RESET
+5V
CD4040B
CLK
1011
8
15
40
TRC
OSC IN
*TBR1–8
NOTE:
17
39
EPE
38
CLS1
37
CLS2
36
SBS
35
GND
PI
34
CRL
TRE
DRR
DR
TBRL
TBRE
MR
For lowest power consumption, TBR1–TBR8 inputs
should have 100kΩ pull-up resistors to +5V.
+5V
26–33
24
18
19
23
22
21
GND
GND
6
8
1
GND
25
BUFF OSC OUT
2
STATUS
19
HBEN
3–8
B9–B12,
POL, OR
9–16
B1–B8
17
TEST
18
LBEN
21
MODE
20
CE/LOAD
27
SEND
TC7109A
V
REF IN
REF CAP
REF CAP
REF IN
IN HI
IN LO
COM
INT
AZ
BUFF
REF OUT
V
RUN/HOLD
OSC SEL
OSC OUT
OSC IN
40
+
39
–
38
–
+
37
+
36
35
34
33
32
31
30
29
28
–
26
24
23
22
+5V
1µF
1MΩ
0.01µF
C
INT
0.15µF
C
AZ
0.33µF
R
20k
INT
–5V
+5V OR OPEN
GND
100kΩΩ
3.58MHz
CRYSTAL
–
EXTERNAL
REFERENCE
+
+
INPUT
–
ANALOG
GND
0.2V
REF
1V
REF
3-96
Figure 1. TC7109A UART Interface (Send Any Word to UART to Transmit Latest Result)
TELCOM SEMICONDUCTOR, INC.
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGIT AL CONVERTERS
1
TC7109
TC7109A
+5V
GND
+5V
+5V
+5V
+5V
GND
23
1
TO
4
RESET
5
SS
6
INT
8748/8049
MICROCOMPUTER
7
EA
8
WR
9
PSEN
11
ALE
25
PROG
26
V
DD
39
TL
40
V
CC
20
GND
CMOS
XTAL2XTALI
P20–P27
P14–P17
P13
P12
P11
P10
DB0–DB7
RD
2
21–24,
35–38
31–34
30
29
28
27
12–19
10
8
5
OTHER I/O
8
40
+5V
GND
6
8
17
26
18
19
3–8
9–16
20
V
1
GND
TEST
RUN/HOLD
2
STATUS
LBEN
HBEN
B9–B12,
POL, OR
B1–B8
CE/LOAD
+
REF IN
REF CAP
REF CAP
REF IN
TC7109A
REF OUT
BUFF OSC OUT
OSC SEL
OSC OUT
IN HI
HI LO
COM
INT
AZ
BUFF
V
SEND
OSC IN
MODE
39
–
38
–
C
AZ
0.33µF
–5V
GND
1µF
1MΩ
0.01µF
C
INT
0.15µF
R
20k
10 kΩΩ
3.58MHz
CRYSTAL
37
+
36
+
35
34
33
32
31
30
29
28
–
27
25
24
23
22
21
INT
–
EXTERNAL
REFERNCE
+
+
INPUT
–
ANALOG
GND
0.2 V
REF
1 V
REF
2
3
4
Figure 2. TC7109A Parallel Interface With 8048/8049 Microcomputer
DETAILED DESCRIPTION
(All Pin Designations Refer to 40-Pin DIP)
Analog Section
The functional diagram shows a block diagram of the
analog section of the TC7109A. The circuit will perform
conversions at a rate determined by the clock frequency
(8192 clock periods per cycle), when the RUN/HOLD input
is left open or connected to V+. Each measurement cycle is
divided into four phases, as shown in Figure 3. They are:
(1) Auto-Zero (AZ), (2) Signal Integrate (INT), (3) Reference
Deintegrate (DE), and (4) Zero Integrator (ZI).
Auto-Zero Phase
The buffer and the integrator inputs are disconnected
from input high and input low and connected to analog
common. The reference capacitor is charged to the reference voltage. A feedback loop is closed around the system
to charge the auto-zero capacitor, CAZ, to compensate for
offset voltage in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the AZ
accuracy is limited only by the noise of the system. The offset
referred to the input is less than 10 µV.
Signal-Integrate Phase
The buffer and integrator inputs are removed from
common and connected to input high and input low. The
auto-zero loop is opened. The auto-zero capacitor is placed
in series in the loop to provide an equal and opposite
compensating offset voltage. The differential voltage between input high and input low is integrated for a fixed time
of 2048 clock periods. At the end of this phase, the polarity
of the integrated signal is determined. If the input signal has
no return to the converter's power supply, input low can be
tied to analog common to establish the correct commonmode voltage.
Deintegrate Phase
Input high is connected across the previously-charged
reference capacitor and input low is internally connected to
analog common. Circuitry within the chip ensures the capacitor will be connected with the correct polarity to cause
the integrator output to return to the zero crossing (established by auto-zero) with a fixed slope. The time, represented by the number of clock periods counted for the output
to return to zero, is proportional to the input signal.
5
6
7
8
TELCOM SEMICONDUCTOR, INC.
3-97
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