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12-BIT µP-COMP ATIBLE ANALOG-TO-DIGITAL CONVERTERS
1
TC7109
TC7109A
FEATURES
■ Zero-Integrator Cycle for Fast Recovery From
Input Overloads
■ Eliminates Cross -Talk in Multiplexed Systems
■ 12-Bit Plus Sign Integrating A/D Converter With
Overrange Indication
■ Sign Magnitude Coding Format
■ True Differential Signal Input and Differential
Reference Input
■ Low Noise............................................ 15 µV
P-P
Typ
■ Input Current .............................................. 1 pA Typ
■ No Zero Adjustment Needed
■ TTL-Compatible, Byte-Organized Tri-State
Outputs
■ UART Handshake Mode for Simple Serial Data
Transmission
ORDERING INFORMATION
PART CODE TC7109X
A or blank*
Package Temperature
Code Package Range
CKW 44-Pin PQFP 0°C to +70°C
CLW 44-Pin PLCC 0°C to +70°C
CPL 40-Pin Plastic DIP 0°C to +70°C
IJL 40-Pin CerDIP –25°C to +85°C
* The "A" version has a higher I
on the digital lines.
OUT
GENERAL DESCRIPTION
The TC7109A is a 12-bit plus sign, CMOS low-power
analog-to-digital converter (ADC). Only eight passive components and a crystal are required to form a complete
dual-slope integrating ADC.
The improved VOH source current TC7109A has features that make it an attractive per-channel alternative to
analog multiplexing for many data acquisition applications. These features include typical input bias current of
1pA drift of less than 1µV/°C, input noise typically 15µV
and auto-zero. True differential input and reference allow
measurement of bridge-type transducers such as load
cells, strain gauges, and temperature transducers.
The TC7109A provides a versatile digital interface. In
the direct mode, chip select and HIGH/LOW byte enables
control parallel bus interface. In the handshake mode, the
TC7109A will operate with industry-standard UARTs in
controlling serial data transmission — ideal for remote
data logging. Control and monitoring of conversion timing
is provided by the RUN/HOLD input and STATUS output.
For applications requiring more resolution, see the
TC500, 15-bit plus sign ADC data sheet.
The TC7109A has improved overrange recovery performance and higher output drive capability than the original TC7109. All new (or existing) designs should specify
the TC7109A wherever possible.
P-P
2
3
,
4
5
FUNCTIONAL BLOCK DIAGRAM
C
REF
REF
REF
+
IN
+
CAP
37 36
AZZIAZ
INT
35
INPUT
COMMON
INPUT
HI
33
INT
34
LO
DE
(–)DE(+)
AZ
DE
DE
(+)
(–)
AZ
DE (±)
ZI
29
28 40
–
REF
V
OUT
TELCOM SEMICONDUCTOR, INC.
HIGH-ORDER
R
REF
IN
ZI
INT
REF
–
–
CAP
3839
BUFFER
–
+
ZI
TC7109A
10 µA
–
+
6.2V
C
AZBUFF
3130
INTEGRATOR
–
+
AZ
ANALOG
SECTION
+
V
AZ
32
TO
C
INT
INT
COMPARATOR
COMP OUT
AZ
INT
DE (±)
ZI
COMP
OUT
BYTE OUTPUTS
B12B11B10B9B8B7B6B5B4B3B2B
POL
OR
TEST
17 3 4 5 6 7 8 9 10 11 12 13 14
16 THREE-STATE OUTPUTS
CONVERSION
CONTROL
LOGIC
226222324
OSC
STATUS
RUN/
HOLD
14 LATCHES
12-BIT COUNTER
LATCH
OSCILLATOR
AND CLOCK
CIRCUITRY
OSC
OSC
SEL
IN
OUT
LOW-ORDER
BYTE OUTPUTS
CLOCK
HANDSHAKE
21
25
BUF
MODE
OSC
OUT
15 16
LOGIC
1
27
SEND
1
GND
18
LBEN
19
HBEN
20
CE/LOAD
TC7109/A-7 11/6/96
6
7
8
3-91
TC7109
TC7109A
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
ABSOLUTE MAXIMUM RATINGS*
Positive Supply Voltage (GND to V+) ..................... +6.2V
Negative Supply voltage (GND to V–) ....................... –9V
Analog Input Voltage (Low to High) (Note 1).......V+ to V
Reference Input Voltage (Low to High (Note 1) ..V+ to V
Digital Input Voltage (Pins 2–27) (Note 2)..... GND –0.3V
Power Dissipation, TA < 70°C, (Note 3)
CerDIP............................................................. 2.29W
Plastic DIP....................................................... 1.23W
PLCC ............................................................... 1.23W
PQFP............................................................... 1.00W
Operating Temperature Range
Plastic Package (C)...............................0°C to +70°C
Ceramic Package (I)....................... – 25°C to +85°C
(M) ................... – 55°C to +125°C
Storage Temperature Range ............... – 65°C to +150°C
Lead Temperature (Soldering, 10 sec) .................+300°C
ELECTRICAL CHARACTERISTICS: All parameters with V
*Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional
–
operation of the device at these or any other conditions above those
–
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
NOTES: 1. Input voltages may exceed supply voltages if input current is
limited to ±100 µA.
2. Connecting any digital inputs or outputs to voltages greater
than V+ or less than GND may cause destructive device latchup. Therefore, it is recommended that inputs from sources
other than the same power supply should not be applied to
the TC7109A before its power supply is established. In
multiple supply systems, the supply to the device should be
activated first.
3. This limit refers to that of the package and will not occur during
normal operation.
+
= +5V, V– = –5V, GND = 0V, TA = +25°C,
unless otherwise indicated.
Symbol Parameter Test Conditions Min Typ Max Unit
Analog
Overload Recovery Time — 0 1 Measurement
(TC7109A) Cycle
Zero Input Reading V
Ratio Metric Reading V
NL Nonlinearity (Max Deviation Full Scale = 409.6 mV to –1 ±0.2 +1 Count
From Best Straight Line Fit) 2.048V Over Full Operating
Roll-Over Error (Difference in Full Scale = 409.6 mV to –1 ±0.02 +1 Count
Reading for Equal Positive and 2.048V Over Full Operating
Negative Inputs Near (Full Scale) Temperature Range
CMRR Input Common-Mode V
Rejection Ratio Full Scale = 409.6 mV
V
CMR
Common-Mode Voltage Input High, Input Low, V–+1.5 — V+–1 V
Range and Common Pins
e
N
Noise (P-P Value Not VIN = 0V — 15 — µV
Exceeded 95% of Time) Full Scale = 409.6 mV
I
IN
TC
TC
ZS
FS
Leakage Current at Input VIN, All Packages: +25°C—110pA
Zero Reading Drift VIN = 0V — 0.2 1 µV/°C
Scale-Factor VIN = 408.9 mV = >7770
Temperature Coefficient Reading, Ext Ref = 0 ppm/°C
+
I
Supply Current VIN = 0V, Crystal Oscillator — 700 1500 µA
(V+ to GND) 3.58 MHz Test Circuit
I
S
Supply Current (V+ to V–) Pins 2–21, 25, 26, 27, 29 Open — 700 1500 µA
= 0V – 00008±00008+00008Octal Reading
IN
Full Scale = 409.6 mV
= V
IN
REF
V
= 204.8 mV 4000
REF
3777
3777840008Octal Reading
8
8
Temperature Range
±1V, VIN = 0V — 50 — µV/V
CM
C Device: 0°C ≤ T
I Device: –25°C ≤ T
≤ +70°C 20 100 pA
A
≤ +85°C 100 250 pA
A
M Device: –55°C ≤ TA ≤ +125°C25nA
8
—15µV/°C
3-92
TELCOM SEMICONDUCTOR, INC.
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGIT AL CONVERTERS
ELECTRICAL CHARACTERISTICS (Cont.)
1
TC7109
TC7109A
Symbol Parameter Test Conditions Min Typ Max Unit
V
REF
TC
REF
Digital
V
OH
V
OL
V
IH
V
IL
t
W
Ref Out Voltage Referenced to V+, 25 kΩ – 2.4 – 2.8 – 3.2 V
Between V+ and Ref Out
Ref Out Temperature 25 kΩ Between V+ and Ref Out — 80 — ppm/°C
Coefficient 0°C ≤ TA ≤ +70°C
Output High Voltage TC7109: I
TC7109A: I
Pins 3–16, 18, 19, 20
Output Low Voltage I
Output Leakage Current Pins 3–16 High Impedance — ±0.01 ±1 µA
Control I/O Pins 18, 19, 20 V
Pull-Up Current Mode Input at GND
Control I/O Loading HBEN, Pin 19; LBEN, Pin 18 — — 50 pF
Input High Voltage Pins 18–21, 26, 27 2.5 — — V
Input Low Voltage Pins 18-21, 26, 27 — — 1 V
Input Pull-Up Current Pins 26, 27; V
Input Pull-Down Current Pin 21; V
Oscillator Output Current, High V
Oscillator Output Current, Low V
Buffered Oscillator Output V
Current, High
Buffered Oscillator Output V
Current, Low
Mode Input Pulse Width 60 — — nsec
= 1.6 mA — 0.2 0.4 V
OUT
Referenced to GND
Referenced to GND
Pins 17, 24; V
= 2.5V — 1 — mA
OUT
= 2.5V — 1.5 — mA
OUT
= 2.5V — 2 — mA
OUT
= 2.5V — 5 — mA
OUT
= 100 µA 3.5 4.3 — V
OUT
= 700 µA
OUT
= V+–3V — 5 — µA
OUT
= V+–3V — 5 — µA
OUT
= V+–3V 25 µA
OUT
= GND = +3V — 1 — µA
OUT
2
3
4
5
HANDLING PRECAUTIONS: These devices are CMOS and must be handled correctly to prevent damage. Package
and store only in conductive foam, anti-static tubes, or other conducting material. Use proper anti-static handling
procedures. Do not connect in circuits under "power-on" conditions, as high transients may cause permanent
damage.
TELCOM SEMICONDUCTOR, INC.
6
7
8
3-93
TC7109
TC7109A
PIN CONFIGURATIONS
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
+
+
–
–
+
–
–
+
12
B
44 43 42 41 39 3840
B
1
11
B
2
10
B
3
9
B
4
8
B
5
7
6
NC
B
7
6
B
5
B
4
B
3
B
2
12 13 14 15 17 18
1
B
OR
TEST
POL
LBEN
STATUS
TC7109ACKW
TC7109CKW
HBEN
GND
(PQFP)
16
CE/LOAD
NC
NC
+
V
MODE
REF CAP
REF CAP
REF IN
37 36 35 34
19
20 21 22
OSC IN
OSC SEL
OSC OUT
STATUS
CE/LOAD
REF IN
33
32
31
30
29
28
27
268
259
2410
2311
BUFF
OSC OUT
GND
POL
OR
B
12
B
11
B
10
B
B
B
B
B
B
B
B
B
TEST
LBEN
HBEN
IN HI
IN LO
COMMON
INT
AZ
NC
BUFF
REF OUT
–
V
SEND
RUN/HOLD
1
2
3
4
5
6
7
9
8
9
8
7
10
6
11
12
5
13
4
14
3
2
15
1
16
17
18
19
20
B
B
10
B
B
B
NC
B
B
B
B
B
TC7109A
TC7109
(CPL, IJL,
MJL)
(PDIP)
(CerDIP)
12
OR
B
6543 1442
7
11
8
9
9
10
8
11
7
12
13
6
5
4
3
2
18 19 20 21 23 24
1
B
TEST
+
40
V
39
REF IN
38
REF CAP
37
REF CAP
36
REF IN
35
IN HI
IN LO
34
33
COMMON
32
INT
31
AZ
30
BUFF
REF OUT
29
–
28
V
27
SEND
26
RUN/HOLD
25
BUFF OSC OUT
24
OSC SEL
23
OSC OUT
22
OSC IN
21
MODE
STATUS
POL
TC7109ACLW
TC7109CLW
LBEN
HBEN
–
–
+
+
GND
(PLCC)
22
CE/LOAD
NC
NC
+
V
MODE
REF CAP
REF CAP
REF IN
43 42 41 40
25
26 27 28
OSC IN
OSC SEL
OSC OUT
REF IN
39
38
37
36
35
34
33
3214
3115
3016
2917
BUFF
OSC OUT
IN HI
IN LO
COMMON
INT
AZ
NC
BUFF
REF OUT
–
V
SEND
RUN/HOLD
3-94
NC = NO INTERNAL CONNECTION
TELCOM SEMICONDUCTOR, INC.
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGIT AL CONVERTERS
TC7109/A PIN DESCRIPTION
1
TC7109
TC7109A
40-Pin PDIP
Pin Number Symbol Description
1 GND Digital ground, 0V, ground return for all digital logic.
2 STATUS Output HIGH during integrate and deintegrate until data is latched. Output LOW
when analog section is in auto-zero or zero-integrator configuration.
3 POL Polarity — High for positive input.
4 OR Overrange — High if overranged.
5B12Bit 12 (Most Significant Bit)
6B11Bit 11
7B10Bit 10
8B
9B
10 B
11 B
12 B
13 B
14 B
15 B
16 B
17 TEST Input High — Normal operation. Input LOW — Forces all bit outputs HIGH.
18 Low-Byte Enable — With MODE (Pin 21) LOW, and CE/LOAD (Pin 20) LOW,
19 High-Byte Enable — With MODE (Pin 21) LOW, and CE/LOAD (Pin 20) LOW,
20 Chip Enable/Load — With MODE (Pin 21) LOW, CE/LOAD serves as a master
21 MODE Input LOW — Direct output mode where CE/LOAD (Pin 20), HBEN (Pin 19), and
22 OSC IN Oscillator Input
23 OSC OUT Oscillator Output
24 OSC SEL Oscillator Select — Input HIGH configures OSC IN, OSC OUT, BUF OSC OUT as
25 BUF OSC OUT Buffered Oscillator Output
26 Input HIGH — Conversions continuously performed every 8192 clock pulses.
9
8
7
6
5
4
3
2
1
LBEN
HBEN
CE/LOAD
RUN/HOLD
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 (Least Significant Bit)
Note: This input is used for test purposes only.
taking this pin LOW activates low-order byte outputs, B1–B8. With MODE (Pin 21)
HIGH, this pin serves as low-byte flag output used in handshake mode. See
Figures 7, 8, and 9.
taking this pin LOW activates high-order byte outputs, B9–B12, POL, OR. With
MODE (Pin 21) HIGH, this pin serves as high-byte flag output used in handshake
mode. See Figures 7, 8, and 9.
output enable. When HIGH, B1–B12, POL, OR outputs are disabled. When
MODE (Pin 21) is HIGH, a load strobe is used in handshake mode. See Figure 7,
8, and 9.
LBEN (Pin 18) act as inputs directly controlling byte outputs.
Input Pulsed HIGH — Causes immediate entry into handshake mode and output
of data as in Figure 9.
Input HIGH — Enables CE/LOAD (Pin 20), HBEN (Pin 19), and LBEN (Pin 18)
as outputs, handshake mode will be entered and data output as in Figures 7 and
8 at conversions completion.
RC oscillator — clock will be same phase and duty cycle as BUF OSC OUT. Input
LOW configures OSC IN, OSC OUT for crystal oscillator — clock frequency will
be 1/58 of frequency at BUF OSC OUT.
Input LOW — Conversion in progress completed; converter will stop in auto-zero
seven counts before integrate.
All Three-State Data Bits
2
3
4
5
6
7
8
TELCOM SEMICONDUCTOR, INC.
3-95
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
TC7109
TC7109A
TC7109/A PIN DESCRIPTION (Cont.)
40-Pin PDIP
Pin Number Symbol Description
27 SEND Input — Used in handshake mode to indicate ability of an external device to
accept data.
Connect to V+ if not used.
28 V
29 REF OUT Reference Voltage Output — Nominally 2.8V down from V+ (Pin 40).
30 BUFFER Buffer Amplifier Output
31 AUTO-ZERO Auto-Zero Node — Inside foil of CAZ.
32 INTEGRATOR Integrator Output — Outside foil of C
33 COMMON Analog Common — System is auto-zeroed to COMMON.
34 INPUT LOW Differential Input Low Side
35 INPUT HIGH Differential Input High Side
36 REF IN + Differential Reference Input Positive
37 REF CAP + Reference Capacitor Positive
38 REF CAP – Reference Capacitor Negative
39 REF IN – Differential Reference Input Negative
40 V
NOTE: All digital levels are positive true.
–
+
Analog Negative Supply — Nominally –5V with respect to GND (Pin 1).
.
INT
Positive Supply Voltage — Nominally +5V with respect to GND (Pin 1).
+5V
GND
+5V
5–12
GND
SERIAL
INPUT
SERIAL
OUTPUT
1
V
2
OSC CONTROL
3
GND
4
RRD
RBR1–8
13
14
15
16
20
25
CMOS UART
PE
FE
OE
SFD
RR1
TRO
6403
*
Q11
RESET
+5V
CD4040B
CLK
1011
8
15
40
TRC
OSC IN
*TBR1–8
NOTE:
17
39
EPE
38
CLS1
37
CLS2
36
SBS
35
GND
PI
34
CRL
TRE
DRR
DR
TBRL
TBRE
MR
For lowest power consumption, TBR1–TBR8 inputs
should have 100kΩ pull-up resistors to +5V.
+5V
26–33
24
18
19
23
22
21
GND
GND
6
8
1
GND
25
BUFF OSC OUT
2
STATUS
19
HBEN
3–8
B9–B12,
POL, OR
9–16
B1–B8
17
TEST
18
LBEN
21
MODE
20
CE/LOAD
27
SEND
TC7109A
V
REF IN
REF CAP
REF CAP
REF IN
IN HI
IN LO
COM
INT
AZ
BUFF
REF OUT
V
RUN/HOLD
OSC SEL
OSC OUT
OSC IN
40
+
39
–
38
–
+
37
+
36
35
34
33
32
31
30
29
28
–
26
24
23
22
+5V
1µF
1MΩ
0.01µF
C
INT
0.15µF
C
AZ
0.33µF
R
20k
INT
–5V
+5V OR OPEN
GND
100kΩΩ
3.58MHz
CRYSTAL
–
EXTERNAL
REFERENCE
+
+
INPUT
–
ANALOG
GND
0.2V
REF
1V
REF
3-96
Figure 1. TC7109A UART Interface (Send Any Word to UART to Transmit Latest Result)
TELCOM SEMICONDUCTOR, INC.
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGIT AL CONVERTERS
1
TC7109
TC7109A
+5V
GND
+5V
+5V
+5V
+5V
GND
23
1
TO
4
RESET
5
SS
6
INT
8748/8049
MICROCOMPUTER
7
EA
8
WR
9
PSEN
11
ALE
25
PROG
26
V
DD
39
TL
40
V
CC
20
GND
CMOS
XTAL2XTALI
P20–P27
P14–P17
P13
P12
P11
P10
DB0–DB7
RD
2
21–24,
35–38
31–34
30
29
28
27
12–19
10
8
5
OTHER I/O
8
40
+5V
GND
6
8
17
26
18
19
3–8
9–16
20
V
1
GND
TEST
RUN/HOLD
2
STATUS
LBEN
HBEN
B9–B12,
POL, OR
B1–B8
CE/LOAD
+
REF IN
REF CAP
REF CAP
REF IN
TC7109A
REF OUT
BUFF OSC OUT
OSC SEL
OSC OUT
IN HI
HI LO
COM
INT
AZ
BUFF
V
SEND
OSC IN
MODE
39
–
38
–
C
AZ
0.33µF
–5V
GND
1µF
1MΩ
0.01µF
C
INT
0.15µF
R
20k
10 kΩΩ
3.58MHz
CRYSTAL
37
+
36
+
35
34
33
32
31
30
29
28
–
27
25
24
23
22
21
INT
–
EXTERNAL
REFERNCE
+
+
INPUT
–
ANALOG
GND
0.2 V
REF
1 V
REF
2
3
4
Figure 2. TC7109A Parallel Interface With 8048/8049 Microcomputer
DETAILED DESCRIPTION
(All Pin Designations Refer to 40-Pin DIP)
Analog Section
The functional diagram shows a block diagram of the
analog section of the TC7109A. The circuit will perform
conversions at a rate determined by the clock frequency
(8192 clock periods per cycle), when the RUN/HOLD input
is left open or connected to V+. Each measurement cycle is
divided into four phases, as shown in Figure 3. They are:
(1) Auto-Zero (AZ), (2) Signal Integrate (INT), (3) Reference
Deintegrate (DE), and (4) Zero Integrator (ZI).
Auto-Zero Phase
The buffer and the integrator inputs are disconnected
from input high and input low and connected to analog
common. The reference capacitor is charged to the reference voltage. A feedback loop is closed around the system
to charge the auto-zero capacitor, CAZ, to compensate for
offset voltage in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the AZ
accuracy is limited only by the noise of the system. The offset
referred to the input is less than 10 µV.
Signal-Integrate Phase
The buffer and integrator inputs are removed from
common and connected to input high and input low. The
auto-zero loop is opened. The auto-zero capacitor is placed
in series in the loop to provide an equal and opposite
compensating offset voltage. The differential voltage between input high and input low is integrated for a fixed time
of 2048 clock periods. At the end of this phase, the polarity
of the integrated signal is determined. If the input signal has
no return to the converter's power supply, input low can be
tied to analog common to establish the correct commonmode voltage.
Deintegrate Phase
Input high is connected across the previously-charged
reference capacitor and input low is internally connected to
analog common. Circuitry within the chip ensures the capacitor will be connected with the correct polarity to cause
the integrator output to return to the zero crossing (established by auto-zero) with a fixed slope. The time, represented by the number of clock periods counted for the output
to return to zero, is proportional to the input signal.
5
6
7
8
TELCOM SEMICONDUCTOR, INC.
3-97
TC7109
TC7109A
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
Zero-Integrator Phase
The ZI phase only occurs when an input overrange
condition exists. The function of the ZI phase is to eliminate
residual charge on the integrator capacitor after an overrange
measurement. Unless removed, the residual charge will be
transferred to the auto-zero capacitor and cause an error in
the succeeding conversion.
The ZI phase virtually eliminates hysteresis or "cross
talk" in multiplexed systems. An overrange input on one
channel will not cause an error on the next channel measured. This feature is especially useful in thermocouple
measurements, where unused (or broken thermocouple)
inputs are pulled to the positive supply rail.
During ZI, the reference capacitor is charged to the
reference voltage. The signal inputs are disconnected from
the buffer and integrator. The comparator output is connected to the buffer input, causing the integrator output to be
driven rapidly to 0V (Figure 3). The ZI phase only occurs
following an overrange and lasts for a maximum of 1024
clock periods.
Differential Input
The TC7109A has been optimized for operation with
analog common near digital ground. With +5V and –5V
power supplies, a full ±4V full-scale integrator swing maximizes the analog section's performance.
A typical CMRR of 86 dB is achieved for input differential
voltages anywhere within the typical common-mode range
of 1V below the positive supply to 1.5V above the negative
supply. However, for optimum performance, the IN HI and IN
LO inputs should not come within 2V of either supply rail.
Since the integrator also swings with the common-mode
voltage, care must be exercised to ensure the integrator
output does not saturate. A worst-case condition is near a
full-scale negative differential input voltage with a large
positive common-mode voltage. The negative input signal
drives the integrator positive when most of its swing has
been used up by the positive common-mode voltage. In
such cases, the integrator swing can be reduced to less than
the recommended ±4V full-scale value, with some loss of
accuracy. The integrator output can swing to within 0.3V of
either supply without loss of linearity.
reference for (+) or (–) input voltages will cause a roll-over
error. This error can be held to less than 0.5 count worst case
by using a large reference capacitor in comparison to the
stray capacitance. To minimize roll-over error from these
sources, keep the reference common-mode voltage near or
at analog common.
Digital Section
The digital section is shown in the block diagram (Figure 4) and includes the clock oscillator and scaling circuit,
a 12-bit binary counter with output latches and TTL compatible three-state output drivers, UART handshake logic,
polarity, overrange, and control logic. Logic levels are referred to as LOW or HIGH.
Inputs driven from TTL gates should have 3 kΩ to 5 kΩ
pull-up resistors added for maximum noise immunity. For
minimum power consumption, all inputs should swing from
GND (LOW) to V+ (HIGH).
STATUS Output
During a conversion cycle, the STATUS output goes
HIGH at the beginning of signal integrate and goes LOW
one-half clock period after new data from the conversion has
been stored in the output latches (see Figure 3). The signal
may be used as a "data valid" flag to drive interrupts, or for
monitoring the status of the converter. (Data will not change
while status is LOW.)
MODE Input
The output mode of the converter is controlled by the
MODE input. The converter is in its "direct" output mode,
when the MODE input is LOW or left open. The output data
is directly accessible under the control of the chip and byte
enable inputs (this input is provided with a pull-down resistor
to ensure a LOW Level when the pin is left open). When the
MODE input is pulsed high, the converter enters the UART
handshake mode and outputs the data in 2 bytes, then
returns to "direct" mode. When the MODE input is kept
HIGH, the converter will output data in the handshake mode
at the end of every conversion cycle. With MODE = 0 (direct
bus transfer), the send input should be tied to V+. (See
"Handshake Mode.")
Differential Reference
The reference voltage can be generated anywhere
within the power supply voltage of the converter. Roll-over
voltage is the main source of common-mode error, caused
by the reference capacitor losing or gaining charge due to
stray capacity on its nodes. With a large common-mode
voltage, the reference capacitor can gain charge (increase
voltage) when called upon to deintegrate a positive signal
and lose charge (decrease voltage) when called upon
to deintegrate a negative input signal. This difference in
3-98
RUN/HOLD Input
With the RUN/HOLD input high, or open, the circuit
operates normally as a dual-slope ADC, as shown in Figure
3. Conversion cycles operate continuously with the output
latches updated after zero crossing in the deintegrate mode.
An internal pull-up resistor is provided to ensure a HIGH
level with an open input.
TELCOM SEMICONDUCTOR, INC.
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGIT AL CONVERTERS
1
TC7109
TC7109A
INTEGRATOR OUTPUT
FOR OVERRANGE INPUT
INTEGRATOR OUTPUT
FOR NORMAL INPUT
INTERNAL CLOCK
INTERNAL LATCH
STATUS OUTPUT
NUMBER OF COUNTS TO ZERO CROSSING
INTEGRATOR
SATURATES
AZ
PHASE I
2048
COUNTS
MIN
PROPORTIONAL TO V
Figure 3. Conversion Timing (RUN/HOLD Pin High)
PHASE II
COUNTS
INT
FIXED
2048
IN
ZI
AZ
ZERO INTEGRATOR
NO ZERO
CROSSING
ZERO CROSSING
OCCURS
ZERO CROSSING
DETECTED
DE
PHASE III
4096
COUNTS
MAX
AFTER ZERO CROSSING, ANALOG SECTION
WILL BE IN AUTO-ZERO CONFIGURATION
AZ
PHASE FORCES
INTEGRATOR
OUTPUT TO 0V
2
3
4
TO
ANALOG
SECTION
COMP OUT
AZ
INT
DE (±)
TEST17POL3OR
ZI
HIGH-ORDER
BYTE OUTPUTS
B
B
B
B
12
11
10
4
5
6
7
14 THREE-STATE OUTPUTS
CONVERSION
CONTROL
LOGIC
2262223242521
STATUS RUN/
HOLD
B
9
8
8
9
14 LATCHES
12-BIT COUNTER
OSCILLATOR
AND CLOCK
CIRCUITRY
OSCINOSC
OUT
LOW-ORDER
BYTE OUTPUTS
B
B
7
6
10
11
12
LATCH
CLOCK
OSC
BUFF
SEL
OSC
OUT
B
B
5
4
13
14
HANDSHAKE
MODE
B
3
15
LOGIC
B
2
B
1
16
27
SEND
1
GND
18
19
20
5
LBEN
HBEN
CE/LOAD
6
7
TELCOM SEMICONDUCTOR, INC.
Figure 4. Digital Section
8
3-99
TC7109
TC7109A
INTEGRATOR OUTPUT
INTERNAL CLOCK
INTERNAL LATCH
STATUS OUTPUT
RUN/HOLD INPUT
*
NOTE:
ANALOG-TO-DIGITAL CONVERTERS
AUTO-ZERO
DETERMINATED
AT ZERO CROSSING
DETECTION
RUN/HOLD input is ignored until end of auto-zero phase.
Figure 5. TC7109A RUN/HOLD Operation
PHASE I
MIN 1790 COUNTS
MAX 2041 COUNTS
*
12-BIT
STATIC IN
HOLD STATE
µP-COMPATIBLE
INT
PHASE II
7 COUNTS
The RUN/HOLD input may be used to shorten conversion time. If RUN/HOLD goes LOW any time after zero
crossing in the deintegrate mode, the circuit will jump to
auto-zero and eliminate that portion of time normally spent
in deintegrate.
If RUN/HOLD stays or goes LOW, the conversion will
complete with minimum time in deintegrate. It will stay in
auto-zero for the minimum time and wait in auto-zero for a
HIGH at the RUN/HOLD input. As shown in Figure 5, the
STATUS output will go HIGH 7 clock periods after RUN/
HOLD is changed to HIGH, and the converter will begin the
integrate phase of the next conversion.
The RUN/HOLD input allows controlled conversion interface. The converter may be held at idle in auto-zero with
RUN/HOLD LOW. The conversion is started when RUN/
HOLD goes HIGH, and the new data is valid when the
STATUS output goes LOW (or is transferred to the UART;
see "Handshake Mode"). RUN/HOLD may now go LOW,
terminating deintegrate and ensuring a minimum auto-zero
time before stopping to wait for the next conversion. Conversion time can be minimized by ensuring RUN/HOLD goes
LOW during deintegrate, after zero crossing, and goes
HIGH after the hold point is reached. The required activity on
the RUN/HOLD input can be provided by connecting it to the
buffered oscillator output. In this mode, the input value
measured determines the conversion time.
Direct Mode
The data outputs (bits 1 through 8, low-order bytes; bits
9 through 12, polarity and overrange high-order bytes) are
accessible under control of the byte and chip enable terminals as inputs with the MODE pin at a LOW level. These
three inputs are all active LOW. Internal pull-up resistors are
provided for an inactive HIGH level when left open. When
chip enable is LOW, a byte-enable input LOW will allow the
outputs of the byte to become active. A variety of parallel
data accessing techniques may be used, as shown in the
"Interfacing" section. (See Figure 6 and Table 1.)
The access of data should be synchronized with the
conversion cycle by monitoring the STATUS output. This
prevents accessing data while it is being updated and
eliminates the acquisition of erroneous data.
t
CE/LOAD
AS INPUT
HBEN
AS INPUT
LBEN
AS INPUT
HIGH-BYTE
DATA
LOW-BYTE
DATA
t
BEA
t
DAB
Figure 6. TC7109A Direct Mode Output Timing
DATA
VALID
= HIGH IMPEDANCE
t
DAB
t
DAC
CEA
DATA
VALID
DATA
VALID
t
DHC
Table 1. TC7109A Direct Mode Timing Requirements
Symbol Description Min Typ Max Units
t
BEA
t
DAB
t
DHB
t
CEA
t
DAC
t
DHC
Byte Enable Width 200 500 nsec
Data Access Time 150 300 nsec
From Byte Enable
Data Hold Time 150 300 nsec
From Byte Enable
Chip Enable Width 300 500 nsec
Data Access Time 200 400 nsec
From Chip Enable
Data Hold Time 200 400 nsec
From Chip Enable
3-100
TELCOM SEMICONDUCTOR, INC.
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
Handshake Mode
An alternative means of interfacing the TC7109A to
digital systems is provided when the handshake output
mode of the TC7109A becomes active in controlling the
flow of data instead of passively responding to chip and
byte enable inputs. This mode allows a direct interface
between the TC7109A and industry-standard UARTs with
no external logic required. The TC7109A provides all the
control and flag signals necessary to sequence the two
bytes of data into the UART and initiate their transmission
in serial form when triggered into the handshake mode.
The cost of designing remote data acquisition stations is
reduced using serial data transmission to minimize the
number of lines to the central controlling processor.
The MODE input controls the handshake mode. When
the MODE input is held HIGH, the TC7109A enters the
handshake mode after new data has been stored in the
output latches at the end of every conversion performed
(see Figures 7 and 8). Entry into the handshake mode may
be triggered on demand by the MODE input. At any time
during the conversion cycle, the LOW-to-HIGH transition of
a short pulse at the MODE input will cause immediate entry
into the handshake mode. If this pulse occurs while new
data is being stored, the entry into handshake mode is
delayed until the data is stable. The MODE input is ignored
in the handshake mode, and until the converter completes
the output cycle and clears the handshake mode, data
updating will be inhibited (see Figure 9).
When the MODE input is HIGH or when the converter
enters the handshake mode, the chip and byte enable
inputs become TTL-compatible outputs which provide the
output cycle control signals (see Figures 7, 8 and 9).
The SEND input is used by the converter as an indication of the ability of the receiving device (such as a UART)
to accept data in the handshake mode. The sequence of
the output cycle with SEND held HIGH is shown in Figure
7. The handshake mode (internal MODE HIGH) is entered
after the data latch pulse (the CE/LOAD, LBEN and HBEN
terminals are active as outputs since MODE remains HIGH).
The HIGH level at the SEND input is sensed on the
same HIGH-to-LOW internal clock edge. On the next LOWto-HIGH internal clock edge, the high-order byte (bits 9
through 12, POL, and OR) outputs are enabled and the CE/
LOAD and the HBEN outputs assume a LOW level. The
CE/LOAD output remains LOW for one full internal clock
period only; the data outputs remain active for 1-1/2 internal clock periods; and the high-byte enable remains LOW
for 2 clock periods. The CE/LOAD output LOW level or
LOW-to-HIGH edge may be used as a synchronizing signal to ensure valid data, and the byte enable as an output
may be used as a byte identification flag. With SEND
TC7109
TC7109A
remaining HIGH the converter completes the output cycle
using CE/LOAD and LBEN while the low-order byte outputs (bits 1 through 8) are activated. When both bytes are
sent, the handshake mode is terminated. The typical UART
interfacing timing is shown in Figure 8. The SEND input is
used to delay portions of the sequence, or handshake, to
ensure correct data transfer. This timing diagram shows an
industry-standard HD6403 or CDP1854 CMOS UART to
interface to serial data channels. The SEND input to the
TC7109A is driven by the TBRE (Transmitter Buffer Register Empty) output of the UART, and the CE/LOAD input of
the TC7109A drives the TBRL (Transmitter Buffer Register
Load) input to the UART. The eight transmitter buffer register inputs accept the parallel data outputs. With the UART
transmitter buffer register empty, the SEND input will be
HIGH when the handshake mode is entered after new data
is stored. The high-order byte outputs become active and
the CE/LOAD and HBEN inputs will go LOW after SEND is
sensed. When CE/LOAD goes HIGH at the end of one
clock period, the high-order byte data is clocked into the
UART transmitter buffer register. The UART TBRE output
will go LOW, which halts the output cycle with the HBEN
output LOW, and the high-order byte outputs active. When
the UART has transferred the data to the transmitter register and cleared the transmitter buffer register, the TBRE
returns HIGH. The high-order byte outputs are disabled on
the next TC7109A internal clock HIGH-to-LOW edge, and
one-half internal clock later, the HBEN output returns HIGH.
The CE/LOAD and LBEN outputs go LOW at the same
time as the low-order byte outputs become active. When
the CE/LOAD returns HIGH at the end of one clock period,
the low-order data is clocked into the UART transmitter
buffer register, and TBRE again goes LOW. The next
TC7109A internal clock HIGH-to-LOW edge will sense
when TBRE returns to a HIGH, disabling the data inputs.
One-half internal clock later, the handshake mode is cleared,
and the CE/LOAD, HBEN and LBEN terminals return
HIGH and stay active, if MODE still remains HIGH.
Handshake output sequences may be performed on
demand by triggering the converter into handshake mode
with a LOW-to-HIGH edge on the MODE input. A handshake output sequence triggered is shown in Figure 9. The
SEND input is LOW when the converter enters handshake
mode. The whole output sequence is controlled by the
SEND input, and the sequence for the first (high order) byte
is similar to the sequence for the second byte.
Figure 9 also shows that the output sequence can take
longer than a conversion cycle. New data will not be latched
when the handshake mode is still in progress and is therefore lost.
1
2
3
4
5
6
7
8
TELCOM SEMICONDUCTOR, INC.
3-101
TC7109
TC7109A
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
INTEGRATOR
OUTPUT
INTERNAL CLOCK
INTERNAL LATCH
STATUS OUTPUT
MODE INPUT
INTERNAL MODE
SEND INPUT
CE/LOAD
HBEN
HIGH-BYTE DATA
LBEN
LOW-BYTE DATA
UART
NORM
ZERO CROSSING OCCURS
ZERO CROSSING DETECTED
MODE HIGH ACTIVATES
CE/LOAD, HBEN, LBEN
= DON'T CARE
SEND SENSED SEND SENSED
DATA VALID
DATA VALID
THREE-STATE
=
HIGH IMPEDANCE
THREE-STATE
=
WITH PULL-UP
TERMINATES
UART MODE
MODE LOW,
NOT IN
HANDSHAKE
MODE
DISABLES
OUTPUTS
CE/LOAD,
HBEN,
LBEN
INTEGRATOR OUTPUT
INTERNAL CLOCK
INTERNAL LATCH
STATUS OUTPUT
MODE INPUT
INTERNAL MODE
SEND INPUT (UART TBRE)
CE/LOAD OUTPUT (UART TBRL)
HBEN
HIGH-BYTE DATA
LBEN
LOW-BYTE DATA
Figure 7. TC7109A Handshake With SEND INPUT Held Positive
ZERO CROSSING OCCURS
ZERO CROSSING DETECTED
UART
NORM
SEND
SENSED
DATA VALID
SEND
SENSED
DATA VALID
SEND
SENSED
TERMINATES
UART MODE
3-102
= DON'T CARE
Figure 8. TC7109A Handshake — Typical UART Interface Timing
=
THREE-STATE HIGH IMPEDANCE
TELCOM SEMICONDUCTOR, INC.
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
POSITIVE TRANSITION
CAUSES ENTRY INTO
UART MODE
INTERNAL CLOCK
INTERNAL LATCH
STATUS OUTPUT
STATUS OUTPUT UNCHANGED
IN UART MODE
DE PHASE III
ZERO CROSSING OCCURS
ZERO CROSSING DETECTED
LATCH PULSE INHIBITED
IN UART MODE
1
TC7109
TC7109A
2
MODE INPUT
INTERNAL MODE
SEND INPUT
CE/LOAD AS OUTPUT
HIGH-BYTE DATA
LOW-BYTE DATA
HBEN
LBEN
UART
NORM
SEND
SENSED
DATA VALID
= DON'T CARE
Figure 9. TC7109A Handshake Triggered by MODE Input
=
Oscillator
The oscillator may be overdriven, or may be operated as
an RC or crystal oscillator. The OSCILLATOR SELECT
input optimizes the internal configuration of the oscillator for
RC or crystal operation. The OSCILLATOR SELECT input
is provided with a pull-up resistor. When the OSCILLATOR
SELECT input is HIGH or left open, the oscillator is configured for RC operation. The internal clock will be the same
frequency and phase as the signal at the BUFFERED
OSCILLATOR OUTPUT. Connect the resistor and capacitor as in Figure 10. The circuit will oscillate at a frequency
given by f = 0.45/RC. A 100 kΩ resistor is recommended for
useful ranges of frequency. The capacitor value should be
chosen such that 2048 clock periods are close to an integral
multiple of the 60 Hz period for optimum 60 Hz line rejection.
With OSCILLATOR SELECT input LOW, two on-chip
capacitors and a feedback device are added to the oscillator.
In this configuration, the oscillator will operate with most
crystals in the 1 to 5 MHz range with no external components
(Figure 11). The OSCILLATOR SELECT input LOW inserts
TERMINATES
SEND
SENSED
DATA VALID
THREE-STATE
HIGH IMPEDANCE
a fixed 458 divider circuit between the BUFFERED OSCILLATOR OUTPUT and the internal clock. A 3.58 MHz TV
crystal gives a division ratio providing an integration time
given by:
t = (2048 clock periods) = 33.18 ms
The error is less than 1% from two 60 Hz periods, or
33.33 ms, which will give better than 40 dB, 60 Hz rejection.
The converter will operate reliably at conversion rates up
to 30 per second, corresponding to a clock frequency of
245.8 kHz.
When the oscillator is to be overdriven, the OSCILLA-
TOR OUTPUT should be left open, and the overdriving
signal should be applied at the OSCILLATOR INPUT. The
internal clock will be of the same duty cycle, frequency and
phase as the input signal. When the OSCILLATOR SELECT
is at GND, the clock will be 1/58 of the input frequency.
SEND
SENSED
THREE-STATE
=
WITH PULL-UP
3.58 MHz
UART MODE
58
3
4
5
6
7
TELCOM SEMICONDUCTOR, INC.
8
3-103
TC7109
TC7109A
24
OSC
SEL
+
V OR OPEN
+
V
22
OSC
IN
f = 0.45/RC
OSC
Figure 10. TC7109A RC Oscillator
23
OSC
OUT
R
C
25
BUFFERED
OSC OUT
CLOCK
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
roll-over errors will be slightly worse than in the ±4V case.
For large common-mode voltage ranges, the integrator
output swing must be reduced further. This will increase both
noise and roll-over errors. To improve performance, ±6V
supplies may be used.
Integrating Capacitor
The integrating capacitor, C
give the maximum integrator output voltage swing that will
not saturate the integrator to within 0.3V from either supply.
A ±3.5V to ±4V integrator output swing is nominal for the
TC7109A, with ±5V supplies and analog common connected to GND. For 7-1/2 conversions per second (61.72
kHz internal clock frequency), nominal values C
are 0.15 µF and 0.33 µF, respectively. These values should
be changed if different clock frequencies are used to maintain the integrator output voltage swing. The value of C
given by:
, should be selected to
INT
and C
INT
INT
AZ
is
÷
58
GND
24
22
OSC
OSC
SEL
IN
CRYSTAL
Figure 11. TC7109A Crystal Oscillator
23
OSC
OUT
25
BUFFERED
OSC OUT
Test Input
The counter and its outputs may be tested easily. When
the TEST input is connected to GND, the internal clock is
disabled and the counter outputs are all forced into the HIGH
state. When the input returns to the 1/2 (V+–GND) voltage or
to V+ and one clock is input, the counter outputs will all be
clocked to the LOW state.
The counter output latches are enabled when the TEST
input is taken to a level halfway between V+ and GND,
allowing the counter contents to be examined anytime.
Component Value Selection
The integrator output swing for full-scale should be as
large as possible. For example, with ±5V supplies and
COMMON connected to GND, the nominal integrator output
swing at full-scale is ±4V. Since the integrator output can go
to 0.3V from either supply without significantly effecting
linearity, a 4V integrator output swing allows 0.7V for variations in output swing due to component value and oscillator
tolerances. With ±5V supplies and a common-mode voltage
range of ±1V required, the component values should be
selected to provide ±3V integrator output swing. Noise and
C
(2048 3 Clock Period) (20 µA)
=
INT
Integrator Output Voltage Swing
The integrating capacitor must have low dielectric absorption to prevent roll-over errors. Polypropylene capacitors give undetectable errors, at reasonable cost, up to
+85°C. Teflon® capacitors are recommended for the military
temperature range. While their dielectric absorption characteristics vary somewhat between units, devices may be
selected to less than 0.5 count of error due to dielectric
absorption.
Integrating Resistor
The integrator and buffer amplifiers have a class A
output stage with 100 µA of quiescent current. They supply
20 µA of drive current with negligible nonlinearity. The
integrating resistor should be large enough to remain in this
very linear region over the input voltage range, but small
enough that undue leakage requirements are not placed on
the PC board. For 2.048V full-scale a 100 kΩ resistor is
recommended and for 409.6 mV full-scale a 20 kΩ resistor
is recommended. R
may be selected for other values of
INT
full scale by:
R
Full-Scale Voltage
=
INT
20 µA
Auto-Zero Capacitor
As the auto-zero capacitor is made large, the system
noise is reduced. Since the TC7109A incorporates a zero
integrator cycle, the size of the auto-zero capacitor does not
affect overload recovery. The optimal value of the auto-zero
capacitor is between 2 and 4 times C
. A typical value for
INT
CAZ is 0.33 µF.
3-104
TELCOM SEMICONDUCTOR, INC.
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
1
TC7109
TC7109A
The inner foil of CAZ should be connected to pin 31 and
the outer foil to the RC summing junction. The inner foil of
C
should be connected to the RC summing junction and
INT
the outer foil to pin 32 for best rejection of stray pickups. For
low leakage at temperatures above +85°C, use Teflon
capacitors.
Reference Capacitor
A 1 µF capacitor is recommended for most circuits.
However, where a large common-mode voltage exists, a
larger value is required to prevent roll-over error (e.g., the
reference low is not analog common), and a 409.6 mV scale
is used. The roll-over error will be held to 0.5 count with a 10
µF capacitor. For temperatures above +80°C use Teflon or
equivalent capacitors for their low leakage characteristics.
Reference Voltage
To generate full-scale output of 4096 counts, the analog
input required is VIN = 2 V
a reference of 204.8 mV. In many applications, where the
ADC is connected to a transducer, a scale factor will exist
between the input voltage and the digital reading. For
instance, in a measuring system, the designer might like to
have a full-scale reading when the voltage for the transducer
is 700 mV. Instead of dividing the input down to 409.6 mV,
the designer should use the input voltage directly and select
V
= 350 mV. Suitable values for integrating resistor and
REF
capacitor would be 34 kΩ and 0.15 µF. This makes the
system slightly quieter and also avoids a divider network on
the input. Another advantage of this system occurs when
temperature and weight measurements with an offset or tare
are desired for non-zero input. The offset may be introduced
by connecting the voltage output of the transducer between
common and analog high, and the offset voltage between
common and analog low, observing polarities carefully. In
processor-based systems using the TC7109A, it may be
more desirable to use software and perform this type of
scaling or tare subtraction digitally.
Reference Sources
A major factor in the absolute accuracy of the ADC is the
stability of the reference voltage. The 12-bit resolution of the
TC7109A is one part in 4096, or 244 ppm. Thus, for the onboard reference temperature coefficient of 70 ppm/°C, a
temperature difference of 3°C will introduce a one-bit absolute error. Where the ambient temperature is not controlled,
or where high-accuracy absolute measurements are being
made, it is recommended that an external high-quality
reference be used.
. For 409.6 mV full scale, use
REF
A reference output (pin 29) is provided which may be
used with a resistive divider to generate a suitable reference
voltage (20 mA may be sunk without significant variation in
output voltage). A pull-up bias device is provided which
sources about 10 µA. The output voltage is nominally 2.8V
below V+. When using the on-board reference, REF OUT
(pin 29) should be connected to REF– (pin 39), and REF
should be connected to the wiper of a precision potentiometer between REF OUT and V+. The test circuit shows the
circuit for a 204.8 mV reference, generated by a 2 kΩ
precision potentiometer in series with a 24 kΩ fixed resistor.
Interfacing
Direct Mode
Combinations of chip-enable and byte-enable control
signals which may be used when interfacing the TC7109A
to parallel data lines are shown in Figure 12. The CE/LOAD
input may be tied low, allowing either byte to be controlled
by its own enable (Figure 12A). Figure 12B shows the
HBEN and LBEN as flag inputs, and CE/LOAD as a master
enable, which could be the READ strobe available from
most microprocessors. Figure 12C shows a configuration
where the two byte enables are connected together. The
CE/LOAD is a chip enable, and the HBEN and LBEN may
be used as a second chip enable, or connected to ground.
The 14 data outputs will be enabled at the same time. In
the direct MODE, SEND should be tied to V+.
Figure 13 shows interfacing several TC7109A's to a
bus, ganging the HBEN and LBEN signals to several converters together, and using the CE/LOAD input to select
the desired converter.
Figures 14–19 give practical circuits utilizing the parallel three-state output capabilities of the TC7109A. Figure
14 shows parallel interface to the Intel MCS-48, -80 and 85 systems via an 8255 PPI, where the TC7109A data
outputs are active at all times. The 8155 I/O ports may be
used in an identical manner. This interface can be used in a
read-after-update sequence, as shown in Figure 15. The
data is accessed by the high-to-low transition of the STATUS driving an interrupt to the microprocessor.
The RUN/HOLD input is also used to initiate conversions under software control. Figure 16 gives an interface
to Motorola MC6800 or MOS Technology MCS650X system.
An interrupt is generated through the Control Register
B, CB1 line from the high-to-low transition of the STATUS
output. The RUN/HOLD pin is controlled by CB2 through
Control Register B, allowing software control of conversions.
2
+
3
4
5
6
7
TELCOM SEMICONDUCTOR, INC.
8
3-105
TC7109
TC7109A
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
Direct interfacing to most microprocessor busses is
easily accomplished through the three-state output of the
TC7109A.
Figures 1, 17 and 18 are typical connection diagrams.
To ensure requirements for setup and hold times, minimum
met, it is necessary to carefully consider the system timing
in this type of interface. This type of interface is used when
the memory peripheral address density is low, providing
simple address decoding. Interrupt handling can be simplified by using an interface to reduce the component count.
pulse widths, and the drive limitations on long busses are
GND
A. B. C.
MODE CE/LOAD
B9–B12
POL, OR
6
GND
TC7109A
ANALOG
IN
B1–B8
RUN/HOLD
LBENHBEN
CONTROL
8
CONVERT
Figure 12. Direct Mode Chip and Byte Enable Combinations
ANALOG
IN
GND OR
CHIP SELECT 2
CHIP SELECT 1
MODE CE/LOAD
B1–B12
POL, OR
TC7109A
RUN/HOLD
LBENHBEN
14
CONVERT
GND
ANALOG
IN
CHIP SELECT
MODE CE/LOAD
B9–B12
POL, OR
TC7109A
B1–B8
RUN/HOLD
LBENHBEN
BYTE FLAGS
6
8
CONVERT
GND
ANALOG
MODE CE/LOAD
TC7109A
IN
CONVERTER
SELECT
B9–B12
POL, OR
B1–B8
RUN/HOLD
LBENHBEN
BYTE SELECT FLAGS
6
8
+5V
Figure 13. Three-Stating Several TC7109A's to a Small Bus
GND
ANALOG
IN
CONVERTER
SELECT
MODE CE/LOAD
B9–B12
POL, OR
TC7109A
B1–B8
RUN/HOLD
LBENHBEN
CONVERTER
SELECT
GND
MODE CE/LOAD
6
B9–B12
POL, OR
6
TC7109A
8
+5V
ANALOG
IN
B1–B8
RUN/HOLD
LBENHBEN
8
+5V
3-106
TELCOM SEMICONDUCTOR, INC.
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
1
TC7109
TC7109A
GND
ANALOG
GND
ADDRESS BUS
2
CONTROL BUS
DATA BUS
3
MODE CE/LOAD
B9–B12
IN
TC7109A
POL, OR
RUN/HOLD
B1–B8
STATUS
LBENHBEN
Figure 14. Full-Time Parallel Interface to MCS-48, -80, -85 Microcomputers
6
+5V
8
SEE TEXT
RD WR D7–D0
PA5–PA0
8255
PB7–PB0
PC5
(MODE 0)
A0–A1
CS
87C48
8008, 8080,
8085, 8048, ETC.
4
GND
ANALOG
GND
5
ADDRESS BUS
CONTROL BUS
DATA BUS
6
MODE CE/LOAD
B9–B12
POL, OR
IN
TC7109A
RUN/HOLD
B1–B8
STATUS
LBENHBEN
6
8
STB
1µF
10kΩ
+5V
(SEE TEXT)
A
RD WR D7–D0
PA5–PA0
PC6
PB7–PB0
PC4
8255
A0–A1
CS
INTR
PC6 INTR
87C48
8008, 8080,
8085, 8048, ETC.
A
7
Figure 15. Full-Time Parallel Interface to MCS-48, -80, -85 Microcomputers With Interrupt
TELCOM SEMICONDUCTOR, INC.
8
3-107
TC7109
TC7109A
ANALOG
IN
GND
MODE
TC7109A
CE/
LOAD
B9–B12
POL, OR
B1–B8
RUN/HOLD CB1
STATUS
LBEN
HBEN
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
PA–5
6
CRB - -11R-01
PB–7
8
CB2
MC6820
MC6800
OR
MCS650X
GND
ADDRESS
BUS
Figure 16. Full-Time Parallel Interface to MC6800 or MCS650X Microprocessor
ADDRESS BUS
A15A14
CONTROL BUS
RD
*
DATA BUS
LBEN
B9–B12
POL, OR
B1–B8
6
8
ANALOG
HBEN
IN
TC7109A
DATA
BUS
8008, 8080, 8085
CONTROL
BUS
3-108
CE/LOAD
RUN/HOLDMODE
+5VGND
Figure 17. TC7109A Direct Interface to 8080/8085
* MEMR or IOR for 8080/8228 system.
TELCOM SEMICONDUCTOR, INC.
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
1
TC7109
TC7109A
ANALOG
GND
+5V
2
MODE
IN
TC7109A
RUN/HOLD
CE/LOAD
B9–B12
POL, OR
B1–B8
HBEN
LBEN
6
8
74C42
74C30
A0–A2
A15–A10
R/W, VMA
ADDRESS
BUS
DATA
BUS
CONTROL
BUS
MC6800
OR
MCS650X
3
4
Figure 18. TC7109A Direct Interface to MC6800 Bus
ADDRESS BUS
ANALOG
IN
TC7109A
CONTROL BUS
DATA BUS
A
A
PA7–PA0
PC4
PC5
PC
PC6
PC7
RD WR D7–D0
8255
(MODE 1)
B9–B12
POL, OR
B1–B8
CE/LOAD
SEND
RUN/HOLD
MODE
Figure 19. TC7109A Handshake Interface to MCS-48, -80, -85 Microcomputers
6
8
STB
IBF
A0–A1
CS
PC3
INTR
5
6
87C48
8008, 8080,
8085, 8048, ETC.
7
TELCOM SEMICONDUCTOR, INC.
8
3-109
TC7109
TC7109A
Handshake Mode
The handshake mode provides an interface to a wide
variety of external devices. The byte enables may be used
as byte identification flags or as load enables and external
latches may be clocked by the rising edge of CE/LOAD. A
handshake interface to Intel microprocessors using an 8255
PPI is shown in Figure 19. The handshake operation with
the 8255 is controlled by inverting its Input Buffer Full (IBF)
flag to drive the SEND input to the TC7109A, and using the
CE/LOAD to drive the 8255 strobe. The internal control
register of the PPI should be set in MODE 1 for the port
used. If the 8255 IBF flag is LOW and the TC7109A is in
handshake mode, the next word will be strobed into the
port. The strobe will cause IBF to go HIGH (SEND goes
LOW), which will keep the enabled byte outputs active. The
PPI will generate an interrupt which, when executed, will
result in the data being read. The IBF will be reset LOW
when the byte is read, causing the TC7109A to sequence
into the next byte. The MODE input to the TC7109A is
connected to the control line on the PPI.
The data from every conversion will be sequenced in
two bytes in the system, if this output is left HIGH, or tied
HIGH separately. (The data access must take less time
than a conversion.) The output sequence can be obtained
on demand if this output is made to go from LOW to HIGH
and the interrupt may be used to reset the MODE bit.
Conversions may be obtained on command under software control by driving the RUN/HOLD input to the TC7109A
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
by a bit of the 8255. Another peripheral device may be
serviced by the unused port of the 8255. The 8155 may be
used in a similar manner. The MCS650X microprocessors
are shown in Figure 20 with MODE and RUN/HOLD tied
HIGH to save port outputs.
The handshake mode is particularly useful for directly
interfacing to industry-standard UARTs (such as Western
Digital TR1602), providing a means of serially transmitting
converted data with minimum component count.
A typical UART connection is shown in Figure 1. In this
circuit, any word received by the UART causes the UART
DR (Data Ready) output to go HIGH. The MODE input to
the TC7109A goes HIGH, triggering the TC7109A into
handshake mode. The high-order byte is output to the
UART and when the UART has transferred the data to the
Transmitter register, TBRE (SEND) goes HIGH again, LBEN
will go HIGH, driving the UART DRR (Data Ready Reset)
which will signal the end of the transfer of data from the
TC7109A to the UART.
An extension of the typical connection to several
TC7109A's with one UART is shown in Figure 21. In this
circuit, the word received by the UART (available at the
RBR outputs when DR is HIGH) is used to select which
converter will handshake with the UART. Up to eight
TC7109A's may interface with one UART, with no external
components. Up to 256 converters may be accessed on
one serial line with additional components.
ANALOG
3-110
+5V
MODE
IN
LBEN
RUN/HOLD
CRA - -100-01
TC7109A
CE/LOAD CA1
SEND
HBEN
Figure 20. TC7109A Handshake Interface to MCS-6800, MCS650X Microprocessors
PA0–PA7
CA2
MC6820
ADDRESS
BUS
DATA
BUS
CONTROL
BUS
MC6800
OR
MCS650X
TELCOM SEMICONDUCTOR, INC.
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
1
TC7109
TC7109A
ANALOG
IN
CE/
LOAD
TC7109A
RUN/HOLD
SENDMODE
B9–B12
POL, OR
B1-B8
LBENHBEN
SERIAL OUTPUT
6402 CMOS UART
TBRL DRR
6
8
Figure 21. Handshake Interface for Multiplexed Converters
TBRE RBR1–RBR8 SFD TBR1–TBR8
23
8-BIT DATA BUS
SENDMODE
CE/
LOAD
B9–B12
POL, OR
RUN/HOLD
LBENHBEN
+5V
ANALOG
IN
TC7109A
GND
B1–B8
SERIAL INPUT
6
8
+5V
ANALOG
2
3
SENDMODE
CE/
LOAD
B9–B12
POL, OR
IN
B1–B8
TC7109A
RUN/HOLD
LBENHBEN
6
8
+5V
4
5
Integrating Converter Features
The output of integrating ADCs represents the integral,
or average, of an input voltage over a fixed period of time.
Compared with techniques in which the input is sampled and
held, the integrating converter averages the effects of noise.
A second important characteristic is that time is used to
quantize the answer, resulting in extremely small nonlinearity
errors and no missing output codes. The integrating converter also has very good rejection of frequencies whose
periods are an integral multiple of the measurement period.
This feature can be used to advantage in reducing line
frequency noise (Figure 22).
30
t = MEASUREMENT
PERIOD
20
10
0
NORMAL MODE REJECTION PLAN
0.1/t 1/t 10/t
INPUT FREQUENCY
Figure 22. Normal Mode Rejection of Dual-Slope Converter as a
Function of Frequency
6
7
8
TELCOM SEMICONDUCTOR, INC.
3-111
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