■ Low Power Operation..................................... 10mW
ORDERING INFORMATION
PART CODETC710X X X XXX
6 = LCD
7 = LED
A or blank*
R (reversed pins) or blank (CPL pkg only)
}
GENERAL DESCRIPTION
The TC7106A and TC7107A 3-1/2 digit direct-display
drive analog-to-digital converters allow existing 7106/7107
based systems to be upgraded. Each device has a precision reference with a 20ppm/°C max temperature coefficient. This represents a 4 to 7 times improvement over
similar 3-1/2 digit converters. Existing 7106 and 7107 based
systems may be upgraded without changing external passive component values. The TC7107A drives common
anode light emitting diode (LED) displays directly with 8mA
per segment. A low-cost, high-resolution indicating meter
requires only a display, four resistors, and four capacitors.
The TC7106A low power drain and 9V battery operation
make it suitable for portable applications.
The TC7106A/TC7107A reduces linearity error to less
than 1 count. Rollover error – the difference in readings for
equal magnitude but opposite polarity input signals – is
below ±1 count. High impedance differential inputs offer
1pA leakage current and a 10
differential reference input allows ratiometric measurements
for ohms or bridge transducer measurements. The
15µV
noise performance guarantees a “rock solid” read-
P–P
ing. The auto-zero cycle guarantees a zero display reading with a zero-volts input.
12
Ω input impedance. The
* "A" parts have an improved reference TC
Package Code (see below):
PackageTemperature
CodePackagePin LayoutRange
CKW44-Pin PQFPFormed Leads0°C to +70°C
CLW44-Pin PLCC—0°C to +70°C
CPL40-Pin PDIPNormal0°C to +70°C
IPL40-Pin PDIPNormal– 25°C to +85°C
IJL40-Pin CerDIPNormal– 25°C to +85°C
“C” Devices............................................0°C to +70°C
“I” Devices ........................................– 25°C to +85°C
Storage Temperature ............................ – 65°C to +150°C
Lead Temperature (Soldering, 10 sec) ................. +300°C
*Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
–
–
+
ELECTRICAL CHARACTERISTICS (Note 3)
TC7106/A & TC7107/A
ParametersTest ConditionsMinTypMaxUnit
Zero Input ReadingVIN = 0.0 V– 000.0±000.0+000.0Digital
Full-Scale = 200.0mVReading
Ratiometric ReadingVIN = V
Roll-Over Error (Difference inV
Reading for Equal Positive and
Negative Reading Near Full-Scale)
Linearity (Max. Deviation FromFull-Scale = 200mV– 1±0.2+1Counts
Best Straight Line Fit)or Full-Scale = 2.000 V
Common-ModeV
Rejection Ratio (Note 4)Full Scale = 200.0 mV
Noise (Pk – Pk Value NotV
Exceeded 95% of Time)Full-Scale = 200.0mV
Leakage Current @ InputVIN = 0 V—110pA
Zero Reading DriftV
Scale FactorVIN = 199.0mV,
Temperature Coefficient“C” Device = 0°C to +70°C—15ppm/°C
Supply Current (Does NotVIN = 0—0.81.8mA
Include LED Current For TC7107/A)
Analog Common Voltage25kΩ Between Common2.73.053.35V
(With Respect to Pos. Supply)and Pos. Supply
Temp. Coeff. of25kΩ Between Common
Analog Commonand Pos. Supply
(With Respect0°C ≤ T
to Pos. Supply)("C", Commercial Temp. Range Devices)7106/780—ppm/°C
Temp. Coeff. of25kΩ Between Common
Analog Commonand Pos. Supply
(With Respect– 25°C ≤ T
to Pos. Supply)(“I,” Industrial Temp. Range Devices)
TC7106A ONLY Pk – PkV+ to V– = 9V456V
Segment Drive Voltage (Note 5)
TC7106A ONLY Pk – PkV+ to V– = 9V456V
Backplane Drive Voltage (Note 5)
TC7107A ONLYV+ = 5.0V58.0—mA
Segment Sinking Current (Except Pin 19)Segment Voltage = 3V
TC7107A ONLYV
Segment Sinking Current (Pin 19)Segment Voltage = 3V
NOTES: 1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA.
2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
3. Unless otherwise noted, specifications apply to both the TC7106/A and TC7107/A at TA = 25°C, f
circuit of Figure 1.
4. Refer to “Differential Input” discussion.
5. Backplane drive is in phase with segment drive for “OFF” segment, 180° out of phase for “ON” segment. Frequency is 20 times
conversion rate. Average DC component is less than 50mV.
30(11)V
31(10)V
32(9) ANALOGThis pin is primarily used to set the analog common-mode voltage
33(8)C
+
1
1
1
1
1
1
1
2
2
2
2
2
2
3
3
3
3
4
GND
3
3
3
2
–
INT
BUFF
AZ
–
IN
+
IN
COMMON
–
REF
Positive supply voltage.
Activates the D section of the units display.
Activates the C section of the units display.
Activates the B section of the units display.
Activates the A section of the units display.
Activates the F section of the units display.
Activates the G section of the units display.
Activates the E section of the units display.
Activates the D section of the tens display.
Activates the C section of the tens display.
Activates the B section of the tens display.
Activates the A section of the tens display.
Activates the F section of the tens display.
Activates the E section of the tens display.
Activates the D section of the hundreds display.
Activates the B section of the hundreds display.
Activates the F section of the hundreds display.
Activates the E section of the hundreds display.
Activates both halves of the 1 in the thousands display.
Digital ground (TC7107A).
Activates the G section of the hundreds display.
Activates the A section of the hundreds display.
Activates the C section of the hundreds display.
Activates the G section of the tens display.
Negative power supply voltage.
Integrator output. Connection point for integration capacitor. See
INTEGRATING CAPACITOR section for more details
Integration resistor connection. Use a 47kΩ resistor for a 200mV full-
scale range and a 470kΩ resistor for 2V full-scale range.
The size of the auto-zero capacitor influences system noise. Use a
0.47µF capacitor for 200mV full scale, and a 0.047µF capacitor for
2V full scale. See Paragraph on AUTO-ZERO CAPACITOR for more
details.
The analog LOW input is connected to this pin.
The analog HIGH input signal is connected to this pin.
for battery operation or in systems where the input signal is
referenced to the power supply. It also acts as a reference voltage
source. See paragraph on ANALOG COMMON for more details.
A 0.1µF capacitor is used in most applications. If a large commonmode voltage exists (for example, the V
common), and a 200mV scale is used, a 1µF capacitor is recommended and will hold the roll-over error to 0.5 count.
See pin 36.
The analog input required to generate a full-scale output (1999
counts). Place 100mV between pins 35 and 36 for 199.9mV
full-scale. Place 1V between pins 35 and 36 for 2V full scale. See
paragraph on REFERENCE VOLTAGE.
and the display should read –1888. It may also be used as a negative
supply for externally-generated decimal points. See paragraph under
TEST for additional information.
3
2
1
See pin 40.
See pin 40.
Pins 40, 39, 38 make up the oscillator section. For a 48kHz clock
(3 readings per section), connect pin 40 to the junction of a 100kΩ
resistor and a 100pF capacitor. The 100kΩ resistor is tied to pin 39
and the 100pF capacitor is tied to pin 38.
3-1/2 Digit A/D Converters
–
pin is not at analog
IN
+
) all segments will be turned on
General Theory of Operation
Dual Slope Conversion Principles
(All Pin Designations Refer to the 40-Pin DIP)
The TC7106A and TC7107A are dual slope, integrating
analog-to-digital converters. An understanding of the dual
slope conversion technique will aid in following the detailed
operation theory.
The conventional dual slope converter measurement
cycle has two distinct phases:
•Input Signal Integration
•Reference Voltage Integration (Deintegration)
The input signal being converted is integrated for a fixed
time period (TSI). Time is measured by counting clock
pulses. An opposite polarity constant reference voltage is
then integrated until the integrator output voltage returns to
zero. The reference integration time is directly proportional
to the input signal (TRI). (Figure 2A).
In a simple dual slope converter a complete conversion
requires the integrator output to “ramp-up” and “ramp-
down.”
A simple mathematical equation relates the input signal,
reference voltage and integration time:
The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values as long as they are
stable during a measurement cycle. An inherent benefit is
noise immunity. Noise spikes are integrated or averaged to
zero during the integration periods. Integrating ADCs are
immune to the large conversion errors that plague successive approximation converters in high-noise environments.
Interfering signals with frequency components at multiples
of the averaging period will be attenuated. Integrating ADCs
commonly operate with the signal integration period set to a
multiple of the 50/60Hz power line period. (Figure 2B)
30
20
10
NORMAL MODE REJECTION (dB)
0
0.1/T1/T10/T
Figure 2B. Normal-Mode Rejection of Dual Slope Converter
T = MEASUREMENT PERIOD
INPUT FREQUENCY
ANALOG SECTION
In addition to the basic signal integrate and deintegrate
cycles discussed, the circuit incorporates an auto-zero
cycle. This cycle removes buffer amplifier, integrator, and
comparator offset voltage error terms from the conversion.
A true digital zero reading results without adjusting external
potentiometers. A complete conversion consists of three
cycles: an auto-zero, signal-integrate and reference-integrate cycle.
Signal Integrate Cycle
When the auto-zero loop is opened, the internal differential inputs connect to V
signal is integrated for a fixed time period. The signal
integration period is 1000 counts. The externally set clock
frequency is divided by four before clocking the internal
counters. The integration time period is:
TSI = x 1000
where: f
= External Clock Frequency
OSC
The differential input voltage must be within the device
common-mode range (1V of either supply) when the converter and measured system share the same power supply
common (ground). If the converter and measured system do
not share the same power supply common, V
tied to analog common.
Polarity is determined at the end of the signal integrate
phase. The sign bit is a true polarity indication in that signals
less than 1 LSB are correctly determined. This allows
precision null detection, limited only by device noise and
auto-zero residual offsets.
+
and V
IN
4
f
OSC
–
. The differential input
IN
–
should be
IN
Reference Integrate Cycle
The final phase is reference integrate or de-integrate.
–
V
is internally connected to analog common and V
IN
+
is
IN
connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be
connected with the correct polarity to cause the integrator
output to return to zero. The time required for the output to
return to zero is proportional to the input signal and is
between 0 and 2000 counts. The digital reading displayed is:
V
1000 x
V
IN
REF
DIGITAL SECTION (TC7106A)
Auto-Zero Cycle
During the auto-zero cycle the differential input signal is
disconnected from the circuit by opening internal analog
gates. The internal nodes are shorted to analog common
(ground) to establish a zero-input condition. Additional analog gates close a feedback loop around the integrator and
comparator. This loop permits comparator offset voltage
error compensation. The voltage level established on C
compensates for device offset voltages. The offset error
referred to the input is less than 10µV.
The auto-zero cycle length is 1000 to 3000 counts.
The TC7106A (Figure 3) contains all the segment drivers necessary to directly drive a 3-1/2 digit liquid crystal
display (LCD). An LCD backplane driver is included. The
backplane frequency is the external clock frequency divided
by 800. For three conversions/second the backplane frequency is 60Hz with a 5V nominal amplitude. When a
segment driver is in phase with the backplane signal the
segment is “OFF.” An out of phase segment drive signal
causes the segment to be “ON” or visible. This AC drive
configuration results in negligible DC voltage across each
LCD segment. This insures long LCD display life. The
polarity segment driver is “ON” for negative analog inputs. If
When the TEST pin on the TC7106A is pulled to V+, all
segments are turned “ON.” The display reads –1888. During
this mode the LCD segments have a constant DC voltage
impressed. DO NOT LEAVE THE DISPLAY IN THIS MODE
FOR MORE THAN SEVERAL MINUTES! LCD displays
may be destroyed if operated with DC levels for extended
periods.
The display font and the segment drive assignment are
shown in Figure 4.
DISPLAY FONT
1000's100's10's1's
Figure 4. Display Font and Segment Assignment
In the TC7106A, an internal digital ground is generated
from a 6 volt zener diode and a large P channel source
follower. This supply is made stiff to absorb the large
capacitive currents when the backplane voltage is switched.
DIGITAL SECTION (TC7107A)
Figure 5 shows the TC7107A. It is designed to drive
common anode LEDs. It is identical to the TC7106A except
that the regulated supply and backplane drive have been
eliminated and the segment drive is typically 8mA. The
1000's output (pin 19) sinks current from two LED segments,
and has a 16mA drive capability.
In both devices, the polarity indication is “ON” for negative analog inputs. If V
–
and V
IN
+
are reversed, this indication
IN
can be reversed also, if desired.
The display font is the same as the TC7106A.
System Timing
The oscillator frequency is divided by 4 prior to clocking
the internal decade counters. The three-phase measurement cycle takes a total of 4000 counts or 16000 clock
pulses. The 4000 count cycle is independent of input signal
magnitude.
Each phase of the measurement cycle has the following
length:
•Auto-Zero Phase: 1000 to 3000 Counts
(4000 to 12000 Clock Pulses)
For signals less than full-scale, the auto-zero phase is
assigned the unused reference integrate time period.
This time period is fixed. The integration period is:
1
Where f
TSI = 4000
is the externally set clock frequency.
OSC
[]
f
OSC
•Reference Integrate: 0 to 2000 Counts
(0 to 8000 Clock Pulses)
The TC7106A/7107A are drop-in replacements for the
7106/7107 parts. External component value changes are
not required to benefit from the low drift internal reference.
Clock Circuit
Three clocking methods may be used:
1. An external oscillator connected to pin 40.
2. A crystal between pins 39 and 40.
3. An R-C oscillator using all three pins.
TC7106A
TC7107A
TO
4
÷
COUNTER
EXT
OSC
40
CRYSTAL
RC NETWORK
TO TEST PIN ON TSC7106A
TO GND PIN ON TSC7107A
Figure 6. Clock Circuits
39
38
COMPONENT VALUE SELECTION
Auto-Zero Capacitor – C
The CAZ capacitor size has some influence on system
noise. A 0.47µF capacitor is recommended for 200mV fullscale applications where 1 LSB is 100µV. A 0.047µF capacitor is adequate for 2.0V full-scale applications. A mylar
dielectric capacitor is adequate.
Reference Voltage Capacitor – C
The reference voltage used to ramp the integrator
output voltage back to zero during the reference-integrate
cycle is stored on C
when V
voltage exists (V
–
is tied to analog common. If a large common-mode
IN
–
REF
requires 200mV full-scale, increase C
error will be held to less than 1/2 count. A mylar dielectric
capacitor is adequate.
output voltage swing without causing output saturation. Due
to the TC7106A/7107A superior temperature coefficient
specification, analog common will normally supply the differential voltage reference. For this case a ±2V full-scale
integrator output swing is satisfactory. For 3 readings/
second (f
different oscillator frequency is used, C
= 48kHz) a 0.22µF value is suggested. If a
OSC
must be changed
INT
in inverse proportion to maintain the nominal ±2 V integrator
swing.
An exact expression for C
V
f
OSC
1
INT
(4000) () ()
C
=
INT
is:
INT
V
FS
R
INT
Where:
f
= Clock frequency at Pin 38
OSC
VFS = Full-scale input voltage
R
= Integrating resistor
INT
V
= Desired full-scale integrator output swing
INT
C
must have low dielectric absorption to minimize
INT
rollover error. A polypropylene capacitor is recommended.
Integrating Resistor – R
INT
The input buffer amplifier and integrator are designed
with class A output stages. The output stage idling current
is 100µA. The integrator and buffer can supply 20µA drive
currents with negligible linearity errors. R
is chosen to
INT
remain in the output stage linear drive region but not so large
that printed circuit board leakage currents induce errors. For
a 200mV full-scale, R
is 47kΩ. 2.0V full-scale requires
INT
470kΩ.
ComponentNominal Full-Scale Voltage
Value
200.0mV2.000V
C
AZ
R
INT
C
INT
Note:1. f
= 48kHz (3 readings/sec)
OSC
0.47µF0.047µF
47kΩ470kΩ
0.22µF0.22µF
Oscillator Components
R
(Pin 40 to Pin 39) should be 100kΩ. C
OSC
OSC
is
selected using the equation:
0.45
=
RC
is 100pF nominally.
OSC
For f
OSC
Note that f
f
OSC
of 48kHz, C
is divided by four to generate the TC7106A
OSC
internal control clock. The backplane drive signal is derived
by dividing f
OSC
by 800.
To achieve maximum rejection of 60Hz noise pickup,
the signal-integrate period should be a multiple of 60Hz.
Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz,
48kHz, 40kHz, etc. should be selected. For 50 Hz rejection,
oscillator frequencies of 200kHz, 100kHz, 66 2/3kHz, 50kHz,
40kHz, etc. would be suitable. Note that 40kHz (2.5 readings/second) will reject both 50Hz and 60Hz.
Reference Voltage Selection
A full-scale reading (2000 counts) requires the input
signal be twice the reference voltage.
Required Full-Scale Voltage*V
200.0mV100.0mV
2.000V1.000V
* VFS = 2 V
REF
In some applications a scale factor other than unity may
exist between a transducer output voltage and the required
digital reading. Assume, for example, a pressure transducer
output is 400mV for 2000 lb/in2. Rather than dividing the
input voltage by two the reference voltage should be set to
200mV. This permits the transducer input to be used
directly.
The differential reference can also be used when a
digital zero reading is required when VIN is not equal to zero.
This is common in temperature measuring instrumentation.
A compensating offset voltage can be applied between
analog common and V
nected between V
–
. The transducer output is con-
IN
+
and analog common.
IN
The internal voltage reference potential available at
analog common will normally be used to supply the converter's reference. This potential is stable whenever the supply
potential is greater than approximately 7V. In applications
where an externally-generated reference voltage is desired,
refer to Figure 7.
Device Pin Functional Description
Differential Signal Inputs
+
(V
(Pin 31), V
IN
The TC7106A/7017A is designed with true differential
inputs and accepts input signals within the input stage
common mode voltage range (VCM). The typical range is V
–1.0 to V– +1 V. Common-mode voltages are removed from
the system when the TC7106A/TC7107A operates from a
battery or floating power source (isolated from measured
system) and V
See Figure 8.
In systems where common-mode voltages exist, the
86dB common-mode rejection ratio minimizes error. Common-mode voltages do, however, affect the integrator output level. Integrator output saturation must be prevented. A
worst-case condition exists if a large positive VCM exists in
conjunction with a full-scale negative differential signal. The
negative signal drives the integrator output positive along
with VCM (Figure 9). For such applications the integrator
output swing can be reduced below the recommended 2.0V
full-scale swing. The integrator output will swing within 0.3V
of V+ or V– without increasing linearity errors.
–
(Pin 30))
IN
–
is connected to analog common (V
IN
COM
INPUT
+
V
IN
–
V
CM
Figure 9. Common-Mode Voltage Reduces Available Integrator
Differential Reference
+
(V
(Pin 36), V
REF
BUFFER
+
–
Where:
Swing. (V
R
I
V
=
I
RI C
INTEGRATION TIMET
==
I
C
INTEGRATION CAPACITOR
=
I
=
INTEGRATION RESISTOR
R
I
≠ VIN)
COM
–
(Pin 35))
REF
C
I
–
+
INTEGRATOR
T
I
V
–
[
CMVIN
I
The reference voltage can be generated anywhere
within the V+ to V– power supply range.
To prevent rollover errors from being induced by large
common-mode voltages, C
+
should be large compared to
REF
stray node capacitance.
The TC7106A/TC7107A circuits have a significantly
lower analog common temperature coefficient. This gives a
very stable voltage suitable for use as a reference. The
):
temperature coefficient of analog common is 20ppm/°C
typically.
The analog common pin is set at a voltage potential
approximately 3.0V below V+. The potential is guaranteed
to be between 2.7V and 3.35 V below V+. Analog common
is tied internally to the N channel FET capable of sinking
20mA. This FET will hold the common line at 3.0V should an
external load attempt to pull the common line toward V+.
Analog common source current is limited to 10µA. Analog
common is therefore easily pulled to a more negative
voltage (i.e., below V+ – 3.0V).
The TC7106A connects the internal V
to analog common during the auto-zero cycle. During the
reference-integrate phase, V
mon. If V
–
is not externally connected to analog common,
IN
–
is connected to analog com-
IN
+
and V
IN
–
inputs
IN
a common-mode voltage exists. This is rejected by the
converter's 86dB common-mode rejection ratio. In battery
operation, analog common and V
removing common-mode voltage concerns. In systems where
–
V
is connected to the power supply ground or to a given
IN
voltage, analog common should be connected to V
–
are usually connected,
IN
–
.
IN
The analog common pin serves to set the analog section
reference or common point. The TC7106A is specifically
designed to operate from a battery or in any measurement
system where input signals are not referenced (float) with
respect to the TC7106A power source. The analog common
potential of V+ – 3.0V gives a 6 V end of battery life voltage.
The common potential has a 0.001%/% voltage coefficient
and a 15 Ω output impedance.
With sufficiently high total supply voltage (V+ – V
> 7.0V) analog common is a very stable potential with
excellent temperature stability—typically 20ppm/°C. This
potential can be used to generate the reference voltage. An
external voltage reference will be unnecessary in most
cases because of the 50ppm/°C maximum temperature
coefficient. See Internal Voltage Reference discussion.
Test (Pin 37)
The TEST pin potential is 5V less than V+. TEST may be
used as the negative power supply connection for external
CMOS logic. The TEST pin is tied to the internally generated
negative logic supply (Internal Logic Ground) through a
500Ω resistor in the TC7106A. The TEST pin load should be
no more than 1mA .
If TEST is pulled to V+ all segments plus the minus sign
will be activated. Do not operate in this mode for more than
several minutes with the TC7106A. With TEST = V+ the LCD
segments are impressed with a DC voltage which will
destroy the LCD.
The TEST pin will sink about 10mA when pulled to V+.
Internal Voltage Reference Stability
The analog common voltage temperature stability has
been significantly improved (Figure 10). The “A” version of
the industry standard circuits allow users to upgrade old
systems and design new systems without external voltage
references. External R and C values do not need to be
changed. Figure 11 shows analog common supplying the
necessary voltage reference for the TC7106A/TC7107A.
The TC7107A is designed to work from ±5V supplies.
However, if a negative supply is not available, it can be
generated from the clock output with two diodes, two capacitors, and an inexpensive IC. (Figure 12)
In selected applications a negative supply is not required. The conditions to use a single +5V supply are:
•The input signal can be referenced to the center of the
common-mode range of the converter.
•The signal is less than ±1.5V.
•An external reference is used.
The TSC7660 DC to DC converter may be used to
generate – 5 V from +5 V (Figure 13).
+
V
CD4009
+
V
OSC
1
OSC
OSC
TC7107A
GND
–
V
2
3
0.047
µF
1N914
10
µF
1N914
+
–
TC7107 Power Dissipation Reduction
The TC7107A sinks the LED display current and this
causes heat to build up in the IC package. If the internal
voltage reference is used, the changing chip temperature
can cause the display to change reading. By reducing the
LED common anode voltage the TC7107A package power
dissipation is reduced.
Figure 14 is a photograph of a curve-tracer display
showing the relationship between output current and output
voltage for a typical TC7107CPL. Since a typical LED has
1.8 volts across it at 7mA, and its common anode is connected to +5V, the TC7107A output is at 3.2V (point A on
Figure 13). Maximum power dissipation is 8.1mA x 3.2V x
24 segments = 622mW.
Notice, however, that once the TC7107A output voltage
is above two volts, the LED current is essentially constant as
output voltage increases. Reducing the output voltage by
0.7V (point B in Figure 14) results in 7.7mA of LED current,
only a 5 percent reduction. Maximum power dissipation is
only 7.7mA x 2.5 V x 24 = 462mW, a reduction of 26%. An
output voltage reduction of 1 volt (point C) reduces LED
current by 10% (7.3mA) but power dissipation by 38%!
(7.3mA x 2.2V x 24 = 385mW).
V– = –3.3V
Figure 12. Generating Negative Supply From +5 V
+5 V
1
+
36
+
V
V
REF
35
–
V
REF
32
COM
31
+
V
IN
30
–
V
IN
21
–
GND
V
26
10µF
LED
DRIVE
TC7107A
8
2
+
TC7660
4
3
(–5 V)
5
+
10µF
Figure 14. TC7107A Output Current vs Output Voltage
Reduced power dissipation is very easy to obtain.
Figure 15 shows two ways: either a 5.1 ohm, 1/4 watt resistor
V
IN
or a 1 Amp diode placed in series with the display (but not in
series with the TC7107A). The resistor will reduce the
TC7107A output voltage, when all 24 segments are “ON,” to
point “C” of Figure 14. When segments turn off, the output
voltage will increase. The diode, on the other hand, will result
in a relatively steady output voltage, around point “B.”
Figure 13. Negative Power Supply Generation with TC7660
In addition to limiting maximum power dissipation, the
resistor reduces the change in power dissipation as the
display changes. This effect is caused by the fact that, as
fewer segments are “ON,” each “ON” output drops more
voltage and current. For the best case of six segments (a
“111” display) to worst case (a “1888” display) the resistor
will change about 230mW, while a circuit without the resistor
will change about 470mW. Therefore, the resistor will reduce the effect of display dissipation on reference voltage
drift by about 50%.
The change in LED brightness caused by the resistor is
almost unnoticeable as more segments turn off. If display
brightness remaining steady is very important to the designer, a diode may be used instead of the resistor.
0.47
µF
0.22
µF
4
–5V
150Ω
DISPLAY
20101
+5V
24kΩ
1kΩ
100
TP5
100
kΩ
40TP
pF
TP2
TP1
0.1
µF
+
Ω
1 M
TP3
TC7107A
IN
–
0.01
µF
47
kΩ
3021
APPLICATIONS INFORMATION
Liquid Crystal Display Sources
Several LCD manufacturers supply standard LCD displays to interface with the TC7106A 3-1/2 digit analog-todigital converter.
Hewlett-Packard640 Page Mill Rd.LED
ComponentsPalo Alto, CA 94304
AND720 Palomar Ave.LED
Sunnyvale, CA 94086
15
TC7106/6A/7/7A-7 11/4/96
TC7106
TC7106A
TC7107
TC7107A
3-1/2 Digit A/D Converters
Decimal Point and Annunciator Drive
The TEST pin is connected to the internally-generated
digital logic supply ground through a 500 Ω resistor. The
TEST pin may be used as the negative supply for external
CMOS gate segment drivers. LCD display annunciators for
decimal points, low battery indication, or function indication
may be added without adding an additional supply. No more
than 1mA should be supplied by the TEST pin: its potential
is approximately 5V below V+.
+
+
V
TC7106A
TEST
BP
21
37
V
4049
TO LCD
DECIMAL
POINT
GND
TO LCD
BACKPLANE
Ratiometric Resistance Measurements
The true differential input and differential reference
make ratiometric reading possible. Typically in a ratiometric
operation, an unknown resistance is measured with respect
to a known standard resistance. No accurately defined
reference voltage is needed.
The unknown resistance is put in series with a known
standard and a current passed through the pair. The voltage
developed across the unknown is applied to the input and
the voltage across the known resistor is applied to the
reference input. If the unknown equals the standard, the
display will read 1000. The displayed reading can be determined from the following expression:
Displayed Reading =x 1000
The display will overrange for R Unknown ≥ 2 x R
standard.
R
STANDARD
R Unknown
R Standard
+
V
V
REF
–
V
REF
+
+
V
+
V
BP
TC7106A
TEST
Figure 16. Decimal Point Drive Using TEST as Logic Ground
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by
updates. It is your re sponsib ility to en sure that your applicati on mee ts with your specifica tions. No repr esentation or warra nty is given and no liability is
assumed by Micro chip Technology Incorporated with respe ct to the a ccuracy or use of such infor mati on, or infrin gemen t of patents or o th er int ell ec tua l
property rights arising from such use or otherwise. Use of Microchipís products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellectual property rights. The Mi crochip logo and name are registered trad emarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights
reserved. All other trademarks mentioned herein are the property of their respective companies.
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