Tektronix TMS855 Instruction Manual

Instruction Manual

TMS855

HyperTransport Bus Software Support

071-1170-00

www.tektronix.com

Tektronix products are covered by U.S. and foreign patents, issued and pending. Information in this publication supercedes that in all previously published material. Specifications and price c hange privileges reserved.

Tektronix, Inc., P.O. Box 500, Bea verton, OR 97077

TEKTRONIX and TEK are registered trademarks of Tektronix, Inc.

MagniVu is a trademark of Tektronix, Inc.

SOFTWARE WARRANTY

Tektronix warrants that the media on which this software product is furnished and the encoding of the programs on the media will be free from defects in materials and workmanship for a period of three (3) months from the date of shipment. If a medium or encoding proves defective during the warra nty period, Tektronix will provide a replacement in exchange for the defective medium. Except as to the media on which this software product is furnished, this software product is provided “as is” without warranty of any kind, either e xpress or implied. Tektronix does not warrant that the func tions contained in this software product will meet Customer’s requirements or that the operation of the programs will be uninterrupted or error-free.

In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration of the warranty period. If Tektronix is unable to provide a replacement that is free from defects in materials and workmanship within a reasonable time thereafter, Customer may terminate the license for this software product and return this software product and any associated materials for credit or refund.

THIS WARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER WARRANTIES, EXPRESS OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’ RESPONSIBILITY TO REPLACE DEFECTIVE MEDIA OR REFUND CUSTOMER’S PAYMENT IS THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS WARRANTY. TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.

Getting Started

Operating Basics

Preface vii...................................................

Manual Conventions vii..............................................

Contacting Tektronix viii.............................................

Support Package Description 1--1.......................................

Disassembly Support 1--1..........................................

Logic Analyzer Software Compatibility 1--2..............................

Logic Analyzer Configuration 1--2......................................

Requirements and Restrictions 1--3......................................

Hardware Reset 1--3..............................................

Clock Rate 1--3..................................................

Setup/Hold Time Adjustments 1--3..................................

Nonintrusive Acquisition 1--3......................................

Limitations of the Support 1--4.........................................

Connecting the Logic Analyzer to a Target System 1--4.....................

Labeling P6880 Probes 1--5............................................

Setting Up the Support 2--1.....................................

Installing the Support Software 2--1.....................................

Support Package Setups 2--2...........................................

Clocking Options 2--3................................................

Acquiring and Viewing Disassembled Data 2--5....................

Acquiring Data 2--5..................................................

Changing How Data is Displayed 2--5...................................

Optional Display Selections 2--6....................................

Bus Specific Fields 2--6...........................................

Marking Cycles 2--7..................................................

Cycle Type Labels 2--8...............................................

Special Messages 2--9................................................

Viewing Disassembled Data 2--10........................................

All Display Format 2--11...........................................

No NOP Packets Display Format 2--13................................

Trigger Programs 2--15..........................................

Loading Trigger Programs 2--15.........................................

HT and HT_Tek Trigger Programs 2--16...............................

Setup/Hold Time Adjustments 2--19...............................

Reference

Channel Group Definitions 3--1..................................

Channel Groups 3--1.................................................

TMS855 HyperTransport Bus Software Support

Table of Contents

Specifications

Replaceable Parts List

Symbol and Channel Assignment Tables 3--9......................

Symbol Tables 3--9..................................................

Channel Assignment Tables 3--9........................................

HT Channel Group Assignments 3--10................................

Setup/Hold Calibration Groups 3--10..................................

Disassembly Groups for HT Support Package 3--11......................

HT_Tek Channel Group Assignments 3--13............................

Setup/Hold Calibration Groups 3--13..................................

Disassembly Groups for HT_Tek Support Package 3--14..................

Signal Source To Probe Connections 3--17.................................

Connections for HT and HT_Cal Support Packages 3--18.................

Connections for HT_Tek and HT_Tek_Cal Support Packages 3--25.........

Signal Acquisition 3--33.........................................

Signal Acquisition in HT and HT_Tek Support Packages 3--33.................

Specifications Table 4--1..............................................

Index

Parts Ordering Information 5 --1.........................................

Using the Replaceable Parts List 5--1....................................

TMS855 HyperTransport Bus Software Support

List of Figures

Table of Contents

Figure 2--1: Disassembly display options for HT support

package 2--6...............................................

Figure 2--2: Example of All Display format for the HT_Tek support

package 2--11...............................................

Figure 2--3: Example of All display format with CRC and NOP

packets filtered for the HT_Tek support package 2--12...........

Figure 2--4: Example of No NOP Packets with Post Process filtering

in HT_Tek support package 2--13..............................

Figure 2--5: Loading trigger programs 2--16........................

Figure 3--1: P6880 differential probe land footprint for HT and

HT_Cal support packages 3--18...............................

Figure 3--2: P6880 differential probe land footprint for HT_Tek

and HT_Tek_Cal support packages 3--25.......................

Figure 3--3: P6880 differential probe land footprint for HT_Tek

and HT_Tek_Cal support packages 3--26.......................

Figure 3--4: Timing diagram for Upstream or Downstream bus 3--34....

Figure 3--5: Timing diagram for Upstream and Downstream bus

with Clock Inverted. 3--35....................................

Figure 3--6: Timing diagram for Upstream and Downstream bus 3--36..

Figure 3--7: Timing diagram for Upstream and Downstream bus

with skew 3--37.............................................

Figure 3--8: Timing diagram for Upstream and Downstream with

180 degree phase shift 3--38...................................

TMS855 HyperTransport Bus Software Support

iii

Table of Contents

List of Tables

Table 1--1: Probe requirements for the TMS855 HyperTransport

bus support packages 1--3...................................

Table 2--1: Disassembly display options 2--6.......................

Table 2--2: Mark selections and definitions for HT and HT_Tek

support packages 2--8......................................

Table 2--3: Cycle type labels for control p ackets in HT and HT_Tek

support packages 2--8......................................

Table 2--4: Cycle type labels for data packets for HT and HT_Tek

support packages 2--9......................................

Table 2--5: Cycle type labels for packet continuation for HT and

HT_Tek support packages 2--9...............................

Table 2--6: Description of special messages in the display 2--10........

T able 2--7: Description of special characters in the display 2--10.......

Table 3--1: HT and HT_Tek Channel groups 3--1..................

Table 3--2: HT_Ctrl group symbol table definitions 3--9.............

Table 3--3: HT Setup/Hold calibration groups 3--10..................

Table 3--4: U_CAD group assignments for HT support package 3--11...

Table 3--5: U_CAD_DM group assignments for HT support

package 3--11..............................................

Table 3--6: U_Control group assignments for HT support

package 3--12..............................................

Table 3--7: D_CAD group assignments for HT support package 3--12...

Table 3--8: D_CAD_DM group assignments for HT support

package 3--12..............................................

Table 3--9: D_Control group assignments for HT support

package 3--13..............................................

Table 3--10: HT_Tek Setup/Hold calibration groups 3--13............

Table 3--11: U_CAD group assignments for HT_Tek support

package 3--14..............................................

Table 3--12: U_CAD_DM group assignments for HT_Tek support

package 3--15..............................................

Table 3--13: U_Control group assignments for HT_Tek support

package 3--15..............................................

Table 3--14: D_CAD group assignments for HT_Tek support

package 3--15..............................................

TMS855 HyperTransport Bus Software Support

Table of Contents

Table 3--15: D_CAD_DM group assignments for HT_Tek support

package 3--16..............................................

Table 3--16: D_Control group assignments for HT_Tek support

package 3--16..............................................

Table 3--17: Clock and qualifier channel assignments for HT support

package 3--19..............................................

Table 3--18: A3 probe Upstream channel assignments for HT support

package 3--20..............................................

Table 3--19: D3 probe channel assignments for Upstream bus demuxed

from A3 for HT support package 3--21........................

Table 3--20: C3 probe Upstream channel assignments for HT support

package 3--21..............................................

Table 3--21: C1 probe channel assignments for Upstream bus demuxed

from C3 for HT support package 3--22.........................

Table 3--22: A1 probe Downstream channel assignments for HT

support package 3--22.......................................

Table 3--23: D1 probe channel assignments for Downstream bus

demuxed from A1 for HT support package 3--23.................

Table 3--24: E3 probe Downstream channel assignments for HT

support package 3--23.......................................

Table 3--25: E1 probe channel assignments for Downstream bus

demuxed from E3 for HT support package 3--24.................

Table 3--26: Clock and qualifier channel assignments for HT_Tek

support package 3--26.......................................

Table 3--27: A3 probe Upstream channel assignments for HT_Tek

support package 3--27.......................................

Table 3--28: D3 probe channel assignments for Upstream bus demuxed

from A3 for HT_Tek support package 3--28.....................

Table 3--29: C3 probe Upstream channel assignments for HT_Tek

support package 3--28.......................................

Table 3--30: C1 probe channel assignments for Upstream bus demuxed

from C3 for HT_Tek support package 3--29....................

Table 3--31: A1 probe Downstream channel assignments for HT_Tek

support package 3--29.......................................

Table 3--32: D1 probe channel assignments for Downstream bus

demuxed from A1 for HT_Tek support package 3--30............

Table 3--33: E3 probe Downstream channel assignments for

HT_Tek support package 3--30...............................

Table 3--34: E1 probe channel assignments for Downstream bus

demuxed from E3 for HT_Tek support package 3 --31............

Table 3--35: Reference of figures corresponding to combinations

of acquisition modes and clocking options 3--33.................

TMS855 HyperTransport Bus Software Support

Table of Contents

Table 3--36: Sample points in the HT and HT_Tek support

packages 3--39.............................................

T able 4--1: Electrical specifications 4--1...........................

TMS855 HyperTransport Bus Software Support

Preface

This instruction manual contains specific information about the TMS855 HyperTransport bus software support product and is part of a set of information on how to operate this product on compatible Tektronix logic analyzers.

If you are familiar with operating bus support products on the logic analyzer, you will probably only need this instruction manual to set up and run the support.

If you are not familiar with operating bus support products, you will need to supplement this instruction manual with information on basic operations to set up and run the support.

Information on basic operations of bus support packages is included with each product. Each logic analyzer includes basic information that describes how to perform tasks common to support packages on that platform. This information can be in the form of logic analyzer online help, an installation manual, or a user manual.

This manual provides detailed information on the following topics:

H Connecting the logic analyzer to the target system

Manual Conventions

H Setting up the logic analyzer to acquire data from the target system

H Acquiring and viewing disassembled data

This manual uses the following conventions:

H The term “disassembler” refers to the software that disassembles Hyper-

Transport bus cycles.

H The phrase “information on basic operations” refers to logic analyzer online

help or user manual.

H The phrase “logic analyzer” refers to the Tektronix logic analyzer for which

this product was purchased.

TMS855 HyperTransport Bus Software Support

vii

Contacting Tektronix

Preface

Phone 1-800-833-9200*

Address Tektronix, Inc.

Department or name (if known) 14200 SW Karl Braun Drive P.O. Box 500 Beaverton, OR 97077 USA

Web site www.tektronix.com

Sales support 1-800-833-9200, select option 1*

Service support 1-800-833-9200, select option 2*

Technical support Email: techsupport@tektronix.com

1-800-833-9200, select option 3*

6:00 a.m. -- 5:00 p.m. Pacific time

* This phone number is toll free in North America. After office hours, please leave a

voice mail message. Outside North America, contact a Tektronix sales office or distributor; see the Tektronix web site for a list of offices.

TMS855 HyperTransport Bus Software Supportviii

Getting Started

This section contains information on the TMS855 HyperTransport bus support product, and information on connecting your logic analyzer to your target system.

Support Package Description

The TMS855 HyperTransport bus support product acquires, decodes and displays HyperTransport bus cycles. The support product allows you to acquire bus cycles with minimal impact on the normal environment of the system.

The TMS855 HyperTransport bus support product contains four support packages that you can load to handle the various combinations of Upstream and Downstream bus widths and data rates. A description of each support package is listed here.

H HT provides state, timing, triggering, and disassembly support.

H HT_Cal helps adjust the Setup/Hold time.

H HT_Tek provides state, timing, triggering, and disassembly support.

Disassembly Support

H HT_Tek_Cal helps adjust the Setup/Hold time.

NOTE. The support packages HT and HT_Cal differ from HT_Tek, and HT_Tek_Cal, only in the channel assignments. Refer to the section Symbol and Channel Assignment Tables on page 3--11 for details.

Triggering Support. The HT and HT_Tek support packages contain a library of EasyTrigger programs to enable you to quickly trigger on HyperTransport control packets and to filter CRC and NOP packets in real time.

The HT and HT_Tek support packages disassemble data acquired from the HyperTransport bus. The features of the disassembler are:

H Decoding all types of HyperTransport Packets.

H Identifying CRC packets using heuristics.

H Supporting disassembly for the 8-bit and 16-bit bus widths for Upstream and

Downstream.

TMS855 HyperTransport Bus Software Support

1--1

H Providing trigger programs for real time filtering of the CRC and NOP

packets and to trigger on the HyperTransport packets.

H Color coding for easier identification of the different packet fields.

H Using packet style display for the existing logic analyzer listing window

architecture.

H Acquiring Upstream and Downstream 8 and 16-bit buses in one 136-channel

TLA7Axx module, when the bus is operating in synchronous mode.

To use this support package efficiently, refer to these documents:

H HYPERTRANSPORT I/O LINK SPECIFICATION, {HyperTransport

Technology Consortium, 22nd November 2002, and Revision 1.05}

H HyperTransport Technology, Interface Design Guide, {May, 2002, Revision

1.04}

Logic Analyzer Software Compatibility

Getting Started

The label on the bus support CD-ROM states which version of logic analyzer software this support package is compatible with.

Logic Analyzer Configuration

The TMS855 HyperTransport bus support product allows a choice of required minimum module configurations. The support package requires one 136-channel TLA7Axx module. You can simultaneously capture different combinations of Upstream and the Downstream buses from the target system assuming that both the Upstream and Downstream clocks are running at the same speed and derived from the same crystal. The different combinations are:

H 8-bit Upstream Bus and 8-bit Downstream Bus

H 16-bit Upstream Bus and 16-bit Downstream Bus

H 8-bit Upstream Bus and 16-bit Downstream Bus

H 16-bit Upstream Bus and 8-bit Downstream Bus

Systems with unique clocks for the U pstream and Downstream buses require two independent 136-channel TLA7Axx modules for simultaneous capture. Module acquisition speed depends on the requirements but is 450 MHz by default for 16-bit and 8-bit buses.

1--2

TMS855 HyperTransport Bus Software Support

Getting Started

Table 1--1 lists the probe requirements for each of the TMS855 HyperTransport bus support packages.

Table 1--1: Probe requirements for the TMS855 HyperTransport bus support packages

Support package

HT, and HT_Cal Four P6880 probes for

HT_Tek, and HT_Tek_Cal

Upstream and Downstream 16-bit buses

TLA7Axx

Four P6880 probes for TLA7Axx

Requirements and Restrictions

Review the electrical specifications in the Specifications section on page 4-1 in this manual as they pertain to your target system, as well as the following descriptions of TMS855 HyperTransport bus support product requirements and restrictions.

Hardware Reset

Clock Rate

If a hardware reset occurs in your HyperTransport system during an acquisition, the application might acquire an invalid sample.

The maximum rate for state acquisition is 450 MHz

Upstream and Downstream 8-bit buses

Two P6880 probes for TLA7Axx

Four P6880 probes for TLA7Axx

Upstream or Downstream 16-bit buses

Two P6880 probes for TLA7Axx

Upstream or Downstream 8-bit buses

One P6880 probe for TLA7Axx

Two P6880 probes for TLA7Axx

Setup/Hold Time

Adjustments

For correct acquisition, the target system must provide a data valid window of 750 ps. Some target systems may require an adjustment in the Setup/Hold time settings of the logic analyzer to match the data valid window. The HT_Cal and HT_Tek_Cal support packages can be used along with the SHAnalyzer application to find the optimum Setup/Hold time settings for the logic analyzer. For more information, refer to the section Setup/Hold Time Adjustments on page 2-19.

Nonintrusive Acquisition

Acquiring HyperTransport bus cycles is nonintrusive to the target system. That is, the TMS855 HyperTransport bus support product does not intercept, modify or present signals back to the target system.

Specification at time of printing. Contact your Tektronix sales representative for current information on the fastest bus supported.

TMS855 HyperTransport Bus Software Support

1--3

Limitations of the Support

The TMS855 HyperTransport bus support product has these limitations.

H If the TMS855 HyperTransport bus support product cannot find the start of a

H Since the trigger programs wait until they encounter a Low to High transition

H When the CTL signal is asserted, the CAD signals carry either a control

Getting Started

control packet or a CRC packet, it displays a message “Insufficient Data to Disassemble” in the listing window. This usually occurs if there are no data packets or CRC packets in the acquisition. Use the marking options (see page 2--7) to mark the start of a control packet. Once the start of a control packet is known the support package disassembles the HyperTransport packets.

in the CTL signal (to identify the start of a control packet), the trigger programs do not trigger the logic analyzer, if there are no transitions on the CTL signal.

packet or a CRC packet. Since the trigger programs cannot differentiate between a CRC packet and a control packet, false triggering may occur. If the logic analyzer triggered on a CRC packet, then try again to trigger on the desired control packet. This happens when CRC and NOP packets are not filtered.

Connecting the Logic Analyzer to a Target System

You can use the channel probes and clock probes, to make the connections between the logic analyzer and your target system.

To connect the probes to the HyperTransport bus signals described in the TMS855 product channel assignment to the target system, follow these steps:

1. Power off your target system. It is not necessary to power off the logic

analyzer.

CAUTION. To prevent static damage, handle the target systems, probes, and the logic analyzer module in a static-free environment. Static discharge can damage these components.

Always wear a grounding wrist strap, heel strap, or similar device while handling the target system.

2. Place the target system on a horizontal, static-free surface.

3. Use Tables 3--17 through 3--34 starting on page 3--19 to connect the channel

probes to HyperTransport bus signals in the target system.

1--4

TMS855 HyperTransport Bus Software Support

Getting Started

Labeling P6880 Probes

The TMS855 HyperTransport bus support product relies on the channel mapping and labeling scheme for the P6880 probe. Apply labels, using the instructions described in the P6810, P6860, P6880 Logic Analyzer Probes Instruction manual (Tektronix part number 071-1059-XX).

TMS855 HyperTransport Bus Software Support

1--5

Getting Started

1--6

TMS855 HyperTransport Bus Software Support

Operating Basics

Setting Up the Support

This section provides information on how to set up the software support and covers the following topics:

H Installing the support software

H Support package setups

H Clocking options

The information in this section is specific to the operations and functions of the TMS855 HyperTransport bus support product on a Tektronix logic analyzer. Information on basic operations describes general tasks and functions.

Before you acquire and display disassembled data, you need to load the support package and specify the setups for clocking and triggering as described in the logic analyzer online help under “Microprocessor Support”. The support package provides default values for each of these setups, but you can change the setups as needed.

Installing the Support Software

NOTE. Before you install any support software, it is recommended you verify that the bus support software is compatible with the logic analyzer software.

To install the TMS855 HyperTransport bus support product on your Tektronix logic analyzer, follow these steps:

1. Insert the CD-ROM in the CD drive.

2. Click the Windows Start button, point to Settings, and click Control Panel.

3. In the Control Panel window, double-click Add/Remove Programs.

4. Follow the instructions on the screen for installing the software from the

CD-ROM. A copy of the instruction manual is available on the CD-ROM.

To remove or uninstall software, follow the above instructions and select Uninstall. You need to close all windows before you uninstall any software.

TMS855 HyperTransport Bus Software Support

2--1

Setting Up the Support

Support Package Setups

The TMS855 HyperTransport bus support product installs four support packages. Each support package offers different clocking and display options.

H HT: This support package has the channel assignment derived from the pin

H HT_Cal: This support package has the channel assignment derived from the

H HT_Tek: Use this support package to acquire and decode the HyperTransport

escape defined in HyperTransport Technology, Interface Design Guide.Use this support package to acquire and decode the HyperTransport bus cycles. It supports clock rates from DC up to 450 MHz and data rates from DC up to 900 Mb/s. This package supports both Upstream and Downstream 8-bit and 16-bit buses.

pin escape defined in the HyperTransport Technology, Interface Design Guide. Use this support package to optimize the Setup/Hold window of the logic analyzer for the HyperTransport bus. This support package does not decode and display acquired data. It should only be used in conjunction with the SHAnalyzer application.

bus cycles. It supports clock rates from DC up to 450 MHz and data rates from DC up to 900 Mb/s. This package supports both Upstream and Downstream 8-bit and 16-bit buses.

H HT_Tek_Cal: Use this support package to optimize the Setup/Hold window

of the logic analyzer for the HyperTransport bus. This support package does not decode and display acquired data. It should only be used in conjunction with the SHAnalyzer application.

2--2

TMS855 HyperTransport Bus Software Support

Clocking Options

Setting Up the Support

A special custom clocking program is loaded into the module every time you load one of the HT, HT_Tek, HT_Cal, or HT_Tek_Cal support packages from the TMS855 HyperTransport bus support product. Each support package offers different clocking options. You may use the default clocking option or choose an alternate by clicking the “More...” button in the logic analyzer setup window.

HT, HT_Tek, HT_Cal, and HT_Tek_Cal . These four support packages provide eight custom clocking options.

H 1: Upstream UCLK0 (default)

For a system with common clocks for the Upstream and Downstream buses,

choose this option to acquire both Upstream and Downstream cycles using

the Upstream CLK0 (U_CLK0). Setup/Hold values for signals on the

Upstream and Downstream buses must be referenced to Upstream CLK0

(U_CLK0). Special groups are created to assist in specifying Setup/Hold

values.

H 2: Upstream UCLK0 inverted

Choose this option if the polarity of the Upstream clock is reversed. For a

system with common clocks for the Upstream and Downstream buses,

choose this option to acquire both Upstream and Downstream cycles using

the Upstream CLK0 (U_CLK0). Setup/Hold values for signals on the

Upstream and Downstream buses must be referenced to Upstream CLK0

(U_CLK0). Special groups are created to assist in specifying Setup/Hold

values.

H 3: Upstream UCLK1

For a system with common clocks for the Upstream and Downstream buses,

choose this option to acquire both Upstream and Downstream cycles using

the Upstream CLK1 (U_CLK1). Setup/Hold values for signals on the

Upstream and Downstream buses must be referenced to Upstream CLK1

(U_CLK1). Special groups are created to assist in specifying Setup/Hold

values.

H 4: Upstream UCLK1 inverted

Choose this option if the polarity of the Upstream clock is reversed. For a

system with common clocks for the Upstream and Downstream buses,

choose this option to acquire both Upstream and Downstream cycles using

the Upstream CLK1 (U_CLK1). Setup/Hold values for signals on the

Upstream and Downstream buses must be referenced to Upstream CLK1

(U_CLK1). Special groups are created to assist in specifying Setup/Hold

values.

H 5: Downstream CLK0

For a system with common clocks for the Upstream and Downstream buses,

choose this option to acquire both Upstream and Downstream cycles using

TMS855 HyperTransport Bus Software Support

2--3

Setting Up the Support

the Downstream CLK0 (D_CLK0). Setup/Hold values for signals on the Upstream and Downstream buses must be referenced to Downstream CLK0 (D_CLK0). Special groups are created to assist in specifying Setup/Hold values.

H 6: Downstream CLK0 inverted

Choose this option if the polarity of the Downstream clock is reversed. For a system with common clocks for the Upstream and Downstream buses, choose this option to acquire both Upstream and Downstream cycles using the Downstream CLK0 (D_CLK0). Setup/Hold values for signals on the Upstream and Downstream buses must be referenced to Downstream CLK0 (D_CLK0). Special groups are created to assist in specifying Setup/Hold values.

H 7: Downstream CLK1

For a system with common clocks for the Upstream and Downstream buses, choose this option to acquire both Upstream and Downstream cycles using the Downstream CLK1 (D_CLK1). Setup/Hold values for signals on the Upstream and Downstream buses must be referenced to Downstream CLK1 (D_CLK1). Special groups are created to assist in specifying Setup/Hold values.

H 8: Downstream CLK1 inverted

Choose this option if the polarity of the Downstream clock is reversed. For a system with common clocks for the Upstream and Downstream buses, choose this option to acquire both Upstream and Downstream cycles using the Downstream CLK1 (D_CLK1). Setup/Hold values for signals on the Upstream and Downstream buses must be referenced to Downstream CLK1 (D_CLK1). Special groups are created to assist in specifying Setup/Hold values.

NOTE. Systems with unique clocks for the Upstream and Downstream buses require two independent 136-channel modules for simultaneous capture.

2--4

TMS855 HyperTransport Bus Software Support

Acquiring and Viewing Disassembled Data

This section describes how to acquire data and view it disassembled. The following information covers these topics and tasks:

H Acquiring data

H Changing how data is displayed

H Viewing cycle type labels

H Viewing disassembled data in various display formats

Acquiring Data

The TMS855 HyperTransport bus support product installs four different support packages: HT, HT_Tek, HT_Cal, and HT_Tek_Cal.

NOTE. HT_Cal and HT_Tek_Cal support packages are added for Setup/Hold time adjustments. Use these support packages only when you need to adjust the Setup/Hold time values.

Once you load a support package, choose a clocking mode, and specify the trigger, you are ready to acquire and disassemble data.

If you have any problems acquiring data, refer to information on basic operations in your logic analyzer online help.

Changing How Data is Displayed

Common fields and features allow you to further modify displayed data to suit your needs. You can make common and optional display selections in the Disassembly property page.

You can make selections unique to the TMS855 HyperTransport bus support product to do the following tasks:

H Change how data is displayed across all display formats

H Change the interpretation of disassembled cycles

TMS855 HyperTransport Bus Software Support

2--5

Acquiring and Viewing Disassembled Data

Optional Display

Selections

Bus Specific Fields

Table 2--1 lists the logic analyzer disassembly display options for the TMS855 HyperTransport bus support product.

Table 2--1: Disassembly display options

Description Option

Show All (default)

No NOP Packets

Highlight None (default)

Disassemble Across Gaps Yes

No (default)

You can make optional selections for disassembled data. In addition to the common selections (described in the information on basic operations).You can change the displayed data in the following ways, for the HT and HT_Tek support packages. The submenu has the titles HT Controls and HT_Tek Controls. Figure 2-1 displays the listing window for the disassembly optons.

Figure 2--1: Disassembly display options for HT support package

2--6

TMS855 HyperTransport Bus Software Support

Acquiring and Viewing Disassembled Data

Disassemble. Select one of the two options for the disassembly of either Upstream or Downstream cycles.

Upstream (Default) Downstream

Upstream Bus Width: Select the Upstream bus width from these options.

8 bit (default) 16 bit None

Downstream Bus Width: Select the Downstream bus width from these options.

8 bit (default) 16 bit None

Marking Cycles

x86 Decode: Two options are available. Set this option to “Ye s” to view the x86 packets.

No (default) Yes

NOPs and CRCs Filtered: Two options are available. Set this option to “Yes ” if the CRC and NOP packets are filtered in real time through trigger programs.

No (default) Yes

The disassembler has a Mark Opcode function that allows you to change the interpretation of a cycle type. Using this function, you can select a cycle and change it.

Marks are placed by using the Mark Opcode button. The Mark Opcode button will always be available when disassembly is available. If the sample being marked is not a Control Packet, a note indicating that “An opcode Mark cannot be placed at the selected data sample” will replace the Mark Opcode selections.

When a cycle is marked, the character “»” is displayed immediately to the left of the “HT Frames” or “HT_Tek Frames” column. Cycles can be unmarked by using the “Undo Mark” selection, which will remove the character “»”.

TMS855 HyperTransport Bus Software Support

2--7

Acquiring and Viewing Disassembled Data

Table 2--2 shows the mark selections available on the control packets.

Table 2--2: Mark selections and definitions for HT and HT_Tek support packages

Mark selection Definition

Control Marks cycle as start of control packet

Undo Mark Remove all marks for the current sample

Cycle Type Labels

The HT and HT_Tek support packages decode and display all the individual fields of each packet type. These fields are displayed in different colors.

The control packet names are highlighted in cyan except for Sync Pattern which is highlighted in yellow. Table 2--3 lists the cycle type labels for the HyperTransport control packets.

Table 2--3: Cycle type labels for control packets in HT and HT_Tek support packages

Cycle type labels Description

NOP Packet NOP Packet Name

Reserved-HOST Control packet with a reserved command code

Flush Flush Packet Name

Write Request Sized Write Request Packet Name

Read Request Sized Read Request Packet Name

Reserved-I/O Control packet with a reserved command code

Read Response Read Response (RdResponse) Packet Name

Target Done Target Done (TgtDone) Packet Name

Broadcast Message Broadcast Message Packet Name

Fence Fence Packet Name

Atomic Read-Modify-Write Request

Sync Pattern Sync Pattern Packet Name

Interrupt Request Interrupt Request Packet Name

End of Interrupt EOIPacketName

System Management Request-WrSized

System Management Request-Broadcast

Atomic Read-Modify-Write (RMW) Request Packet Name

System Management Request WrSized Packet Name

System Management Request Broadcast Packet Name

2--8

TMS855 HyperTransport Bus Software Support

+ 68 hidden pages

Tektronix TMS855 Instruction Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

SOFTWARE WARRANTY

Table of Contents

List of Figures

List of Tables

Preface

Manual Conventions

Contacting Tektronix

Getting Started

Support Package Description

Logic Analyzer Software Compatibility

Logic Analyzer Configuration

Requirements and Restrictions

Limitations of the Support

Connecting the Logic Analyzer to a Target System

Labeling P6880 Probes

Setting Up the Support

Installing the Support Software

Support Package Setups

Clocking Options

Acquiring and Viewing Disassembled Data

Acquiring Data

Changing How Data is Displayed

Marking Cycles

Cycle Type Labels