Tektronix TMS817, TMS818 Instruction Manual

Instruction Manual

TMS817 and TMS818
PCIExpress Bus Supports

071-1214-00

www.tektronix.com

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Tektronix, Inc., P.O. Box 500, Beaverton, OR 97077

TEKTRONIX and TEK are registered trademarks of Tektronix, Inc.

SOFTWARE WARRANTY

Tektronix warrants that the media on which this software product is furnished and the encoding of the programs on the
media will be free from defects in materials and workmanship for a period of three (3) months from the date of shipment.
If a medium or encoding proves defective during the warranty period, Tektronix will provide a replacement in exc hange
for the defective medium. Except as to the media on which this software product is furnished, this software product is
provided “as is” without warranty of any kind, either express or impli ed. Tektronix does not warrant that the functions
contained in this software product will meet Customer’s requirem ents or that the operation of the programs will be
uninterrupted or error-free.

In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expira tion of the
warranty period. If Tektronix is unable to provide a replacement that is free from defects in materials and workmanship
within a reasonable time thereafter, Customer may terminate the license for this software product and return this software
product and any associated materials for credit or refund.

THIS WARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER WARRANTIES, EXPRESS OR
IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’ RESPONSIBILITY TO
REPLACE DEFECTIVE MEDIA OR REFUND CUSTOMER’S PAYMENT IS THE SOLE AND EXCLUSIVE
REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS WARRANTY. TEKTRONIX AND ITS
VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
DAMAGES IRRESPECTIVE OF WHETHER TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF
THE POSSIBILITY OF SUCH DAMAGES.

HARDWARE WARRANTY

Tektronix warrants that the products that it manufactures and sells will be free from defects in materials and workmanship
for a period of one (1) year from the date of shipment. If a product proves defec tive during this warranty period, Tektronix,
at its option, either will repair the defective product without charge for parts and labor, or will provide a replacement in
exchange for the defective product.

In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expira tion of the
warranty period and make suitable arrangements for the performance of service. Customer shall be responsible for
packaging and shipping the defective product to the service center designated by Tektronix, with shipping charges prepaid.
Tektronix shall pay for the return of the product to Customer if the shipment is to a loc ation within the country in which the
Tektronix service center is located. Customer shall be responsible for paying all shipping charges, duties, taxes, and any
other charges for products returned to any other locations.

This warranty shall not apply to any de fect, failure or damage caused by improper use or improper or inadequate
maintenance and care. Tektronix shall not be obligated to furnish service under this warranty a) to repair damage resulting
from attempts by personnel other than Tektronix representatives to install, repair or service the product; b) to repair
damage resulting from improper use or connection to incompatible equipment; c) to repair any damage or malfunction
caused by the use of non-Tektronix supplies; or d) to service a product that has been modified or integrated with other
products when the effect of such modification or integration increa ses the time or difficulty of servicing the product.

THIS WARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER WARRANTIES, EXPRESS OR
IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’ RESPONSIBILITY TO
REPAIR OR REPLACE DEFECTIVE PRODUCTS IS THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO
THE CUSTOMER FOR BREACH OF THIS WARRANTY. TEKTRONIX AND ITS VENDORS WILL NOT BE
LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE
OF WHETHER TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH
DAMAGES.

Table of Contents

Getting Started

General Safety Summary xiii..........................................

Service Safety Summary xv...........................................

Preface xvii...................................................

Manual Conventions xvii..............................................

Contacting Tektronix xviii..............................................

Product Description 1--1..............................................

Trigger Support 1--1..............................................

Logic Analyzer Software Compatibility 1--1...............................

Logic Analyzer Configuration 1--2......................................

LAI Cables 1--3.....................................................

Standard and Optional Accessories 1--4..................................

Probe Adapter Review 1--5............................................

Connect the Logic Analyzer to the Target System 1--6.......................

Task Summary 1--6...............................................

Connecting the Midbus Probe Head 1--7..............................

Connecting the Slot Board 1--10......................................

Cable Configurations 1--12..........................................

What Next 1--17......................................................

External Clocking 1--18............................................

Adjust the Preprocessor Unit Settings 1--20.............................

Connect the LAI Cables 1--22........................................

Applying Power 1--25..............................................

Removing Power 1--26.............................................

Capture Training Sequence 1--27.........................................

Troubleshooting 1--29.................................................

Self Test 1--29....................................................

Check list for Troubleshooting 1--36......................................

Care and Maintenance 1--38.............................................

Ship the Probe Adapter 1--39............................................

Operating Basics

Setting Up the Support 2--1.....................................

Installing the Support Software 2--1......................................

Support Packages 2--1................................................

Custom Clocking Option 2--2..........................................

Reference Tables 2--3.................................................

Installing Trigger Programs 2--3........................................

Loading Trigger Programs 2--3.........................................

Acquiring and Viewing Disassembled Data 2--7....................

Acquiring Data 2--7..................................................

Viewing Disassembled Data 2--7........................................

Changing How Data is Displayed 2--11....................................

Hardware-Assisted Search 2--14.........................................

Special Messages 2--20................................................

TMS817/TMS818 PCIExpress Bus Support

i

Table of Contents

Specifications

Reference

Viewing an Example of Disassembled Data 2--24............................

Specifications 3--1............................................

Circuit Description 3--1...............................................

Derived Signals 3--2..................................................

Specification Tables 3--2..............................................

Load Models 3--5....................................................

Dimensions 3--7.....................................................

Symbol Tables 4--1............................................

PCIEx1 Symbol Tables 4--1............................................

PCIEx2 Symbol Tables 4--8............................................

PCIEx4 Symbol Tables 4--16............................................

PCIEx8 Symbol Tables 4--23............................................

PCIEx16 Symbol Tables 4--36...........................................

Common Symbol Tables 4--62...........................................

Group Definitions Tables 4--69...................................

PCIEx1 Group Definitions 4--69.........................................

PCIEx2 Group Definitions 4--77.........................................

PCIEx4 Group Definitions 4--87.........................................

PCIEx8 Group Definitions 4--100.........................................

PCIEx16 Group Definitions 4--124........................................

Channel Assignment Tables 4--173.................................

Conventions 4--173....................................................

PCIEx1 4--174........................................................

PCIEx2 4--179........................................................

PCIEx4 4--184........................................................

PCIEx8 4--189........................................................

PCIEx16 4--194.......................................................

Replaceable Parts

Glossary
Index

ii

Replaceable Parts 5--1..........................................

Parts Ordering Information 5--1.........................................

TMS817/TMS818 PCIExpress Bus Support

List of Figures

Table of Contents

Figure 1--1: Configuration of the Master and Slave1 modules 1--2.....

Figure 1--2: LAI Cables 1--3.....................................

Figure 1--3: Connecting the retention fixtures 1--8..................

Figure 1--4: Connecting the probe head to the retention fixtures 1--9...

Figure 1--5: Connecting the Slot board and PCIExpress card 1--10.....

Figure 1--6: Preprocessor unit configuration for two x8-wide

unidirectional links 1--12.....................................

Figure 1--7: Preprocessor unit configuration for four x4-wide links 1--13

Figure 1--8: Preferred midbus footprint configurations 1--14..........

Figure 1--9: Preprocessor unit (front) 1--15.........................

Figure 1--10: Attaching the probe-head cables 1--16..................

Figure 1--11: External clocking connections 1--18....................

Figure 1--12: Adjust the preprocessor unit settings 1--20..............

Figure 1--13: LAI cable and preprocessor unit 1--22..................

Figure 1--14: Preprocessor unit (back) 1--23.........................

Figure 1--15: Apply LAI labels 1--24...............................

Figure 1--16: Configuration of the Master and Slave1 modules 1--25....

Figure 1--17: Training sequence display 1--28.......................

Figure 1--18: Self test connector 1--30..............................

Figure 1--19: Place the probe head in a static shielding bag 1--40.......

Figure 1--20: Place the end caps on the preprocessor 1--40.............

Figure 1--21: Place the preprocessor unit in the carton 1--41...........

Figure 2--1: Trigger window 2--4.................................

Figure 2--2: Waveform display 2--8...............................

Figure 2--3: PCIEx4 display with Extended Details ON 2--9..........

Figure 2--4: Disassembly tab in listing window 2--12..................

Figure 2--5: MWr TLP starting positions and relevant fields 2--17......

Figure 2--6: Search for a memory write to address 0A000000 2--19.....

Figure 3--1: Midbus load model 3--5..............................

Figure 3--2: Slot load model 3--5.................................

Figure 3--3: Dimensions of the preprocessor unit 3--7................

Figure 3--4: Dimensions of the cables and probe heads 3--8...........

Figure 4--1: Configuration of the Master and Slave1 modules 4--173.....

TMS817/TMS818 PCIExpress Bus Support

iii

Table of Contents

List of Tables

Table 1--1: Number and Type of modules 1--2......................

Table 1--2: Task summary 1--6...................................

Table 1--3: Extra x16 link-width signals 1--11.......................

Table 1--4: Preprocessor unit settings 1--20........................

Table 1--5: LAI cable quantities 1--23..............................

Table 1--6: Probe-head channel connections 1--30...................

Table 1--7: Test package load options 1--31.........................

Table 1--8: Front panel switch settings 1--31........................

Table 1--9: Type and number of module for test package 1--32.........

Table 1--10: Probe adaptor connections for channel E, F, G, and H 1--34

Table 1--11: Troubleshooting checklist 1--36.......................

Table 2--1: Description of special characters in the display 2--9.......

Table 2--2: Groups displayed in the listing window

(for all link widths) 2--10.....................................

Table 2--3: Logic analyzer disassembly display options 2--12..........

Table 2--4: Clause description search rules 2--17....................

Table 2--5: Training sequence messages 2--20.......................

Table 2--6: Packet framing messages 2--21..........................

Table 2--7: DLLP messages 2--22.................................

Table 2--8: TLP header messages 2--22.............................

Table 2--9: TLP payload messages 2--23............................

Table 2--10: TLP digest messages 2--23............................

Table 2--11: CRC checking messages 2--23.........................

Table 2--12: General acquisition messages 2--24.....................

Table 3--1: Derived signals 3--2..................................

Table 3--2: Electrical specifications 3--2..........................

Table 3--3: Environmental specifications 3--3......................

Table 3--4: Certifications and compliances 3--6.....................

Table 4--1: PCIEx1_TLP_fmttype symbol table 4--1................

Table 4--2: PCIEx1_TLP_msg symbol table 4--3....................

Table 4--3: PCIEx1_TLP_comp_status symbol table 4--6............

Table 4--4: PCIEx1_DLLP_type symbol table 4--7..................

Table 4--5: PCIEx2_fmttype symbol table 4--8.....................

Table 4--6: PCIEx2_msg symbol table 4--11........................

Table 4--7: PCIEx2_comp_status symbol table 4--13.................

iv

TMS817/TMS818 PCIExpress Bus Support

Table of Contents

Table 4--8: PCIEx2_DLLP_type symbol table 4--14..................

Table 4--9: PCIEx4_fmttype symbol table 4--16.....................

Table 4--10: PCIEx4_msg symbol table 4--18.......................

Table 4--11: PCIEx4_comp_status symbol table 4--20................

Table 4--12: PCIEx4_DLLP_type symbol table 4--21.................

Table 4--13: PCIEx8_fmttype symbol table 4--23....................

Table 4--14: PCIEx8_msg_L0 symbol table 4--27....................

Table 4--15: PCIEx8_msg_L4 symbol table 4--30....................

Table 4--16: PCIEx8_comp_status symbol table 4--32................

Table 4--17: PCIEx8_DLLP_type symbol table 4--33.................

Table 4--18: PCIEx16_fmttype_L0 symbol table 4--36................

Table 4--19: PCIEx16_fmttype_L4 symbol table 4--38................

Table 4--20: PCIEx16_fmttype_L8 symbol table 4--41................

Table 4--21: PCIEx16_fmttype_L12 symbol table 4--43...............

Table 4--22: PCIEx16_msg_L0 symbol table 4--45...................

Table 4--23: PCIEx16_msg_L4 symbol table 4--47...................

Table 4--24: PCIEx16_msg_L8 symbol table 4--50...................

Table 4--25: PCIEx16_msg_L12 symbol table 4--52..................

Table 4--26: PCIEx16_comp_status_L8 symbol table 4--54............

Table 4--27: PCIEx16_comp_status_L4 symbol table 4--55............

Table 4--28: PCIEx16_comp_status_L8 symbol table 4--56............

Table 4--29: PCIEx16_comp_status_L12 symbol table 4--57...........

Table 4--30: PCIEx16_DLLP_type_L0 symbol table 4--58.............

Table 4--31: PCIEx16_DLLP_type_L4 symbol table 4--59.............

Table 4--32: PCIEx16_DLLP_type_L12 symbol table 4--61............

Table 4--33: PCIEx_RecErr symbol table 4--62......................

Table 4--34: PCIEx_Rule_viol symbol table 4--63....................

Table 4--35: PCIEx_Rule_viol symbol table 4--64....................

Table 4--36: PCIEx_10b Name symbol table 4--65...................

Table 4--37: PCIEx_LN_color symbol table 4--66....................

Table 4--38: PCIEx_color symbol table 4--67........................

Table 4--39: Channel groups for PCIEx1 4--69......................

Table 4--40: L00_protocol group assignments 4--70..................

Table 4--41: L00_data8b group assignments 4--70...................

Table 4--42: L00_data10b group assignments 4--71..................

Table 4--43: Link8bit group assignments 4--71......................

Table 4--44: STP_cntr group assignments 4--71.....................

Table 4--45: TLP_fmttype group assignments 4--72..................

TMS817/TMS818 PCIExpress Bus Support

v

Table of Contents

Table 4--46: TLP_msg group assignments 4--73.....................

Table 4--47: TLP_comp_status group assignments 4--74..............

Table 4--48: DLLP_type group assignments 4--75....................

Table 4--49: L00_RecErr group assignments 4--75...................

Table 4--50: Error_bits group assignments 4--76.....................

Table 4--51: Rule_viol group assignments 4--76.....................

Table 4--52: Status group assignments 4--76........................

Table 4--53: Channel groups for PCIEx2 4--77......................

Table 4--54: L00_protocol group assignments 4--77..................

Table 4--55: L01_protocol group assignments 4--78..................

Table 4--56: L00_data8b group assignments 4--79...................

Table 4--57: L01_data8b group assignments 4--79...................

Table 4--58: L00_data10b group assignments 4--79..................

Table 4--59: L01_data10b group assignments 4--80..................

Table 4--60: Link8bit group assignments 4--80......................

Table 4--61: STP_cntr group assignments 4--81.....................

Table 4--62: TLP_fmttype group assignments 4--81..................

Table 4--63: TLP_msg group assignments 4--82.....................

Table 4--64: TLP_comp_status group assignments 4--83..............

Table 4--65: DLLP_type group assignments 4--84....................

Table 4--66: L00_RecErr group assignments 4--85...................

Table 4--67: L01_RecErr group assignments 4--85...................

Table 4--68: Error_bits group assignments 4--85.....................

Table 4--69: Rule_viol group assignments 4--85.....................

Table 4--70: Status group assignments 4--86........................

Table 4--71: Channel groups for PCIEx4 4--87......................

Table 4--72: L00_protocol group assignments 4--87..................

Table 4--73: L01_protocol group assignments 4--88..................

Table 4--74: L02_protocol group assignments 4--89..................

Table 4--75: L03_protocol group assignments 4--89..................

Table 4--76: L00_data8b group assignments 4--90...................

Table 4--77: L01_data8b group assignments 4--90...................

Table 4--78: L02_data8b group assignments 4--91...................

Table 4--79: L03_data8b group assignments 4--91...................

Table 4--80: L00_data10b group assignments 4--92..................

Table 4--81: L01_data10b group assignments 4--92..................

Table 4--82: L02_data10b group assignments 4--92..................

Table 4--83: L03_data10b group assignments 4--93..................

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TMS817/TMS818 PCIExpress Bus Support

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Table 4--84: Link8bit group assignments 4--93......................

Table 4--85: STP_cntr group assignments 4--94.....................

Table 4--86: TLP_fmttype group assignments 4--94..................

Table 4--87: TLP_msg group assignments 4--95.....................

Table 4--88: TLP_comp_status group assignments 4--96..............

Table 4--89: DLLP_type group assignments 4--97....................

Table 4--90: L00_RecErr group assignments 4--98...................

Table 4--91: L01_RecErr group assignments 4--98...................

Table 4--92: L02_RecErr group assignments 4--98...................

Table 4--93: L03_RecErr group assignments 4--99...................

Table 4--94: Error_bits group assignments 4--99.....................

Table 4--95: Rule_viol group assignments 4--99.....................

Table 4--96: Status group assignments 4--99........................

Table 4--97: Channel groups for PCIEx8 4--100......................

Table 4--98: L00_protocol group assignments 4--101..................

Table 4--99: L01_protocol group assignments 4--102..................

Table 4--100: L02_protocol group assignments 4--102.................

Table 4--101: L03_protocol group assignments 4--103.................

Table 4--102: L04_protocol group assignments 4--103.................

Table 4--103: L05_protocol group assignments 4--104.................

Table 4--104: L06_protocol group assignments 4--105.................

Table 4--105: L07_protocol group assignments 4--105.................

Table 4--106: L00_data8b group assignments 4--106..................

Table 4--107: L01_data8b group assignments 4--106..................

Table 4--108: L02_data8b group assignments 4--107..................

Table 4--109: L03_data8b group assignments 4--107..................

Table 4--110: L04_data8b group assignments 4--108..................

Table 4--111: L05_data8b group assignments 4--108...................

Table 4--112: L06_data8b group assignments 4--108..................

Table 4--113: L07_data8b group assignments 4--109..................

Table 4--114: L00_data10b group assignments 4--109.................

Table 4--115: L01_data10b group assignments 4--110.................

Table 4--116: L02_data10b group assignments 4--110.................

Table 4--117: L03_data10b group assignments 4--111.................

Table 4--118: L04_data10b group assignments 4--111.................

Table 4--119: L05_data10b group assignments 4--111.................

Table 4--120: L06_data10b group assignments 4--112.................

Table 4--121: L07_data10b group assignments 4--112.................

TMS817/TMS818 PCIExpress Bus Support

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Table of Contents

Table 4--122: Link8bit group assignments 4--113.....................

Table 4--123: STP_cntr group assignments 4--114....................

Table 4--124: TLP_fmttype group assignments 4--114.................

Table 4--125: TLP_msg_L0 group assignments 4--115.................

Table 4--126: TLP_msg_L4 group assignments 4--116.................

Table 4--127: TLP_comp_status group assignments 4--117.............

Table 4--128: DLLP_type group assignments 4--118...................

Table 4--129: L00_RecErr group assignments 4--119..................

Table 4--130: L01_RecErr group assignments 4--120..................

Table 4--131: L02_RecErr group assignments 4--120..................

Table 4--132: L03_RecErr group assignments 4--120..................

Table 4--133: L04_RecErr group assignments 4--120..................

Table 4--134: L05_RecErr group assignments 4--121..................

Table 4--135: L06_RecErr group assignments 4--121..................

Table 4--136: L07_RecErr group assignments 4--121..................

Table 4--137: Error_bits group assignments 4--122....................

Table 4--138: Rule_viol group assignments 4--122....................

Table 4--139: Status group assignments 4--122.......................

Table 4--140: Channel groups for PCIEx16 4--124....................

Table 4--141: L00_protocol group assignments 4--125.................

Table 4--142: L01_protocol group assignments 4--125.................

Table 4--143: L02_protocol group assignments 4--126.................

Table 4--144: L03_protocol group assignments 4--127.................

Table 4--145: L04_protocol group assignments 4--127.................

Table 4--146: L05_protocol group assignments 4--128.................

Table 4--147: L06_protocol group assignments 4--129.................

Table 4--148: L07_protocol group assignments 4--129.................

Table 4--149: L08_protocol group assignments 4--130.................

Table 4--150: L09_protocol group assignments 4--131.................

Table 4--151: L10_protocol group assignments 4--131.................

Table 4--152: L11_protocol group assignments 4--132.................

Table 4--153: L12_protocol group assignments 4--133.................

Table 4--154: L13_protocol group assignments 4--133.................

Table 4--155: L14_protocol group assignments 4--134.................

Table 4--156: L15_protocol group assignments 4--135.................

Table 4--157: L00_data8b group assignments 4--135..................

Table 4--158: L01_data8b group assignments 4--136..................

Table 4--159: 02_data8b group assignments 4--136....................

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Table 4--160: L03_data8b group assignments 4--136..................

Table 4--161: L04_data8b group assignments 4--137..................

Table 4--162: L05_data8b group assignments 4--137..................

Table 4--163: L06_data8b group assignments 4--138..................

Table 4--164: L07_data8b group assignments 4--138..................

Table 4--165: L08_data8b group assignments 4--138..................

Table 4--166: L09_data8b group assignments 4--139..................

Table 4--167: L10_data8b group assignments 4--139..................

Table 4--168: L11_data8b group assignments 4--140..................

Table 4--169: L12_data8b group assignments 4--140..................

Table 4--170: L13_data8b group assignments 4--140..................

Table 4--171: L14_data8b group assignments 4--141..................

Table 4--172: L15_data8b group assignments 4--141..................

Table 4--173: L00_data10b group assignments 4--142.................

Table 4--174: L01_data10b group assignments 4--142.................

Table 4--175: L02_data10b group assignments 4--142.................

Table 4--176: L03_data10b group assignments 4--143.................

Table 4--177: L04_data10b group assignments 4--143.................

Table 4--178: L05_data10b group assignments 4--144.................

Table 4--179: L06_data10b group assignments 4--144.................

Table 4--180: L07_data10b group assignments 4--145.................

Table 4--181: L08_data10b group assignments 4--145.................

Table 4--182: L09_data10b group assignments 4--146.................

Table 4--183: L10_data10b group assignments 4--146.................

Table 4--184: L11_data10b group assignments 4--147.................

Table 4--185: L12_data10b group assignments 4--147.................

Table 4--186: L13_data10b group assignments 4--147.................

Table 4--187: L14_data10b group assignments 4--148.................

Table 4--188: L15_data10b group assignments 4--148.................

Table 4--189: Link8bit group assignments 4--149.....................

Table 4--190: STP_cntr group assignments 4--151....................

Table 4--191: TLP_fmttype_L0 group assignments 4--151..............

Table 4--192: TLP_fmttype_L4 group assignments 4--152..............

Table 4--193: TLP_fmttype_L8 group assignments 4--153..............

Table 4--194: TLP_fmttype_L12 group assignments 4--153.............

Table 4--195: TLP_msg_L0 group assignments 4--154.................

Table 4--196: TLP_msg_L4 group assignments 4--155.................

Table 4--197: TLP_msg_L8 group assignments 4--156.................

TMS817/TMS818 PCIExpress Bus Support

ix

Table of Contents

Table 4--198: TLP_msg_L12 group assignments 4--157................

Table 4--199: TLP_comp_status_L0 group assignments 4--158..........

Table 4--200: TLP_comp_status_L4 group assignments 4--159..........

Table 4--201: TLP_comp_status_L8 group assignments 4--160..........

Table 4--202: TLP_comp_status_L12 group assignments 4--160.........

Table 4--203: DLLP_type_L0 group assignments 4--161...............

Table 4--204: DLLP_type_L4 group assignments 4--162...............

Table 4--205: DLLP_type_L8 group assignments 4--162...............

Table 4--206: DLLP_type_L12 group assignments 4--163..............

Table 4--207: L00_RecErr group assignments 4--164..................

Table 4--208: L01_RecErr group assignments 4--164..................

Table 4--209: L02_RecErr group assignments 4--164..................

Table 4--210: L03_RecErr group assignments 4--165..................

Table 4--211: L04_RecErr group assignments 4--165..................

Table 4--212: L05_RecErr group assignments 4--165..................

Table 4--213: L06_RecErr group assignments 4--165..................

Table 4--214: L07_RecErr group assignments 4--166..................

Table 4--215: L08_RecErr group assignments 4--166..................

Table 4--216: L09_RecErr group assignments 4--166..................

Table 4--217: L10_RecErr group assignments 4--167..................

Table 4--218: L11_RecErr group assignments 4--167..................

Table 4--219: L12_RecErr group assignments 4--167..................

Table 4--220: L13_RecErr group assignments 4--168..................

Table 4--221: L14_RecErr group assignments 4--168..................

Table 4--222: L15_RecErr group assignments 4--168..................

Table 4--223: Error_bits group assignments 4--168....................

Table 4--224: Rule_viol group assignments 4--169....................

Table 4--225: Status group assignments 4--169.......................

Table 4--226: Explanation of LXX_RecErr group 4--170...............

Table 4--227: Explanation of Rule Violation Group 4--171.............

Table 4--228: Explanation of STP_Packet_0 and

STP_Packet_1 signals 4--171..................................

Table 4--229: Explanation of SDP_Packet_0 and

SDP_Packet_1 signals 4--171..................................

Table 4--230: Explanation of STP_Packet_3 4--171...................

Table 4--231: Explanation of SDP_Packet_3 4--172...................

Table 4--232: Explanation of STP_Packet_2 4--172...................

Table 4--233: Explanation of SDP_Packet_2 4--172...................

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TMS817/TMS818 PCIExpress Bus Support

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Table 4--234: PCIEx1 Clock channels

(also stored as acquisition data) 4--174..........................

Table 4--235: PCIEx1 QUAL channels

(also stored as acquisition data) 4--174..........................

Table 4--236: PCIEx1 A channels 4--174............................

Table 4--237: PCIEx1 D channels 4--176............................

Table 4--238: PCIEx1 C channels 4--177............................

Table 4--239: PCIEx2 Clock channels

(also stored as acquisition data 4--179...........................

Table 4--240: PCIEx2 QUAL channels

(also stored as acquisition data) 4--179..........................

Table 4--241: PCIEx2 A channels 4--179............................

Table 4--242: PCIEx2 D channels 4--181............................

Table 4--243: PCIEx2 C channels 4--182............................

Table 4--244: PCIEx4 Clock channels

(also stored as acquisition data) 4--184..........................

Table 4--245: PCIEx4 QUAL channels

(also stored as acquisition data) 4--184..........................

Table 4--246: PCIEx4 A channels 4--184............................

Table 4--247: PCIEx4 D channels 4--186............................

Table 4--248: PCIEx4 C channels 4--187............................

Table 4--249: PCIEx8 Clock channels

(also stored as acquisition data) 4--189..........................

Table 4--250: PCIEx8 QUAL channels

(also stored as acquisition data) 4--189..........................

Table 4--251: PCIEx8 A channels 4--189............................

Table 4--252: PCIEx8 D channels 4--191............................

Table 4--253: PCIEx8 C channels 4--192............................

Table 4--254: PCIEx8 E channels 4--193............................

Table 4--255: PCIEx16 Clock

(also stored as acquisition data) 4--194..........................

Table 4--256: PCIEx16 QUAL channels

(also stored as acquisition data) 4--195.............................

Table 4--257: PCIEx16 A channels 4--195...........................

Table 4--258: PCIEx16 D channels 4--196...........................

Table 4--259: PCIEx16 C channels 4--198...........................

Table 4--260: PCIEx16 E channels 4--199...........................

Table 4--261: PCIEx16 Clock channels

(also stored as acquisition data) 4--200..........................

TMS817/TMS818 PCIExpress Bus Support

xi

Table of Contents

Table 4--262: PCIEx16 QUAL channels

(also stored as acquisition data) 4--200..........................

Table 4--263: PCIEx16 Slave A channels 4--201......................

Table 4--264: PCIEx16 Slave D channels 4--202......................

Table 4--265: PCIEx16 C channels 4--203...........................

Table 4--266: PCIEx16 E channels 4--204...........................

xii

TMS817/TMS818 PCIExpress Bus Support

General Safety Summary

Review the following safety precautions to avoid injury and prevent damage to
this product or any products connected to it. To avoid potential hazards, use this
product only as specified.

Only qualified personnel should perform service procedures.

While using this product, you may need to access other parts of the system. Read
the General Safety Summary in other system manuals for warnings and cautions
related to operating the system.

ToAvoidFireor

Personal Injury

Use Proper Power Cord. Use only the power cord specified for this product and
certified for the country of use.

Connect and Disconnect Properly. Do not connect or disconnect probes or test
leads while they are connected to a voltage source.

Connect and Disconnect Properly. Connect the probe output to the measurement
instrument before connecting the probe to the circuit under test. Disconnect the
probe input and the probe ground from the circuit under test before disconnecting
the probe from the measurement instrument.

Ground the Product. This product is grounded through the grounding conductor
of the power cord. To avoid electric shock, the grounding conductor must be
connected to earth ground. Before making connections to the input or output
terminals of the product, ensure that the product is properly grounded.

Observe All Terminal Ratings. T o avoid fire or shock hazard, observe all ratings
and markings on the product. Consult the product manual for further ratings
information before making connections to the product.

Do not apply a potential to any terminal, including the common terminal, that
exceeds the maximum rating of that terminal.

Do Not Operate Without Covers. Do not operate this product with covers or panels
removed.

Use Proper Fuse. Use only the fuse type and rating specified for this product.

Avoid Exposed Circuitry. Do not touch exposed connections and components

when power is present.

Do Not Operate With Suspected Failures. If you suspect there is damage to this
product, have it inspected by qualified service personnel.

Do Not Operate in Wet/Damp Conditions.

Do Not Operate in an Explosive Atmosphere.

Keep Product Surfaces Clean and Dry.

TMS817/TMS818 PCIExpress Bus Support

xiii

General Safety Summary

Provide Proper Ventilation. Refer to the manual’s installation instructions for
details on installing the product so it has proper ventilation.

Symbols and Terms

Terms in this Manual. These terms may appear in this manual:

WARNING. Warning statements identify conditions or practices that could result
in injury or loss of life.

CAUTION. Caution statements identify conditions or practices that could result in
damage to this product or other property.

Terms on the Product. These terms may appear on the product:

DANGER indicates an injury hazard immediately accessible as you read the
marking.

WARNING indicates an injury hazard not immediately accessible as you read the
marking.

CAUTION indicates a hazard to property including the product.

Symbols on the Product. The following symbols may appear on the product:

CAUTION

Refer to Manual

CAUTION

Hot Surface

WARNING

High Voltage

Protective Ground

(Earth) Terminal

Mains Disconnected

OFF (Power)

Mains Connected

ON (Power)

xiv

TMS817/TMS818 PCIExpress Bus Support

Service Safety Summary

Only qualified personnel should perform service procedures. Read this Service
Safety Summary and the General Safety Summary before performing any service

procedures.

Do Not Service Alone. Do not perform internal service or adjustments of this
product unless another person capable of rendering first aid and resuscitation is
present.

Disconnect Power. To avoid electric shock, switch off the instrument power, then
disconnect the power cord from the mains power.

Use Care When Servicing With Power On. Dangerous voltages or currents may
exist in this product. Disconnect power, remove battery (if applicable), and
disconnect test leads before removing protective panels, soldering, or replacing
components.

To avoid electric shock, do not touch exposed connections.

TMS817/TMS818 PCIExpress Bus Support

xv

Service Safety Summary

xvi

TMS817/TMS818 PCIExpress Bus Support

Preface

Manual Conventions

This instruction manual contains specific information about the TMS817 and
TMS818 Bus support products and is part of a set of information on how to
operate this product on compatible Tektronix logic analyzers.

If you are not familiar with operating support products, you need to supplement
this instruction manual with introductory information about how to set up and
run a support package on the logic analyzer. Go to the logic analyzer online help
index under Microprocessor support packages.

For help in understanding terms in this manual that may be new to you, see the
Glossary at the end of the manual.

This manual uses the following conventions:

H The term “disassembler” refers to the software that decodes bus cycles into

instruction mnemonics and cycle types.

H The terms “Master” and “Slave” refer to modules that are located in

numbered slots (see Figure 1--1 on page 1--2).

TMS817/TMS818 PCIExpress Bus Support

xvii

Preface

Contacting Tektronix

Phone [phone]*

Address Tektronix, Inc.

Department or name (if known)
14200 SW Karl Braun Drive
P.O. Box 500
Beaverton, OR 97077
USA

Web site www.tektronix.com

Sales support 1-800-833-9200, select option 1*

Service support 1-800-833-9200, select option 2*

Technical support Email: [e-mail]

1-800-833-9200, select option 3*

6:00 a.m. -- 5:00 p.m. Pacific time

* This phone number is toll free in North America. After office hours, please leave a

voice mail message.
Outside North America, contact a Tektronix sales office or distributor; see the
Tektronix web site for a list of offices.

xviii

TMS817/TMS818 PCIExpress Bus Support

Getting Started

Getting Started

Product Description

This section contains the following information for the TMS817 and TMS818
PCIExpress Bus Support products:

H Product description

H Logic analyzer configuration

H Connecting the logic analyzer to the target system

The TMS817 and TMS818 probe adapters are designed to connect to a midbus
or slot target system. This allows you to acquire data from a PCIExpress Bus
with little effect on the target system.

When a probe adapter is connected to the target system, the signals from the
PCIExpress system flow through the probe head, into the preprocessor unit, and
then through the LAI cables to the logic analyzer.

The TMS817 and TMS818 bus software provides decoding of the serial-data
stream. There are five software packages, x1, x2, x4, x8, and x16, one for each
of the PCIExpress bus-width links and three test software packages.

H TMS817 supports x1, x2, x4, x8, and x16 lane widths

H TMS818 supports x1, x2, and x4 lane widths

The probe adapter assumes that all lanes in a link are affected the same way by
repeater chips. Specifically, if the repeater chip adds or deletes x SKIP symbol(s)
from a SKIP packet on one lane it adds or deletes x SKIP symbols from the same
SKIP packet on all lanes.

Trigger Support

Trigger libraries containing EasyTrigger programs are provided for each support
package. See page 2--3 for a list of the trigger programs.

Logic Analyzer Software Compatibility

The label on the CD-ROM states that version 4.2 of the logic analyzer software
is compatible with the TMS817 and TMS818 products.

TMS817/TMS818 PCIExpress Bus Support

1- 1

Getting Started

Logic Analyzer Configuration

To use either of the probe adapters, you need a minimum module speed of
450 MHz. See Table 1--1 for the number and type of modules needed for
different lane widths.

If you use more than one module, the modules must be merged. See the logic
analyzer online help for how to merge your modules.

Table 1- 1: Number and Type of modules

Lane width Module type

x1, x2, x4 TLA7AX3* or TLA7AX4** 1

x8 TLA7AX4** 1

x16 TLA7AX4** 2 (merged)

* 102 channels

** 136 channels

Module
number

The term Master (M) module refers to the middle module of a 5-wide module
chassis. The term Slave1 (S1) module refers to the module to the right of the
Master module of a 5-wide module chassis. Figure 1--1 s hows the configuration
for a 2-wide module merge (x16-wide link only).

x16 wide link needs

two merged modules

x1, x2, x4, x8 wide link

M
A
S
T
E
R

S
L
A
V
E
1

1- 2

Figure 1- 1: Configuration of the Master and Slave1 modules

TMS817/TMS818 PCIExpress Bus Support

LAI Cables

Getting Started

The LAI cables are specifically designed for use with the TMS817 and TMS818
probe adapter products. The link widths you choose require a specific number of
LAI cables. For more detailed information on connecting your LAI cables to the
preprocessor unit, see page 1--22.

LAI cables

TMS817 probe adapter

Figure 1- 2: LAI Cables

Labeling

LAI Cables

Preprocessor unit

(Rear view)

Module end of cables

To apply labels to the LAI cables, see page 1--24.

TMS817/TMS818 PCIExpress Bus Support

1- 3

Getting Started

Standard and Optional Accessories

A complete list of standard and optional accessories is provided in the Replaceable
Parts List on page 5--3.

For the TMS817 product:

H The following options are available only when ordering a TMS817 product.

Option 01 — midbus probe head

Option 02 — x16 slot board

Option 03 — x8 slot board

Option 04 — LAI cables (4)

For an additional midbus probe head assembly with attaching parts order:

H TMSIC6 — midbus probe head for the TMS817

For the TMS818 product:

H The following options are available only when ordering a TMS818 product.

Option 01 — midbus probe head

Option 02 — x4 board

Option 03 — x1 board

Option 04— LAI cables (2)

For an additional midbus probe head assembly with attaching parts order:

H TMSIC8 — midbus probe head for TMS818

1- 4

TMS817/TMS818 PCIExpress Bus Support

Probe Adapter Review

Getting Started

Review the electrical specifications beginning on page 3--1 as they relate to the
target system, as well as the following descriptions of other product information.

System Data Rate

Nonintrusive Acquisition

Storage Qualified Data

Bus Width

Linking of Requests to

Completions

The probe adapters are designed to acquire data from a PCIExpress bus operating
at 2.5 GT/s and have been tested at
adapters are capable of acquiring spread spectrum data at 0.5 ppm at a rate of
33 KHz. An external clock is required for acquiring data at
and for spread spectrum data.

Contact your Tektronix sales representative for current information on the fastest
buses supported.

The probe adapters do not modify or present signals back to the target system.

The disassembler is not designed to work with gaps in the acquisition data.
Disassembly of storage qualified data can be indeterminate and incorrect.

The TMS817 and TMS818 products support bus link widths of x1, x2, x4, x,8,
and x16. The TMS817 product supports bus link widths of x1, x2, and x4.

Linking of Requests to Completions across separate links and analysis of
separate directions on the same link are not supported in the disassembler. Only
timestamp correlation is available.

±10% of the nominal frequency. These probe

±10% of 2.5 GT/s

Lane Changes

Detect Mechanism

Triggering

Training Packets

Packet Payload

TMS817/TMS818 PCIExpress Bus Support

On-the-fly lane reordering and link-width adjustments are not supported.

The detect mechanism is not supported.

Due to the logic analyzer trigger resource, triggering capabilities are different for
different width links.

Training packets are captured and displayed as they are acquired from the link,
but lane ordering and polarity settings need to be set manually.

Only PCIExpress protocol tracking is performed. The disassembler does not
perform decoding for any packet payloads.

1- 5

Getting Started

Connect the Logic Analyzer to the Target System

Read the entire following section before beginning the installation procedure.

Tools

Task Summary

The following is a list of required tools:

H Flatbladed screwdriver (0.1 inch tip width) to adjust the Width or Mode

switch

H POZIDRIV (PZ1) screwdriver to connect the clam shell housings on the

preprocessor unit.

H Optional: A torque wrench helps to ensure reliable connections by meeting

the nominal torque values that may be listed in these instructions. When
attaching screws to the probe head use 4 in-lbs (0.451 Newton meters) of
torque.

CAUTION. To prevent static damage to the probe adapter, the LAI cables, and the
module, handle components only in a static-free environment.

Always wear a grounding wrist strap, heel strap, or similar device while
handling a probe adapter.

Table 1--2 list the tasks that you must do to connect either a midbus probe
adapter or a slot board to the logic analyzer.

Table 1- 2: Task summary

1- 6

Tasks See page

Solder the retention fixtures and attach the interconnect strip to a mi dbus
footprint on either the target system or the slot board.

Connect the midbus probe head to the midbus footprint. 1--9

(Slot board only) Connect the Slot board. 1--10

Connect the plugs on the midbus cables to the front of the preprocessor
unit.

Connect External Clocking. 1--18

Adjust the preprocessor settings. 1--20

Connect the LAI cables between the preprocessor unit and logic analyzer. 1--23

Check the lane polarity and lane order. 1--27

1--8

1--12

TMS817/TMS818 PCIExpress Bus Support