Tektronix TMS817, TMS818 Instruction Manual

Instruction Manual

TMS817 and TMS818 PCIExpress Bus Supports

071-1214-00

www.tektronix.com

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Tektronix, Inc., P.O. Box 500, Beaverton, OR 97077

TEKTRONIX and TEK are registered trademarks of Tektronix, Inc.

SOFTWARE WARRANTY

Tektronix warrants that the media on which this software product is furnished and the encoding of the programs on the media will be free from defects in materials and workmanship for a period of three (3) months from the date of shipment. If a medium or encoding proves defective during the warranty period, Tektronix will provide a replacement in exc hange for the defective medium. Except as to the media on which this software product is furnished, this software product is provided “as is” without warranty of any kind, either express or impli ed. Tektronix does not warrant that the functions contained in this software product will meet Customer’s requirem ents or that the operation of the programs will be uninterrupted or error-free.

In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expira tion of the warranty period. If Tektronix is unable to provide a replacement that is free from defects in materials and workmanship within a reasonable time thereafter, Customer may terminate the license for this software product and return this software product and any associated materials for credit or refund.

THIS WARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER WARRANTIES, EXPRESS OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’ RESPONSIBILITY TO REPLACE DEFECTIVE MEDIA OR REFUND CUSTOMER’S PAYMENT IS THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS WARRANTY. TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.

HARDWARE WARRANTY

Tektronix warrants that the products that it manufactures and sells will be free from defects in materials and workmanship for a period of one (1) year from the date of shipment. If a product proves defec tive during this warranty period, Tektronix, at its option, either will repair the defective product without charge for parts and labor, or will provide a replacement in exchange for the defective product.

In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expira tion of the warranty period and make suitable arrangements for the performance of service. Customer shall be responsible for packaging and shipping the defective product to the service center designated by Tektronix, with shipping charges prepaid. Tektronix shall pay for the return of the product to Customer if the shipment is to a loc ation within the country in which the Tektronix service center is located. Customer shall be responsible for paying all shipping charges, duties, taxes, and any other charges for products returned to any other locations.

This warranty shall not apply to any de fect, failure or damage caused by improper use or improper or inadequate maintenance and care. Tektronix shall not be obligated to furnish service under this warranty a) to repair damage resulting from attempts by personnel other than Tektronix representatives to install, repair or service the product; b) to repair damage resulting from improper use or connection to incompatible equipment; c) to repair any damage or malfunction caused by the use of non-Tektronix supplies; or d) to service a product that has been modified or integrated with other products when the effect of such modification or integration increa ses the time or difficulty of servicing the product.

THIS WARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER WARRANTIES, EXPRESS OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’ RESPONSIBILITY TO REPAIR OR REPLACE DEFECTIVE PRODUCTS IS THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS WARRANTY. TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.

Getting Started

General Safety Summary xiii..........................................

Service Safety Summary xv...........................................

Preface xvii...................................................

Manual Conventions xvii..............................................

Contacting Tektronix xviii..............................................

Product Description 1--1..............................................

Trigger Support 1--1..............................................

Logic Analyzer Software Compatibility 1--1...............................

Logic Analyzer Configuration 1--2......................................

LAI Cables 1--3.....................................................

Standard and Optional Accessories 1--4..................................

Probe Adapter Review 1--5............................................

Connect the Logic Analyzer to the Target System 1--6.......................

Task Summary 1--6...............................................

Connecting the Midbus Probe Head 1--7..............................

Connecting the Slot Board 1--10......................................

Cable Configurations 1--12..........................................

What Next 1--17......................................................

External Clocking 1--18............................................

Adjust the Preprocessor Unit Settings 1--20.............................

Connect the LAI Cables 1--22........................................

Applying Power 1--25..............................................

Removing Power 1--26.............................................

Capture Training Sequence 1--27.........................................

Troubleshooting 1--29.................................................

Self Test 1--29....................................................

Check list for Troubleshooting 1--36......................................

Care and Maintenance 1--38.............................................

Ship the Probe Adapter 1--39............................................

Operating Basics

Setting Up the Support 2--1.....................................

Installing the Support Software 2--1......................................

Support Packages 2--1................................................

Custom Clocking Option 2--2..........................................

Reference Tables 2--3.................................................

Installing Trigger Programs 2--3........................................

Loading Trigger Programs 2--3.........................................

Acquiring and Viewing Disassembled Data 2--7....................

Acquiring Data 2--7..................................................

Viewing Disassembled Data 2--7........................................

Changing How Data is Displayed 2--11....................................

Hardware-Assisted Search 2--14.........................................

Special Messages 2--20................................................

TMS817/TMS818 PCIExpress Bus Support

Table of Contents

Specifications

Reference

Viewing an Example of Disassembled Data 2--24............................

Specifications 3--1............................................

Circuit Description 3--1...............................................

Derived Signals 3--2..................................................

Specification Tables 3--2..............................................

Load Models 3--5....................................................

Dimensions 3--7.....................................................

Symbol Tables 4--1............................................

PCIEx1 Symbol Tables 4--1............................................

PCIEx2 Symbol Tables 4--8............................................

PCIEx4 Symbol Tables 4--16............................................

PCIEx8 Symbol Tables 4--23............................................

PCIEx16 Symbol Tables 4--36...........................................

Common Symbol Tables 4--62...........................................

Group Definitions Tables 4--69...................................

PCIEx1 Group Definitions 4--69.........................................

PCIEx2 Group Definitions 4--77.........................................

PCIEx4 Group Definitions 4--87.........................................

PCIEx8 Group Definitions 4--100.........................................

PCIEx16 Group Definitions 4--124........................................

Channel Assignment Tables 4--173.................................

Conventions 4--173....................................................

PCIEx1 4--174........................................................

PCIEx2 4--179........................................................

PCIEx4 4--184........................................................

PCIEx8 4--189........................................................

PCIEx16 4--194.......................................................

Replaceable Parts

Glossary Index

Replaceable Parts 5--1..........................................

Parts Ordering Information 5--1.........................................

TMS817/TMS818 PCIExpress Bus Support

List of Figures

Table of Contents

Figure 1--1: Configuration of the Master and Slave1 modules 1--2.....

Figure 1--2: LAI Cables 1--3.....................................

Figure 1--3: Connecting the retention fixtures 1--8..................

Figure 1--4: Connecting the probe head to the retention fixtures 1--9...

Figure 1--5: Connecting the Slot board and PCIExpress card 1--10.....

Figure 1--6: Preprocessor unit configuration for two x8-wide

unidirectional links 1--12.....................................

Figure 1--7: Preprocessor unit configuration for four x4-wide links 1--13

Figure 1--8: Preferred midbus footprint configurations 1--14..........

Figure 1--9: Preprocessor unit (front) 1--15.........................

Figure 1--10: Attaching the probe-head cables 1--16..................

Figure 1--11: External clocking connections 1--18....................

Figure 1--12: Adjust the preprocessor unit settings 1--20..............

Figure 1--13: LAI cable and preprocessor unit 1--22..................

Figure 1--14: Preprocessor unit (back) 1--23.........................

Figure 1--15: Apply LAI labels 1--24...............................

Figure 1--16: Configuration of the Master and Slave1 modules 1--25....

Figure 1--17: Training sequence display 1--28.......................

Figure 1--18: Self test connector 1--30..............................

Figure 1--19: Place the probe head in a static shielding bag 1--40.......

Figure 1--20: Place the end caps on the preprocessor 1--40.............

Figure 1--21: Place the preprocessor unit in the carton 1--41...........

Figure 2--1: Trigger window 2--4.................................

Figure 2--2: Waveform display 2--8...............................

Figure 2--3: PCIEx4 display with Extended Details ON 2--9..........

Figure 2--4: Disassembly tab in listing window 2--12..................

Figure 2--5: MWr TLP starting positions and relevant fields 2--17......

Figure 2--6: Search for a memory write to address 0A000000 2--19.....

Figure 3--1: Midbus load model 3--5..............................

Figure 3--2: Slot load model 3--5.................................

Figure 3--3: Dimensions of the preprocessor unit 3--7................

Figure 3--4: Dimensions of the cables and probe heads 3--8...........

Figure 4--1: Configuration of the Master and Slave1 modules 4--173.....

TMS817/TMS818 PCIExpress Bus Support

iii

Table of Contents

List of Tables

Table 1--1: Number and Type of modules 1--2......................

Table 1--2: Task summary 1--6...................................

Table 1--3: Extra x16 link-width signals 1--11.......................

Table 1--4: Preprocessor unit settings 1--20........................

Table 1--5: LAI cable quantities 1--23..............................

Table 1--6: Probe-head channel connections 1--30...................

Table 1--7: Test package load options 1--31.........................

Table 1--8: Front panel switch settings 1--31........................

Table 1--9: Type and number of module for test package 1--32.........

Table 1--10: Probe adaptor connections for channel E, F, G, and H 1--34

Table 1--11: Troubleshooting checklist 1--36.......................

Table 2--1: Description of special characters in the display 2--9.......

Table 2--2: Groups displayed in the listing window

(for all link widths) 2--10.....................................

Table 2--3: Logic analyzer disassembly display options 2--12..........

Table 2--4: Clause description search rules 2--17....................

Table 2--5: Training sequence messages 2--20.......................

Table 2--6: Packet framing messages 2--21..........................

Table 2--7: DLLP messages 2--22.................................

Table 2--8: TLP header messages 2--22.............................

Table 2--9: TLP payload messages 2--23............................

Table 2--10: TLP digest messages 2--23............................

Table 2--11: CRC checking messages 2--23.........................

Table 2--12: General acquisition messages 2--24.....................

Table 3--1: Derived signals 3--2..................................

Table 3--2: Electrical specifications 3--2..........................

Table 3--3: Environmental specifications 3--3......................

Table 3--4: Certifications and compliances 3--6.....................

Table 4--1: PCIEx1_TLP_fmttype symbol table 4--1................

Table 4--2: PCIEx1_TLP_msg symbol table 4--3....................

Table 4--3: PCIEx1_TLP_comp_status symbol table 4--6............

Table 4--4: PCIEx1_DLLP_type symbol table 4--7..................

Table 4--5: PCIEx2_fmttype symbol table 4--8.....................

Table 4--6: PCIEx2_msg symbol table 4--11........................

Table 4--7: PCIEx2_comp_status symbol table 4--13.................

TMS817/TMS818 PCIExpress Bus Support

Table of Contents

Table 4--8: PCIEx2_DLLP_type symbol table 4--14..................

Table 4--9: PCIEx4_fmttype symbol table 4--16.....................

Table 4--10: PCIEx4_msg symbol table 4--18.......................

Table 4--11: PCIEx4_comp_status symbol table 4--20................

Table 4--12: PCIEx4_DLLP_type symbol table 4--21.................

Table 4--13: PCIEx8_fmttype symbol table 4--23....................

Table 4--14: PCIEx8_msg_L0 symbol table 4--27....................

Table 4--15: PCIEx8_msg_L4 symbol table 4--30....................

Table 4--16: PCIEx8_comp_status symbol table 4--32................

Table 4--17: PCIEx8_DLLP_type symbol table 4--33.................

Table 4--18: PCIEx16_fmttype_L0 symbol table 4--36................

Table 4--19: PCIEx16_fmttype_L4 symbol table 4--38................

Table 4--20: PCIEx16_fmttype_L8 symbol table 4--41................

Table 4--21: PCIEx16_fmttype_L12 symbol table 4--43...............

Table 4--22: PCIEx16_msg_L0 symbol table 4--45...................

Table 4--23: PCIEx16_msg_L4 symbol table 4--47...................

Table 4--24: PCIEx16_msg_L8 symbol table 4--50...................

Table 4--25: PCIEx16_msg_L12 symbol table 4--52..................

Table 4--26: PCIEx16_comp_status_L8 symbol table 4--54............

Table 4--27: PCIEx16_comp_status_L4 symbol table 4--55............

Table 4--28: PCIEx16_comp_status_L8 symbol table 4--56............

Table 4--29: PCIEx16_comp_status_L12 symbol table 4--57...........

Table 4--30: PCIEx16_DLLP_type_L0 symbol table 4--58.............

Table 4--31: PCIEx16_DLLP_type_L4 symbol table 4--59.............

Table 4--32: PCIEx16_DLLP_type_L12 symbol table 4--61............

Table 4--33: PCIEx_RecErr symbol table 4--62......................

Table 4--34: PCIEx_Rule_viol symbol table 4--63....................

Table 4--35: PCIEx_Rule_viol symbol table 4--64....................

Table 4--36: PCIEx_10b Name symbol table 4--65...................

Table 4--37: PCIEx_LN_color symbol table 4--66....................

Table 4--38: PCIEx_color symbol table 4--67........................

Table 4--39: Channel groups for PCIEx1 4--69......................

Table 4--40: L00_protocol group assignments 4--70..................

Table 4--41: L00_data8b group assignments 4--70...................

Table 4--42: L00_data10b group assignments 4--71..................

Table 4--43: Link8bit group assignments 4--71......................

Table 4--44: STP_cntr group assignments 4--71.....................

Table 4--45: TLP_fmttype group assignments 4--72..................

TMS817/TMS818 PCIExpress Bus Support

Table of Contents

Table 4--46: TLP_msg group assignments 4--73.....................

Table 4--47: TLP_comp_status group assignments 4--74..............

Table 4--48: DLLP_type group assignments 4--75....................

Table 4--49: L00_RecErr group assignments 4--75...................

Table 4--50: Error_bits group assignments 4--76.....................

Table 4--51: Rule_viol group assignments 4--76.....................

Table 4--52: Status group assignments 4--76........................

Table 4--53: Channel groups for PCIEx2 4--77......................

Table 4--54: L00_protocol group assignments 4--77..................

Table 4--55: L01_protocol group assignments 4--78..................

Table 4--56: L00_data8b group assignments 4--79...................

Table 4--57: L01_data8b group assignments 4--79...................

Table 4--58: L00_data10b group assignments 4--79..................

Table 4--59: L01_data10b group assignments 4--80..................

Table 4--60: Link8bit group assignments 4--80......................

Table 4--61: STP_cntr group assignments 4--81.....................

Table 4--62: TLP_fmttype group assignments 4--81..................

Table 4--63: TLP_msg group assignments 4--82.....................

Table 4--64: TLP_comp_status group assignments 4--83..............

Table 4--65: DLLP_type group assignments 4--84....................

Table 4--66: L00_RecErr group assignments 4--85...................

Table 4--67: L01_RecErr group assignments 4--85...................

Table 4--68: Error_bits group assignments 4--85.....................

Table 4--69: Rule_viol group assignments 4--85.....................

Table 4--70: Status group assignments 4--86........................

Table 4--71: Channel groups for PCIEx4 4--87......................

Table 4--72: L00_protocol group assignments 4--87..................

Table 4--73: L01_protocol group assignments 4--88..................

Table 4--74: L02_protocol group assignments 4--89..................

Table 4--75: L03_protocol group assignments 4--89..................

Table 4--76: L00_data8b group assignments 4--90...................

Table 4--77: L01_data8b group assignments 4--90...................

Table 4--78: L02_data8b group assignments 4--91...................

Table 4--79: L03_data8b group assignments 4--91...................

Table 4--80: L00_data10b group assignments 4--92..................

Table 4--81: L01_data10b group assignments 4--92..................

Table 4--82: L02_data10b group assignments 4--92..................

Table 4--83: L03_data10b group assignments 4--93..................

TMS817/TMS818 PCIExpress Bus Support

Table of Contents

Table 4--84: Link8bit group assignments 4--93......................

Table 4--85: STP_cntr group assignments 4--94.....................

Table 4--86: TLP_fmttype group assignments 4--94..................

Table 4--87: TLP_msg group assignments 4--95.....................

Table 4--88: TLP_comp_status group assignments 4--96..............

Table 4--89: DLLP_type group assignments 4--97....................

Table 4--90: L00_RecErr group assignments 4--98...................

Table 4--91: L01_RecErr group assignments 4--98...................

Table 4--92: L02_RecErr group assignments 4--98...................

Table 4--93: L03_RecErr group assignments 4--99...................

Table 4--94: Error_bits group assignments 4--99.....................

Table 4--95: Rule_viol group assignments 4--99.....................

Table 4--96: Status group assignments 4--99........................

Table 4--97: Channel groups for PCIEx8 4--100......................

Table 4--98: L00_protocol group assignments 4--101..................

Table 4--99: L01_protocol group assignments 4--102..................

Table 4--100: L02_protocol group assignments 4--102.................

Table 4--101: L03_protocol group assignments 4--103.................

Table 4--102: L04_protocol group assignments 4--103.................

Table 4--103: L05_protocol group assignments 4--104.................

Table 4--104: L06_protocol group assignments 4--105.................

Table 4--105: L07_protocol group assignments 4--105.................

Table 4--106: L00_data8b group assignments 4--106..................

Table 4--107: L01_data8b group assignments 4--106..................

Table 4--108: L02_data8b group assignments 4--107..................

Table 4--109: L03_data8b group assignments 4--107..................

Table 4--110: L04_data8b group assignments 4--108..................

Table 4--111: L05_data8b group assignments 4--108...................

Table 4--112: L06_data8b group assignments 4--108..................

Table 4--113: L07_data8b group assignments 4--109..................

Table 4--114: L00_data10b group assignments 4--109.................

Table 4--115: L01_data10b group assignments 4--110.................

Table 4--116: L02_data10b group assignments 4--110.................

Table 4--117: L03_data10b group assignments 4--111.................

Table 4--118: L04_data10b group assignments 4--111.................

Table 4--119: L05_data10b group assignments 4--111.................

Table 4--120: L06_data10b group assignments 4--112.................

Table 4--121: L07_data10b group assignments 4--112.................

TMS817/TMS818 PCIExpress Bus Support

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Table of Contents

Table 4--122: Link8bit group assignments 4--113.....................

Table 4--123: STP_cntr group assignments 4--114....................

Table 4--124: TLP_fmttype group assignments 4--114.................

Table 4--125: TLP_msg_L0 group assignments 4--115.................

Table 4--126: TLP_msg_L4 group assignments 4--116.................

Table 4--127: TLP_comp_status group assignments 4--117.............

Table 4--128: DLLP_type group assignments 4--118...................

Table 4--129: L00_RecErr group assignments 4--119..................

Table 4--130: L01_RecErr group assignments 4--120..................

Table 4--131: L02_RecErr group assignments 4--120..................

Table 4--132: L03_RecErr group assignments 4--120..................

Table 4--133: L04_RecErr group assignments 4--120..................

Table 4--134: L05_RecErr group assignments 4--121..................

Table 4--135: L06_RecErr group assignments 4--121..................

Table 4--136: L07_RecErr group assignments 4--121..................

Table 4--137: Error_bits group assignments 4--122....................

Table 4--138: Rule_viol group assignments 4--122....................

Table 4--139: Status group assignments 4--122.......................

Table 4--140: Channel groups for PCIEx16 4--124....................

Table 4--141: L00_protocol group assignments 4--125.................

Table 4--142: L01_protocol group assignments 4--125.................

Table 4--143: L02_protocol group assignments 4--126.................

Table 4--144: L03_protocol group assignments 4--127.................

Table 4--145: L04_protocol group assignments 4--127.................

Table 4--146: L05_protocol group assignments 4--128.................

Table 4--147: L06_protocol group assignments 4--129.................

Table 4--148: L07_protocol group assignments 4--129.................

Table 4--149: L08_protocol group assignments 4--130.................

Table 4--150: L09_protocol group assignments 4--131.................

Table 4--151: L10_protocol group assignments 4--131.................

Table 4--152: L11_protocol group assignments 4--132.................

Table 4--153: L12_protocol group assignments 4--133.................

Table 4--154: L13_protocol group assignments 4--133.................

Table 4--155: L14_protocol group assignments 4--134.................

Table 4--156: L15_protocol group assignments 4--135.................

Table 4--157: L00_data8b group assignments 4--135..................

Table 4--158: L01_data8b group assignments 4--136..................

Table 4--159: 02_data8b group assignments 4--136....................

viii

TMS817/TMS818 PCIExpress Bus Support

Table of Contents

Table 4--160: L03_data8b group assignments 4--136..................

Table 4--161: L04_data8b group assignments 4--137..................

Table 4--162: L05_data8b group assignments 4--137..................

Table 4--163: L06_data8b group assignments 4--138..................

Table 4--164: L07_data8b group assignments 4--138..................

Table 4--165: L08_data8b group assignments 4--138..................

Table 4--166: L09_data8b group assignments 4--139..................

Table 4--167: L10_data8b group assignments 4--139..................

Table 4--168: L11_data8b group assignments 4--140..................

Table 4--169: L12_data8b group assignments 4--140..................

Table 4--170: L13_data8b group assignments 4--140..................

Table 4--171: L14_data8b group assignments 4--141..................

Table 4--172: L15_data8b group assignments 4--141..................

Table 4--173: L00_data10b group assignments 4--142.................

Table 4--174: L01_data10b group assignments 4--142.................

Table 4--175: L02_data10b group assignments 4--142.................

Table 4--176: L03_data10b group assignments 4--143.................

Table 4--177: L04_data10b group assignments 4--143.................

Table 4--178: L05_data10b group assignments 4--144.................

Table 4--179: L06_data10b group assignments 4--144.................

Table 4--180: L07_data10b group assignments 4--145.................

Table 4--181: L08_data10b group assignments 4--145.................

Table 4--182: L09_data10b group assignments 4--146.................

Table 4--183: L10_data10b group assignments 4--146.................

Table 4--184: L11_data10b group assignments 4--147.................

Table 4--185: L12_data10b group assignments 4--147.................

Table 4--186: L13_data10b group assignments 4--147.................

Table 4--187: L14_data10b group assignments 4--148.................

Table 4--188: L15_data10b group assignments 4--148.................

Table 4--189: Link8bit group assignments 4--149.....................

Table 4--190: STP_cntr group assignments 4--151....................

Table 4--191: TLP_fmttype_L0 group assignments 4--151..............

Table 4--192: TLP_fmttype_L4 group assignments 4--152..............

Table 4--193: TLP_fmttype_L8 group assignments 4--153..............

Table 4--194: TLP_fmttype_L12 group assignments 4--153.............

Table 4--195: TLP_msg_L0 group assignments 4--154.................

Table 4--196: TLP_msg_L4 group assignments 4--155.................

Table 4--197: TLP_msg_L8 group assignments 4--156.................

TMS817/TMS818 PCIExpress Bus Support

Table of Contents

Table 4--198: TLP_msg_L12 group assignments 4--157................

Table 4--199: TLP_comp_status_L0 group assignments 4--158..........

Table 4--200: TLP_comp_status_L4 group assignments 4--159..........

Table 4--201: TLP_comp_status_L8 group assignments 4--160..........

Table 4--202: TLP_comp_status_L12 group assignments 4--160.........

Table 4--203: DLLP_type_L0 group assignments 4--161...............

Table 4--204: DLLP_type_L4 group assignments 4--162...............

Table 4--205: DLLP_type_L8 group assignments 4--162...............

Table 4--206: DLLP_type_L12 group assignments 4--163..............

Table 4--207: L00_RecErr group assignments 4--164..................

Table 4--208: L01_RecErr group assignments 4--164..................

Table 4--209: L02_RecErr group assignments 4--164..................

Table 4--210: L03_RecErr group assignments 4--165..................

Table 4--211: L04_RecErr group assignments 4--165..................

Table 4--212: L05_RecErr group assignments 4--165..................

Table 4--213: L06_RecErr group assignments 4--165..................

Table 4--214: L07_RecErr group assignments 4--166..................

Table 4--215: L08_RecErr group assignments 4--166..................

Table 4--216: L09_RecErr group assignments 4--166..................

Table 4--217: L10_RecErr group assignments 4--167..................

Table 4--218: L11_RecErr group assignments 4--167..................

Table 4--219: L12_RecErr group assignments 4--167..................

Table 4--220: L13_RecErr group assignments 4--168..................

Table 4--221: L14_RecErr group assignments 4--168..................

Table 4--222: L15_RecErr group assignments 4--168..................

Table 4--223: Error_bits group assignments 4--168....................

Table 4--224: Rule_viol group assignments 4--169....................

Table 4--225: Status group assignments 4--169.......................

Table 4--226: Explanation of LXX_RecErr group 4--170...............

Table 4--227: Explanation of Rule Violation Group 4--171.............

Table 4--228: Explanation of STP_Packet_0 and

STP_Packet_1 signals 4--171..................................

Table 4--229: Explanation of SDP_Packet_0 and

SDP_Packet_1 signals 4--171..................................

Table 4--230: Explanation of STP_Packet_3 4--171...................

Table 4--231: Explanation of SDP_Packet_3 4--172...................

Table 4--232: Explanation of STP_Packet_2 4--172...................

Table 4--233: Explanation of SDP_Packet_2 4--172...................

TMS817/TMS818 PCIExpress Bus Support

Table of Contents

Table 4--234: PCIEx1 Clock channels

(also stored as acquisition data) 4--174..........................

Table 4--235: PCIEx1 QUAL channels

(also stored as acquisition data) 4--174..........................

Table 4--236: PCIEx1 A channels 4--174............................

Table 4--237: PCIEx1 D channels 4--176............................

Table 4--238: PCIEx1 C channels 4--177............................

Table 4--239: PCIEx2 Clock channels

(also stored as acquisition data 4--179...........................

Table 4--240: PCIEx2 QUAL channels

(also stored as acquisition data) 4--179..........................

Table 4--241: PCIEx2 A channels 4--179............................

Table 4--242: PCIEx2 D channels 4--181............................

Table 4--243: PCIEx2 C channels 4--182............................

Table 4--244: PCIEx4 Clock channels

(also stored as acquisition data) 4--184..........................

Table 4--245: PCIEx4 QUAL channels

(also stored as acquisition data) 4--184..........................

Table 4--246: PCIEx4 A channels 4--184............................

Table 4--247: PCIEx4 D channels 4--186............................

Table 4--248: PCIEx4 C channels 4--187............................

Table 4--249: PCIEx8 Clock channels

(also stored as acquisition data) 4--189..........................

Table 4--250: PCIEx8 QUAL channels

(also stored as acquisition data) 4--189..........................

Table 4--251: PCIEx8 A channels 4--189............................

Table 4--252: PCIEx8 D channels 4--191............................

Table 4--253: PCIEx8 C channels 4--192............................

Table 4--254: PCIEx8 E channels 4--193............................

Table 4--255: PCIEx16 Clock

(also stored as acquisition data) 4--194..........................

Table 4--256: PCIEx16 QUAL channels

(also stored as acquisition data) 4--195.............................

Table 4--257: PCIEx16 A channels 4--195...........................

Table 4--258: PCIEx16 D channels 4--196...........................

Table 4--259: PCIEx16 C channels 4--198...........................

Table 4--260: PCIEx16 E channels 4--199...........................

Table 4--261: PCIEx16 Clock channels

(also stored as acquisition data) 4--200..........................

TMS817/TMS818 PCIExpress Bus Support

Table of Contents

Table 4--262: PCIEx16 QUAL channels

(also stored as acquisition data) 4--200..........................

Table 4--263: PCIEx16 Slave A channels 4--201......................

Table 4--264: PCIEx16 Slave D channels 4--202......................

Table 4--265: PCIEx16 C channels 4--203...........................

Table 4--266: PCIEx16 E channels 4--204...........................

xii

TMS817/TMS818 PCIExpress Bus Support

General Safety Summary

Review the following safety precautions to avoid injury and prevent damage to this product or any products connected to it. To avoid potential hazards, use this product only as specified.

Only qualified personnel should perform service procedures.

While using this product, you may need to access other parts of the system. Read the General Safety Summary in other system manuals for warnings and cautions related to operating the system.

ToAvoidFireor

Personal Injury

Use Proper Power Cord. Use only the power cord specified for this product and certified for the country of use.

Connect and Disconnect Properly. Do not connect or disconnect probes or test leads while they are connected to a voltage source.

Connect and Disconnect Properly. Connect the probe output to the measurement instrument before connecting the probe to the circuit under test. Disconnect the probe input and the probe ground from the circuit under test before disconnecting the probe from the measurement instrument.

Ground the Product. This product is grounded through the grounding conductor of the power cord. To avoid electric shock, the grounding conductor must be connected to earth ground. Before making connections to the input or output terminals of the product, ensure that the product is properly grounded.

Observe All Terminal Ratings. T o avoid fire or shock hazard, observe all ratings and markings on the product. Consult the product manual for further ratings information before making connections to the product.

Do not apply a potential to any terminal, including the common terminal, that exceeds the maximum rating of that terminal.

Do Not Operate Without Covers. Do not operate this product with covers or panels removed.

Use Proper Fuse. Use only the fuse type and rating specified for this product.

Avoid Exposed Circuitry. Do not touch exposed connections and components

when power is present.

Do Not Operate With Suspected Failures. If you suspect there is damage to this product, have it inspected by qualified service personnel.

Do Not Operate in Wet/Damp Conditions.

Do Not Operate in an Explosive Atmosphere.

Keep Product Surfaces Clean and Dry.

TMS817/TMS818 PCIExpress Bus Support

xiii

General Safety Summary

Provide Proper Ventilation. Refer to the manual’s installation instructions for details on installing the product so it has proper ventilation.

Symbols and Terms

Terms in this Manual. These terms may appear in this manual:

WARNING. Warning statements identify conditions or practices that could result in injury or loss of life.

CAUTION. Caution statements identify conditions or practices that could result in damage to this product or other property.

Terms on the Product. These terms may appear on the product:

DANGER indicates an injury hazard immediately accessible as you read the marking.

WARNING indicates an injury hazard not immediately accessible as you read the marking.

CAUTION indicates a hazard to property including the product.

Symbols on the Product. The following symbols may appear on the product:

CAUTION

Refer to Manual

CAUTION

Hot Surface

WARNING

High Voltage

Protective Ground

(Earth) Terminal

Mains Disconnected

OFF (Power)

Mains Connected

ON (Power)

xiv

TMS817/TMS818 PCIExpress Bus Support

Service Safety Summary

Only qualified personnel should perform service procedures. Read this Service Safety Summary and the General Safety Summary before performing any service

procedures.

Do Not Service Alone. Do not perform internal service or adjustments of this product unless another person capable of rendering first aid and resuscitation is present.

Disconnect Power. To avoid electric shock, switch off the instrument power, then disconnect the power cord from the mains power.

Use Care When Servicing With Power On. Dangerous voltages or currents may exist in this product. Disconnect power, remove battery (if applicable), and disconnect test leads before removing protective panels, soldering, or replacing components.

To avoid electric shock, do not touch exposed connections.

TMS817/TMS818 PCIExpress Bus Support

Service Safety Summary

xvi

TMS817/TMS818 PCIExpress Bus Support

Preface

Manual Conventions

This instruction manual contains specific information about the TMS817 and TMS818 Bus support products and is part of a set of information on how to operate this product on compatible Tektronix logic analyzers.

If you are not familiar with operating support products, you need to supplement this instruction manual with introductory information about how to set up and run a support package on the logic analyzer. Go to the logic analyzer online help index under Microprocessor support packages.

For help in understanding terms in this manual that may be new to you, see the Glossary at the end of the manual.

This manual uses the following conventions:

H The term “disassembler” refers to the software that decodes bus cycles into

instruction mnemonics and cycle types.

H The terms “Master” and “Slave” refer to modules that are located in

numbered slots (see Figure 1--1 on page 1--2).

TMS817/TMS818 PCIExpress Bus Support

xvii

Preface

Contacting Tektronix

Phone 1-800-833-9200*

Address Tektronix, Inc.

Department or name (if known) 14200 SW Karl Braun Drive P.O. Box 500 Beaverton, OR 97077 USA

Web site www.tektronix.com

Sales support 1-800-833-9200, select option 1*

Service support 1-800-833-9200, select option 2*

Technical support Email: techsupport@tektronix.com

1-800-833-9200, select option 3*

6:00 a.m. -- 5:00 p.m. Pacific time

* This phone number is toll free in North America. After office hours, please leave a

voice mail message. Outside North America, contact a Tektronix sales office or distributor; see the Tektronix web site for a list of offices.

xviii

TMS817/TMS818 PCIExpress Bus Support

Getting Started

Product Description

This section contains the following information for the TMS817 and TMS818 PCIExpress Bus Support products:

H Product description

H Logic analyzer configuration

H Connecting the logic analyzer to the target system

The TMS817 and TMS818 probe adapters are designed to connect to a midbus or slot target system. This allows you to acquire data from a PCIExpress Bus with little effect on the target system.

When a probe adapter is connected to the target system, the signals from the PCIExpress system flow through the probe head, into the preprocessor unit, and then through the LAI cables to the logic analyzer.

The TMS817 and TMS818 bus software provides decoding of the serial-data stream. There are five software packages, x1, x2, x4, x8, and x16, one for each of the PCIExpress bus-width links and three test software packages.

H TMS817 supports x1, x2, x4, x8, and x16 lane widths

H TMS818 supports x1, x2, and x4 lane widths

The probe adapter assumes that all lanes in a link are affected the same way by repeater chips. Specifically, if the repeater chip adds or deletes x SKIP symbol(s) from a SKIP packet on one lane it adds or deletes x SKIP symbols from the same SKIP packet on all lanes.

Trigger Support

Trigger libraries containing EasyTrigger programs are provided for each support package. See page 2--3 for a list of the trigger programs.

Logic Analyzer Software Compatibility

The label on the CD-ROM states that version 4.2 of the logic analyzer software is compatible with the TMS817 and TMS818 products.

TMS817/TMS818 PCIExpress Bus Support

1- 1

Getting Started

Logic Analyzer Configuration

To use either of the probe adapters, you need a minimum module speed of 450 MHz. See Table 1--1 for the number and type of modules needed for different lane widths.

If you use more than one module, the modules must be merged. See the logic analyzer online help for how to merge your modules.

Table 1- 1: Number and Type of modules

Lane width Module type

x1, x2, x4 TLA7AX3* or TLA7AX4** 1

x8 TLA7AX4** 1

x16 TLA7AX4** 2 (merged)

* 102 channels

** 136 channels

Module number

The term Master (M) module refers to the middle module of a 5-wide module chassis. The term Slave1 (S1) module refers to the module to the right of the Master module of a 5-wide module chassis. Figure 1--1 s hows the configuration for a 2-wide module merge (x16-wide link only).

x16 wide link needs

two merged modules

x1, x2, x4, x8 wide link

M A S T E R

S L A V E 1

1- 2

Figure 1- 1: Configuration of the Master and Slave1 modules

TMS817/TMS818 PCIExpress Bus Support

LAI Cables

Getting Started

The LAI cables are specifically designed for use with the TMS817 and TMS818 probe adapter products. The link widths you choose require a specific number of LAI cables. For more detailed information on connecting your LAI cables to the preprocessor unit, see page 1--22.

LAI cables

TMS817 probe adapter

Figure 1- 2: LAI Cables

Labeling

LAI Cables

Preprocessor unit

(Rear view)

Module end of cables

To apply labels to the LAI cables, see page 1--24.

TMS817/TMS818 PCIExpress Bus Support

1- 3

Getting Started

Standard and Optional Accessories

A complete list of standard and optional accessories is provided in the Replaceable Parts List on page 5--3.

For the TMS817 product:

H The following options are available only when ordering a TMS817 product.

Option 01 — midbus probe head

Option 02 — x16 slot board

Option 03 — x8 slot board

Option 04 — LAI cables (4)

For an additional midbus probe head assembly with attaching parts order:

H TMSIC6 — midbus probe head for the TMS817

For the TMS818 product:

H The following options are available only when ordering a TMS818 product.

Option 01 — midbus probe head

Option 02 — x4 board

Option 03 — x1 board

Option 04— LAI cables (2)

For an additional midbus probe head assembly with attaching parts order:

H TMSIC8 — midbus probe head for TMS818

1- 4

TMS817/TMS818 PCIExpress Bus Support

Probe Adapter Review

Getting Started

Review the electrical specifications beginning on page 3--1 as they relate to the target system, as well as the following descriptions of other product information.

System Data Rate

Nonintrusive Acquisition

Storage Qualified Data

Bus Width

Linking of Requests to

Completions

The probe adapters are designed to acquire data from a PCIExpress bus operating at 2.5 GT/s and have been tested at adapters are capable of acquiring spread spectrum data at 0.5 ppm at a rate of 33 KHz. An external clock is required for acquiring data at and for spread spectrum data.

Contact your Tektronix sales representative for current information on the fastest buses supported.

The probe adapters do not modify or present signals back to the target system.

The disassembler is not designed to work with gaps in the acquisition data. Disassembly of storage qualified data can be indeterminate and incorrect.

The TMS817 and TMS818 products support bus link widths of x1, x2, x4, x,8, and x16. The TMS817 product supports bus link widths of x1, x2, and x4.

Linking of Requests to Completions across separate links and analysis of separate directions on the same link are not supported in the disassembler. Only timestamp correlation is available.

±10% of the nominal frequency. These probe

±10% of 2.5 GT/s

Lane Changes

Detect Mechanism

Triggering

Training Packets

Packet Payload

TMS817/TMS818 PCIExpress Bus Support

On-the-fly lane reordering and link-width adjustments are not supported.

The detect mechanism is not supported.

Due to the logic analyzer trigger resource, triggering capabilities are different for different width links.

Training packets are captured and displayed as they are acquired from the link, but lane ordering and polarity settings need to be set manually.

Only PCIExpress protocol tracking is performed. The disassembler does not perform decoding for any packet payloads.

1- 5

Getting Started

Connect the Logic Analyzer to the Target System

Read the entire following section before beginning the installation procedure.

Tools

Task Summary

The following is a list of required tools:

H Flatbladed screwdriver (0.1 inch tip width) to adjust the Width or Mode

switch

H POZIDRIV (PZ1) screwdriver to connect the clam shell housings on the

preprocessor unit.

H Optional: A torque wrench helps to ensure reliable connections by meeting

the nominal torque values that may be listed in these instructions. When attaching screws to the probe head use 4 in-lbs (0.451 Newton meters) of torque.

CAUTION. To prevent static damage to the probe adapter, the LAI cables, and the module, handle components only in a static-free environment.

Always wear a grounding wrist strap, heel strap, or similar device while handling a probe adapter.

Table 1--2 list the tasks that you must do to connect either a midbus probe adapter or a slot board to the logic analyzer.

Table 1- 2: Task summary

1- 6

Tasks See page

Solder the retention fixtures and attach the interconnect strip to a mi dbus footprint on either the target system or the slot board.

Connect the midbus probe head to the midbus footprint. 1--9

(Slot board only) Connect the Slot board. 1--10

Connect the plugs on the midbus cables to the front of the preprocessor unit.

Connect External Clocking. 1--18

Adjust the preprocessor settings. 1--20

Connect the LAI cables between the preprocessor unit and logic analyzer. 1--23

Check the lane polarity and lane order. 1--27

1--8

1--12

TMS817/TMS818 PCIExpress Bus Support

Getting Started

Connecting the Midbus

Probe Head

Follow these steps to connect the probe head to a midbus footprint:

1. Power off the preprocessor unit, if necessary. Refer to Applying Power and

Removing Power on page 1--25.

2. Power off the target system. It is not necessary to power off the logic

analyzer.

CAUTION. To prevent static damage, handle these components only in a static-free environment. Static discharge can damage the probe adapter, the probes, and the logic analyzer module.

Always wear a grounding wrist strap, heel strap, or similar device while handling the probe adapter.

3. To discharge the stored static electricity, touch the ground connector located

on the back of the logic analyzer.

4. Make sure the target system is in a static-free environment.

CAUTION. To prevent damage to the target board, soldering must be done by qualified service personnel.

5. Locate the midbus footprint on the target system or slot board.

6. Remove the two retention fixtures from the hardware bag. Notice that one

retention fixture is gold and is keyed, and the other is silver and is not keyed

(see Figure 1-- 3 on page 1--8).

7. Correctly position one retention fixture on each side of the midbus footprint

(see Figure 1-- 3 on page 1--8).

CAUTION. To prevent resoldering a retention fixture, check that the retention fixture “nose” is pointing toward the midbus footprint as shown in Figure 1--3.

TMS817/TMS818 PCIExpress Bus Support

1- 7

Getting Started

8. Solder the four retention-fixture pins to the back of the circuit board.

Key (TMS818) — If the key hole is missing from the target system board, you can clip the key from the fixture. Check that you connected the golden fixture with its nose pointing toward (CH A) on the midbus footprint .

2. Solder pins to circuit board

Pins (insert into circuit board, and then

solder on the other side of the board)

Retention fixture

(gold; has key)

Retention fixture

(silver)

Circuit board

Minibus footprint

Nose (point inward)

1. Install retention fixtures 3. Install interconnect strip

(TMS817 probe adapter)

Figure 1- 3: Connecting the retention fixtures

Interconnect strip

(place between retention fixtures)

Interconnect strip must be flush with circuit board

1- 8

9. Remove the plastic interconnect strip from the hardware bag.

10. Place the interconnect strip on top of the midbus footprint and press into

place.

NOTE. The interconnect strip must lay flat against the circuit board; no gaps are allowed between the strip and the board.

11. Remove the probe head from the protective packaging.

TMS817/TMS818 PCIExpress Bus Support

Getting Started

NOTE. When you attach the probe head, match the colors on either sides of the retention fixtures to the probe head. One side of the probe head is gold and the other is silver.

12. Connect the probe head to the midbus footprint (see Figure 1--4).

CAUTION

Hot Suffice

To prevent burns, handle the

Midbus probe head carefully, since it may be hot.

Probe head

(gold side)

Retention fixture

(gold)

Circuit board

To preprocessor unit (front panel)

Screw (2)

Interconnect strip

Figure 1- 4: Connecting the probe head to the retention fixtures

CAUTION. To prevent damage to the connector on the target system, always position the probe head perpendicular to the connector. Do not twist or bend the probe adapter while it is attached to the target system and support the probehead cables in a way that keeps the mechanical forces on the connectors to a minimum.

13. Tighten the screws (on both sides of the probe head) to the threaded studs on

the retention fixtures.

TMS817/TMS818 PCIExpress Bus Support

1- 9

Getting Started

Connecting the Slot Board

1. Remove the PCIExpress card from the target system.

2. Connect the midbus probe head to the slot board. See steps 5 through 12

startingonpage1--7.

3. Connect the PCIExpress card to the PCIExpress connect on the slot board.

If you need more mechanical support for the PCIExpress card, attach the optional support bracket to the slot boar. Place the PCIExpress bracket on top of the Support bracket and attach it using the two supplied screws.

CAUTION. To avoid damage to the PCIExpress connector, check that the PCIExpress bracket is on top of the support bracket.

PCIExpress

bracket

Support bracket

(optional)

PCIExpress connector

Extra signals

(use lead set )

J7 is for the

External Clock

cable

Connect two midbus probe heads to the slot board

PCIExpress

card (Intel)

1- 10

Slot board

Connect to

target system

(x16 example)

Figure 1- 5: Connecting the Slot board and PCIExpress card

4. Connect the Slot board to your target system.

Extra Signals. The extra signals listed in Table 1--3 (except for J17) are not needed by the TMS817 and TMS818 support packages, but have been provided should you need to monitor them.

Use lead sets to connect the extra pins on the slot board to the logic analyzer. The extra signals need to be connected to a logic analyzer module separate from the modules that you are using for the TMS817 and TMS818 supports.

TMS817/TMS818 PCIExpress Bus Support

Getting Started

The slot board is labeled with an A and B side which lists these extra signal you may want to acquire. Table 1--3 lists the extra signals for each side of the slot board.

Table 1- 3: Extra x16 link-width signals

Connector Pin Signal name

J3--1 WAKE#

J3--2 GND

J4--1 PWRGD

J4--2 GND

J5--1 SMCLK

J5--2 GND

J6--1 SMDAT

J6--2 GND

J7--1* REFCLK+

J7--2* GND

J7--3* REFCLK--

* For Ext Clock cable

5. Optional: Attach a tie-down strap(s) to the probe-head cables to stabilize the

probe adapter while it is attached to the target system, if necessary.

TMS817/TMS818 PCIExpress Bus Support

1- 11

Getting Started

Cable Configurations

Each preprocessor unit is capable of acquiring signals from a complete link. A complete link is two unidirectional links. The complete data link may be composed of 1, 2, 4, 8 or 16 channels (unidirectional lanes). Following are two examples of preprocessor-unit configurations.

Figure 1--6 shows an example of a preprocessor-unit configuration for two x8-width links.

Midbus footprint

x8 Link

Device A Device B

x8 Link

Midbus

probe head

Preprocessor unit

1- 12

Figure 1- 6: Preprocessor unit configuration for two x8-wide unidirectional links

TMS817/TMS818 PCIExpress Bus Support

Getting Started

Figure 1--7 shows an example of a preprocessor-unit configuration for four unidirectional x4-width links (two x4 width links).

Midbus footprint

x4 Link x4 Link

Device A Device B

x4 Link x4 Link

Probe head

Preprocessor units

Plugs

Figure 1- 7: Preprocessor unit configuration for four x4-wide links

Create a Configuration Plan. Before connecting the probe-head plugs to the

preprocessor unit, you must complete the following steps:

1. Determine the number of complete links (see examples of different link

configurations on pages 1--12 and 1--13).

2. Assign the particular lanes that make up the complete links. These links go

through specific pins on the midbus footprint.

TMS817/TMS818 PCIExpress Bus Support

1- 13

Getting Started

NOTE. The recommended midbus footprint for the target system is shown in Figure 1--8. If the midbus footprint is different than Figure 1--8, you may need to create a cross reference for your configuration.

GGGGGGGG

xyy

yyyyy

yyyy

x16 Midbus Footprint

GGGG

x8 Midbus Footprint

Figure 1- 8: Preferred midbus footprint configurations

GGGGGGGG

Polarity

GGGGGGGG

1- 14

3. You must choose which upstream or downstream connector on the preprocessor unit your link attaches to (see Figure 1--9).

The upstream and downstream connectors are located on the front of the preprocessor unit and it does not matter which connector you choose. The labels upstream and downstream do not refer to signal direction. These terms are used only to differentiate between the two connectors.

TMS817/TMS818 PCIExpress Bus Support

Getting Started

Downstream

L15

MIDBUSFOOTPRINT

GGGGGGGG

CI xCKxCMxCPx

xyyCHxyyyyy

xy CD

CJxCLxCNxCQ

GGGGGGGG

CLK0

CLK1

CLK2

CLK0

CLK1

CLK2

MODE WIDTH

SELF TEST

L00 L02 L04L06 L08L10 L12 L14 PN PN PN PN PN PN PN PN

PN L01PNL03PNL05PNL07PNL09PNL11PNL13

L01 L03 L05L07 L09L11 L13 L15

ON OFF

EXT CLOCK

SELF TEST

L00 L02 L04L06 L08L10 L12 L14 PN PN PN PN PN PN PN PN

PN L01 L03 L05L07 L09L11 L13 L15

L01PNL03PNL05PNL07PNL09PNL11PNL13

ON OFF

EXT CLOCK

PN L15

PROBE POWE R

PN L15

PROBE POWE R

Upstream

WIDTH

DOWNSTREAM

X16

UPSTREAM

xCExyCGxyyyyy

GGGGGGGG

CBxCF

CLKNL00PNL01NPL02NPL03PNL04PNL05NPL06NPL07PNL08PNL09NPL10NPL11PNL12PNL13NPL14

PN P

CLKNL00PNL01NPL02NPL03PNL04PNL05NPL06NPL07PNL08PNL09NPL10NPL11PNL12PNL13NPL14NPL15

PN P

MODE

8b DESCRAMBLE ON

0 1

8b DESCRAMBLE OFF

10b DESCRAMBLEOFF

RAWDATA

SELF TEST

TMS817 Probe Adapter

Figure 1- 9: Preprocessor unit (front)

4. You must choose which side of the plug is positive or negative (X or Y) on the probe-head cable (see Figure 1--10 on page 1--16 for the location of the polarity references on the plug).

Connecting the Probe-Head Plugs. Use the following procedure to connect the probe head plugs to the front of the preprocessor unit:

NOTE. All probe-head plugs must be connected to the preprocessor unit, regardless of the configuration. For example, if your configuration has four lanes, then L00--L03 have active channels, and L04--L15 have all inactive channel. All probe-head plugs will be connected. For the inactive channels, the order and polarity is not important.

1. Power off the preprocessor unit. Refer to Applying Power and Removing Power on page 1--25. It is not necessary to power off the target system or the

logic analyzer.

2. Attach the appropriate probe head cable plugs to the front of the preprocessor unit (see Figure 1-- 10 on page 1--16).

NOTE. The name of the pad on the midbus footprint is printed on each probehead plug for ease of use (see Figure 1--10 on page 1--16).

3. Connect the probe head power plug(s) to the front of the preprocessor unit (see Figure 1-- 12 on page 1--20).

TMS817/TMS818 PCIExpress Bus Support

1- 15

Getting Started

Clam shell top

Probe head plugs

TMS817 probe adapter

Clam shell screws (2)

Clam shell tray

Probe cable

connectors

External clock input

Figure 1- 10: Attaching the probe-head cables

Polarity reference

Midbus pad name

Note: Your x y label configuration depends on how your channels are routed to the midbus footprint and may look different than shown in this figure.

1- 16

TMS817/TMS818 PCIExpress Bus Support

What Next

Getting Started

Read the information on External Clocking on page 1--18. For most situations you will need to use the External clock cable.

After completing the external clocking section, you are ready to:

1. Make the adjustments to the front of the preprocessor unit (see page 1--20)

2. Check the polarity and order of the lanes (see page 1--27)

3. Attach the LAI cables (see page 1--22)

NOTE. If you have trouble acquiring data from the target system after you complete these procedures, use the Self Test procedure on page 1--29 to ensure that the preprocessor unit is working correctly. Also, recheck your lane polarity and lane ordering.

TMS817/TMS818 PCIExpress Bus Support

1- 17

Getting Started

Clocks

(1,2,3)

External Clocking

MODE WIDTH

CLK0

CLK1

CLK2

CLK0

CLK1

CLK2

MODE WIDTH

ON OFF

External clocking is the recommended mode of operation due to the frequency difference between the preprocessor unit and the target system. External clocking is required if the following two conditions apply:

H The target system is statically exceeding the

±100 ppm data-rate variation

from 2.5 GT/s; for example, frequency margining.

H The target system is dynamically exceeding the

±100 ppm date-rate variation

from 2.5 GT/s; for example, spread-spectrum clocking.

For both of the above conditions, you need to attach the included external clock input cable to the 100 MHz clock on the target system (see Figure 1--11).

Clock input connector

(left of L00)

SELF TEST

L00 L02 L04 L06 L08 L10 L12 L14 PN PN PN PN PN PN PN PN

PN L01PNL03PNL05PNL07PNL09PNL11PNL13

L01 L03 L05 L07 L09 L11 L13 L15

EXT CLOCK

SELF TEST

L00 L02 L04 L06 L08 L10 L12 L14 PN PN PN PN PN PN PN PN

PN L01PNL03PNL05PNL07PNL09PNL11PNL13

L01 L03 L05 L07 L09 L11 L13 L15

EXT CLOCK

PN L15

PROBE POWE R

PN L15

PROBE POWE R

TMS817 Probe Adapter

CLKNL00PNL01NPL02NPL03PNL04PNL05NPL06NPL07PNL08PNL09NPL10NPL11PNL12PNL13NPL14

CLKNL00PNL01NPL02NPL03PNL04PNL05NPL06NPL07PNL08PNL09NPL10NPL11PNL12PNL13NPL14 PN

PN P

CLKNL00PNL01NPL02NPL03PNL04PNL05NPL06NPL07PNL08PNL09NPL10NPL11PNL12PNL13NPL14NPL15

CLKNL00PNL01NPL02NPL03PNL04PNL05NPL06NPL07PNL08PNL09NPL10NPL11PNL12PNL13NPL14NPL15 PN P

PN P

MODE

8b DESCRAMBLE ON

8b DESCRAMBLE OFF

10b DESCRAMBLEOFF

RAWDATA

SELF TEST

WIDTH

0 1

2 3

3 4

UPSTREAM

DOWNSTREAM

X2 X4

X4 X8

X8 X16

X16

L15

GGGGGGGG

MIDBUSFOOTPRINT

CExyCG

GGGGGGGG

CIxCKxCMxCP

xyyyyy

xyyCHxyyyyy

CJxCLxCN

xCQx

GGGGGGGG

EXT Clock

Figure 1- 11: External clocking connections

Use the following procedure to connect the external clock input cable (the clock polarity does not matter):

NOTE. We recommend separate clock connection from the target system to the preprocessor unit for each unidirectional link.

1. Power off both the probe adapter and the target system.

1- 18

TMS817/TMS818 PCIExpress Bus Support

Getting Started

2. On the target system, attach the included external clock input cable to the three-pin 100 MHz (nominal) clock connector. The female end of the external clock input cable attaches to the male connector on the target system. The external clock polarity is not important.

3. On the front of the preprocessor unit, attach the male end of the external clock input cable to the CLK input connector (see Figure 1--11).

4. On the front of the preprocessor unit, set the EXT CLK switch to ON (see Figure 1--11).

5. If you are using both upstream and downstream portions of the preprocessor unit you can:

H (Recommended) Use a separate clock input cable for each unidirectional

link.

H Attach another clock cable between the CLK (0, 1, 2) connector and the

CLK input connector (to the left of the L00 connection) on the other portion of the preprocessor unit. Set the EXT Clock switch to ON.

The CLK (0, 1, 2) connector is replicated from the CLK input connector.

If you have multiple preprocessor units requiring the 100 MHz clock, then you can interconnect the preprocessor units with the provided clock cables, and use the above steps 3 through 5.

Use the following procedure to disconnect the external clock input:

1. Power off the probe adapter and the target system.

2. Disconnect all clock cables that connect the target system to the preprocessor

unit, and disconnect the preprocessor-to-preprocessor cables. Retain these cables for future use.

3. Set all EXT CLK selector switches to OFF.

TMS817/TMS818 PCIExpress Bus Support

1- 19

Getting Started

Adjust the Preprocessor

Use Figure 1--12 and Table 1--4 on page 1--20 to set up the preprocessor unit.

Unit Settings

Link Width

Mode

CLK0

Clocks

(1,2,3)

Clocks

(1,2,3)

CLK1

CLK2

CLK0

CLK1

CLK2

Figure 1- 12: Adjust the preprocessor unit settings

EXT Clock

MODE WIDTH

ON OFF

EXT Clock

(spread spectrum)

SELF TEST

L00 L02 L04 L06 L08 L10 L12 L14 PN PN PN PN PN PN PN PN

PN L01PNL03PNL05PNL07PNL09PNL11PNL13

L01 L03 L05 L07 L09 L11 L13 L15

EXT CLOCK

SELF TEST

L00 L02 L04 L06 L08 L10 L12 L14 PN PN PN PN PN PN PN PN

PN L01 L03 L05 L07 L09 L11 L13 L15

L01PNL03PNL05PNL07PNL09PNL11PNL13

EXT CLOCK

PN L15

PROBE POWE R

PN L15

PROBE POWE R

TMS817 Probe Adapter

Self-Test LED

Probe head power

UpstreamSelf-Test

WIDTH

1 2

2 3

UPSTREAM

DOWNSTREAM

X1 X2

X2 X4

X4 X8

X8 X16

X16

CLKNL00PNL01NPL02NPL03PNL04PNL05NPL06NPL07PNL08PNL09NPL10NPL11PNL12PNL13NPL14

CLKNL00PNL01NPL02NPL03PNL04PNL05NPL06NPL07PNL08PNL09NPL10NPL11PNL12PNL13NPL14 PN

PN P

CLKNL00PNL01NPL02NPL03PNL04PNL05NPL06NPL07PNL08PNL09NPL10NPL11PNL12PNL13NPL14NPL15

CLKNL00PNL01NPL02NPL03PNL04PNL05NPL06NPL07PNL08PNL09NPL10NPL11PNL12PNL13NPL14NPL15 PN P

PN P

MODE

8b DESCRAMBLE ON

8b DESCRAMBLE OFF

10b DESCRAMBLEOFF

RAWDATA

SELF TEST

Downstream

GGGGGGGG

MIDBUSFOOTPRINT

CExyCG

GGGGGGGG

CIxCKxCMxCP

xyyyyy

xyyCHxyyyyy

L15

CJxCLxCNxCQ

GGGGGGGG

CAUTION. To prevent damage to the preprocessor unit, you must power off the preprocessor unit before changing any settings.

Table 1- 4: Preprocessor unit settings

TMS817 settings

Name

Mode (rotary switch with multiple positions)

and connections

0 1.0a — descramble on 1 8b — descramble off 2 10b — descramble off 3 Raw data 4 Self Test 5 1.0 — descramble on

TMS818 settings and connections

Description

Same Use the mode switch to select

the type of data you are acquiring.

1- 20

TMS817/TMS818 PCIExpress Bus Support

Table 1- 4: Preprocessor unit settings (Cont.)

Getting Started

TMS817 settings

Name Description

Self Test (midbus footprint)

and connections

Connect the probe head to the Self-Test connector on the front

Caution, static sensitive.

of the prepr ocessor unit where

TMS818 settings and connections

Same Use the Self Test connection to

test that the preprocessor unit is operating proper ly.

you are running the self test.

Set the mode switch to Self Test (position 4).

Link Width (Rotatory switch with multiple positions) Note: For self test this switch has different settings. Refer to

0x1 1x2 2x4 3x8 4 x16

0x1 1x2 2x4

Use the link width setting to specify the width of your link. (Use a flatbladed screwdriver to make the adjustments.)

Table 1--8 on page 1--31.

Ext clock (Spread Spectrum slide switch)

On/off Same Use the spr ead spectrum

clocking switch to specify if it is enabled on the target system.

Clocks (connector) Three clock connections are

available.

Same If needed, use when the exter-

nal clock and target system does not pr ovide a separate clock for each unidirectional link.

Upstream (connector) Downstream (connector)

Connect the appropr iate probehead plugs to one of the connectors on the front of the preprocessor unit.

Same Use to acquire bus information.

Before connecting, you must determine which connector, upstream or downstream, to connect to the front of the preprocessor unit.

TMS817/TMS818 PCIExpress Bus Support

1- 21

Getting Started

Connect the LAI Cables

The LAI cables connect the logic analyzer module(s) to the back of the preprocessor unit (see Figure 1--13). Before you connect the LAI cables, you need to determine the number of cables and then apply labels.

LAI cables

TMS817 probe adapter

Module end of cables

Figure 1- 13: LAI cable and preprocessor unit

CAUTION. To prevent static damage to the probe adapter, LAI cables, probes, and the module, handle components only in a static-free environment.

Always wear a grounding wrist strap, heel strap, or similar device while handling probe adapter.

Preprocessor unit

(Rear view)

1- 22

TMS817/TMS818 PCIExpress Bus Support

Getting Started

Number of LAI Cables. The link widths that you choose require a specific number of LAI cables. To determine the number of cables you need, see Table 1--5.

For example, a x1 unidirectional link and a x16 unidirectional link require six LAI cables, or two cables for x1 and four cables for x16 connections.

Table 1- 5: LAI cable quantities

Link widths LAI cable quantity

SLAVE

L13... L15

SLAVE

L13... L15

A2A3D3

E2E3E0

x1 unidirectional upstream

x1 bidirectional up/downstream

x2 unidirectional upstream

x2 bidirectional up/downstream

x4 unidirectional upstream

x4 bidirectional up/downstream

x8 unidirectional upstream

x8 bidirectional up/downstream

x16 unidirectional upstream

x16 bidirectional up/downstream

Figure 1--14 shows the back of the preprocessor unit.

E2E3E0

A2A3D3

SLAVE

L08... L12

SLAVE

L08... L12

C2C3C0C1A1A0D1

MASTER

L00... L01

MASTER

L00... L01

C2C3C0C1A1A0D1

MASTER

L02... L07

MASTER

L02... L07

E2E3E0

A2A3D3

E2E3E0

UPSTREAM

DOWNSTREAM

POWER

AC Power Power switch

Figure 1- 14: Preprocessor unit (back)

TMS817/TMS818 PCIExpress Bus Support

TO AVOID ELECTR IC SH OCK TH E POWER CO RD P ROTECTIV E

GROUNDINGCONDUCTORMUST BE CONNECTEDTO GROUND.

NO OPERATORSERVICEABLECOMPONETSINSIDE.DO NOT

REMOVECOVERS,REFERSERVICING TO QUALIFIEDPERSONNEL.

TEKTRONIX INC. BEAVERTON,OREGON,USA

TMS817 probe adapter

1- 23

Getting Started

Applying Labels. You need to attach labels to the module end and the preprocessor-unit end of the LAI cables. Read the following note before you begin attaching labels.

NOTE. Always use flat-nosed tweezers to remove the labels from the sheet of labels. Never peel labels with your fingers. The labels are made of soft vinyl and can stretch and distort easily. To avoid stretching the label, always grasp it from the top right corner while removing it from the sheet of labels.

The adhesive on the vinyl labels is extremely strong. Carefully align the label to the indented outline on the module end and preprocessor unit end. Once labels are placed on the LAI Cables, they become very difficult to remove.

To attach labels, perform the following steps:

1. Determine which channel groups you are planning to use, and identify the matching labels.

2. Follow the steps in Figure 1--15 while attaching the labels.

Blank

Module end

Blank

Figure 1- 15: Apply LAI labels

Align and place the labels in

the label indents, as shown in

step 1. Repeat for all steps.

LAI Cable

color and the

channel name

Probe-head

end

Match the

1- 24

TMS817/TMS818 PCIExpress Bus Support

Getting Started

LAI Cable Configuration. Following is the minimum configuration for disassembly support.

1. Match the A, D, C, and E LAI cables from the Master module with the corresponding D3/D2 and A3/A2, D1/D0 and A1/A0, C1/C0 and C3/C2, and E3/E2, and E1/E2 LAI connector labels on the preprocessor unit. Connect the LAI cables.

Do not connect the E1/E2, E3/E2 connector if you are using an 102 channel module (for x1, x2, or x4 link widths).

2. (x16-wide link only) Repeat step 1 to make LAI cable connections between the Slave module and the preprocessor unit.

Figure 1--16 shows the configuration for the Master and Slave1 modules.

x16 wide link needs

two merged modules

x1, x2, x4, x8 wide link

Applying Power

M A S T E R

Figure 1- 16: Configuration of the Master and Slave1 modules

To apply power to the probe adapter and target system, follow these steps:

WARNING. To prevent personal injury or damage to the preprocessor unit, there are no operator serviceable parts inside the cover of the preprocessor unit. Refer servicing of parts in the preprocessor unit to Tektronix authorized personnel only.

S L A V E 1

TMS817/TMS818 PCIExpress Bus Support

1- 25

Getting Started

1. Make sure the power switch on the preprocessor unit is in the off position. The (zero) is depressed on the power switch, which is located on the rear panel of the preprocessor unit.

2. Plug the AC power cord into the IEC connector on the back of the preprocessor unit.

3. Plug the AC power cord into an electrical outlet that you know is working properly.

4. Power on the preprocessor unit. Two green LEDs light on the front of the preprocessor unit, indicating that the probe adapter is active.

5. Power on the target system.

Removing Power

To remove power from the target system and the probe adapter, follow these steps:

1. Power off the target system.

2. Power off the probe adapter at the back of the preprocessor unit.

1- 26

TMS817/TMS818 PCIExpress Bus Support

Capture Training Sequence

For the logic analyzer to receive coherent data you must have the correct lane polarity and order. To determine the correct lane polarity and order , you need to load the training sequence EasyTrigger.

The training sequence EasyTrigger detects TS1/TS2 training packets. These packets, when displayed, show the polarity and order of the lanes (see Figure 1--17).

Follow these steps to verify the lane polarity and order:

NOTE. Always correct the lane polarity first and then the lane position. If you correct the lane position first, the polarity information will be incorrect.

1. If you have not loaded the software support package, load it now (refer to page 2--3). The EasyTriggers are loaded when the software support is loaded.

2. In the EasyTrigger window, select Trig_on_Training_Sequence (refer to page 2--3).

Getting Started

3. On the logic analyzer, select Run.

4. On your target system, initiate a TS1/TS2 sequence.

5. After the logic analyzer triggers, scroll down to the last TS1/TS2 sequence

(see Figure 1-- 17).

Scrolling to the last TS1/TS2 sequence ensures that you are looking at the final polarity and lane order.

6. Check the last ten polarity symbols in each lane (see Figure 1--17). These symbols must be 45 or 4A indicating correct polarity.

If any lane has a BA or a B5 polarity symbol, the polarity of that lane needs to be inverted. To invert the polarity of a lane:

a. Unplug the lane from the preprocessor unit

b. Invert the plug

c. Reconnect the plug

TMS817/TMS818 PCIExpress Bus Support

1- 27

Getting Started

7. After all the lane polarities are corrected, initiate a TS1/TS2 sequence on the target system and select RUN. After logic analyzer triggers, scroll down to the last TS1TS2 sequence. Check that there are no BA or B5 in the lane and that the lane ordering in the Link Details column is correct (see Figure 1--17).

The lane ordering must be in an ascending order starting from lane 00. If a lane is not in the correct order, then unplug that lane from the preprocessor unit and plug it into the correct lane, taking care that the polarity remains the same.

Lane Order in the

Link Details column

Last TS1/TS2 sequence

Figure 1- 17: Training sequence display

1- 28

Last ten polarity symbols in a lane

TMS817/TMS818 PCIExpress Bus Support

Troubleshooting

Getting Started

If you cannot acquire data from the target system using the probe adapter, use the following self-test procedure to ensure that the preprocessor unit is working correctly.

Also, recheck your lane polarity and lane ordering (see Load Training Sequence on page 1--27).

Use the Trouble shooting check list on page 1--36 to check that the probe adapter is set up correctly.

WARNING. To prevent personal injury or damage to the preprocessor unit, there are no operator serviceable parts inside the cover of the preprocessor unit. Refer servicing of internal parts in the preprocessor unit to Tektronix authorized personnel only.

Self Test

Before you begin the self test example, check that power is supplied to the preprocessor unit by observing the lighted LED on the front of the case. If the LED is not lighted:

H Check that the power switch on the back of the preprocessor unit is

powered on. If powered off, a 1 (one) is depressed on the switch.

H Check that the AC power cord is plugged into an electrical outlet that

you know is working properly.

H If the LED is still not lighted, unplug the unit from the electrical outlet

and call a Tektronix Service representative.

NOTE. We recommend that you save the system. This ensures that system properties are retained for future use. However, care must be taken while restoring the system to exactly the same system as previously restored. Any changes (hardware or software) to the system causes the saved system not to restore. Saving the system should only be done on stable systems.

TMS817/TMS818 PCIExpress Bus Support

1- 29

Getting Started

L00 L02 L04 L06 L08 L10 L12 L14

Mode

CLK0

CLK1

CLK2

CLK0

CLK1

CLK2

MODE WIDTH

PN PN PN PN PN PN PN PN

PN L01PNL03PNL05PNL07PNL09PNL11PNL13

L01 L03 L05 L07 L09 L11 L13 L15

ON OFF

EXT CLOCK

L00 L02 L04 L06 L08 L10 L12 L14 PN PN PN PN PN PN PN PN

PN L01PNL03PNL05PNL07PNL09PNL11PNL13

L01 L03 L05 L07 L09 L11 L13 L15

ON OFF

EXT CLOCK

TMS817 Probe Adapter

Self Test LED

Figure 1- 18: Self test connector

SELF TEST

PN L15

PROBE POWE R

PN L15

PROBE POWE R

WIDTH

1 2

2 3

UPSTREAM

DOWNSTREAM

X1 X2

X2 X4

X4 X8

X8 X16

X16

GGGGGGGG

MIDBUSFOOTPRINT

CExyCG

GGGGGGGG

CIxCKxCMxCP

xyyyyy

xyyCHxyyyyy

CLKNL00PNL01NPL02NPL03PNL04PNL05NPL06NPL07PNL08PNL09NPL10NPL11PNL12PNL13NPL14

PN P

CLKNL00PNL01NPL02NPL03PNL04PNL05NPL06NPL07PNL08PNL09NPL10NPL11PNL12PNL13NPL14NPL15

PN P

MODE

8b DESCRAMBLE ON

8b DESCRAMBLE OFF

10b DESCRAMBLEOFF

RAWDATA

SELF TEST

L15

CJxCLxCNxCQ

GGGGGGGG

Follow these steps to run the self test:

1. Connect the midbus probe head to the self test midbus footprint on the preprocessor unit. Check that you also connected the interconnect strip correctly (see Figure 1--4 on page 1--9).

2. Connect the probe-head plugs to the front of the preprocessor unit as listed in Table 1--6. Connect the power connector to the front of the preprocessor unit.

Table 1- 6: Probe-head channel connections

Probe head channel name

Channel A L00 X=N

Channel B L01 X=N

Channel C L02 X=N

Channel D L03 X=N

Channel E L04 X=N

Channel F L05 X=N

Channel G L06 X=N

Channel H L07 X=N

Preprocessor unit channel name

Probe head polarity

1- 30

Channel I L08 X=P

Channel J L09 X=P

Channel K L10 X=P

Channel L L11 X=P

TMS817/TMS818 PCIExpress Bus Support

Table 1- 6: Probe-head channel connections (Cont.)

Getting Started

Probe head channel name

Channel M L12 X=P

Channel N L13 X=P

Channel P L14 X=P

Channel Q L15 X=P

Preprocessor unit channel name

Probe head polarity

3. Choose a support package that matches your link width using Table 1--7.

Table 1- 7: Test package load options

Support package

PCIEx421_test x1, x2, and x4

PCIEx8_test x8

PCIEx16a_test x16

PCIEx16b_test x16

PCIEx16c_test x16

Lane width

NOTE. To test a complete x16 unidirectional link, all three of the x16 support packages need to be used.

4. Set the front panel switches as listed in Table 1 --8.

Table 1- 8: Front panel switch settings

Name

Link width switch Position 2 for x1,x2,and x4 (for self test)

Mode switch Set to switch position 4

External clocking switch Set to OFF

Position

Position 3 for x8

Position 4 for x16 (part a)

Position 5 for x16 (part b)

Position 3 for x16 (part c)

TMS817/TMS818 PCIExpress Bus Support

1- 31

Getting Started

5. Load the appropriate test support package on the module. For example, if testing a x8 link, load the PCIEx8_test support package. Table 1--9 lists module configurations for each test support package:

Table 1- 9: Type and number of module for test package

Support package Module

PCIEx421_test One unmerged, 102- or 136 channel module

PCIEx8_test One unmerged, 136 channel module

PCIEx16a_test Two merged, 136 channel modules

PCIEx16b_test Two merged, 136 channel modules

PCIEx16c_test Two merged, 136 channel modules

6. Power off all modules other than the module that has the PCIEx8_test support package loaded on it.

NOTE. PCIEx8_test needs one unmerged 136 channel module.

a. Click on System, and then select System Trigger.

b. Enable “System triggered by this module”, and select the module on

which the test support package is loaded.

c. Click OK.

7. ClickontheSetup button, and then click on Define Compare.

a. In the compare window, enable “Enable Data Compare”.

b. Click on Add Data Source and browse to:

C:\Program Files\TLA700\Supports\PCIEx8_Test\PCIEx8_ComparisonData.tla (example for a x8 test)

c. Click OK, and close the compare window.

NOTE. For the PCIEx421_test support package there are two comparison data files. Use the PCIEx421_102ch_ComparisonData.tla file for an 102 channel module and the PCIEx421_136ch_ComparisonData.tla file for an 136 channel module.

1- 32

8. Click on Setup and change the memory depth to 1024.

TMS817/TMS818 PCIExpress Bus Support

Getting Started

9. In the Setup window, click on Channel Compare in the Table Shows box, and then:

a. Click on the check mark beside the clk channel. This disables the clock

signal from being compared during self test.

b. Minimize the Setup window.

10. Click on System, and then select Repetitive Properties in the pull down

menu.

a. Enable “Stop if compare with reference is not equal”.

b. Click OK.

11. Add a new data listing window for the PCIEx8_Test module.

12. Right click on a group name in the Listing Window and select Properties.

a. Click on the Listing Window tab.

b. Enable Acq != Ref, and select the color red. Enable Acq = Ref, and

select the color green. Click OK.

13. Click on System, and enable Repetitive.

14. ClickontheStatus button and use the scroll bar to scroll to the PCIEx8_test

module.

15. In the logic analyzer system command bar, press the Run button.

16. In the Status window, look at Data Compare. If you see Data Compare:Equal

it means that the preprocessor unit is working correctly and the self test has finished successfully. Press the Stop button.

If the system stops by itself, you will see DataCompare:Not Equal. This means that there are bad channels and you will need to check the listing window for these bad channels. All bad data is displayed in red.

TMS817/TMS818 PCIExpress Bus Support

1- 33

Getting Started

For TMS818. To test all eight channels of the probe head:

H Test Channel A, Channel B, Channel C, and Channel D using the procedure

above. To test Channel E, Channel F, Channel G and Channel H connect to the preprocessor unit as shown in Table 1--10:

Table 1- 10: Probe adapter connections for channel E, F, G, and H

Probe head channel name

Channel E L00 X=N

Channel F L01 X=N

Channel G L02 X=N

Channel H L03 X=N

Preprocessor unit channel name

Probe head Polarity

H Follow the Self Test procedure for a X4 link.

Test Characteristics. Following is a list of test characteristics:

H The system stops as soon as acquired data does not match the reference data.

Acquired data can be seen in the listing window; incorrect data is red and correct data is green.

H If the system is manually stopped while it is running, errors are seen in the

listing window because the trigger is not aligned to the trigger in the comparison data.

H The self test is effective at finding stuck bits, but it will not stop if one or

more of the incoming lanes are dead. If there is a dead lane, 17C is shown on all lanes when manually stopped.

1- 34

H Power to the probe head is not connected. If this is the case, connect the

power to the power connector on the probe head.

H One or more of the incoming serial channels are dead.

To find out which channel is dead:

1. Load the appropriate support package on the module (in this example load the PCIEx8 support package), and change the mode switch setting to the appropriate position.

2. Attach the probe head to the target system (see page 1-- 4).

3. Take an acquisition.

TMS817/TMS818 PCIExpress Bus Support

Getting Started

If one or more lanes show 1BC in the listing window that means that those lanes are dead.

4. To verify that the bad channels are on the probe head and not the preprocessor unit, swap the bad lane(s) with a good lane(s).

If the good lanes show 1BC, either the probe head channels are dead or the channels on the target system are dead. If you received 17C during the self test, the channel on the probe head is dead.

If performing the preceding steps did not reveal the problem, call a Tektronix sales representative.

TMS817/TMS818 PCIExpress Bus Support

1- 35

Getting Started

Check list for Troubleshooting

Table 1- 11: Troubleshooting checklist

 Description Notes

Check that the lane polarity and lane ordering is correct. See page 1--27.

Check that the interconnect strip is connected. See page 1--8.

Check that the midbus retention mechanisms are soldered correctly. See page 1--8.

Check that the power cable for the probe head is connected to the probe power on the front of the preprocessor unit. See Figure 1--12.

Check that the mode and the link width switches are set to the appropriate settings. See page 1--20.

Check that the correct software support package is loaded.

Check that the logic analyzer modules are the correct modules and that they have the maximum frequency setting. See page 1--2.

Check that the Self Test runs. See page 1--29.

Check that the external clock cable is connected. See Figure 1--11.

Check that the data eye of the target system meets the minimum requirements. See page 3--3.

Check that the external clock signal meets minimum requirements. See page 3--3.

1- 36

TMS817/TMS818 PCIExpress Bus Support

Getting Started

TMS817/TMS818 PCIExpress Bus Support

1- 37

Getting Started

Care and Maintenance

Before cleaning this product, read the following information.

WARNING. To prevent personal injury or damage to the preprocessor unit, refer servicing of internal parts in the preprocessor unit to Tektronix authorized personnel only. There are no user-serviceable parts inside the cover of the preprocessor unit.

CAUTION. Static discharge can damage the probe adapter, the probes, and the module. To prevent static damage, you must handle components only in a static-free environment.

The probe adapter, consisting of the probe head and preprocessor unit, does not require scheduled or periodic maintenance. However, to keep good electrical contact and efficient heat dissipation, keep the probe adapter free of dirt, dust, and contaminants. When not in use, store the probe adapter in the original shipping bags and cardboard carton.

External Cleaning Only

Clean dirt and dust with a soft bristle brush. For more extensive cleaning, use only a damp cloth moistened with deionized water; do not use any other chemical cleaning agents.

WARNING. To prevent harm to yourself or damage to the preprocessor unit, do not open the preprocessor unit for cleaning or allow any moisture inside the unit. Refer servicing of internal parts in the preprocessor unit to Tektronix authorized personnel only. External parts may be replaced by qualified service personnel.

1- 38

TMS817/TMS818 PCIExpress Bus Support

Ship the Probe Adapter

Getting Started

To commercially transport the TMS817 and TMS818 probe adapters, package as follows:

1. Use the existing cardboard shipping carton and cushioning material.

If the existing shipping carton is not available, use a double-walled, corrugated cardboard shipping carton that allows a 3 inch (7.62 cm) minimum on all sides of the product.

2. If you are shipping a probe adapter to a Tektronix service center for Warranty service, attach a tag to the probe adapter s howing the following:

H Owner’s name and address

H Name of a person who can be contacted

H Probe adapter type and serial number

H Description of the problem

TMS817/TMS818 PCIExpress Bus Support

1- 39

Getting Started

3. Place the midbus probe head in a separate static shielding bag and close with nonstatic generating tape.

CAUTION. To prevent damage to the probe head and preprocessor unit, do not place the probe head in the large static shielding bag with the processor unit.

Figure 1- 19: Place the probe head in a static shielding bag

4. Place the preprocessor unit inside a static shielding bag.

5. Place the foam end caps on both sides of the preprocessor unit and place the

preprocessor unit inside the cardboard carton (see Figures 1--20).

1- 40

Figure 1- 20: Place the end caps on the preprocessor

TMS817/TMS818 PCIExpress Bus Support

Getting Started

6. To stabilize the preprocessor unit, place the smaller cardboard carton next to the preprocessor unit (see Figure 1--21). If you are returning the slot board, place it inside a static shielding bag and inside the smaller carton.

7. Place the midbus probe head and cable on top of the preprocessor unit.

Figure 1- 21: Place the preprocessor unit in the carton

8. Close and tape the cardboard carton.

TMS817/TMS818 PCIExpress Bus Support

1- 41

Getting Started

1- 42

TMS817/TMS818 PCIExpress Bus Support

Operating Basics

Setting Up the Support

This section provides information on how to set up the TMS817 and TMS818 PCIExpress bus support products with a Tektronix logic analyzer. The information covers software installation.

Before you acquire and display data, you must load the appropriate support and specify setups for clocking and triggering. The support provides default values for each of these setups, but you can change them on the Tektronix logic analyzer as needed.

Installing the Support Software

NOTE. Before you install any software, you should verify that the bus support software is compatible with the logic analyzer software.

To install the software on your Tektronix logic analyzer, follow these steps:

1. Insert the CD-ROM in the CD drive.

Support Packages

PCIEx1

PCIEx2

PCIEx4

PCIEx8

2. Click the Windows Start button, point to Settings, and click Control Panel.

3. In the Control Panel window, double-click Add/Remove Programs.

4. Follow the instructions on the screen for installing the software from the CD.

To remove or uninstall software, follow the above instructions except select Uninstall. You must close all windows before you uninstall any software.

The probe adapter products install support packages on the Tektronix logic analyzer. Each support package can offer different clocking and display options.

This support package provides disassembly support for a x1 unidirectional link.

This support package provides disassembly support for a x2 unidirectional link.

This support package provides disassembly support for a x4 unidirectional link.

This support package provides disassembly support for a x8 unidirectional link (TMS817 only).

TMS817/TMS818 PCIExpress Bus Support

2- 1

Setting Up the Support

PCIEx16

PCIEx421_test

PCIEx8_test

PCIEx16a_test

PCIEx16b_test

PCIEx16c_test

This support package provides disassembly support for a x16 unidirectional link (TMS817 only).

This support package is used in the self-test procedure to verify correct operation of the preprocessor unit and cables when configured for x1, x2, or x4 link widths when using a 102 or 136 channel Tektronix logic analyzer modules.

This support package is used in the self-test procedure to verify correct operation of the preprocessor and cables when configured for a x8 link width when using a 136 channel Tektronix logic analyzer module.

These support packages are used in the self-test procedure to verify correct operation of the preprocessor and cables when configured for a x16 link width and using two 136 channel Tektronix logic analyzer modules.

Custom Clocking Option

A special clocking program is loaded to the module every time you load one of the support packages. Each support package offers different clocking options.

Custom is one of three menu choices found in the Clocking Options menu (the other two options are External and Internal clocking).

All Cycle Types

Valid Packet Cycles Only

TLPs and DLLPs Only

TLPs Only

All supports provide the following Custom clocking options:

H All Cycles Types

H Valid Packet Cycles Only

H TLPs and DLLPs Only

H TLPs Only

All channels are acquired at each edge of the clock.

All channels are acquired at each edge of the clock when TS1/TS2, Fast Training Sequences, Skip packets, and TLPs or DLLPs are detected by the preprocessor unit.

All channels are acquired at each edge of the clock when TLPs (Transaction Layer Packets) or DLLPs (Data Link Layer Packets) are detected by the preprocessor unit.

All channels are acquired at each edge of the clock when a TLP is detected by preprocessor unit.

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TMS817/TMS818 PCIExpress Bus Support

Reference Tables

Setting Up the Support

The Reference section of this manual contains three groups of tables which are listed below:

Group Definitions

Symbols

Channel Assignments

Group definition tables are located on page 4--69 of the Reference section.

Symbol tables are located on page 4--1 of the Reference section.

The software automatically creates channel assignments for each support package. Channel assignment tables are located on page 4--173 of the Reference section.

Installing Trigger Programs

The following trigger programs are installed along with the TMS817 and TMS818 PCIExpress bus support packages.

H Trigger Programs for the PCIEx1 support package are installed in the

C:\Program Files\TLA700\Supports\PCIEx1\EasyTriggers folder.

H Trigger Programs for the PCIEx2 support package are installed in the

C:\Program Files\TLA700\Supports\0PCIEx02\EasyTriggers folder.

H Trigger Programs for the PCIEx4 support package are installed in the

C:\Program Files\TLA700\Supports\0PCIEx04\EasyTriggers folder.

H Trigger Programs for the PCIEx8 support package are installed in the

C:\Program Files\TLA700\Supports\0PCIEx08\EasyTriggers folder.

H Trigger Programs for the PCIEx16 support package are installed in the

C:\Program Files\TLA700\Supports\PCIEx16\EasyTriggers folder.

Loading Trigger Programs

To load a trigger program from a support package, follow these steps:

1. Load the support package.

2. From the system window, click the

Figure 2--1 on page 2--4 shows an open trigger window.

3. Scroll through the EasyTrigger programs to find the trigger program that you need.

TMS817/TMS818 PCIExpress Bus Support

Trigger button.

2- 3

Setting Up the Support

A description of an EasyTrigger program is provided in the Trigger window (see Figure 2-- 1 for the location of the description). In this description some programs include an illustration of the packet that highlights the packet fields the program uses as trigger criteria.

4. Select an EasyTrigger program from the list, and fill in the fields.

You may not be able to fill out as many fields as you want in the Trigger window because some link widths do not allow all fields to be specified within the EasyTrigger program due to trigger resource limitations.

You are now ready to trigger on the acquired data. For additional information on triggering, refer to the logic analyzer online help.

2- 4

Description

Figure 2- 1: Trigger window

TMS817/TMS818 PCIExpress Bus Support

Setting Up the Support

Trigger Programs

Following is a list of EasyTrigger programs:

Triggering on specific types of packets:

DLLP

Trigger on Ack or Nak DLLP

Trigger on Flow Control DLLP

Trigger on Power Management DLLP

Trigger on Vendor Specific DLLP

TLP

Trigger on 32--bit Memory Request TLP

Trigger on 64--bit Memory Request TLP

Trigger on I/O Request TLP

Trigger on Configuration Request TLP

Trigger on Message Request TLP

Trigger on Completion TLP

Triggering on packets by type:

DLLPs

Trigger on DLLP

Trigger on DLLP1 or DLLP2

TriggeronDLLP1followedbyDLLP2

Trigger on DLLP1 or DLLP2 or DLLP3

TriggeronDLLP1followedbyDLLP2followedbyDLLP3

TLPs

Trigger on TLP

Trigger on TLP1 or TLP2

TriggeronTLP1followedbyTLP2

Trigger on TLP1 or TLP2 or TLP3

TriggeronTLP1followedbyTLP2followedbyTLP3

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Setting Up the Support

TLPs and DLLPs

Trigger on DLLP followed by TLP

Trigger on TLP followed by DLLP

Trigger on DLLP or TLP

TriggeronDLLP1followedbyDLLP2followedbyTLP

TriggeronTLP1followedbyTLP2followedbyDLLP

Trigger on Simple Events

Trigger on Hot Reset (Reset bit Asserted)

Trigger on rule violation

Trigger on Electrical Idle

Trigger on Training Sequence

Trigger on FTS

Trigger on skip packet

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TMS817/TMS818 PCIExpress Bus Support

Acquiring and Viewing Disassembled Data

This section describes how to acquire data and view it disassembled.

Acquiring Data

Once you load the support package, choose a clocking mode, and specify the trigger, you are ready to acquire and disassemble data.

If you have problems acquiring data, refer to your logic analyzer online help for more information about acquiring data.

Viewing Disassembled Data

You can view data in two display formats:

H Waveform (state)

H Listing (disassembly)

TMS817/TMS818 PCIExpress Bus Support

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Acquiring and Viewing Disassembled Data

Waveform Window Format

The waveform display shows each lane of data in rows. This data is not disassembled.

NOTE. If a channel group is not visible, you must use Add waveform in the waveform window to make the group visible. Refer to Changing How Data is Displayed on page 2--11 for more information.

Figure 2--2: Waveform display

Listing Window Format

2--8

The listing display shows the packet fields as searchable columns. Figure 2--3 shows an example of a disassembled Listing-Window display format with the Extended Detail control ON.

NOTE. If a channel group is not visible, you must use Add Column in the Listing window to make the group visible. Refer to Changing How Data is Displayed on page 2--11.

TMS817/TMS818 PCIExpress Bus Support

Link Details

Column

Acquiring and Viewing Disassembled Data

Figure 2--3: PCIEx4 display with Extended Details ON

The disassembler displays special characters and strings to indicate significant events. Table 2--1 describes these special characters and strings.

Table 2--1: Description of special characters in the display

Character or string

Definition

Insufficient room on the screen to show all available data.

Invalid data or group, including read data.

TMS817/TMS818 PCIExpress Bus Support

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Acquiring and Viewing Disassembled Data

Table 2--2 lists the groups displayed in the listing window for all link widths.

Table 2--2: Groups displayed in the listing window (for all link widths)

Group Radix Number of bits Default state

L00 – L15* TEXT N/A ON

Link_Details TEXT N/A ON

TLP_Seq_No HEX 8 ON

FMT BIN 2 ON

Type BIN 5 ON

TC BIN 3 ON

TD BIN 1 ON

EP BIN 1 ON

Attr BIN 2 ON

DataLength DEC 10 ON

Requester_ID HEX 16 ON

Req_Bus_No HEX 8 ON

Req_Dev_No HEX 5 ON

Req_Ftn_No HEX 3 ON

Completer_ID HEX 16 ON

Cpl_Bus_No HEX 8 ON

Cpl_Dev_No HEX 5 ON

Cpl_Ftn_No HEX 3 ON

Bus_No HEX 8 ON

Device_No HEX 5 ON

Function_No HEX 3 ON

Tag HEX 8 ON

Last_DWBE HEX 4 ON

First_DWBE HEX 4 ON

Addr64 HEX 32 ON

Addr32 HEX 32 ON

Register_No HEX 10 ON

Lower_Addr HEX 6 ON

Msg_Code HEX 8 ON

Vendor_ID HEX 16 ON

Cpl_Stat HEX 3 ON

BCM BIN 1 ON

Byte_Count HEX 12 ON

2--10

TMS817/TMS818 PCIExpress Bus Support

Acquiring and Viewing Disassembled Data

Table 2--2: Groups displayed in the listing window (for all link widths) (Cont.)

Group Default stateNumber of bitsRadix

TLP_Digest HEX 32 ON

TLP_CRC HEX 32 ON

AckNak_Seq_Num HEX 12 ON

VC_ID HEX 3 ON

HdrFC HEX 8 ON

DataFC HEX 12 ON

Vendor HEX 24 ON

DLLP_CRC HEX 16 ON

* The actual number of lane columns that are displayed depends on the support

package that is loaded

Invalid groups. The disassembler invalidates any group that is not valid for a given sample. The disassembler uses dashes to represent invalid groups.

Searching Through Data. Data searching is supported in the listing display. See Hardware-Assisted Searching on page 2--14 of this manual and the logic analyzer online help for additional search information.

Changing How Data is Displayed

There are other options listed in the Disassembly property page to control how you analyze and display disassembled data in the listing window.

For example, if you are searching for a TLP packet and do not want to see any other types of packets, choose Show TLPs Only.

In the listing window, the following bus specific fields allow you to further modify disassembled data to suit your needs.

TMS817/TMS818 PCIExpress Bus Support

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Acquiring and Viewing Disassembled Data

Figure 2--4: Disassembly tab in listing window

Table 2--3: Logic analyzer disassembly display options

Disassembly window Option Description

Show: All (default) All required data is disassembled and shown

including logical idle samples.

Non-Idle Samples Logical idle samples are hidden.

TLP/DLLPs Only

TLPs Only Only samples containing TLPs are shown.

TLP Headers Only Only samples containing TLP headers are

Highlight None (default) None (default)

Disassemble Across Gaps: Ye s

No (default)

Only samples containing TLPs and DLLPs are shown.

shown.

General listing window setting. (not recommended for PCIExpress data) No (default)

Any errors in link traffic detected by the disassembler are displayed regardless of the display option that you selected.

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TMS817/TMS818 PCIExpress Bus Support

Acquiring and Viewing Disassembled Data

Bus Specific Fields

In the Controls submenus you can select any of the following controls to change the way data is displayed.

Extended Link Details. The Link_Details column of the listing window can be set to show or hide extended packet information by setting the Extended Link Details mode to ON or OFF (see page 2--9).

If set to OFF, the Link_Details column displays general packet information on a single line only.

If it is set to ON, the Link_Details column displays extended packet information on multiple lines. All packet fields are decoded and displayed in the Link_Details column. TLP payload data is displayed double word aligned along with the lower word address starting with the address acquired in the TLP header.

OFF (Default)

Calculate DLLP CRC. The disassembler calculates the CRC for DLLPs when this property is set to ON. If the calculated value differs from the value acquired from the link, an error message is displayed in the Link_Details column.

OFF (Default)

Calculate TLP ECRC. The disassembler calculates the ECRC for TLPs when this property is set to ON. If the calculated value differs from the value acquired from the link, an error message is displayed in the Link_Details column.

Off (Default)

Calculate TLP LCRC. The disassembler calculates the LCRC for TLPs when this property is set to ON. If the calculated value differs from the value acquired from the link, an error message is displayed in the Link_Details column.

Off (Default)

TMS817/TMS818 PCIExpress Bus Support

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Acquiring and Viewing Disassembled Data

Align hdr fields to fmttype. This property controls the placement of the TLP header and DLLP field values displayed in individual columns. The values for each packet are displayed on the same line despite the fact that they may be extracted from data spanning multiple samples. Displaying packets on the same line is done to make searching for packets by specifying the values of multiple packet fields possible.

By default, the field values are aligned with the sample containing the STP if it is a TLP or with the sample containing the SDP if it is a DLLP. By setting this property to ON, the packet field values are displayed on the same line as the TLP_fmttype and DLLP_type group values.

Off (Default)

10-bit Mode Acquisition

When the preprocessor unit is configured to acquire the link in 10-bit mode, the listing window displays the symbol encoding in the individual lane columns. No further link analysis is performed.

Hardware-Assisted Search

To use the hardware-assisted search you need software version 4.3 on your Tektronix logic analyzer. This section covers the following hardware-assisted search information:

H Behavior on page 2--15

H Rules for setting up hardware-assisted searches on page 2--15

H Example of a x16 link hardware-assisted search on page 2--19

Features

Following is a list of hardware-assisted search features:

H You can enter hardware search criteria in the Search Definition dialog box of

the listing window.

You can display disassembly columns in the listing window and use hardware-assisted searching.

2--14

H Elements of a search clause, such as groups and channels, do not need to be

visible in the listing window.

H You can mix groups and channels (defined in the Search Definition dialog

box) with disassembly groups in the same search clause, and then use the hardware-assisted search to search acquisition data.

TMS817/TMS818 PCIExpress Bus Support

Acquiring and Viewing Disassembled Data

Hardware-Assisted

Search Behavior

The hardware-assisted search processes data in two parts. First, the hardware portion of the search finds samples that match the criteria defined by the setup groups. Then the software is used to determine if the sample matches the remaining criteria.

Once the hardware portion of the hardware-assisted search is started, the software processing is delayed until the hardware-assisted search finds a sample that matches the hardware portion of the search definition.

Hardware-Assisted Search Speed. If you follow the rules of ordering and logical combinations of setup groups, the hardware-assisted search can significantly reduce your search time and make it faster than using a software-driven search.

Review the following areas that may affect search speed:

H The setup groups defined in the Setup window contain channels that the

hardware can search.

Groups of channels from a single module are faster to process than groups from multiple modules that have their channels searched independently on more than one module. Multiple-module searches can result in false-positive matches (reported by individual modules) that need to be correlated with search results from other modules. A multiple-module search has the potential to slow the hardware-assisted search significantly.

Hardware-Assisted

Search Rules

H The type of data acquired and the type of search performed.

If the module acquisition contains large amounts of data that is identical to the search criteria (from the perspective of the hardware), then the search speed is the same for the software-driven search and the hardware-assisted search. This is because the modules find many matches that the software needs to qualify.

If the module acquisition contains data that is mostly different from the search criteria, hardware-assisted searches may be faster than software-driven searches.

For the hardware-assisted search to occur in the listing window, you must follow the Module Search rules and the Clause Description rules.

Module Search Rules. Failure to meet these rules turns off hardware-assisted searching:

1. The module search expression must contain only one active clause. All other defined searches must be disabled (turned off).

2. The clause must use the When Present condition.

TMS817/TMS818 PCIExpress Bus Support

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Acquiring and Viewing Disassembled Data

Clause DescriptionSearch Rules

software events determines when a hardware-assisted search is used. The search clause can contain events that are combined using AND and OR.

Events that are searched using hardware are called hardware events and events that can only be searched using software are called software events.

H Hardware events include user groups and channels without support package

names, for example, L00_protocols and TLP_fmttype.

H Software events include sample, timestamp, anything events, and any group

event using a disassembly group (groups prefixed with the support package name), for example, PCIEx8 L00 and PCIEx8 TLP_fmttype.

When evaluating the list of events in a clause, use the following rules:

NOTE. The first rule met is used to set up the hardware-assisted search. If no rule is met, software searching occurs.

Evaluate the expression starting with the first event and ending with the last.

1. If all events in the expression are ORed together, for example, “(((A | B) | C) | D)...”, then all must be hardware events to use hardware-as-

sisted search. The use of any software event in this expression disables the hardware-assisted search.

. The logical combination of hardware and

2. When an OR expression is followed by one or more ANDs, for example,

“(((A | B) & C) & D)” and if the OR contains all hardware events, then these are used for hardware-assisted search. The OR must precede any AND expression in the list of events.

Evaluate the expression starting with the last event, and ending with the first.

3. For all continuous ANDed events, any hardware events in this series can be

used in hardware-assisted search. For example, “(((A & B) & C) & D)...” all software events within the ANDed set are ignored during hardware-assisted search. If none are hardware events, then a software search is used.

4. When OR expressions are to the left of one or more ANDs, for example,

“(((A | B) & C) & D)...”, and fail Clause Description search rule 2, only those hardware events that are ANDed are considered for hardware-assisted search.

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TMS817/TMS818 PCIExpress Bus Support

Acquiring and Viewing Disassembled Data

5. For all contiguous OR event, expressions to the right determine if they are all hardware events. If they are, then look through the next set of ANDed events to the left for one hardware event and include this in the OR. For example, “(((A & B) | C) | D)...”. Hardware-assisted search is then executed on this set of events.

Table 2--4: Clause description search rules

Hardware-Assisted

Search Example

Rule Expression

“(((A | B)|C)|D)...”

(((A | B) & C) & D)...”

“(((A & B) & C) & D)...”

“(((A | B) & C)&D)...”

“(((A & B) | C)|D)...”

As evaluated from ...

Left to Right All events must be hardware events

Left to Right All OR events must be hardware

Right to Left One or more events must be hard-

Right to Left One or more AND events must be

Right to left All OR events must be hardware

Requirements for enabling hardware-assisted searching

events

ware events

hardware events

events. One or more AND events must be hardware vents.

Starting on page 2--17 is a hardware-assisted search example you can perform that uses a PCIExpress acquisition and contains data acquired from a x16 link. You can also use this example for other link widths, but you may need to use different groups depending on which support is loaded.

The TLPs can start in one of four lanes in a x16 link. Figure 2--5 shows the four TLP starting positions and the format type field locations for a memory write TLP .

TLP starting position

Format type field location (memory write TLP)

Figure 2--5: MWr TLP starting positions and relevant fields

TMS817/TMS818 PCIExpress Bus Support

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Acquiring and Viewing Disassembled Data

To execute a hardware-assisted search for a memory write TLP at a specific address for a x16 link, follow this example:

1. In the Define Search dialog box, click the group arrow and add these groups:

TLP_fmttype_L0

TLP_fmttype_L4

TLP_fmttype_L8

TLP_fmttype_L12

Using these groups in the Define Search dialog box enables a hardware-assisted search. The groups are defined in the setup window.

These groups have symbol tables that describe the type of TLP. There is a TLP_fmttype group for each TLP starting lane in the x16 support package.

2. Click the AND/OR button and choose OR for each group. This step ORs the groups together.

3. Select the = comparison operator.

4. Click the value arrow and choose MWr for memory write TLPs starting in

each starting lane.

Now the modules are configured for a hardware-assisted search for memory write TLP packets starting in all four starting lanes.

5. Click the group arrow and select the PCIEx16 Addr32 group.

The PCIEx16 Addr32 group contains the address value for packets starting in all four starting positions.

6. For the PCIEx16 Addr32 group, click the AND/OR button and select And. This adds PCIEx16 Addr32 group to the rest of the search clause.

7. Select the = comparison operator.

8. Enter the hexadecimal address, 0A000000, in the Hex field. This allows a

search for a particular 32-bit address value for the memory write TLP.

9. Click the When condition arrow and select Present.

When all the search criteria are entered, the Search Definition dialog box displays a Boolean expression describing the clause. See Figure 2--6. The search clause must match one of the search rules on page 2--16 for the hardware-assisted search to run.

2--18

TMS817/TMS818 PCIExpress Bus Support

Acquiring and Viewing Disassembled Data

Click Or

Add the group(s)

Select t= Comparison

3 4

operator

Select MWr

value

6 5

Click And

Add PCIEx16 Addr32 group

Present

RunSelect

Select =

Comparison

operator

Enter hex

address

Boolean expression

(matches module

search rule 2 on

page 2--15)

Figure 2--6: Search for a memory write to address 0A000000

In Figure 2--6, the Boolean expression matches rule 2 of the Module Search rules on page 2--16 and the hardware should be used to help find a match.

10. Click the <<Search Back or Search Forward>> buttons to start the hardwareassisted search.

Troubleshooting Hardware-Assisted Searches. If a hardware-assisted search takes too long, then the Boolean expression may not match one of the Search Clause Description rules or the Boolean expression may contain events that slow the hardware-assisted search.

H Check that your Boolean expression matches one of the rules listed on

page 2--16.

If the expression does not match one of the Search Clause Description rules, then the search is performed entirely in software.

H To increase the speed of the hardware-assisted search, see Hardware-Assisted

Search Speed on page 2--15.

TMS817/TMS818 PCIExpress Bus Support

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Acquiring and Viewing Disassembled Data

NOTE. The search requires all field values from all groups to be displayed in the same line. If one or more of the groups have values displayed on different lines, the search will fail to find a match, even if all the information is obtained from the same packet.

For x1 and x2 link widths, packet field information from disassembly processing is displayed in columns aligned with the start of packet symbol, not the TLP_fmttype textual value. To perform a search similar to this example for these link widths, set the disassembly property field, Align hdr fields to fmttype, to ON (see page 2--14).

Special Messages

This section provides information about the special messages used in this software support. The disassembler uses special messages to indicate significant events. These messages are highlighted in red in the Link Details column of the listing window. Tables 2--5 through 2--12 show the messages and their descriptions.

The special messages are in addition to the errors detected by the preprocessor hardware listed in PCIEx_RuleViol.tsf and PCIEX_RecErr.tsf files. These files are located in the TLA700\Supports\PCIEx directories. These symbol tables are used by the Rule_viol and L??_RecErr groups.

Table 2--5: Training sequence messages

Message Description

Error: Duplicate Lane Number Assignment Indicates that more than one lane has been

assigned the lane number.

Error: Lane No. value in ‘L??’ exceeds max link width

Lane??: Lane Polarity Inversion Indicates that the lane is inverted. The

Indicates that the lane number as acquired in the training sequence is higher than the link width.

corresponding cable at the input to the preprocessor needs to be inverted.

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TMS817/TMS818 PCIExpress Bus Support

Acquiring and Viewing Disassembled Data

Table 2--6: Packet framing messages

Message Description

Error: Malformed packet – Expected END symbol

Indicates that the END symbol was not found in the lane and sample as determined based on type of packet and packet starting lane.

Error: Malformed TLP? Indicates that the TLP is not framed by STP

and END or EDB symbols, or starts in an incorrect lane.

Error: Invalid symbol between END and SDP Indicates that something other than PAD

symbols was acquired between the END symbol from the 1

packet and the SDP symbol of next packet, or two packets are in one symbol time and the next packet does not start immediately following the END symbol of

the 1

packet.

Error: SDP expected in lane 00 Indicates that an SDP symbol was found in a

lane other than lane 00 when not following another packet, or when a previous packet ended in the previous sample.

Error: STP expected in lane 00 Indicates that an STP symbol was found in a

lane other than lane 00 when not following another packet, or when a previous packet ended in the previous sample.

Error: Malformed packet preceding TLP??? Indicates that the TLP is not framed by STP

and END or EDB symbols, starts in an incorrect lane.

Error: Invalid symbol between END and STP Indicates that something other than PAD

symbols was acquired between the END symbol from 1

packet and the STP symbol of next packet or when two packets are in one symbol time and the next packet does not start immediately following the END symbol of the

packet.

Error: Malformed packet -- Missing END??? Indicates that no END/EDB symbol was found

in the expected sample and lane.

Error: Abnormal packet termination Indicates that the packet was interrupted and

terminated by a skip ordered set, training sequence, or FTS, TLP, DLLP.

Non--Idle Bus Indicates the link is supposed be in logical idle

at this sample, but a nonzero value is found in one or more lanes.

TMS817/TMS818 PCIExpress Bus Support

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Acquiring and Viewing Disassembled Data

Table 2--7: DLLP messages

Message Description

Error reading DLLP Indicates that a general error occurred while

Table 2--8: TLP header messages

Message Description

Error reading TLP Indicates a general error occurred while trying

Error Forwarding/Poisoned TLP Indicates that the EP field of TLP header is

trying to decode the DLLP possibly caused by a gap/suppression of data.

to decode the TLP header possibly caused by a gap/suppression of data.

HIGH.

Error: Invalid 1stDWBE/Length values for Req TLP

Error: Invalid LastDWBE/Length values for Req TLP

Zero Length Read Request ---- Possible Flush Indicates that the TLP length field is 1, Last

Error: Invalid Traffic Class for Message TLP Indicates that the TC field was not zero.

Completion Status: + ‘Unsupported Request’, ‘Config Req Rtry Stat ’,or‘Completer Abort’

TLP: Msg – + ‘ERR_COR’, ‘ERR_NONFATAL’, or ‘ERR_FATAL’

Indicates that the TLP length field > 1 and First DWBE field is 0 for request TLPs.

Indicates that the TLP length field is 1 and Last DWBE field is not 0, or TLP length field > 1 and Last DWBE field is 0 for request TLPs.

DWBE is 0, First DWBE is 0, for Memory Read Request.

Indicates completion status other than ‘Successful Completion’.

Indicates that an error message TLP was acquired.

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TMS817/TMS818 PCIExpress Bus Support

Acquiring and Viewing Disassembled Data

Table 2--9: TLP payload messages

Message Description

Error: Expecting valid data in Lane?? Indicates that an invalid data such as a Kcode

was found in a sample and lane that should be TLP payload data.

Error: Payload exceeds TLP Length Field: # Indicates that the payload data exceeds what

the length field indicated. Possible causes include: a missing END symbol, or the inclusion of TLP Digest field without the TD field HIGH.

Error: Packet data total: # DW – does not match length field

Indicates that the payload data exceeds what the length field indicated. Possible causes include: a missing END symbol, or the inclusion of TLP Digest field without the TD field HIGH.

Table 2--10: TLP digest messages

Message Description

Error: Missing TLP Digest or Gap in acquisition Indicates that the TLP digest field was not

found in the sample expected.

Error: Expected TLP Digest starting in Lane?? Indicates that the TLP digest field was not

found in the lane expected.

Table 2--11: CRC checking messages

Message Description

Error: ECRC mismatch ECRC value acquired in TLP digest field does

not match the ECRC value calculated by applying the ECRC algorithm to the acquired data. Possible causes include incorrect ECRC at the transmitter, poor signal quality at probe head, different algorithm used between transmitter and TLA software, incorrect polarity or ordering of cables at the input of the preprocessor, problem with the cables or connecting the preprocessor to the TLA.

Error: CRC mismatch The TLP or DLLP CRC acquired does not

match the CRC value calculated by applying the CRC algorithm to the acquired data.

TMS817/TMS818 PCIExpress Bus Support

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Acquiring and Viewing Disassembled Data

Table 2--12: General acquisition messages

Message Description

Error: Missing Data -- Gap in TLP header Complete decode of TLP header was not

Error: Missing Data -- Gap in DLLP Complete decode of DLLP was not possible

possible due to a gap/suppression of data.

due to a gap/suppression of data.

Error: Missing Data -- Gap in Training Sequence

Error: Missing Data -- Gap in packet Complete decode of Training Sequence

Lane--to--Lane Deskew Error The link was not properly deskewed by

Viewing an Example of Disassembled Data

The demonstration system file (or demonstration reference memory), provided on your CD-ROM, lets you view an example of how the Bus cycles look when they are disassembled. Viewing this system file is not a requirement when preparing the module for use. You can view the system file without connecting the logic analyzer to your target system.

Complete decode of Training Sequence ordered set was not possible due to a gap/suppression of data.

ordered set was not possible due to a gap/suppression of data.

preprocessor unit. Also displayed when sample contains SKP (K28.0) symbols in one or more lanes but not all lanes of the link. This error message is displayed until a sample containing all SKP (K28.0) symbols is found. No further post processing of packets is performed when the link is not deskewed.

2--24

For information on how to view the file refer to the logic analyzer online help.

TMS817/TMS818 PCIExpress Bus Support

Specifications

Circuit Description

This section contains information regarding the specifications of the TMS817 and TMS818 products.

The probe adapter preprocesses all signals on the PCIExpress bus before the PCIExpress bus signals are captured by the logic analyzer. Following is a list of probe head and preprocessor unit functions.

Probe head

Preprocessor unit

The probe head performs the following functions:

H The probe head accesses the PCIExpress bus signals.

H The plugs at the end of the probe head cables allow you to acquire different

combinations of lane positionings and polarities.

The preprocessor unit preprocesses the PCIExpress bus signals for the logic analyzer in the following sequence:

1. Frames the serial data into 10 b symbols based on K28.5 patterns on the bus.

2. Converts the 10 b serial data to 10 b parallel symbols and then converts them

into8bparallel symbols with a few extra control bits.

3. Descrambles the 8 b symbols. Then based on SKIP ordered sets that occurred on those lanes, aligns multiple lanes of8bsymbols.

4. Finally, the preprocessor unit generates qualifiers for the logic analyzer to allow for easy triggering.

TMS817/TMS818 PCIExpress Bus Support

3--1

Specifications

Derived Signals

Table 3--1 lists and defines the derived signals.

Table 3--1: Derived signals

Derived signal Definition

STP_packet_ (0--3) These signals indicate the the sample is part of a TLP, the position of

the STP symbol, and the lane where the TLP started.

STP_cntr (0--12) These signals indicate and track the number of symbol times that

elapse on the PCIExpress bus since the beginning of the present TLP packet. Counter is cleared by STP.

SDP_packet_(0--3)

These signals indicate the sample is part of a DLLP, the position of the SDP symbol, and the lane where the DLLP started.

Specification Tables

Rule_viol (0--2)

SKP_detect

Elec_idle_flag

TS_detect

FTS_detect

END_EDB_detect

These signals indicate that a violation of a specific PCIExpress protocol rule.

This signal indicates the sample is part of a skip ordered-set.

This signal indicates the link is in the electrical idle state.

This signal indicates that the sample is part of a training sequence ordered-set.

This signal indicates that the sample is part of a fast-training sequence ordered-set.

This signals indicates that either an END or EDB is present on a lane in this sample.

Table 3--2 lists the electrical requirements the target system must produce for the probe adapter to acquire correct data.

Table 3--2: Electrical specifications

Characteristics Requirements

Preprocessor unit AC power requirements

Input Voltage 100 -- 240 VAC ± 10% CAT-II

3--2

Input Frequency 50 -- 60 Hz

Input Current 4.0 A (400 VA) Maximum

TMS817/TMS818 PCIExpress Bus Support

Specifications

Table 3--2: Electrical specifications (cont.)

Characteristics Requirements

Target system

Specified data rate 2.5 Gb/s ±100 ppm maximum with no

external clock

2.5 Gb/s ±10% ppm maximum with external clock

Spread Spectrum Frequence modulation rate 0--0.5% @ 33 kHz maximum (must

use clock cable)

Minimum Eye requirement 190 ps wide, 100 m V

trapezoidal (at midbus footprint with probe load)

External Clock input

External Clock differential swing 800 m V

100 MHz ±300 ppm maximum

p--p

maximum (400 mV swing per side of differential pair)

External clock voltage range 0to2V

Midbus probe head timing violation

Insertion loss -- 1 . 0 d B

Insertion jitter 40 ps p-p

Slot board with probe head timing violation

Insertion loss -- 2 . 7 d B

Insertion jitter 25 ps p-p

Table 3--3: Environmental specifications

Characteristic Description

Temperature

differential

p--p

minimum, 4.0 V

p--p

Maximum operating +40° C (+104° F)

Minimum operating 10° C (50° F)

Nonoperating -- 3 0 ° Cto+70° C(--22° F to +158° F)

Humidity 10 to 90% relative humidity, noncondensing up to 30° C,

Altitude

Operating 3 km (10,000 ft) maximum

Nonoperating 12 km (40,000 ft) maximum

Electrostatic immunity The probe adapter is static sensitive

TMS817/TMS818 PCIExpress Bus Support

maximum wet bulb temperature of 29° Cto40° C

3--3

Specifications

Table 3--3: Environmental specifications (cont.)

Characteristic Description

Required airflow clearances (preprocessor unit)

Sides 2in(5.08cm)

3--4

TMS817/TMS818 PCIExpress Bus Support

Load Models

Specifications

Figure 3--1 shows the load model for the midbus probe adapter PCIExpress signals.

50 Ω

0.387 pF

midbus probe

parasitics

0.387 pF

midbus probe

parasitics

200 Ω

1nF

Figure 3--1: Midbus load model

Figure 3--2 shows the load model for the Slot board PCIExpress signals.

Mated

slot

connector

Zo =50 Ω

L = 5.500 mil D = 0.794 ns A = 0.582 dB R = 2.107 Ω

0.193 pF

midbus pad

parasitics

0.387 pF

midbus probe

parasitics

250Ω midbus probe parasitics

1000 pF midbus probe parasitics

Zo =50 Ω

L = 1.000 mil D = 0.144 ns A = 0.106 dB R = 0.383 Ω

Figure 3--2: Slot load model

Mated

slot

connector

TMS817/TMS818 PCIExpress Bus Support

3--5

Specifications

gyp

Table 3--4: Certifications and compliances

Category Standards or description

EC Declaration of Conformity -Low Voltage

U.S. Nationally Recognized Testing Laboratory Listing

Canadian Certification CAN/CSA C22.2 No. 1010.1 Safety requirements for electrical equipment for measurement,

Installation (Overvoltage) Category Descriptions

Equipment Type Test and measuring

Safety Class Class 1 (as defined in IEC 61010-1, Annex H) -- grounded product

Overvoltage Category Mains input: Overvoltage Category II (as defined in IEC 61010-1, Annex J)

Pollution Degree Descriptions Pollution Degree 2 (as defined in IEC 61010-1). Note: Rated for indoor use only.

Compliance was demonstrated to the following specification as listed in the Official Journal of the European Communities:

Low Voltage Directive 73/23/EEC, amended by 93/68/EEC

EN 61010-1/A2:1995 Safety requirements for electrical equipment for measurement

control and laboratory use.

UL3111-1 Standard for electrical measuring and test equipment.

control, and laboratory use.

Terminals on this product may have different installation (overvoltage) category designations. The installation categories are:

CAT III Distribution-level mains (usually permanently connected). Equipment at this level is

typically in a fixed industrial location.

CAT II Local-level mains (wall sockets). Equipment at this level includes appliances, portable

tools, and similar products. Equipment is usually cord-connected.

CAT I Secondary (signal level) or battery operated circuits of electronic equipment.

All other inputs and outputs: 5 V maximum

3--6

TMS817/TMS818 PCIExpress Bus Support

Tektronix TMS817, TMS818 Instruction Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

SOFTWARE WARRANTY

HARDWARE WARRANTY

Table of Contents

List of Figures

List of Tables

General Safety Summary

Service Safety Summary

Preface

Manual Conventions

Contacting Tektronix

Getting Started

Product Description

Logic Analyzer Software Compatibility

Logic Analyzer Configuration

LAI Cables

Standard and Optional Accessories

Probe Adapter Review

Connect the Logic Analyzer to the Target System

What Next

Capture Training Sequence

Troubleshooting

Self Test

Check list for Troubleshooting

Care and Maintenance

Ship the Probe Adapter

Setting Up the Support

Installing the Support Software

Support Packages

Custom Clocking Option

Reference Tables

Installing Trigger Programs

Loading Trigger Programs

Acquiring and Viewing Disassembled Data

Acquiring Data

Viewing Disassembled Data

Changing How Data is Displayed

Hardware-Assisted Search

Special Messages

Viewing an Example of Disassembled Data

Specifications

Circuit Description

Derived Signals

Specification Tables

Load Models