Tektronix TMS805 User manual

Instruction Manual

TMS805
RapidIO Bus Support

071-1081-01

www.tektronix.com

Copyright © Tektronix, Inc. All rights reserved.

Tektronix products are covered by U.S. and foreign patents, issued and pending. Information in this publication supercedes
that in all previously published material. Specifications and price change privileges reserved.

Tektronix, Inc., P.O. Box 500, Beaverton, OR 97077

TEKTRONIX and TEK are registered trademarks of Tektronix, Inc.

MagniVu is a trademark of Tektronix, Inc.

SOFTWARE WARRANTY

Tektronix warrants that the media on which this software product is furnished and the encoding of the programs on
the media will be free from defects in materials and workmanship for a period of three (3) months from the date of
shipment. If a medium or encoding proves defective during the warranty period, Tektronix will provide a
replacement in exchange for the defective medium. Except as to the media on which this software product is
furnished, this software product is provided “as is” without warranty of any kind, either express or implied.
Tektronix does not warrant that the functions contained in this software product will meet Customer’s
requirements or that the operation of the programs will be uninterrupted or error-free.

In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration
of the warranty period. If Tektronix is unable to provide a replacement that is free from defects in materials and
workmanship within a reasonable time thereafter, Customer may terminate the license for this software product
and return this software product and any associated materials for credit or refund.

THIS WARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER WARRANTIES, EXPRESS
OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’
RESPONSIBILITY TO REPLACE DEFECTIVE MEDIA OR REFUND CUSTOMER’S PAYMENT IS
THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS
WARRANTY. TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT,
SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER
TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH
DAMAGES.

Table o f Contents

Getting Started

Preface ix...................................................

Manual Conventions ix..............................................

Contacting Tektronix x.............................................

Support Package Description 1--1.......................................

RIO8 1--1......................................................

RIO16 1--1.....................................................

RIO8_T 1--2....................................................

RIO16_T 1--2...................................................

RIO8_34 1--2...................................................

RIO16_34 1--2..................................................

Logic Analyzer Software Compatibility 1--4..............................

Logic Analyzer Configuration 1--4......................................

Requirements 1--4...................................................

Hardware Reset 1--5..............................................

Clock Rate 1--5..................................................

Setup/Hold Time Adjustments 1--5..................................

Nonintrusive Acquisition 1--5......................................

Limitations of the Support 1--5.........................................

Connecting the Logic Analyzer to a Target System 1--6.....................

Labeling P6880 Probes 1--6............................................

Operating Basics

Setting Up the Support 2--1.....................................

Installing the Support Software 2--1.....................................

Support Package Setups 2--2...........................................

Clocking Options 2--2................................................

Clocking State Machines (CSM) 2--4.................................

Acquiring and Viewing Disassembled Data 2--5....................

Acquiring Data 2--5..................................................

Viewing Disassembled Data 2--5........................................

All Display Format 2--6...........................................

Packets & Symbols Display Format 2--7..............................

Packets Only Display Format 2--7...................................

Disassembled Data 2--8...............................................

Cycle Type Labels 2--9...............................................

Special Messages 2--11................................................

Changing How Data is Displayed 2--11...................................

Optional Display Selections 2--12....................................

Bus Specific Fields 2--12...........................................

Viewing an Example of Disassembled Data 2--15...........................

TMS805 RapidIO Bus Support Instruction Manual

i

Table of Contents

Trigger Programs 2--17..........................................

Loading Trigger Programs 2--17.........................................

RIO8 Trigger Programs 2--19........................................

RIO16 Trigger Programs 2--19.......................................

RIO8_34 Trigger Programs 2--20.....................................

RIO16_34 Trigger Programs 2--20....................................

Linking Function 2--21..........................................

Forward Linking 2--21.................................................

Forward Linking Description 2--22...................................

Backward Linking 2--22...............................................

Backward Linking Description 2--22..................................

Linking Cycle Type Labels 2--23........................................

Limitations 2--23.....................................................

Setup/Hold Time Adjustments 2--25...............................

RIO8 Configurations and Settings 2--26...................................

RIO8 RCLK0 AutoDeskew Configuration 2--26........................

RIO8 TCLK0 AutoDeskew Configuration 2--26.........................

RIO16 Configurations and Settings 2--26..................................

RIO16 RCLK1 AutoDeskew Configuration 2--26........................

RIO16 RCLK0 AutoDeskew Configuration 2--26........................

RIO16 TCLK1 AutoDeskew Configuration 2--26........................

RIO16 TCLK0 AutoDeskew Configuration 2--26........................

RIO8_34 Configurations and Settings 2--27................................

RIO8_34 AutoDeskew Configuration 2--27.............................

RIO16_34 Configurations and Settings 2--27...............................

RIO16_34 AutoDeskew Configuration 2--27............................

Reference

Channel Group Definitions 3--1..................................

Channel Groups 3--1.................................................

Symbol and Channel Assignment Tables 3--7......................

Symbol Tables 3--7..................................................

Channel Assignment Tables 3--8........................................

RIO8 and RIO16 Channel Group Assignments 3--8.....................

RIO8_T and RIO16_T Channel Group Assignments 3--11.................

Clock and Control Signal Channel Assignments 3--13....................

Signals not Required for Clocking and Disassembly for RIO8 and

RIO16 Support 3--15.......................................

Signal Source To Probe Connections 3--16.................................

Connections for RIO8 Support 3--17..................................

Connections for RIO16 Support 3--21.................................

Connections for RIO8_T Support 3--26................................

Connections for RIO16_T Support 3--28...............................

Connections for RIO8_34 Support 3--32...............................

Connections for RIO16_34 Support 3--34..............................

ii

TMS805 RapidIO Bus Support Instruction Manual

Specifications

Index

Table of Contents

Signal Acquisition 3--37.........................................

Signal Acquisition in RIO8 3--37.....................................

Signal Acquisition in RIO16 3--38....................................

Signal Acquisition in RIO8_34 3--40..................................

Signal Acquisition in RIO16_34 3--40.................................

Specification Table 4--1...............................................

TMS805 RapidIO Bus Support Instruction Manual

iii

Table of Contents

List of Figures

Figure 2--1: Example of All display format for the RIO8 support

package 2--6...............................................

Figure 2--2: Example of All display format for the RIO16 support

package 2--7...............................................

Figure 2--3: Disassembly display options 2--12.......................

Figure 2--4: Disassembly display options for the RIO8_34 and

RIO16_34 support packages 2--14.............................

Figure 2--5: Loading trigger programs 2--18........................

Figure 2--6: Example of the Linking Function 2--24..................

Figure 3--1: Bus timing diagram for the RIO8 support package 3--38...

Figure 3--2: Bus timing diagram for the RIO16 support package 3--39..

Figure 3--3: Bus timing diagram for the RIO8_34 support

package 3--40...............................................

Figure 3--4: Bus timing diagram for the RIO16_34 support

package 3--41...............................................

iv

TMS805 RapidIO Bus Support Instruction Manual

List of Tables

Table of Contents

Table 2--1: Description of special characters in the display 2--6.......

Table 2--2: Cycle type labels for RapidIO packet names 2--9.........

Table 2--3: Cycle type labels for control symbol names 2--9..........

Table 2--4: Cycle type labels for training pattern names 2--10.........

Table 2--5: Cycle type labels for packet continuation names 2--10......

Table 2--6: Special messages and their descriptions 2--11.............

Table 2--7: Logic analyzer disassembly display options 2--12..........

Table 2--8: Linking cycle type labels and their descriptions 2--23.......

Table 3--1: RIO8_T channel groups 3--3..........................

Table 3--2: RIO16_T channel groups 3--3.........................

Table 3--3: Color symbol table definitions for transmit interface 3--7..

Table 3--4: Color1 symbol table definitions for receive interface 3--7...

Table 3--5: Tx_Frame group assignments 3--8......................

Table 3--6: Tx_Word group assignments 3--8......................

Table 3--7: Rx_Frame group assignments 3--10.....................

Table 3--8: Rx_Word group assignments 3--10......................

Table 3--9: RIO8 _T Tx_Data group assignments 3--11...............

Table 3--10: RIO8_T Rx_Data group assignments 3--12..............

Table 3--11: RIO16_T Tx_Data group assignments 3--12..............

Table 3--12: RIO16_T Rx_Data group assignments 3--13.............

Table 3--13: RIO8 clock and control signal channel

assignments 3--13...........................................

Table 3--14: RIO16 clock and control signal channel

assignments 3--14...........................................

Table 3--15: RIO8_T clock and control signal channel

assignments 3--14...........................................

Table 3--16: RIO16_T clock and control signal channel

assignments 3--14...........................................

Table 3--17: Recommended pin assignments (component side) 3--16....

Table 3--18: Clock and control signals channel assignments for transmit

and receive bus 3--17........................................

Table 3--19: Demuxed clock and control signal channel assignments

for transmit and receive bus 3--17.............................

Table 3--20: A3 probe channel assignments for transmit bus 3--17......

TMS805 RapidIO Bus Support Instruction Manual

v

Table of Contents

Table 3--21: A2 probe channel assignments for transmit bus demuxed

from A3 3--18..............................................

Table 3--22: D3 probe channel assignments for transmit bus demuxed

from A3 3--18..............................................

Table 3--23: D2 probe channel assignments for transmit bus demuxed

from A3 3--19..............................................

Table 3--24: E3 probe channel assignments for receive bus 3--19.......

Table 3--25: E2 probe channel assignments for receive bus demuxed

from E3 3--20..............................................

Table 3--26: E1 probe channel assignments for receive bus demuxed

from E3 3--20..............................................

Table 3--27: E0 probe channel assignments for receive bus demuxed

from E3 3--21..............................................

Table 3--28: Clock and control signals channel assignments for transmit

and receive bus 3--21........................................

Table 3--29: A3 probe channel assignments for transmit bus 3--22......

Table 3--30: A1 probe channel assignments for receive bus 3--22.......

Table 3--31: D3 probe channel assignments for transmit bus demuxed

from A3 3--23..............................................

Table 3--32: D1 probe channel assignments for receive bus demuxed

from A1 3--23..............................................

Table 3--33: C3 probe channel assignments for transmit bus 3--24......

Table 3--34: C1 probe channel assignments for transmit bus demuxed

from C3 3--25..............................................

Table 3--35: E3 probe channel assignments for receive bus 3--25.......

Table 3--36: E1 probe channel assignments for receive bus demuxed

from E3 3--26..............................................

Table 3--37: Clock and control signals channel assignments for

transmit and receive bus 3--26................................

Table 3--38: A3 probe channel assignments for transmit bus 3--27......

Table 3--39: E3 probe channel assignments for receive bus 3--28.......

Table 3--40: Clock and control signals channel assignments for

transmit and receive bus 3--28................................

Table 3--41: A3 probe channel assignments for transmit bus 3--29......

Table 3--42: A1 probe channel assignments for receive bus 3--30.......

Table 3--43: C3 probe channel assignments for transmit bus 3--30......

Table 3--44: E3 probe channel assignments for receive bus 3--31.......

Table 3--45: Clock and control signals channel assignments 3--32......

Table 3--46: C3 probe channel assignments 3--32....................

Table 3--47: C2 probe channel assignments demuxed from C3 3--33....

Table 3--48: A3 probe channel assignments demuxed from C3 3--33....

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TMS805 RapidIO Bus Support Instruction Manual

Table of Contents

Table 3--49: A2 probe channel assignments demuxed from C3 3--34....

Table 3--50: Clock and control signals channel assignments 3--34......

Table 3--51: C3 probe channel assignments 3--35....................

Table 3--52: C2 probe channel assignments 3--35....................

Table 3--53: A3 probe channel assignments demuxed from C3 3--36....

Table 3--54: A2 probe channel assignments demuxed from C3 3--36....

Table 3--55: Sample points in the RIO8 support 3--38................

Table 3--56: Sample points in the RIO16 support 3--39...............

Table 3--57: Sample points in the RIO8_34 support 3--40.............

Table 3--58: Sample points in the RIO16_34 support 3--41............

Table 4--1: Electrical specifications 4--1...........................

TMS805 RapidIO Bus Support Instruction Manual

vii

Table of Contents

viii

TMS805 RapidIO Bus Support Instruction Manual

Preface

This instruction manual contains specific information about the
TMS805 RapidIO software support package and is part of a set of information on
how to operate this product on compatible Tektronix logic analyzers.

If you are familiar with operating bus support packages on the logic analyzer for
which the TMS805 RapidIO support was purchased, you will probably only need
this instruction manual to set up and run the support.

If you are not familiar with operating bus support packages, you will need to
supplement this instruction manual with information on basic operations to set up
and run the support.

Information on basic operations of bus support packages is included with each
product. Each logic analyzer includes basic information that describes how to
perform tasks common to support packages on that platform. This information
can be in the form of logic analyzer online help, an installation manual, or a user
manual.

This manual provides detailed information on the following topics:

H Connecting the logic analyzer to the target system

Manual Conventions

H Setting up the logic analyzer to acquire data from the target system

H Acquiring and viewing disassembled data

This manual uses the following conventions:

H The term “disassembler” refers to the software that disassembles bus cycles

into packets and control symbols.

H The phrase “information on basic operations” refers to logic analyzer online

help or a user manual, covering the basic operations of the bus support.

H The term “logic analyzer” refers to the Tektronix logic analyzer for which

this product was purchased.

TMS805 RapidIO Bus Support Instruction Manual

ix

Contacting Tektronix

Preface

Phone [phone]*

Address Tektronix, Inc.

Department or name (if known)
14200 SW Karl Braun Drive
P.O. Box 500
Beaverton, OR 97077
USA

Web site www.tektronix.com

Sales support 1-800-833-9200, select option 1*

Service support 1-800-833-9200, select option 2*

Technical support Email: [e-mail]

1-800-833-9200, select option 3*

6:00 a.m. -- 5:00 p.m. Pacific time

* This phone number is toll free in North America. After office hours, please leave a

voice mail message.
Outside North America, contact a Tektronix sales office or distributor; see the
Tektronix web site for a list of offices.

x

TMS805 RapidIO Bus Support Instruction Manual

Getting Started

Getting Started

This section contains information on the TMS805 RapidIO bus support, and
information on connecting your logic analyzer to your target system.

Support Package Description

The TMS805 bus support package acquires, decodes and displays RapidIO bus
cycles. The support package allows you to acquire bus cycles with minimal
impact on the normal environment of the system.

The TMS805 software contains six support packages that you can load to handle
the various combinations of bus widths and data rates. A description of each
support package is listed here.

RIO8

RIO16

The features of the RIO8 support package are:

H Supports 8-bit RapidIO bus implementations

H Clock rates from DC up to 375 MHz

H Data rates from DC up to 750 Mb/s

H Provides state, timing, triggering, and disassembly support

H Combined transmit and receive clocking (assuming a common crystal)

H 100% of trigger machine resources available

H Adjusts Setup/Hold time using AutoDeskew

H Real-time filtering of idle control symbols using EasyTriggers when

acquiring either transmit or receive buses only

The features of the RIO16 support package are:

H Supports 16-bit RapidIO bus implementations

H Clock rates from DC up to 375 MHz

H Data rates from DC up to 750 Mb/s

H Provides state, timing, triggering, and disassembly support

H Combined transmit and receive clocking (assuming a common crystal)

H 100% of trigger machine resources available

TMS805 RapidIO Bus Support Instruction Manual

1- 1

Getting Started

H Adjusts Setup/Hold time using AutoDeskew

H Real-time filtering of idle control symbols using EasyTriggers when

acquiring either transmit or receive buses only

RIO8_T

RIO16_T

RIO8_34

The features of the RIO8_T support package are:

H Supports 8-bit RapidIO bus implementations

H Clock rates from DC up to 500 MHz

H Data rates from DC up to 1 Gb/s

H Provides MagniVu and Analog Mux support

The features of the RIO16_T support package are:

H Supports 16-bit RapidIO bus implementations

H Clock rates from DC up to 500 MHz

H Data rates from DC up to 1 Gb/s

H Provides MagniVu and Analog Mux support

The features of the RIO8_34 support package are:

H Supports 8-bit RapidIO bus implementations

H Clock rates from DC up to 375 MHz

H Data rates from DC up to 750 Mb/s

H Provides MagniVu and Analog Mux support

H Adjusts Setup/Hold time using AutoDeskew

H Acquires only transmit or receive buses but not both

H Provides state, timing, triggering, and disassembly support

RIO16_34

1- 2 TMS805 RapidIO Bus Support Instruction Manual

The features of the RIO16_34 support package are:

H Supports 16-bit RapidIO bus implementations

H Clock rates from DC up to 375 MHz

H Data rates from DC up to 750 Mb/s

H Provides MagniVu and Analog Mux support

Getting Started

H Adjusts Setup/Hold time using AutoDeskew

H Acquires only transmit or receive buses but not both

H Provides state, timing, triggering, and disassembly support

MagniVu Support. The RIO8_T and RIO16_T do not support state acquisition;
however, you may view the data in MagniVu. MagniVu provides a waveform
timing view with 125 ps between samples. MagniVu memory is 16 K samples
deep. Special groups, Tx_Data and Rx_Data, have been created for the waveform
display.

Analog Mux Support. Analog mux provides a way to use an external oscilloscope
to view the analog features of the bus while the bus is being probed by the P6880
differential probes. For more information, refer to the information on basic
operations.

Triggering Support. The RIO8, RIO16, RIO8_34, and RIO16_34 support
packages contain a library of EasyTrigger programs to enable you to quickly
trigger on common aspects of the RapidIO protocol. For RIO8, and RIO16
support packages, you can also use the EasyTriggers to filter idle control symbols
in real-time.

Disassembly Support. The RIO8, RIO16, RIO8_34, and RIO16_34 support
packages disassemble data acquired from the RapidIO bus. The salient features
of these disassemblers are:

H Control symbol decoding and display of individual fields (physical layer)

H Packet decoding and display of individual fields for each protocol layer

(physical, transport, and logical)

H Simultaneous decoding of both transmit and receive data buses (only for

RIO8 and RIO16 support packages)

H Transaction level linking and operation level linking of request and response

packets between the acquired transmit and receive buses (only for RIO8 and
RIO16 support packages)

H Layer-level (physical, transport and logical) color highlighting in the

mnemonics column

H Packet-style display using existing logic analyzer listing window architecture

H Identification and display of training patterns

H CRC computation and error detection

TMS805 RapidIO Bus Support Instruction Manual

1- 3

NOTE. Only RapidIO protocol tracking is performed. The disassembler does not
attempt to perform packet payload decoding.

To use this support package efficiently, refer to these documents:

TM

H RapidIO

RapidIO Trade Association.

H RapidIO

Logical Specification Rev. 1.1, 3/2001

Interconnect Specification, Rev 1.1 3/8/2001, developed by

TM

Interconnect Specification Part V: Globally Shared Memory

Logic Analyzer Software Compatibility

The label on the bus support CD-ROM states which version of logic analyzer
software this support package is compatible with.

Logic Analyzer Configuration

Getting Started

Requirements

The TMS805 support package allows a choice of required minimum module
configurations.

The support packages, RIO8 and RIO16, require one 136-channel TLA7Axx
module for each RapidIO port. This includes capture of both the transmit and the
receive buses of the target port assuming a common clock crystal. Systems with
unique clocks for the transmit and receive buses require two independent
modules for simultaneous capture. The support packages, RIO8_34 and
RIO16_34, require one 34-channel TLA7Axx module for acquiring either
transmit or receive bus. Module acquisition speed depends on your requirements,
but the TLA7Axx module speed is 450 MHz by default. This applies to both
8-bit and 16-bit buses.

For the RIO8 and RIO16 support packages, you need four P6880 high-density
differential probes to probe an entire 16-bit RapidIO port and two probes to
probe an entire 8-bit RapidIO port. If you need to probe only the transmit or
receive half of the port, then you need two probes for a 16-bit bus and one probe
for an 8-bit bus. For the RIO8_34 and RIO16_34 support packages, you need one
P6880 high-density differential probe to probe either the transmit or receive half
of the port for an 8-bit or a 16-bit RapidIO bus.

1- 4

Review the electrical specifications in the Specifications section in this manual as
they pertain to your target system, as well as the following descriptions of
TMS805 RapidIO support package requirements.

TMS805 RapidIO Bus Support Instruction Manual

Getting Started

Hardware Reset

Clock Rate

Setup/Hold Time

Adjustments

Nonintrusive Acquisition

If a hardware reset occurs in your system during an acquisition, the application
disassembler might acquire an invalid sample.

The TMS805 RapidIO bus support package can acquire data from the RapidIO
bus operating at 500 MHz
acquisition is 375 MHz.

After loading the RIO8, RIO16, RIO8_34, and RIO16_34 support packages,
AutoDeskew can be used to deskew and verify the logic analyzer Setup/Hold
window. The adjustments are made for each channel. AutoDeskew can also be
used to test for Setup/Hold violations of the current setting. For more informa­tion, refer to the section Setup/Hold Time Adjustments on page 2--25.

Acquiring RapidIO bus cycles is nonintrusive to the target system. That is, the
TMS805 RapidIO support package does not intercept, modify, or present signals
back to the target system.

Limitations of the Support

The TMS805 RapidIO support package has these limitations:

1

for timing only. The maximum rate for state

H Trigger libraries support only a 16 bit transport type (tt) field in the RapidIO

protocol.

H Trigger libraries do not support extended address bits in logical packets of

the RapidIO protocol.

H For combined transmit and receive capture, the transmit and receive bus

clocks must be based on the same crystal. This ensures that the two clocks do
not phase drift over time.

H The support package performs only RapidIO protocol tracking. The

disassembler does not perform packet payload decoding. The support only
identifies and displays payloads.

H The support package does not decode the first few acquired samples until and

unless, the FRAME signals toggle (Tx_Frame must toggle for the transmitter
and Rx_Frame must toggle for the receiver). Instead the message,
“*** INSUFFICIENT DATA TO DISASSEMBLE ***” is displayed.

1

Specification at time of printing. Contact your Tektronix sales representative for
current information on the fastest devices supported.

TMS805 RapidIO Bus Support Instruction Manual

1- 5

H When you start acquiring data from the middle of a packet, the packet is not

decoded, until the FRAME signal toggles (Tx_Frame must toggle for the

transmitter and Rx_Frame must toggle for the receiver). If the FRAME

signal toggles indicating an embedded control symbol, this control symbol is

decoded properly, but the continuation of the packet is treated as

“UNKNOWN DATA”.

Connecting the Logic Analyzer to a Target System

You can use the channel probes and clock probes to make the connections
between the logic analyzer and your target system.

To connect the probes to TMS805 RapidIO signals in the target system, follow
the steps:

1. Power off your target system. It is not necessary to power off the logic

analyzer.

Getting Started

Labeling P6880 Probes

CAUTION. To prevent static damage, handle the target systems, probes, and the
logic analyzer module in a static-free environment. Static discharge can damage
these components.

Always wear a grounding wrist strap, heel strap, or similar device while
handling the target system.

2. Place the target system on a horizontal, static-free surface.

3. Use Tables 3--18 through 3--54 starting on page 3--17 to connect the channel

probes to TMS805 RapidIO bus signals in the target system.

The TMS805 RapidIO bus support package relies on the channel mapping and
labeling scheme for the P6880 Probes. Apply labels, using the instructions
described in the P6810, P6860, and P6880 Logic Analyzer Probes Instruction
manual (Tektronix part number 071-1059-XX).

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TMS805 RapidIO Bus Support Instruction Manual

Operating Basics

Setting Up the Support

This section provides information on how to set up the software support and use
clocking options.

The information in this section is specific to the operations and functions of the
TMS805 RapidIO support package on any Tektronix logic analyzer for which the
support can be purchased. Information on basic operations describes general
tasks and functions.

Before you acquire and display disassembled data, you need to load the support
package and specify the setups for clocking and triggering as described in the
information on basic operations. The support package provides default values for
each of these setups, but you can change the setups as needed.

Installing the Support Software

To install the TMS805 RapidIO software on your Tektronix logic analyzer,
follow these steps:

1. Insert the CD-ROM in the CD drive.

2. Click the Windows Start button, point to Settings, and click Control Panel.

3. In the Control Panel window, double-click Add/Remove Programs.

4. Follow the instructions on the screen for installing the software from the

CD-ROM. A copy of the instruction manual is available on the CD-ROM.

To remove or uninstall software, follow the above instructions and select
Uninstall. You need to close all windows before you uninstall any software.

TMS805 RapidIO Bus Support Instruction Manual

2- 1

Setting Up the Support

Support Package Setups

The software installs six support packages. Each support package offers different
clocking and display options.

Acquisition Setup. The TMS805 RapidIO support package consists of six
different supports. You must make connections and load the appropriate support
package. The support package affects the logic analyzer setup menus (and
submenus) by modifying existing fields, and adding bus-specific fields. The six
support packages that you can load are:

H RIO8

H RIO16

H RIO8_T

H RIO16_T

H RIO8_34

Clocking Options

H RIO16_34

The TMS805 support adds these six selections to the “Load Support Package”
dialog box, under the File pulldown menu.

A special custom clocking program is loaded into the module every time you
load one of the six support packages from the TMS805 RapidIO support
package. Each support package offers different clocking options. You may use
the default clocking options or choose an alternate by clicking the “More...”
button in the logic analyzer setup window.

RIO8 Custom Clocking. The software provides four custom clocking options for
RIO8 support:

H Tx and Rx (clocked by TCLK0). This option captures both transmit (Tx) and

receive (Rx) buses. The transmit and receive buses are captured by the

transmit clock (TCLK0). Both buses must operate at the same frequency.

Setup/Hold values for data and frame signals on the Tx and Rx buses must be

referenced to TCLK0.

2- 2

TMS805 RapidIO Bus Support Instruction Manual

Setting Up the Support

H Tx and Rx (clocked by RCLK0). This option captures both transmit and

receive buses. The transmit and receive buses are captured by the receive
clock (RCLK0). Both buses must operate at the same frequency. Setup/Hold
values for data and frame signals on the Tx and Rx buses must be referenced
to RCLK0.

H Tx only (clocked by TCLK0). This option captures the transmit bus only.

The transmit clock (TCLK0) is used to capture the bus. Setup/Hold values
for data and frame must be referenced to TCLK0.

H Rx only (clocked by RCLK0). This option captures the receive bus only. The

receive clock (RCLK0) is used to capture the bus. Setup/Hold values for data
and frame must be referenced to RCLK0.

RIO16 Custom Clocking. The software provides eight custom clocking options for
RIO16 support:

H Tx and Rx (clocked by TCLK0). This option captures both transmit and

receive buses. The transmit and receive buses are captured by TCLK0. Both
buses must operate at the same frequency. Setup/Hold values for data and
frame signals on the Tx and Rx buses must be referenced to TCLK0.

H Tx and Rx (clocked by RCLK0). This option captures both transmit and

receive buses. The transmit and receive buses are captured by the receive
clock (RCLK0). Both buses must operate at the same frequency. Setup/Hold
values for data and frame signals on the Tx and Rx buses must be referenced
to RCLK0.

H Tx only (clocked by TCLK0). This option captures the transmit bus only.

The transmit clock (TCLK0) is used to capture the bus. Setup/Hold values
for data and frame must be referenced to TCLK0.

H Rx only (clocked by RCLK0). This option captures the receive bus only. The

receive clock (RCLK0) is used to capture the bus. Setup/Hold values for data
and frame must be referenced to RCLK0.

H Tx and Rx (clocked by TCLK1). This option captures both transmit and

receive buses. The transmit and receive buses are captured by TCLK1. Both
buses must operate at the same frequency. Setup/Hold values for data and
frame signals on the Tx and Rx buses must be referenced to TCLK1.

H Tx and Rx (clocked by RCLK1). This option captures both transmit and

receive buses. The transmit and receive buses are captured by RCLK1. Both
buses must operate at the same frequency. Setup/Hold values for data and
frame signals on the Tx and Rx buses must be referenced to RCLK1.

H Tx only (clocked by TCLK1). This option captures the transmit bus only.

TCLK1 is used to capture the bus. Setup/Hold values for data and frame
must be referenced to TCLK1.

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Setting Up the Support

H Rx only (clocked by RCLK1). This option captures the receive bus only.

RCLK1 is used to capture the bus. Setup/Hold values for data and frame

must be referenced to RCLK1.

NOTE. The first four clocking options give you the option of using an additional
probe head to ease routing. The last four clocking options trade routing for
minimal number of probe heads required.

RIO8_34 and RIO16_34 Custom Clocking. The software provides one custom
clocking option for the supports:

All cycles. This option captures either the transmit (Tx) or the receive (Rx)

bus. Setup/Hold values for data and frame signals on the Tx or Rx buses

must be referenced to the clock signal CLK0 for RIO8_34 and to CLK1 for

RIO16_34.

Clocking State Machines

(CSM)

The Clocking State Machine of each support package is described below:

RIO8 CSM. On a RapidIO bus, data is aligned to a 32-bit boundary. The acquisi­tion module captures an 8-bit bus and performs a four-way demux to 32 bits.
These 32 bits can match the RapidIO 32-bit boundary or be 50% out of phase.
The RIO8 CSM ensures that the captured 32 bits match the RapidIO 32-bit
boundary for both transmit and receive buses before storing the data.

RI016 CSM. In the RIO16 support, the 32 bits of captured data (two-way demuxed
from the 16-bit bus) always matches the alignment of the RapidIO 32-bit
boundary. Therefore, the RIO16 CSM has only one state that stores data on every
clock.

RI08_34 CSM. On a RapidIO bus, data is aligned to a 32-bit boundary. The
acquisition module captures an 8-bit bus and performs a four-way demux to 32
bits. The RIO8_34 CSM ensures that the captured 32 bits match the RapidIO
32-bit boundary before storing the data.

RI016_34 CSM. In the RIO16_34 support, the 32 bits of captured data (two-way
demuxed from the 16-bit bus) always matches the alignment of the RapidIO
32-bit boundary. Therefore, the RIO16_34 CSM has only one state that stores
data on every clock.

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TMS805 RapidIO Bus Support Instruction Manual

Acquiring and Viewing Disassembled Data

This section describes how to acquire data and view it disassembled. The
following information covers these topics and tasks:

H Acquiring data

H Viewing disassembled data in various display formats

H Viewing cycle type labels

H Changing the way data is displayed

Acquiring Data

The TMS805 RapidIO software package installs six different supports: RIO8,
RIO16, RIO8_T, RIO16_T, RIO8_34, and RIO16_34.

Once you load the support package, choose a clocking mode, and specify the
trigger, you are ready to acquire and disassemble data.

If you have any problems acquiring data, refer to information on basic operations
in your logic analyzer online help.

Viewing Disassembled Data

You can view disassembled data in RIO8, RIO16, RIO8_34, and RIO16_34
support packages in three display formats:

All
Packets & Symbols
Packets Only

The information on basic operations describes how to select the disassembly
display formats.

NOTE. You must set the selections in the Disassembly property page correctly for
your acquired data to be disassembled correctly. Refer to Changing How Data is

Displayed on page 2--11.

If a channel group is not visible, you must use Add Column or Ctrl+L to make
the group visible.

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Acquiring and Viewing Disassembled Data

The disassembler displays special characters and strings in the instruction
mnemonics to indicate significant events. Table 2--1 shows these special
characters and strings and describes what they represent.

All Display Format

Table 2- 1:

Character or string displayed Description

> Insufficient room on the screen to show all available data.

h The values of different fields of all three layers are displayed

Description of special characters in the display

in hexadecimal. This character is suffixed with the field value.

In this option the information pertaining to all the three layers along with payload
and special messages are displayed. Figure 2--1 shows an example of the All
display format for the RIO8 support package.

Figure 2- 1: Example of All display format for the RIO8 support package

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TMS805 RapidIO Bus Support Instruction Manual