Tektronix TMS711 Instruction Manual
Instruction Manual
TMS711
320C6211/C6711 Microprocessor Support
071-0877-00
Warning
The servicing instructions are for use by qualified
personnel only. To avoid personal injury, do not
perform any servicing unless you are qualified to
do so. Refer to all safety summaries prior to
performing service.
www.tektronix.com
Copyright © T ektronix, Inc. All rights reserved. Licensed software products are owned by Tektronix or its suppliers and
are protected by United States copyright laws and international treaty provisions.
Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the
Rights in T echnical Data and Computer Software clause at DFARS 252.227-7013, or subparagraphs (c)(1) and (2) of the
Commercial Computer Software – Restricted Rights clause at F AR 52.227-19, as applicable.
T ektronix products are covered by U.S. and foreign patents, issued and pending. Information in this publication supercedes
that in all previously published material. Specifications and price change privileges reserved.
T ektronix, Inc., P.O. Box 500, Beaverton, OR 97077
TEKTRONIX and TEK are registered trademarks of T ektronix, Inc.
SOFTWARE WARRANTY
T ektronix warrants that the media on which this software product is furnished and the encoding of the programs on
the media will be free from defects in materials and workmanship for a period of three (3) months from the date of
shipment. If a medium or encoding proves defective during the warranty period, T ektronix will provide a
replacement in exchange for the defective medium. Except as to the media on which this software product is
furnished, this software product is provided “as is” without warranty of any kind, either express or implied.
T ektronix does not warrant that the functions contained in this software product will meet Customer’s
requirements or that the operation of the programs will be uninterrupted or error-free.
In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration
of the warranty period. If T ektronix is unable to provide a replacement that is free from defects in materials and
workmanship within a reasonable time thereafter, Customer may terminate the license for this software product
and return this software product and any associated materials for credit or refund.
THIS WARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER WARRANTIES, EXPRESS
OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’
RESPONSIBILITY TO REPLACE DEFECTIVE MEDIA OR REFUND CUSTOMER’S PAYMENT IS
THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS
WARRANTY. TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT,
SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER
TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH
DAMAGES.
Table of Contents
Getting Started
Operating Basics
General Safety Summary v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preface ix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Manual Conventions ix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contacting T ektronix x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Support Package Description 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Analyzer Software Compatibility 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Analyzer Configuration 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Requirements and Restrictions 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functionality Not Supported 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features not T ested 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Miscellaneous 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connecting the Logic Analyzer to a System Under T est 1–5. . . . . . . . . . . . . . . . . . .
Setting Up the Support 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Installing the Support Software 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Group Definitions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Support Package Setups 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocking 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acquiring and Viewing Disassembled Data 2–13. . . . . . . . . . . . . . . . . . . . .
Acquiring Data 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing Disassembled Data 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Display Format 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Display Format 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Display Format 2–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Flow Display Format 2–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subroutine Display Format 2–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Changing How Data is Displayed 2–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optional Display Selections 2–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Micro Specific Fields 2–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Marking Cycles 2–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing an Example of Disassembled Data 2–21. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifications
Replaceable Parts
Index
TMS711 320C6211/C6711 Microprocessor Support
i
Table of Contents
List of Figures
Figure 2–1: Bus timing for the SBSRAM Read cycle with a burst of four
data transitions 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2–2: SDSRAM Write cycles with a burst of four data
transitions 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2–3: Bus timing for the ASYNC read cycle 2–7. . . . . . . . . . . . . . .
Figure 2–4: Bus timing for the ASYNC write cycle 2–8. . . . . . . . . . . . . . .
Figure 2–5: Bus timing for the SDRAM fetch cycle with
CAS latency of 3 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2–6: SDRAM Write cycle with default of four data transitions 2–11
Figure 2–7: Hardware display format 2–15. . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2–8: 2–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5–1: Pin assignments for a Mictor connector
(component side) 5–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ii
TMS711 320C6211/C6711 Microprocessor Support
List of Tables
Table of Contents
Table 2–1: Signal acquisition in SBSRAM Read cycle 2–4. . . . . . . . . . . .
Table 2–2: Signal acquisition in SBSRAM Write cycle 2–6. . . . . . . . . . .
Table 2–3: Signal acquisition in ASYNC Write cycle 2–8. . . . . . . . . . . . .
Table 2–4: Signal acquisition in ASYNC Write cycle 2–9. . . . . . . . . . . . .
Table 2–5: Signal acquisition in SDRAM fetch cycle with
CAS latency of 3 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2–6: Signal acquisiton in SDRAM write cycle with
CAS latency of 3 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2–7: Description of special characters in the display 2–13. . . . . . . .
Table 2–8: Cycle type definitions 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2–9: C6211/C6711 Compatible SDRAM Memory
Configuration 2–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3–1: C6211 Electrical specifications 3–1. . . . . . . . . . . . . . . . . . . . .
Table 3–2: C6711 Electrical Specifications 3–2. . . . . . . . . . . . . . . . . . . . .
Table 5–1: Control symbol table definitions 5–1. . . . . . . . . . . . . . . . . . . .
Table 5–2: Address channel group assignments 5–3. . . . . . . . . . . . . . . . .
Table 5–3: Data channel group assignments 5–3. . . . . . . . . . . . . . . . . . . .
Table 5–4: Control channel group assignments 5–5. . . . . . . . . . . . . . . . . .
Table 5–5: Async channel group assignments 5–5. . . . . . . . . . . . . . . . . . .
Table 5–6: CEnable channel group assignments 5–5. . . . . . . . . . . . . . . . .
Table 5–7: BEnable channel group assignments 5–5. . . . . . . . . . . . . . . . .
Table 5–8: Misc channel group assignments 5–6. . . . . . . . . . . . . . . . . . . .
Table 5–9: Clock and Qualifier channel assignments 5–6. . . . . . . . . . . . .
Table 5–10: CPU to Mictor connections for Mictor A pins 5–7. . . . . . . .
Table 5–11: CPU to Mictor connections for Mictor D pins 5–9. . . . . . . .
Table 5–12: CPU to Mictor connections for Mictor C pins 5–10. . . . . . . .
Table 5–13: CPU to Mictor connections for CEnable 5–10. . . . . . . . . . . . .
Table 5–14: CPU to Mictor connections for BEnable 5–10. . . . . . . . . . . . .
Table 5–15: CPU to Mictor connections for Misc 5–11. . . . . . . . . . . . . . . .
Table 5–16: CPU to Mictor connections for clock and qualifiers 5–11. . .
TMS711 320C6211/C6711 Microprocessor Support
iii
Table of Contents
iv
TMS711 320C6211/C6711 Microprocessor Support
General Safety Summary
Review the following safety precautions to avoid injury and prevent damage to
this product or any products connected to it. To avoid potential hazards, use this
product only as specified.
Only qualified personnel should perform service procedures.
While using this product, you may need to access other parts of the system. Read
the General Safety Summary in other system manuals for warnings and cautions
related to operating the system.
To Avoid Fire or Personal Injury
Connect and Disconnect Properly . Do not connect or disconnect probes or test
leads while they are connected to a voltage source.
Ground the Product. This product is indirectly grounded through the grounding
conductor of the mainframe power cord. To avoid electric shock, the grounding
conductor must be connected to earth ground. Before making connections to the
input or output terminals of the product, ensure that the product is properly
grounded.
Observe All Terminal Ratings. To avoid fire or shock hazard, observe all ratings
and marking on the product. Consult the product manual for further ratings
information before making connections to the product.
The common terminal is at ground potential. Do not connect the common
terminal to elevated voltages.
Do Not Operate Without Covers. Do not operate this product with covers or panels
removed.
Avoid Exposed Circuitry. Do not touch exposed connections and components
when power is present.
Do Not Operate in Wet/Damp Conditions.
Do Not Operate in an Explosive Atmosphere.
Keep Product Surfaces Clean and Dry .
TMS711 320C6211/C6711 Microprocessor Support
v
General Safety Summary
Symbols and Terms
T erms in this Manual. These terms may appear in this manual:
WARNING. Warning statements identify conditions or practices that could result
in injury or loss of life.
CAUTION. Caution statements identify conditions or practices that could result in
damage to this product or other property.
T erms on the Product. These terms may appear on the product:
DANGER indicates an injury hazard immediately accessible as you read the
marking.
WARNING indicates an injury hazard not immediately accessible as you read the
marking.
CAUTION indicates a hazard to property including the product.
Symbols on the Product. The following symbols may appear on the product:
WARNING
High Voltage
Protective Ground
(Earth) T erminal
CAUTION
Refer to Manual
Double
Insulated
vi
TMS711 320C6211/C6711 Microprocessor Support
Preface
Manual Conventions
This instruction manual contains specific information about the TMS711
320C6211/C6711 microprocessor support package and is part of a set of
information on how to operate this product on compatible Tektronix logic
analyzers.
If you are familiar with operating microprocessor support packages on the logic
analyzer for which the TMS711 320C6211/C6711 support was purchased, you
will only need this instruction manual to set up and run the support.
If you are not familiar with operating microprocessor support packages, you will
need to supplement this instruction manual with information on basic operations
to set up and run the support. See Manual Conventions below for more information.
This manual uses the following conventions:
H The term “disassembler” refers to the software that disassembles bus cycles
into instruction mnemonics and cycle types.
H The phrase “information on basic operations” refers to online help, an
installation manual, or a user manual covering the basic operations of
microprocessor support.
TMS711 320C6211/C6711 Microprocessor Support
vii
Preface
Contacting Tektronix
Phone 1-800-833-9200*
Address Tektronix, Inc.
Department or name (if known)
14200 SW Karl Braun Drive
P.O. Box 500
Beaverton, OR 97077
USA
Web site www.tektronix.com
Sales support 1-800-833-9200, select option 1*
Service support 1-800-833-9200, select option 2*
Technical support Email: techsupport@tektronix.com
1-800-833-9200, select option 3*
1-503-627-2400
6:00 a.m. – 5:00 p.m. Pacific time
* This phone number is toll free in North America. After office hours, please leave a
voice mail message.
Outside North America, contact a Tektronix sales office or distributor; see the
Tektronix web site for a list of offices.
viii
TMS711 320C6211/C6711 Microprocessor Support
Getting Started
Getting Started
This chapter contains information on the TMS711 320C6211/C6711 microprocessor support package, and information on connecting your logic analyzer to
your system under test.
Support Package Description
The TMS711 320C6211/C6711microprocessor support package displays
disassembled data from systems based on the Texas Instruments C6211/C6711
microprocessor.
To use this support efficiently, you need to have the items listed in the information on basic operations and the following documents:
H TMS320C6000 CPU and Instruction Set Reference Guide, Literature
Number: SPRU189D, March 1999.
H TMS320C6000 Peripheral Reference Guide, Literature Number: SPRU190C,
April 1999.
H TMS320C6000 EMIF to External SDRAM/SGRAM Interface, Literature
Number: SPRA433A, June 1999.
H TMS320C6000 EMIF to External SBSRAM Interface, Literature Number:
SPRA533A, April 1999.
H TMS320C6000 Digital Signal Processor Data Sheet, Literature Number:
SPRS073, March 1999.
H TMS320C6000 EMIF to External Asynchronous SRAM Interface, Literature
Number: SPRA542, April 1999.
Information on basic operations also contains a general description of support.
Logic Analyzer Software Compatibility
The floppy disk label on the microprocessor support states which version of logic
analyzer software this support is compatible with.
TMS711 320C6211/C6711 Microprocessor Support
1–1
Getting Started
Logic Analyzer Configuration
The TMS711 320C6211/C6711support requires a minimum of one 102-channel
module.
NOTE. It is recommended that a logic analyzer acquisition module with a
maximum bus speed of 100 MHz be required when ECLKOUT = 100 MHz
(maximum). For ECLKOUT above 100 MHz (maximum), a logic analyzer
acquisition module with a maximum bus speed of 200 MHz is required.
Requirements and Restrictions
You should review the general requirements and restrictions of microprocessor
support packages in the information on basic operations as they pertain to your
system under test.
System Clock Rate
NonIntrusive Acquisition
Disabling the Instruction
Cache
L2 Cache
You should also review electrical, environmental, and mechanical specifications
in Specifications on page 3–1 as they pertain to your system under test, as well as
the following descriptions of other C6211/C6711 support requirements and
restrictions.
The operating speeds that the C6211/C6711
C6211/C6711 microprocessor are listed on Table 3–1. These specification were
valid at the time this manual was printed. Please contact your Tektronix Sales
Representative for current information on the fastest devices supported.
Acquiring microprocessor bus cycles will be non intrusive to the system under
test. That is, the C6211/C6711 support will not intercept, modify, or present
signals back to the system under test.
To display disassembled acquired data, you must disable the internal instruction
cache. Disabling the cache makes all instruction prefetches visible on the bus
they then can be acquired and displayed disassembled.
Do not configure L2 cache as cache; or external memory bus cycle acquisitions
will not occur with L2 cache.
support can acquire data from the
1–2
Write Cycle
SBSRAM Write Cycle and SDRAM Write Cycle have the same control values,
so they are represented by a single name. For example SDWRITE/SBSWRITE
for a given sequence in the control column, but the corresponding mnemonic
TMS711 320C6211/C6711 Microprocessor Support
Getting Started
column will have clear cut labels, for example ( SDRAM WRITE CYCLE ) and
( SBSRAM WRITE CYCLE ).
Read Cycle
Opcode Fetch/Data Read.
Symbol 11111[bin]
Conditional Branches
SBSRAM Read Cycle and SDRAM Read Cycle have same control values, so
they are represented by a single name. For example SDREAD/SBSREAD for a
given sequence in the control column, but the corresponding mnemonic column
will have clear cut labels, for example ( SDRAM READ CYCLE ) and
( SBSRAM READ CYCLE ).
The C6211/C6711 support does not provide a signal to distinguish between Data
Read and Opcode Fetch. The TMS711 320C6211/C6711 support makes a
reasonable estimate at looking at the address values of a few sequences around
the current sequence or by looking at the processor signal. Yet, in some instances
you may need to use the Mark Opcode function.
The Control symbol table does not have a symbol for 11111[bin], since it can
mean SDRAM Read, Write, or Fetch.
Flushes cannot be shown for conditional branches (where Condition is True)
when the branch instruction is in the first fetch packet, and the target address is in
third and fourth fetch packet from the fetch packet which has Branch instructions
(in either forward or reverse branches).
Alternate Fetch Packet
Branch Instructions
Memory Types
SBSRAM 4
Memory-Space Signals
If a conditional branch instruction is in the fetch packet, and the target address is
in the alternate fetch packet (from the fetch packet which has the branch
instruction; for example 1 to 3 , 2 to 4, or 3 to 5) we do not show flushes, since
fetch packets appear in sequence.
For branch instructions (both conditional and unconditional): B.S2 IRP, B.S2
NRP and B.S2 src2reg, we do not show whether a branch was taken or not in the
listing window of our disassembly. Since we cannot get the contents of the
registers IRP, NRP, Bxx that have the target address.
The C6211/C6711
memory types: SDRAM, SBSRAM, and ASYNC, at a time.
SBSRAM 4 word burst Read and write cycles are supported. But SBSRAM 6
word burst Read and write cycles not supported due to timing considerations.
All Memory space signals CE[3–0]~ must be connected to the logic analyzer.
support disassembles the execution from any one of the
TMS711 320C6211/C6711 Microprocessor Support
1–3
Getting Started
External Memory
In the C6211
programs only at addresses in multiples of 0x20; for example, 80000000,
80000020,80000040. Hence, the user input fields for entering the start address of
the Interrupt-Service-Fetch packets must be appropriate.
Functionality Not Supported
Microprocessor
Alternate Bus master
The signals: HPI, MCBSP 0 & 1, and JTAG are not acquired. If you want to view
these signals, you need to find an alternate way to probe them.
Alternative bus master transactions are acquired by the C6211/C6711 support and
are not disassembled.
Features not Tested
The C6211/C6711 support has been tested for C6711 floating point instructions
by editing the refmem. The C6211/C6711 support is not evaluated by acquiring
cycles from a dedicated C6711 evaluation board.
external memory you can download the C6211/C6711 support
Miscellaneous
The C6211/C6711 support disassembles SDRAM, SBSRAM and ASYNC
memory cycles. The C6211/C6711 support is not tested for SBSRAM and
ASYNC cycles. This C6211/C6711 support has been tested only with 32bit
SDRAM cycles.
The C6211/C6711 support has not been tested for Interrupts.
The C6211/C6711 support has not been tested for Big Endian mode.
The Address shown for the SDRAM ACTV cycle is the row address for the
corresponding user input for the SDRAM Address Configuration.
1–4
TMS711 320C6211/C6711 Microprocessor Support
Connecting the Logic Analyzer to a System Under Test
You can use channel probes, clock probes, and leadsets with a commercial test
clip (or adapter) to make connections between the logic analyzer and your system
under test.
To connect the probes to C6211/C6711 signals in the system under test using a
test clip, follow these steps:
1. Turn off power to your system under test. It is not necessary to turn off
power to the logic analyzer.
CAUTION. Static discharge can damage the microprocessor, the probes, and the
logic analyzer module. To prevent static damage, handle these components only
in a static-free environment.
Always wear a grounding wrist strap, heel strap, or similar device while
handling the microprocessor.
Getting Started
2. To discharge your stored static electricity, touch the ground connector located
on the back of the logic analyzer. If you are using a test clip, touch any of the
ground pins on the clip to discharge stored static electricity from the test clip.
CAUTION. Failure to place the system under test on a horizontal surface before
connecting the test clip can permanently damage the pins on the microprocessor.
3. Place the system under test on a horizontal static-free surface.
4. Use Tables 5–2 through 5–16 beginning on page 5–3 to connect the channel
probes to C6211/C6711 signal pins on the test clip or in the system under
test.
Use leadsets to connect at least one ground lead from each channel probe and
the ground lead from each clock probe to ground pins on your test clip.
TMS711 320C6211/C6711 Microprocessor Support
1–5
Getting Started
1–6
TMS711 320C6211/C6711 Microprocessor Support
Operating Basics
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