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that in all previously published material. Specifications and price c hange privileges reserved.
Tektronix, Inc., P.O. Box 500, Beaverton, OR 97077
TEKTRONIX and TEK are registered trademarks of Tektronix, Inc.
SOFTWARE WARRANTY
Tektronix warrants that the media on which this software product is furnished and the encoding of the programs on
the media will be free from defects in materials and workmanship for a period of three (3) months from the date of
shipment. If a medium or encoding proves defective during the warranty period, Tektronix will provide a
replacement in exchange for the defective medium. Except as to the media on which this software product is
furnished, this software product is provided “as is” without warranty of any kind, either express or implied.
Tektronix does not warrant that the functions contained in this software product will meet Customer’s
requirements or that the operation of the programs will be uninterrupted or error-free.
In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration
of the warranty period. If Tektronix is unable to provide a replacement that is free from defects in materials and
workmanship within a reasonable time thereafter, Customer may terminate the license for this software product
and return this software product and any associated materials for credit or refund.
THIS WARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER W ARRANTIES, EXPRESS
OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’
RESPONSIBILITY TO REPLACE DEFECTIVE MEDIA OR REFUND CUSTOMER’S PAYMENT IS
THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS
WARRANTY. TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT,
SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER
TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH
DAMAGES.
T able 4--1: Electrical specifications4--1...........................
vi
TMS708 MSC8101 Microprocessor Software Support
Preface
This instruction manual contains information specific to the TMS708 MSC8101
microprocessor support package and is part of a set of information on how to
operate this product on compatible Tektronix logic analyzers.
If you are familiar with operating microprocessor support packages on the logic
analyzer for which the TMS708 MSC8101 support was purchased, you will
probably only need this instruction manual to set up and run the support.
If you are not familiar with operating microprocessor support packages, you will
need to supplement this instruction manual with information on basic operations
to set up and run the support.
Information on basic operations of microprocessor support packages is included
with each product. Each logic analyzer includes basic information that describes
how to perform tasks common to s upport packages on that platform. This
information can be in the form of online help, an installation manual, or a user
manual.
This manual provides detailed information on the following topics:
HConnecting the logic analyzer to the target system
Manual Conventions
HSetting up the logic analyzer to acquire data from the target system
HAcquiring and viewing cycle type labels
This manual uses the following conventions:
HThe term “disassembler” refers to the software that decodes bus cycles and
displays cycle types.
HThe phrase “information on basic operations” refers to the logic analyzer
online help, an installation manual, or a user manual covering the basic
operations of the microprocessor support.
HThe term “logic analyzer” refers to the Tektronix logic analyzer for which
this product was purchased.
TMS708 MSC8101 Microprocessor Software Support
vii
Preface
Contacting Tektronix
Phone1-800-833-9200*
AddressTektronix, Inc.
Department or name (if known)
14200 SW Karl Braun Dri ve
P.O. Box 500
Beaverton, OR 97077
USA
Web sitewww.tektronix.com
Sales support1-800-833-9200, select option 1*
Service support1-800-833-9200, select option 2*
Technical supportEmail: techsupport@tektronix.com
1-800-833-9200, select option 3*
6:00 a.m. -- 5:00 p.m. Pacific time
*This phone number is toll free in North America. After office hours, please leave a
voice mail message.
Outside North America, contact a Tektronix sales office or distributor; see the
Tektronix web site for a list of offices.
viii
TMS708 MSC8101 Microprocessor Software Support
Getting Started
Getting Started
This section contains information on the TMS708 MS C8101 microprocessor
support, and information on connecting your logic analyzer to your target
system.
Support Package Description
The TMS708 microprocessor support package displays the Cycle Type labels,
marks the Idle Cycles, and validates the data bus and the address bus. The
TMS708 does not display the instructions nor identify the Fetch cycles. The
Motorola MSC8101 16-bit Digital Signal Processor (DSP) is the first member of
the family of DSPs based on the Starcore SC140 DS P core.
The TMS708 installs two support packages 8101_SNG and 8101_MLT.
H8101_SNG supports the Single Master mode of MSC8101 processor.
H8101_MLT supports the Multi Master mode of MSC8101 processor. You can
use the 8101_MLT support for Internal and External Arbiter configurations.
In the Internal Arbiter configuration, the software supports three more
external masters on the same system bus. In the External Arbiter configuration, the software supports up to four masters. The software decodes the
cycles of all the masters.
The TMS708 microprocessor support package decodes the Cycle Types,
validates the data bus and identifies the Idle Cycles. The support does not decode
Instructions.
Refer to information on basic operations to determine how many modules and
probes your logic analyzer needs to meet the minimum channel requirements for
the TMS708 microprocessor support.
To use this support efficiently, you need the items listed in the information on
basic operations as well as the MSC8101 Microprocessor User Manual
(Motorola, April 2001, and Revision 0, MSC8101RM/D).
Logic Analyzer Software Compatibility
The label on the microprocessor support floppy disk states which version of
logic analyzer software this support is compatible with.
TMS708 MSC8101 Microprocessor Software Support
1- 1
Getting Started
Logic Analyzer Configuration
The TMS708 MSC8101 microprocessor support requires the following
minimum module configuration:
HOne 136-channel, 100 MHz module for 8101_SNG support
HOne 136-channel, 100 MHz module for 8101_MLT support
Requirements and Restrictions
Review the electrical specifications in the Specifications section in this manual
as they pertain to your target system, as well as the following descriptions of
other MSC8101 support requirements and restrictions.
Hardware Reset. If a hardware reset occurs in your MSC8101 system during an
acquisition, the disassembler application might acquire invalid samples.
System Clock Rate CLKOUT. The support can acquire data from the MSC8101
microprocessor operating at speeds of up to 100 MHz
has been tested for speeds up to 50 MHz and the 8101_MLT support up to
66MHz.
T_Code Group in 8101_MLT Group. The T_Code channel group consists of signals
TC0/BR0~, TC1/BG0~, and TC2/DBG0~. By default, this group is hidden in
the support package. If you want to use the support for Internal Arbiter Configuration, you must connect the signals TC0, TC1, and TC2 to the logic analyzer
channels C0:1, C0:0 and C2:6. To view the activities of TC[0-2] signals, add the
T_Code group to the listing using CTRL+L. If you want to use the support for
External Arbiter configuration, connect the signals BR0~, BG0~, and DBG0~ to
the logic analyzer channels C0:1,C0:0, and C2:6. The T_Code group is not valid
in External Arbiter Configuration.
Triggering on Address in a Burst Transaction. The signals BADDR[31--27]
generate the address increments to memory devices for burst accesses and these
are not visible when signals A[31--27] are connected to the logic analyzer
channels A0:[0--4]. You can trigger on an address within a burst transaction only
if signals BADDR[31--27] are connected to the logic analyzer channels A0:[0--4].
The disassembler displays the address increments for burst transactions even
though signals A[31--27] are probed.
1
. The 8101_SNG support
1- 2
1
Specification at time of printing. Contact your Tektronix sales representative for
current information on the fastest devices supported.
TMS708 MSC8101 Microprocessor Software Support
Getting Started
Signals Not Required in t he Channel Assignment. The TMS708 MSC8101 support
package decodes cycle types, validates address and data bus, and identifies the
idle cycles acquired by clock-by-clock acquisition. It does not decode instructions. The channel assignment contains signals that are not required to support
cycle type decoding, validate address and data bus, or identify idle cycles. If you
include the P6434 high-density probe interface in your design, we recommend
that you use these signals.
EAV Bit Setting in 8101_SNG Support. Set the EAV (Enable Address Visibility) bit
of the Bus Configuration Register (BCR) to 1 for correct disassembly. When the
EAV is set to 1, the Bank Select signals are not driven on the address bus.
During READ and WRITE commands to SDRAM devices, the full address is
driven on bus address lines. Therefore, when the EAV bit is set to 1, the full
address is valid at PSDCAS~ asserted and PSDRAS~ deasserted for SDRAM
accesses.
Qualifiers Used in 8101_MLT Support. The Multi Master support uses the internal
memory controller signals for validating Address and Data. The support uses the
ALE signal to qualify a valid Address and the PSDVAL~ signal to qualify a
valid data on the bus. The external masters connected to the system may be an
MSC8101 or a non-MSC8101processor. For an MSC 8101 processor, the ALE
and PSDVAL~ signals are the qualifiers. For a non-MSC8101 processor, the
ALE and TA~ signals are the qualifiers.
Address Pipelining. The TMS708 support is designed to support pipelining up to
one level. While acquiring data from systems with pipelining, you may at the
beginning acquire data tenures without any corresponding address tenures. The
support, by default, starts associating the first data with the first acquired address
tenure. This may cause incorrect Cycle Type decoding. In that case, you must
associate the first acquired address with the correct data tenure using the ‘Invalid
Data’ marking option. You must mark as ‘Invalid Data’ the first data tenure
without any corresponding address. Once you mark the Invalid Data, the support
package adjusts itself to associate the address and data correctly.
Nonintrusive Acquisition. Acquiring microprocessor bus cycles is nonintrusive to
the target system. That is, the TMS708 MSC8101 microprocessor does not
intercept, modify, or present back signals to the target system.
TMS708 MSC8101 Microprocessor Software Support
1- 3
Getting Started
Channel Groups. The channel groups required for clocking and cycle type
decoding in the 8101_SNG support are:
Address
Hi_Data
Lo_Data
Control
Chip_Sel
Byte_Enb
Misc
The channel groups required for clocking and cycle type decoding in the
8101_MLT support are:
Address
Hi_Data
Lo_Data
Control
Chip_Sel
T_Type
T_Size
T_Code
Req_Grant
Timing Display Format
The support has a Timing Display Format file. It sets up the display to show the
following waveforms:
NOTE. The Address, Hi_Data, Lo_Data, Control, Chip_Sel, Byte_Enb, and Misc
groups are displayed in busform.
1- 4
TMS708 MSC8101 Microprocessor Software Support
For 8101_MLT S upport:
CLKOUT
Address
Hi_Data
Lo_Data
TS~
ALE
TA~
TEA~
AACK~
PSDVAL~
T_Type
T_Size
T_Code
Control
Chip_Sel
Req_Grant
Getting Started
NOTE. The Address,Hi_Data, Lo_Data, T_Type, T_Size, T_Code, Control,
Chip_Sel, and Req_Grant groups are displayed in busform.
Functionality Not Supported
The TMS708 software does not support the following functionalities:
HUPM cycles
HDMA cycles
HHDI16 cycles
HMultiple master mode with multiple memory controllers
HPowerPC
local bus cycles
Functionality Supported But Not Tested
The TMS708 software supports the following features, but are not tested.
H60X system bus interface of the MSC8102 processor
HExternal Arbiter Configuration in 8101_MLT support
HAtomic bus operations (RAWA, WARA) in 8101_SNG support
TMS708 MSC8101 Microprocessor Software Support
1- 5
Getting Started
Connecting the Logic Analyzer to a Target System
You can use the channel probes, clock probes, and leadsets with a commercial
test clip (or adapter) to make the connections between the logic analyzer and
your target system.
To connect the probes to MSC8101 signals in the target system using a test clip,
follow the steps:
1. Power off your target system. You do not need to power off the logic
analyzer.
CAUTION. To prevent static damage, handle the microprocessor, probes, and the
logic analyzer module in a static-free environment. Static discharge can damage
these components.
Always wear a grounding wrist strap, heel strap, or similar device while
handling the microprocessor.
Labeling P6434 Probes
2. To discharge your stored static electricity, touch the ground connector
located on the back of the logic analyzer. If you are using a test clip, touch
any of the ground pins on the clip to discharge stored electricity from the test
clip.
CAUTION. To prevent permanent damage to the pins on the microprocessor, place
the target system on a horizontal surface before connecting the test clip.
3. Place the target system on a horizontal, static-free surface.
4. Use Tables 3--27 through 3--34 starting on page 3--21 to connect the channel
probes to MSC8101 signal pins on the test clip or in the target system.
5. Use leadsets to connect at least one ground lead from each channel and the
ground lead from each clock probe to the ground pins on your test clip.
The TMS708 MSC8101 software support package relies on the channel mapping
and labeling scheme for the P6434 Probes. Apply labels using the instructions
described in the P6434 Probe Instructions manual.
1- 6
TMS708 MSC8101 Microprocessor Software Support
Operating Basics
Setting Up the Support
This section provides information on how to set up the support and covers the
following topics:
HInstalling the support software
HChannel group definitions
HClocking options
The information in this section is specific to the operations and functions of the
TMS708 MSC8101 support on any Tektronix logic analyzer for which the
support can be purchased. Information on basic operations describes general
tasks and functions.
Before you acquire and display cycle type labels, you need to load the support
and specify the setups for clocking and triggering as described in the information
on basic operations. The support provides default values for each of these setups,
but you can change the default values as needed.
Installing the Support Software
NOTE. Before you install any software, you should verify that the microprocessor
support software is compatible with the logic analyzer software.
To install the TMS708 MSC8101 software on your Tektronix logic analyzer,
follow these steps:
1. Insert the floppy disk in the disk drive.
2. Click the Windows Start button, point to Settings, and click Control Panel.
3. In the Control Panel window, double-click Add/Remove Programs.
4. Follow the instructions on the screen for installing the software from the
To remove or uninstall software, follow the above instructions and select
Uninstall. You need to close all windows before you uninstall any software.
Channel Group Definitions
The software automatically defines channel groups for the support.
floppy disk.
TMS708 MSC8101 Microprocessor Software Support
2--1
Setting Up the Support
8101_SNG Support
8101_MLT Support
The channel groups for the TMS708 8101_SNG support are: Address, Hi_Data,
Lo_Data, Control, Chip_Sel, Byte_Enb, and Misc. Table 2--1 shows the channel
groups and the display radix for the 8101_SNG support.
Table 2--1: Channel groups for the Single Master
Mode
Group nameDisplay radix
AddressHEX
Hi_DataHEX
Lo_DataHEX
MnemonicsNONE (disassembler generated text)
ControlSYM
Chip_SelSYM
Byte_EnbSYM
MiscHEX (hidden by default)
The channel group for the TMS708 8101_MLT support are: Address, Hi_Data,
Lo_Data, T_Type, T_Size, T_Code, Control, Chip_Sel, and Req_Grant.
Table 2--2 shows the channel groups and the display radix for the 8101_MLT
support.
NOTE. The T_Code group is applicable only in Internal Arbiter Mode.
Table 2--2: Channel groups for the Multi Master Mode
Group nameDisplay radix
AddressHEX
Hi_DataHEX
Lo_DataHEX
MnemonicsNONE (disassembler generated text)
ControlSYM (hidden by default)
Chip_SelSYM
T_TypeSYM
T_SizeSYM
T_CodeSYM (hidden by default)
Req_GrantSYM
2--2
TMS708 MSC8101 Microprocessor Software Support
Clocking
Setting Up the Support
If you want to know which signal is in which group, refer to the channel
assignment tables beginning on page 3--7.
Acquisition Setup
Clocking Options
Custom Clocking
The TMS708 MSC8101 affects the logic analyzer setup menus (and submenus)
by modifying existing fields and adding micro-specific fields.
On the logic analyzer, the TMS708 MSC8101 support adds the selection
‘8101_SNG’ and ‘8101_MLT’ to the Load Support Package dialog box, under
the File pulldown menu. Once ‘TMS708 MSC8101 support’ is loaded, the
‘Custom’ clocking mode selection in the logic analyzer module Setup menu is
also enabled.
The TMS708 support offers a microprocessor-specific clocking mode for the
MSC8101 microprocessor. This clocking mode is the default selection whenever
you load the MSC8101 support.
The disassembly will not be correct when using the Internal or External clocking
modes. Information on basic operations describes how to use these clock
selections for general purpose analysis.
A special clocking program is loaded to the module every time you load the
8101_SNG or 8101_MLT support. This special clocking is called Custom.
With Custom Clocking, the module logs in signals from the multiple channel
groups at every clock on the TMS708 MSC8101 bus. The module then sends all
the logged-in signals to the trigger machine and stores the signals in the
acquisition memory of the module.
When Custom is selected, the Custom Clocking Options menu adds the subtitle:
‘8101_SNG Microprocessor Clocking Support’ or ‘8101_MLT Microprocessor
Clocking Support’, and displays the clocking option—Standard. This is the only
custom clocking option available for this support.
TMS708 MSC8101 Microprocessor Software Support
2--3
Setting Up the Support
2--4
TMS708 MSC8101 Microprocessor Software Support
Acquiring and Viewing Disassembled Data
This section describes how to acquire and view data. The following information
covers these topics and tasks:
HAcquiring data
HViewing cycle type labels
HChanging the way labels are displayed
HTiming diagrams
Acquiring Data
The TMS708 MSC8101 software package installs the 8101_SNG support for the
MSC8101 processor working in Single Master mode and the 8101_MLT for
MSC8101 processor working in Multi Master mode (for up to four masters on
the target system). Once you load the support, by default, the custom clocking
option is selected. Specify the trigger, if any, and you are ready to acquire and
disassemble data.
Signal Acquisition
If you have any problems acquiring data, refer to information on basic operations
in your online help or Appendix A: Error Messages and Disassembly Problems in
the user manual.
8101_SNG Support. The Custom Clock uses the falling edge of the CLKOUT
signal.
TMS708 MSC8101 Microprocessor Software Support
2--5
Acquiring and Viewing Disassembled Data
Figures 2--1 and 2--2 show the Bus Timing diagrams for SDRAM memory and
GPCM memory in the Single Master mode.
CLKOUT
ALE
CS
SDRAS
SDCAS
MA[0--11]
WE
DQM
Data
ZColumn2
MMMMMMMMMMM
Column1
D0D1D0D1
Figure 2--1: Bus timing diagram for SDRAM memory
CLKOUT
Address
PSDVAL
CSx
CSy
BCTLx
POE
Data
M
MM MM
Figure 2--2: Bus timing diagram for GPCM memory
2--6
TMS708 MSC8101 Microprocessor Software Support
Acquiring and Viewing Disassembled Data
Table 2--3 describes the sample points in 8101_SNG support.
Table 2--3: Sample points in Single Master Mode
Sample pointSignals
Master sample point, MA[0--31], D[0--31], D[32--63], CS~[0--7],
You can view cycle type labels only in the Hardware display format. The
information on basic operations describes how to select the disassembly display
formats.
NOTE. You must set the selections in the Disassembly property page (the
Disassembly Format Definition overlay) correctly for your acquired data to be
disassembled correctly. Refer to Changing How Labels are Displayed on page
2--13.
For the 8101_SNG support, the default display format shows the Address,
Hi_Data, Lo_Data, Mnemonics, Control, Chip_Sel, Byte_Enb channel group
values for each sample of acquired data.
For the 8101_MLT support, the default display format shows the Address,
Hi_Data, Lo_Data, Mnemonics, T_Type, T_Size, Chip_Sel channel group values
for each sample of acquired data.
If a channel group is not visible, you can add the required column by pressing
Ctrl + L and selecting the group of interest.
2--8
TMS708 MSC8101 Microprocessor Software Support
Acquiring and Viewing Disassembled Data
Table 2--5 shows the special characters and gives a definition of what they
represent.
Table 2--5: Description of special characters in display
Character or string displayedDescription
>>The sample was manually marked
Hardware Display Format
In the Hardware display format, the support displays all cycle type labels in
parentheses.
In Hardware display format, all cycle type labels are displayed. This is the
default format for viewing the data.
Tables 2--6 and 2--7 show the cycle type labels and their descriptions that the
support recognizes and displays.
Table 2--6: Cycle type label definitions for the 8101_SNG support
Cycle typeDefinition
( SDRAM-Activate Cycle )Indicates a SDRAM Activate command
( SDRAM-Precharge Cycle )Indicates a SDRAM Precharge command
( SDRAM-Refresh Cycle )Indicates a SDRAM Refresh command
( Row Address )Indicates the presence of Row Address on the Address
bus
( Column Address )Indicates the presence of Column Address on the
Address bus
( SDRAM-Read Cycle )Indicates a SDRAM Read cycle
( SDRAM-Write Cycle )Indicates a SDRAM Write cycle
( Hardware Reset Cycle )Indicates a Hardware Reset Operation
( Software Reset Cycle )Indicates a Software Reset Operation
( Power On Reset Cycle )Indicates a Power On Reset Operation
( SDRAM Fetch )Indicates a Fetch Cycle
(Data)Indicates a Data Cycle (can be a Read Data or a Burst
( GPCM-Read Cycle )Indicates a GPCM Read Cycle
( GPCM-Write Cycle )Indicates a GPCM Write Cycle
( GPCM-Wait Cycle )Indicates a GPCM Wait Cycle
(NoDeviceSelectedforCS0)Indicates that Chip Select 0 (CS0~) disassembly option is
TMS708 MSC8101 Microprocessor Software Support
Read Data or a Write Data or a Burst Write Data)
not selecting any device *
2--9
Acquiring and Viewing Disassembled Data
Table 2--6: Cycle type label definitions for the 8101_SNG support (cont.)
Cycle typeDefinition
(NoDeviceSelectedforCS1)Indicates that Chip Select 1 (CS1~) disassembly option is
(NoDeviceSelectedforCS2)Indicates that Chip Select 2 (CS2~) disassembly option is
(NoDeviceSelectedforCS3)Indicates that Chip Select 3 (CS3~) disassembly option is
(NoDeviceSelectedforCS4)Indicates that Chip Select 4 (CS4~) disassembly option is
(NoDeviceSelectedforCS5)Indicates that Chip Select 5 (CS5~) disassembly option is
(NoDeviceSelectedforCS6)Indicates that Chip Select 6 (CS6~) disassembly option is
(NoDeviceSelectedforCS7)Indicates that Chip Select 7 (CS7~) disassembly option is
*
The support displays this label when the CSn~ Disassembly option selected is
‘No_Device’.
not selecting any device *
not selecting any device *
not selecting any device *
not selecting any device *
not selecting any device *
not selecting any device *
not selecting any device *
Table 2--7: Cycle type label definitions for the 8101_MLT support
Cycle typeDefinition
( Transfer Start )
( Transfer Error )Indicates TEA~ is asserted
( Address )Indicates a valid Address
( Address Bus Busy )Indicates ABB~ is asserted
( Address Acknowledge )Indicates AACK~ is asserted
( Address Retry )Indicates ARTRY~ is asserted
(Data)Indicates valid data
( Burst Data )Indicates TBST~ is asserted for Burst Data
(DataBusBusy)Indicates DBB~ is asserted
( Transfer Acknowledge )Indicates TA~ is asserted
( Bus Grant )Indicates BG0~ or BG~ or EXT_BG2~ or EXT_BG3~ is
(NoDeviceSelectedforCS0)Indicates that Chip Select 0 (CS0~) disassembly option is
(NoDeviceSelectedforCS1)Indicates that Chip Select 1 (CS1~) disassembly option is
Indicates TS~ is asserted
asserted
not selecting any device *
not selecting any device *
2--10
TMS708 MSC8101 Microprocessor Software Support
Acquiring and Viewing Disassembled Data
Table 2--7: Cycle type label definitions for the 8101_MLT support (cont.)
Cycle typeDefinition
(NoDeviceSelectedforCS2)Indicates that Chip Select 2 (CS2~) disassembly option is
not selecting any device *
(NoDeviceSelectedforCS3)Indicates that Chip Select 3 (CS3~) disassembly option is
not selecting any device *
(NoDeviceSelectedforCS4)Indicates that Chip Select 4 (CS4~) disassembly option is
not selecting any device *
(NoDeviceSelectedforCS5)Indicates that Chip Select 5 (CS5~) disassembly option is
not selecting any device *
(NoDeviceSelectedforCS6)Indicates that Chip Select 6 (CS6~) disassembly option is
not selecting any device *
(NoDeviceSelectedforCS7)Indicates that Chip Select 7 (CS7~) disassembly option is
not selecting any device *
*
The support displays this label when the CSn~ Disassembly option selected is
‘No_Device’.
A unique label is attached to the cycle type labels that identifies the cycles
corresponding to every processor.
HFor the main master (internal arbiter) or processor0 (external arbiter) cycles,
the support indicates ‘--> Processor_0 Cycle’
HFor the second processor cycles, the support indicates ‘--> Processor_1’
HFor the third processor cycles, the support indicates ‘--> Processor_2’
HFor the fourth processor cycles, the support indicates ‘--> Processor_3’
For example: A ‘Transfer Start’ Cycle of the second processor is labeled as
( Transfer Start ) --> Processor_1
Table 2--8 shows the general cycle type labels and their descriptions that the
support recognizes and displays.
Table 2--8: General cycle type labels
Cycle typeDefinition
( Idle Cycle )Indicates the cycle that is in between two valid cycles
( Unknown Cycle )Indicates the cycle that is not yet identified and decoded
***Un-Associated Data***Indicates that no address is available for associating with a data
TMS708 MSC8101 Microprocessor Software Support
beat (because of incomplete acquisition of the complete cycle)
or when the address is re-tried and data tenure already exists
2--11
Acquiring and Viewing Disassembled Data
NOTE. The label ‘Idle Cycle’ is common for both supports. The label ‘Unknown
Cycle’ is used in 8101_SNG support and the label ***Un-Associated Data*** is
used in 8101_MLT support.
Use the Micro Specific Fields in the 8101_MLT support to view the cycle type
labels of all the processors simultaneously or of one processor at a time.
Figure 2--4 shows an example of the Hardware Display format in the Single
Master Mode.
Figure 2--4: Example of the Hardware Display format in the Single Master Mode
2--12
TMS708 MSC8101 Microprocessor Software Support
Acquiring and Viewing Disassembled Data
Figure 2--5 shows an example of the Hardware Display format in the Multi
Master Mode.
Figure 2--5: Example of the Hardware Display format in the Multi Master Mode
Changing How Labels are Displayed
There are common fields and features that allow you to further modify displayed
data to suit your needs. You can make common and optional display selections in
the Disassembly property page (the Disassembly Format Definition overlay).
You can make selections unique to the TMS708 support to do the following
tasks:
HChange the interpretation of cycle type labels
HDisplay exception cycles
TMS708 MSC8101 Microprocessor Software Support
2--13
Acquiring and Viewing Disassembled Data
Optional Display
Selections
Micro-Specific Fields for
8101_SNG
You can make optional selections for disassembled data. In addition to the
common selections (described in the information on basic operations), you can
change the displayed data as shown in Table 2--9:
The following micro-specific fields are available in the Disassembly options
page.
This submenu has the title: 8101_SNG Controls. For the 8101_SNG Support
package the micro-specific fields are:
Idle Cycles. Use this option to show or suppress the idle cycles in the hardware
display format. Select one of the following options:
Idle Cycles:Show (default)
Suppress
CAS Latency. Select the CAS Latency value for correct disassembly. The CAS
Latency option represents the CL field of the SDRAM configuration register
(PSDMR).
CAS Latency: 1 (default)
2
3
Vector Base Address. Input the base address for the vector table. The vector base
address reflects the value set in the VBA register. The vector base address is a
five digit field that forms the 20-bit MSB of the vector address.
2--14
TMS708 MSC8101 Microprocessor Software Support
Acquiring and Viewing Disassembled Data
CS0~. Select the port size and memory device for CS0~ by selecting one of the
following options.
CS0~:SDRAM-64 Bit (default)
SDRAM-32 Bit
SDRAM-16 Bit
SDRAM-8 Bit
GPCM-64 Bit
GPCM-32 Bit
GPCM-16 Bit
GPCM-8 Bit
No_Device
CS1~. Select the port size and memory device for CS1~ by selecting one of the
following options.
CS1~:SDRAM-64 Bit (default)
SDRAM-32 Bit
SDRAM-16 Bit
SDRAM-8 Bit
GPCM-64 Bit
GPCM-32 Bit
GPCM-16 Bit
GPCM-8 Bit
No_Device
CS2~. Select the port size and memory device for CS2~ by selecting one of the
following options.
CS2~:SDRAM-64 Bit (default)
SDRAM-32 Bit
SDRAM-16 Bit
SDRAM-8 Bit
GPCM-64 Bit
GPCM-32 Bit
GPCM-16 Bit
GPCM-8 Bit
No_Device
TMS708 MSC8101 Microprocessor Software Support
2--15
Acquiring and Viewing Disassembled Data
CS3~. Select the port size and memory device for CS3~ by selecting one of the
following options.
CS3~:SDRAM-64 Bit (default)
CS4~. Select the port size and memory device for CS4~ by selecting one of the
following options.
CS4~:SDRAM-64 Bit (default)
SDRAM-32 Bit
SDRAM-16 Bit
SDRAM-8 Bit
GPCM-64 Bit
GPCM-32 Bit
GPCM-16 Bit
GPCM-8 Bit
No_Device
SDRAM-32 Bit
SDRAM-16 Bit
SDRAM-8 Bit
GPCM-64 Bit
GPCM-32 Bit
GPCM-16 Bit
GPCM-8 Bit
No_Device
CS5~. Select the port size and memory device for CS5~ by selecting one of the
following options.
CS5~:SDRAM-64 Bit (default)
SDRAM-32 Bit
SDRAM-16 Bit
SDRAM-8 Bit
GPCM-64 Bit
GPCM-32 Bit
GPCM-16 Bit
GPCM-8 Bit
No_Device
2--16
TMS708 MSC8101 Microprocessor Software Support
Acquiring and Viewing Disassembled Data
CS6~. Select the port size and memory device for CS6~ by selecting one of the
following options.
CS6~:SDRAM-64 Bit (default)
SDRAM-32 Bit
SDRAM-16 Bit
SDRAM-8 Bit
GPCM-64 Bit
GPCM-32 Bit
GPCM-16 Bit
GPCM-8 Bit
No_Device
CS7~. Select the port size and memory device for CS7~ by selecting one of the
following options.
CS7~:SDRAM-64 Bit (default)
SDRAM-32 Bit
SDRAM-16 Bit
SDRAM-8 Bit
GPCM-64 Bit
GPCM-32 Bit
GPCM-16 Bit
GPCM-8 Bit
No_Device
Micro-Specific Fields for
8101_MLT
This submenu will have the title: 8101_MLT Controls. For the 8101_MLT
Support package the micro-specific fields are:
Idle Cycles. Use the Idle Cycles option to show or suppress the idle cycles in the
hardware display format. Select one of the following options:
Idle Cycles:Show (default)
Suppress
Arbiter. Use the Arbiter option to identify the multi-master configuration (Internal
or External Arbiter) in the target system. Select one of the following options:
Arbiter:Internal (default)
External
Selecting Internal or External changes the definition of the next option ‘Show
Cycles Of’.
TMS708 MSC8101 Microprocessor Software Support
2--17
Acquiring and Viewing Disassembled Data
Show Cycles Of. You can view either the cycles of any one master at a time, or all
the masters by selecting one of the following options.
Show Cycles Of: All (default)
NOTE. When you set the Arbiter option to Internal , the definitions of 0, 1, 2, and
3 are as follows:
0 represents the MSC8101 main master (or the Internal Arbiter)
1, 2, and 3 represent the other three external masters connected on the same bus
BR~, BG~, DBG~ reflect the status of Main master and Processor 1
BR2~, BG2~, DBG2~ reflect the status of Processor 2
BR3~, BG3~, DBG3~ reflect the status of Processor 3
When you set the Arbiter option to External, the definitions of 0, 1, 2, and 3 are
as follows:
0
1
2
3
1, 2, 3, and 4 represent the four external masters connected to the bus
TC0/BR0~, TC1/BG0~, TC2/DBG0~ reflects the status of Processor 0
BR~, BG~, DBG~ reflect the status of Processor 1
BR2~, BG2~, DBG2~ reflect the status of Processor 2
BR3~, BG3~, DBG3~ reflect the status of Processor 3
Signals Connected Are. For burst transactions in the multi master mode, address
increments are visible if signals BADDR[31-27] are connected to logic analyzer
channels A0[0-4]. If signals A[31--27] are connected to logic analyzer channels
A0[0-4], the software performs the address increments. Select one of the
following options.
Signals Connected Are: A[27--31] (default)
BADDR[27--31]
Vector Base Address. Input the base address for the vector table. The vector base
address reflects the value set in the VBA register. The vector base address is a
five digit field that forms the 20-bit MSB of the vector address.
2--18
TMS708 MSC8101 Microprocessor Software Support
Acquiring and Viewing Disassembled Data
CS0~. Select the port size for CS0~ by selecting one of the following options.
CS0~:64 Bit (default)
32 Bit
16 Bit
8Bit
No_Device
CS1~. Select the port size for CS1~ by selecting one of the following options.
CS1~:64 Bit (default)
32 Bit
16 Bit
8Bit
No_Device
CS2~. Select the port size for CS2~ by selecting one of the following options.
CS2~:64 Bit (default)
32 Bit
16 Bit
8Bit
No_Device
CS3~. Select the port size for CS3~ by selecting one of the following options.
CS3~:64 Bit (default)
32 Bit
16 Bit
8Bit
No_Device
CS4~. Select the port size for CS4~ by selecting one of the following options.
CS4~:64 Bit (default)
32 Bit
16 Bit
8Bit
No_Device
TMS708 MSC8101 Microprocessor Software Support
2--19
Acquiring and Viewing Disassembled Data
CS5~. Select the port size for CS5~ by selecting one of the following options.
CS5~:64 Bit (default)
CS6~. Select the port size for CS6~ by selecting one of the following options.
CS6~:64 Bit (default)
CS7~. Select the port size for CS7~ by selecting one of the following options.
CS7~:64 Bit (default)
32 Bit
16 Bit
8Bit
No_Device
32 Bit
16 Bit
8Bit
No_Device
32 Bit
16 Bit
8Bit
No_Device
Marking Cycles
The support has a Mark Opcode function that allows you to change the
interpretation of a cycle type. Using this function, you can select a cycle and
change it.
Marks are placed by using the Mark Opcode button. The Mark Opcode button is
always available. If the sample being marked is not a Data cycle in 8101_MLT or
an Address cycle in 8101_SNG of the potential bus master, the Mark Opcode
selections are replaced by a note indicating that ‘An Opcode Mark cannot be
placed at the selected data sample.’
When a cycle is marked, the character ‘>>’ is displayed immediately to the left
of the Mnemonics column. Cycles can be unmarked by using the ‘Undo Mark’
selection, which removes the character ‘>>’. Tables 2--10 and 2--11 show the
mark selections and definitions for the Single and Multi Master support.
2--20
TMS708 MSC8101 Microprocessor Software Support
Acquiring and Viewing Disassembled Data
The mark selections listed in Table 2--10 are available only for address sequences.
Table 2--10: Mark selections and definitions for 8101_SNG support
Mark selectionsDefinition
Read --> FetchRead can be marked as Fetch
Undo MarkRemoves all marks from the current sequence
The mark selections listed in Table 2--11 are available only for data sequences.
Table 2--11: Mark selections and definitions for 8101_MLT support
Mark selectionsDefinition
Invalid DataAny of the Data Cycles can be marked as Invalid Data
bits. No address is associated for this data.
Undo MarkRemoves all marks from the current sequence
Displaying Exception
Labels
The support can display MSC8101 exception labels. The exception table must
reside in external memory for interrupt and exception cycles to be visible to the
disassembler.
You can enter the table prefix in the Vector Base Address field. The Vector Base
Address field provides the support with the address. Enter a 5-digit hexadecimal
value corresponding to the prefix of the exception table.
These fields are located in the Disassembly property page (Disassembly Format
Definition overlay).
Table 2--12 lists the MSC8101 interrupt and exception labels.
Table 2--12: Interrupt and exception labels
Offset in hexDisplayed interrupt or exception name
000( Internal (TRAP) Exception )
040( Reserved Exception )
080( Illegal Instruction or Set Exception )
0C0( Debug (EOnCE) Exception )
100( Reserved Exception )
140( Overflow (DALU) Exception )
180( Auto-NMI Exception )
1C0( Auto-IRQ Exception )
TMS708 MSC8101 Microprocessor Software Support
2--21
Acquiring and Viewing Disassembled Data
Table 2--12: Interrupt and exception labels (cont.)
Offset in hexDisplayed interrupt or exception name
200-7C0( Reserved Exception )
800( EFCOP(0):Input FIFO Not Full Exception )
840( EFCOP(1):Input FIFO Empty Exception )
880( EFCOP(2):Output FIFO Full Exception )
8C0( EFCOP(3):Output FIFO Not Empty Exception )
900( EFCOP(4):Update Done Exception )
940( HDI16(0):Receive FIFO Full Exception )
980( HDI16(1):Receive FIFO Not Empty Exception )
9C0( HDI16(2):Transmit FIFO Empty Exception )
A00( HDI16(3):Transmit FIFO Not Full Exception )
A40( HDI16(4):External HOST Command Exception )
A80( Bus Controller (x-y contention) Exception )
AC0( Bus Controller (Level 1 Contention) Exception )
B00( Bus Controller (p-x Contention) Exception )
B40( Bus Controller (Non-Aligned Data Error) Exception )
B80( PIC Interrupt Request )
BC0( External IRQ2 Exception )
C00( SIC Interrupt )
C40( External IRQ3 Interrupt )
C80( DMA Interrupt )
CC0( Reserved Exception )
D00( EOnCE Interrupt )
D40-DC0( Reserved Exception )
E00( HDI16:External HOST NMI Interrupt )
E40( Reserved Exception )
E80( Bus Controller (Memory Write Error) Exception )
EC0( Bus Controller (Non-Aligned Error) Exception )
F00( Bus Controller (Bus Error) Exception )
2--22
F40-F80( Reserved Exception )
FC0( SIC NMI Exception )
TMS708 MSC8101 Microprocessor Software Support
Viewing an Example of Cycle Type Labels
A demonstration system file (or demonstration reference memory) for the
support package is provided on your software disk to show an example of how
your MSC8101 microprocessor bus cycles look when they are decoded. Viewing
the system file is not a requirement for preparing the module for use and you can
view it without connecting the logic analyzer to your target system.
Information on basic operations describes how to view the file.
Acquiring and Viewing Disassembled Data
TMS708 MSC8101 Microprocessor Software Support
2--23
Acquiring and Viewing Disassembled Data
2--24
TMS708 MSC8101 Microprocessor Software Support
Reference
Reference: Symbol and Channel Assignment Tables
This section lists the symbol tables and channel assignment tables for disassembly and timing.
Symbol Tables
The TMS708 support supplies nine symbol-table files. In the 8101_SNG
support, the 8101_SNG_Control file replaces specific Control group values with
symbolic values. In the 8101_MLT support, the 8101_MLT_Control file replaces
specific Control group values with symbolic values. Symbol files can be applied
to a group when the radix Symbolic is chosen.
Symbol tables are generally not for use in timing or MSC8101_T support cycle
type decoding.
8101_SNG Support
Tables 3--1 through 3--3 show the definitions for name, bit pattern, and meaning
of the group symbols in the files 8101_SNG_Control, 8101_SNG_Chip_Sel, and
8101_SNG_Byte_Enb for 8101_SNG support.
Table 3 - 1: 8101_SNG_Control group symbol table definitions
IDLE_CYCLE1 1 1 11 1 XXXXXXX#Idle Cycle (SDRAM CAS
HRESET0 XXXXXXXXXXXX#Hardware Reset Cycle
SRESETX0 XXXXXXXXXXX#Software Reset Cycle
PORESETXX0 XXXXXXXXXX#Power On Reset Cycle
PORESET~PSDWE~BCTL1~
PSDRAS~/POE~~PSDAMUXBCTL0~
Latency or GPCM Wait State)
Table 3 - 2: 8101_SNG_Chip_Sel group symbol table definitions
Chip_Sel group value
CS0~CS4~
CS1~CS5~
Symbol
CS2~CS6~
CS3~CS7~
Description
CS0~01111111#Device 0 Selected
CS1~10111111#Device 1 Selected
CS2~11011111#Device 2 Selected
CS3~11101111#Device 3 Selected
CS4~11110111#Device 4 Selected
CS5~11111011#Device 5 Selected
CS6~11111101#Device 6 Selected
CS7~11111110#Device 7 Selected
-11111111#No Devices Selected
Table 3 - 3: 8101_SNG_Byte_Enb group symbol table definitions
Byte_Enb group value
PWE0~PWE4~
PWE1~PWE5~
Symbol
D [0-7]01111111#Byte Lane 0 Selected
D [8-15]10111111#Byte Lane 1 Select ed
PWE2~PWE6~
PWE3~PWE7~
Description
3- 2
TMS708 MSC8101 Microprocessor Software Support
Reference: Symbol and Channel Assignment Tables
Table 3 - 3: 8101_SNG_Byte_Enb group symbol table definitions (cont.)
Byte_Enb group value
PWE0~PWE4~
PWE1~PWE5~
SymbolDescription
D [16-23]11011111#Byte Lane 2 Selected
D [24-31]11101111#Byte Lane 3 Selected
D [32-39]11110111#Byte Lane 4 Selected
D [40-47]11111011#Byte Lane 5 Selected
D [48-55]11111101#Byte Lane 6 Selected
D [56-63]11111110#Byte Lane 7 Selected
D [0-15]00111111#Byte Lane 0-1 Selected
D [8-23]10011111#Byte Lane 1-2 Selected
D [16-31]11001111#Byte Lane 2-3 Selected
D [32-47]11110011#Byte Lane 4-5 Selected
D [40-55]11111001#Byte Lane 5-6 Selected
D [48-63]11111100#Byte Lane 6-7 Selected
D [0-23]00011111#Byte Lane 0-1-2 Selected
D [8-31]10001111#Byte Lane 1-2-3 Selected
D [32-55]11110001#Byte Lane 4-5-6 Selected
D [40-63]11111000#Byte Lane 5-6-7 Selected
D [0-31]00001111#Byte Lane 0-1-2-3 Selected
D [32-63]11110000#Byte Lane 4-5-6-7 Selected
D [0-63]00000000#All Byte Lanes Selected
-11111111#No Byte Lanes Selected
PWE2~PWE6~
PWE3~PWE7~
Information on basic operations describes how to use symbolic values for
triggering and for displaying other channel groups symbolically, such as for the
Address channel group.
TMS708 MSC8101 Microprocessor Software Support
3- 3
Reference: Symbol and Channel Assignment Tables
8101_MLT Support
Tables 3--4 through 3--9 show the definitions for name, bit pattern, and meaning
of the group symbols in the files 8101_MLT_Control, 8101_MLT_Chip_Sel,
8101_MLT_T_Type, 8101_MLT_T_Size, 8101_MLT_T_Code, and
8101_MLT_Req_Grant for 8101_MLT support.
Table 3 - 4: 8101_MLT_Control group symbol table definitions
Table 3 - 5: 8101_MLT_Chip_Sel group symbol table definitions
Chip_Sel group value
CS0~CS4~
CS1~CS5~
Symbol
CS0~01111111#Device 0 Selected
CS1~10111111#Device 1 Selected
CS2~11011111#Device 2 Selected
CS3~11101111#Device 3 Selected
CS4~11110111#Device 4 Selected
CS5~11111011#Device 5 Selected
CS6~11111101#Device 6 Selected
CS7~11111110#Device 7 Selected
-11111111#No Devices Selected
CS2~CS6~
CS3~CS7~
Description
3- 4
TMS708 MSC8101 Microprocessor Software Support
Reference: Symbol and Channel Assignment Tables
Table 3 - 6: 8101_MLT_T_Type group symbol table definitions
T_Type group value
TS~TT3
TT0TT4
Symbol
RESERVED000101Reserved
RESERVED_FOR_CUSTOMER01XX01Reserved for Customer
WRITE000010Write Transaction (Single
READ001010Read Transaction (Single
RESERVED010110Reserved
RESERVED000011Reserved
RESERVED000111Reserved
RESERVED001111Reserved
RESERVED_FOR_CUSTOMER01XX11Reserved for Customer
TT1
TT2
Description
Beat or Burst)
Beat or Burst)
Table 3 - 7: 8101_MLT_T_Size group symbol table definitions
T_Size group value
TS~TSIZ2
TBST~TSIZ3
Symbol
BYTE0100011 Byte Transaction
HALF_WORD0100102 Bytes Transaction
TRIPLE_BYTE0100113 Bytes Transaction
WORD0101004 Bytes Transaction
EXTENDED_5_BYTES010101Extended 5 Bytes
EXTENDED_6_BYTES010110Extended 6 Bytes
EXTENDED_7_BYTES010111Extended 7 Bytes
DOUBLE_WORD0100008 Bytes Transaction
BURST00XXXX Burst Transaction
TSIZ0
TSIZ1
Description
Transaction
Transaction
Transaction
TMS708 MSC8101 Microprocessor Software Support
3- 5
Reference: Symbol and Channel Assignment Tables
Table 3 - 8: 8101_MLT_T_Code group symbol table definitions
Symbol
RESERVED0000Reserved
RESERVED0001Reserved
RESERVED0010Reserved
RESERVED0011Reserved
DMA0100DMA Source
SC140_CORE/DMA0101SC140 or DMA Source
SDMA_FUNCTION_CODE_00110SDMA Function Code 0
SDMA_FUNCTION_CODE_10111SDMA Function Code 1
T_Code group
value
TS~
TC0/BR0~
TC1/BG0~
TC2/DBG0~
Description
Source
Source
NOTE. The T_Code group is applicable only in Internal Arbiter Mode.
Table 3 - 9: 8101_MLT_Req_Grant group symbol table definitions
Req_Grant group value
TCO/BR0~TC1/BG0~TC2/DBG0~
BR~BG~DBG~
Symbol
BG0_ADDRESSXXXX01111111#BG0~ Asserted
BG_ADDRESSXXXX10111111#BG~ Asserted
BG2_ADDRESSXXXX11011111#BG2~ Asserted
BG3_ADDRESSXXXX11101111#BG3~ Asserted
DBG0_DATAXXXX11110111#DBG0~ Asserted
DBG_DATAXXXX11111011#DBG~ Asserted
DBG2_DATAXXXX11111101#DBG2~ Asserted
DBG3_DATAXXXX11111110#DBG3~ Asserted
DP0~/EXT_BR2~DP1/EXT_BG2~DP2~/EXT_DBG2~
DP3~/EXT_BR3~DP4~/EXT_BG3~DP5~/EXT_DBG3~
Description
3- 6
TMS708 MSC8101 Microprocessor Software Support
Channel Assignment Tables
Channel assignments shown in Tables 3--10 through 3--25 use the following
conventions:
HAll signals are required by the support unless indicated otherwise.
HChannels are shown starting with the most significant bit (MSB) descending
to the least significant b it (LSB).
HChannel group assignments are for all modules unless otherwise noted.
HA tilde (~) following a signal name indicates an active low signal.
Reference: Symbol and Channel Assignment Tables
8101_SNG Support
Table 3--10 shows the probe section and channel assignments for the logic
analyzer Address group and the microprocessor signal to which each channel
connects. By default, this channel group is displayed in hexadecimal.
Table 3 - 10: Address group channel assignments for
8101_SNG support
Bit orderMSC8101 signal name
A3:7 (MSB)A0
A3:6A1
A3:5A2
A3:4A3
A3:3A4
A3:2A5
A3:1A6
A3:0A7
A2:7A8
A2:6A9
A2:5A10
A2:4A11
A2:3A12
A2:2A13
A2:1A14
A2:0A15
A1:7A16
A1:6A17
A1:5A18
TMS708 MSC8101 Microprocessor Software Support
3- 7
Reference: Symbol and Channel Assignment Tables
Table 3 - 10: Address group channel assignments for
8101_SNG support (cont.)
Bit orderMSC8101 signal name
A1:4A19
A1:3A20
A1:2A21
A1:1A22
A1:0A23
A0:7A24
A0:6A25
A0:5A26
A0:4A27
A0:3A28
A0:2A29
A0:1A30
A0:0 (LSB)A31
Table 3--11 shows the probe section and channel assignments for the Hi_Data
group and the microprocessor signal to which each channel connects. By default,
this channel group is displayed in hexadecimal.
Table 3 - 11: Hi_Data group channel assignments for
8101_SNG support
Bit orderMSC8101 signal name
E3:7 (MSB)D0
E3:6D1
E3:5D2
E3:4D3
E3:3D4
E3:2D5
E3:1D6
E3:0D7
3- 8
E2:7D8
E2:6D9
E2:5D10
E2:4D11
TMS708 MSC8101 Microprocessor Software Support
Reference: Symbol and Channel Assignment Tables
Table 3 - 11: Hi_Data group channel assignments for
8101_SNG support (cont.)
Bit orderMSC8101 signal name
E2:3D12
E2:2D13
E2:1D14
E2:0D15
E1:7D16
E1:6D17
E1:5D18
E1:4D19
E1:3D20
E1:2D21
E1:1D22
E1:0D23
E0:7D24
E0:6D25
E0:5D26
E0:4D27
E0:3D28
E0:2D29
E0:1D30
E0:0D31
Table 3--12 shows the probe section and channel assignments for the Lo_Data
group and the microprocessor signal to which each channel connects. By default,
this channel group is displayed in hexadecimal.
Table 3 - 12: Lo_Data group channel assignments for
8101_SNG support
Bit orderMSC8101 signal name
D3:7D32
D3:6D33
D3:5D34
D3:4D35
D3:3D36
TMS708 MSC8101 Microprocessor Software Support
3- 9
Reference: Symbol and Channel Assignment Tables
Table 3 - 12: Lo_Data group channel assignments for
8101_SNG support (cont.)
Bit orderMSC8101 signal name
D3:2D37
D3:1D38
D3:0D39
D2:7D40
D2:6D41
D2:5D42
D2:4D43
D2:3D44
D2:2D45
D2:1D46
D2:0D47
D1:7D48
D1:6D49
D1:5D50
D1:4D51
D1:3D52
D1:2D53
D1:1D54
D1:0D55
D0:7D56
D0:6D57
D0:5D58
D0:4D59
D0:3D60
D0:2D61
D0:1D62
D0:0 (LSB)D63
3- 10
TMS708 MSC8101 Microprocessor Software Support
Reference: Symbol and Channel Assignment Tables
Table 3--13 shows the probe section and channel assignments for the Control
group and the microprocessor signal to which each channel connects. By default,
this channel group is displayed as symbols.
Table 3 - 13: Control group channel assignments for 8101_SNG
support
Bit orderMSC8101 signal name
C1:1HRESET~
C1:0SRESET~
C0:6PORESET~
C0:1PSDRAS~/POE~
CLK:3PSDCAS~
CLK:0PSDVAL~
C1:7PSDWE~
C1:4PSDAMUX
C1:6PSDA10
C1:5PGTA~
C0:2BCTL1~
C1:3BCTL0~
C0:7GBL~
Table 3--14 shows the probe section and channel assignments for the Chip_Sel
group and the microprocessor signal to which each channel connects. By default,
this channel group is displayed as symbols.
Table 3 - 14: Chip_Sel group channel assignments for 8101_SNG
support
Bit orderMSC8101 signal name
QUAL:3CS0~
QUAL:2CS1~
QUAL:0CS2~
CLK:2CS3~
C2:7CS4~
C2:6CS5~
C2:5CS6~
C2:4CS7~
TMS708 MSC8101 Microprocessor Software Support
3- 11
Reference: Symbol and Channel Assignment Tables
Table 3--15 shows the probe section and channel assignments for the Byte_Enb
group and the microprocessor signal to which each channel connects. By default,
this channel group is displayed as binary.
Table 3 - 15: Byte_Enb group channel assignments for 8101_SNG
support
Bit orderMSC8101 signal name
C3:7PWE0~
C3:6PWE1~
C3:5PWE2~
C3:4PWE3~
C3:3PWE4~
C3:2PWE5~
C3:1PWE6~
C3:0PWE7~
Table 3--16 shows the probe section and channel assignments for the logic
analyzer Misc group and the microprocessor signal to which each channel
connects. By default, this channel group is not visible.
Table 3 - 16: Misc group channel assignments for
8101_SNG support
Bit orderMSC8101 signal name
CLK:1CLKOUT
C0:5NMI~
C1:2NMI_OUT~
QUAL:1IRQ7~/INT_OUT~
C0:4DP6~/EXT_DACK3~
C0:3DP7~/EXT_DACK4~
3- 12
TMS708 MSC8101 Microprocessor Software Support
Reference: Symbol and Channel Assignment Tables
8101_MLT Support
Table 3--17 shows the probe section and channel assignments for the logic
analyzer Address group and the microprocessor signal to which each channel
connects. By default, this channel group is displayed in hexadecimal.
Table 3 - 17: Address group channel assignments for
8101_MLT support
Bit orderMSC8101 signal name
A3:7 (MSB)A0
A3:6A1
A3:5A2
A3:4A3
A3:3A4
A3:2A5
A3:1A6
A3:0A7
A2:7A8
A2:6A9
A2:5A10
A2:4A11
A2:3A12
A2:2A13
A2:1A14
A2:0A15
A1:7A16
A1:6A17
A1:5A18
A1:4A19
A1:3A20
A1:2A21
A1:1A22
A1:0A23
A0:7A24
A0:6A25
A0:5A26
A0:4BADDR27/A27*
A0:3BADDR28/A28*
TMS708 MSC8101 Microprocessor Software Support
3- 13
Reference: Symbol and Channel Assignment Tables
Table 3 - 17: Address group channel assignments for
8101_MLT support (cont.)
Bit orderMSC8101 signal name
A0:2BADDR29/A29*
A0:1BADDR30/A30*
A0:0 (LSB)BADDR31/A31*
*
You can trigger on Burst Address increments only if
BADDR[31-27] is connected to logic analyzer channels
A0:[0-4]. For more details, refer to Triggering on Addressin a Burst Transaction on page 1- 2.
Table 3--18 shows the probe section and channel assignments for the Hi_Data
group and the microprocessor signal to which each channel connects. By default,
this channel group is displayed in hexadecimal.
Table 3 - 18: Hi_Data group channel assignments for
8101_MLT support
Bit orderMSC8101 signal name
E3:7 (MSB)D0
E3:6D1
E3:5D2
E3:4D3
E3:3D4
E3:2D5
E3:1D6
E3:0D7
E2:7D8
E2:6D9
E2:5D10
E2:4D11
E2:3D12
E2:2D13
E2:1D14
E2:0D15
E1:7D16
3- 14
E1:6D17
E1:5D18
TMS708 MSC8101 Microprocessor Software Support
Reference: Symbol and Channel Assignment Tables
Table 3 - 18: Hi_Data group channel assignments for
8101_MLT support (cont.)
Bit orderMSC8101 signal name
E1:4D19
E1:3D20
E1:2D21
E1:1D22
E1:0D23
E0:7D24
E0:6D25
E0:5D26
E0:4D27
E0:3D28
E0:2D29
E0:1D30
E0:0D31
Table 3--19 shows the probe section and channel assignments for the Lo_Data
group and the microprocessor signal to which each channel connects. By default,
this channel group is displayed in hexadecimal.
Table 3 - 19: Lo_Data group channel assignments for
8101_MLT support
Bit orderMSC8101 signal name
D3:7D32
D3:6D33
D3:5D34
D3:4D35
D3:3D36
D3:2D37
D3:1D38
D3:0D39
D2:7D40
D2:6D41
D2:5D42
D2:4D43
TMS708 MSC8101 Microprocessor Software Support
3- 15
Reference: Symbol and Channel Assignment Tables
Table 3 - 19: Lo_Data group channel assignments for
8101_MLT support (cont.)
Bit orderMSC8101 signal name
D2:3D44
D2:2D45
D2:1D46
D2:0D47
D1:7D48
D1:6D49
D1:5D50
D1:4D51
D1:3D52
D1:2D53
D1:1D54
D1:0D55
D0:7D56
D0:6D57
D0:5D58
D0:4D59
D0:3D60
D0:2D61
D0:1D62
D0:0 (LSB)D63
Table 3--20 shows the probe section and channel assignments for the Control
group and the microprocessor signal to which each channel connects. By default,
this channel group is displayed as symbols.
Table 3 - 20: Control group channel assignments for 8101_MLT
support
Bit orderMSC8101 signal name
CLK:3TS~
3- 16
C3:1ALE
C3:6ABB~
QUAL:1AACK~
TMS708 MSC8101 Microprocessor Software Support
Reference: Symbol and Channel Assignment Tables
Table 3 - 20: Control group channel assignments for 8101_MLT
support (cont .)
Bit orderMSC8101 signal name
CLK:0PSDVAL~
C2:7DBB~
C0:3TA~
C0:2TEA~
C1:6ARTRY~
Table 3--21 shows the probe section and channel assignments for the Chip_Sel
group and the microprocessor signal to which each channel connects. By default,
this channel group is displayed as symbols.
Table 3 - 21: Chip_Sel group channel assignments for 8101_MLT
support
Bit orderMSC8101 signal name
QUAL:3CS0~
QUAL:2CS1~
QUAL:0CS2~
CLK:2CS3~
C3:7CS4~
C3:3CS5~
C2:4CS6~
C2:3CS7~
Table 3--22 shows the probe section and channel assignments for the T_Type
group and the microprocessor signal to which each channel connects. By default,
this channel group is displayed as symbols.
Table 3 - 22: T_Type group channel assignments for 8101_MLT
support
Bit orderMSC8101 signal name
CLK:3TS~
C1:0TT0
C0:7TT1
TMS708 MSC8101 Microprocessor Software Support
3- 17
Reference: Symbol and Channel Assignment Tables
Table 3 - 22: T_Type group channel assignments for 8101_MLT
support (cont .)
Bit orderMSC8101 signal name
C0:6TT2
C0:5TT3
C0:4TT4
Table 3--23 shows the probe section and channel assignments for the T_Size
group and the microprocessor signal to which each channel connects. By default,
this channel group is displayed as symbols.
Table 3 - 23: T_Size group channel assignments for 8101_MLT
support
Bit orderMSC8101 signal name
CLK:3TS~
C1:7TBST~
C1:4TSIZ0
C1:3TSIZ1
C1:2TSIZ2
C1:1TSIZ3
Table 3--24 shows the probe section and channel assignments for the T_Code
group and the microprocessor signal to which each channel connects. By default,
this channel group is displayed as symbols.
Table 3 - 24: T_Code group channel assignments for 8101_MLT
support
Bit orderMSC8101 signal name
CLK:3TS~
C0:1TC0/BR0~
C0:0TC1/BG0~
C2:6TC2/DBG0~
3- 18
TMS708 MSC8101 Microprocessor Software Support
Reference: Symbol and Channel Assignment Tables
NOTE. The T_Code group is applicable only in Internal Arbiter Mode. For more
details refer to T_Code Group in 8101_MLT Group on page 1--2.
Table 3--25 shows the probe section and channel assignments for the Req_Grant
group and the microprocessor signal to which each channel connects. By default,
this channel group is displayed as symbols.
Table 3 - 25: Req_Grant group channel assignments for 8101_MLT
support
Bit orderMSC8101 signal name
C0:1TC0/BR0~*
C3:2BR~
C3:4DP0~/EXT_BR2~
C2:5DP3~/EXT_BR3~
C0:0TC1/BG0~*
C3:5BG~
C2:2DP1~/EXT_BG2~
C2:0DP4~/EXT_BG3~
C2:6TC2/DBG0~*
C3:0DBG~
C2:1DP2~/EXT_DBG2~
C1:5DP5~/EXT_DBG3~
*
When you use the 8101_MLT support for Internal Arbiter
configuration, connect the signals TC0-TC2 to C0:1, C0:0, and
C2:6. For External Arbiter configuration, connect the signals
BR0~, BG0~, and DBG0~ (request and grant signals from the
fourth external master that is connected to the bus) to C0:1, C0:0,
and C2:6.
TMS708 MSC8101 Microprocessor Software Support
3- 19
Reference: Symbol and Channel Assignment Tables
CPU To Mictor Connections
This section contains information about Mictor connections.
For design purposes, you may need to make connections between the CPU and
the Mictor pins of the P6434 Mass Termination Probe. Refer to the P6434 MassTermination Probe manual, Tektronix part number 070-9793-XX, for more
information on mechanical specifications.
NOTE. To preserve signal quality in the target system, you should connect a 180
Ω resistor in series between each ball pad of the CPU and each pin of the
Mictor connector. The resistor must be within 1/2 inch of the ball pad of the
CPU.
The recommended pin assignment is the AMP pin assignment, because the AMP
circuit board layout model and other commercial CAD packages use the AMP
numbering scheme. See Table 3--26.
Table 3- 26: Recommended pin assignments for a Mictor connector (component
side)
Type of pin assignmentComments
Recommended. This pin assignment is the industry
Recommended
Pin 1
Pin 37
AMP Pin Assignment
Pin 2
Pin 38
standard and is what we recommend that you use.
3- 20
TMS708 MSC8101 Microprocessor Software Support
Reference: Symbol and Channel Assignment Tables
8101_SNG Support
Tables 3--27 through 3--30 show the mictor pin connections for the logic analyzer
and the AMP mictors for the 8101_SNG support.
Table 3 - 27: CPU to Mictor connections for Mictor A pins for 8101_SNG support
Logic analyzer
AMP mictor pin number
Mictor A pin 05CLOCK:0PSDVAL~Required
Mictor A pin 07A3:7A0 (MSB)Required
Mictor A pin 09A3:6A1Required
Mictor A pin 11A3:5A2Required
Mictor A pin 13A3:4A3Required
Mictor A pin 15A3:3A4Required
Mictor A pin 17A3:2A5Required
Mictor A pin 19A3:1A6Required
Mictor A pin 21A3:0A7Required
Mictor A pin 23A2:7A8Required
Mictor A pin 25A2:6A9Required
Mictor A pin 27A2:5A10Required
Mictor A pin 29A2:4A11Required
Mictor A pin 31A2:3A12Required
Mictor A pin 33A2:2A13Required
Mictor A pin 35A2:1A14Required
Mictor A pin 37A2:0A15Required
Mictor A pin 38A0:0A31Required
Mictor A pin 36A0:1A30Required
Mictor A pin 34A0:2A29Required
Mictor A pin 32A0:3A28Required
Mictor A pin 30A0:4A27Required
Mictor A pin 28A0:5A26Required
Mictor A pin 26A0:6A25Required
Mictor A pin 24A0:7A24Required
Mictor A pin 22A1:0A23Required
Mictor A pin 20A1:1A22Required
Mictor A pin 18A1:2A21Required
Mictor A pin 16A1:3A20Required
Mictor A pin 14A1:4A19Required
Mictor A pin 12A1:5A18Required
acquisition channel
MSC8101 support
package channel name
Required/Not required
for disassembly
TMS708 MSC8101 Microprocessor Software Support
3- 21
Reference: Symbol and Channel Assignment Tables
Table 3 - 27: CPU to Mictor connections for Mictor A pins for 8101_SNG support (cont.)
Logic analyzer
AMP mictor pin number
Mictor A pin 10A1:6A17Required
Mictor A pin 08A1:7A16Required
Mictor A pin 06CLOCK:1CLKOUTRequired
acquisition channel
MSC8101 support
package channel name
Required/Not required
for disassembly
Table 3 - 28: CPU to Mictor connections for Mictor C pins for 8101_SNG support
Logic analyzer
AMP mictor pin number
Mictor C pin 05CLOCK:3PSDCAS~Required
Mictor C pin 07C3:7PWE0~Required
Mictor C pin 09C3:6PWE1~Required
Mictor C pin 11C3:5PWE2~Required
Mictor C pin 13C3:4PWE3~Required
Mictor C pin 15C3:3PWE4~Required
Mictor C pin 17C3:2PWE5~Required
Mictor C pin 19C3:1PWE6~Required
Mictor C pin 21C3:0PWE7~Required
Mictor C pin 23C2:7CS4~Required
Mictor C pin 25C2:6CS5~Required
Mictor C pin 27C2:5CS6~Required
Mictor C pin 29C2:4CS7~Required
Mictor C pin 31C2:3No connectionNot required
Mictor C pin 33C2:2No connectionNot required
Mictor C pin 35C2:1No connectionNot required
Mictor C pin 37C2:0No connectionNot required
Mictor C pin 38C0:0No connectionNot required
Mictor C pin 36C0:1PSDRAS~/POE~Required
Mictor C pin 34C0:2BCTL1~Not required
Mictor C pin 32C0:3DP7~/DACK4~Not required
Mictor C pin 30C0:4DP6~/DACK3~Not required
Mictor C pin 28C0:5NMI~Not required
Mictor C pin 26C0:6PORESET~Required
Mictor C pin 24C0:7GBL~Not required
Mictor C pin 22C1:0SRESET~Required
acquisition channel
MSC8101 support
package channel name
Required/Not required
for disassembly
3- 22
TMS708 MSC8101 Microprocessor Software Support
Reference: Symbol and Channel Assignment Tables
Table 3 - 28: CPU to Mictor connections for Mictor C pins for 8101_SNG support (cont.)
Logic analyzer
AMP mictor pin number
Mictor C pin 20C1:1HRESET~Required
Mictor C pin 18C1:2NMI_OUT~Not required
Mictor C pin 16C1:3BCTL0~Not required
Mictor C pin 14C1:4PSDAMUXNot required
Mictor C pin 12C1:5PGTA~Not required
Mictor C pin 10C1:6PSDA10Required
Mictor C pin 08C1:7PSDWE~Required
Mictor C pin 06QUAL:1IRQ7~/INT_OUT~Not required
acquisition channel
MSC8101 support
package channel name
Required/Not required
for disassembly
Table 3 - 29: CPU to Mictor connections for Mictor D pins for 8101_SNG support
Logic analyzer
AMP mictor pin number
Mictor D pin 05QUAL:0CS2~Required
Mictor D pin 07D3:7D32Required
Mictor D pin 09D3:6D33Required
Mictor D pin 11D3:5D34Required
Mictor D pin 13D3:4D35Required
Mictor D pin 15D3:3D36Required
Mictor D pin 17D3:2D37Required
Mictor D pin 19D3:1D38Required
Mictor D pin 21D3:0D39Required
Mictor D pin 23D2:7D40Required
Mictor D pin 25D2:6D41Required
Mictor D pin 27D2:5D42Required
Mictor D pin 29D2:4D43Required
Mictor D pin 31D2:3D44Required
Mictor D pin 33D2:2D45Required
Mictor D pin 35D2:1D46Required
Mictor D pin 37D2:0D47Required
Mictor D pin 38D0:0D63Required
Mictor D pin 36D0:1D62Required
Mictor D pin 34D0:2D61Required
Mictor D pin 32D0:3D60Required
acquisition channel
MSC8101 support
package channel name
Required/Not required
for disassembly
TMS708 MSC8101 Microprocessor Software Support
3- 23
Reference: Symbol and Channel Assignment Tables
Table 3 - 29: CPU to Mictor connections for Mictor D pins for 8101_SNG support (cont.)
Logic analyzer
AMP mictor pin number
Mictor D pin 30D0:4D59Required
Mictor D pin 28D0:5D58Required
Mictor D pin 26D0:6D57Required
Mictor D pin 24D0:7D56Required
Mictor D pin 22D1:0D55Required
Mictor D pin 20D1:1D54Required
Mictor D pin 18D1:2D53Required
Mictor D pin 16D1:3D52Required
Mictor D pin 14D1:4D51Required
Mictor D pin 12D1:5D50Required
Mictor D pin 10D1:6D49Required
Mictor D pin 08D1:7D48Required
Mictor D pin 06CLOCK:2CS3~Required
acquisition channel
MSC8101 support
package channel name
Required/Not required
for disassembly
Table 3 - 30: CPU to Mictor connections for Mictor E pins for 8101_SNG support
Logic analyzer
AMP mictor pin number
Mictor E pin 05QUAL:3CS0~Required
Mictor E pin 07E3:7D0 (MSB)Required
Mictor E pin 09E3:6D1Required
Mictor E pin 11E3:5D2Required
Mictor E pin 13E3:4D3Required
Mictor E pin 15E3:3D4Required
Mictor E pin 17E3:2D5Required
Mictor E pin 19E3:1D6Required
Mictor E pin 21E3:0D7Required
Mictor E pin 23E2:7D8Required
Mictor E pin 25E2:6D9Required
Mictor E pin 27E2:5D10Required
Mictor E pin 29E2:4D11Required
Mictor E pin 31E2:3D12Required
Mictor E pin 33E2:2D13Required
Mictor E pin 35E2:1D14Required
acquisition channel
MSC8101 support
package channel name
Required/Not required
for disassembly
3- 24
TMS708 MSC8101 Microprocessor Software Support
Reference: Symbol and Channel Assignment Tables
Table 3 - 30: CPU to Mictor connections for Mictor E pins for 8101_SNG support (cont.)
Logic analyzer
AMP mictor pin number
Mictor E pin 37E2:0D15Required
Mictor E pin 38E0:0D31Required
Mictor E pin 36E0:1D30Required
Mictor E pin 34E0:2D29Required
Mictor E pin 32E0:3D28Required
Mictor E pin 30E0:4D27Required
Mictor E pin 28E0:5D26Required
Mictor E pin 26E0:6D25Required
Mictor E pin 24E0:7D24Required
Mictor E pin 22E1:0D23Required
Mictor E pin 20E1:1D22Required
Mictor E pin 18E1:2D21Required
Mictor E pin 16E1:3D20Required
Mictor E pin 14E1:4D19Required
Mictor E pin 12E1:5D18Required
Mictor E pin 10E1:6D17Required
Mictor E pin 08E1:7D16Required
Mictor E pin 06QUAL:2CS1~Required
acquisition channel
MSC8101 support
package channel name
Required/Not required
for disassembly
TMS708 MSC8101 Microprocessor Software Support
3- 25
Reference: Symbol and Channel Assignment Tables
8101_MLT Support
Tables 3--31 through 3--34 show the mictor pin connections for the logic analyzer
and the AMP mictors for the 8101_MLT support.
Table 3 - 31: CPU to Mictor connections for Mictor A pins for 8101_MLT support
Logic analyzer
AMP mictor pin number
Mictor A pin 05CLOCK:0PSDVAL~Required
Mictor A pin 07A3:7A0 (MSB)Required
Mictor A pin 09A3:6A1Required
Mictor A pin 11A3:5A2Required
Mictor A pin 13A3:4A3Required
Mictor A pin 15A3:3A4Required
Mictor A pin 17A3:2A5Required
Mictor A pin 19A3:1A6Required
Mictor A pin 21A3:0A7Required
Mictor A pin 23A2:7A8Required
Mictor A pin 25A2:6A9Required
Mictor A pin 27A2:5A10Required
Mictor A pin 29A2:4A11Required
Mictor A pin 31A2:3A12Required
Mictor A pin 33A2:2A13Required
Mictor A pin 35A2:1A14Required
Mictor A pin 37A2:0A15Required
Mictor A pin 38A0:0BADDR31/A31*Required
Mictor A pin 36A0:1BADDR30/A30*Required
Mictor A pin 34A0:2BADDR29/A29*Required
Mictor A pin 32A0:3BADDR28/A28*Required
Mictor A pin 30A0:4BADDR27A27*Required
Mictor A pin 28A0:5A26Required
Mictor A pin 26A0:6A25Required
Mictor A pin 24A0:7A24Required
Mictor A pin 22A1:0A23Required
Mictor A pin 20A1:1A22Required
Mictor A pin 18A1:2A21Required
Mictor A pin 16A1:3A20Required
Mictor A pin 14A1:4A19Required
Mictor A pin 12A1:5A18Required
acquisition channel
MSC8101 support
package channel name
Required/Not required
for disassembly
3- 26
TMS708 MSC8101 Microprocessor Software Support
Reference: Symbol and Channel Assignment Tables
Table 3 - 31: CPU to Mictor connections for Mictor A pins for 8101_MLT support (cont.)
Logic analyzer
AMP mictor pin number
Mictor A pin 10A1:6A17Required
Mictor A pin 08A1:7A16Required
Mictor A pin 06CLOCK:1CLKOUTRequired
*
You can trigger on Burst Address increments only if BADDR[31-27] is connected to logic analyzer
channels A0:[0-4]. For more details, refer to Triggering on Address in a Burst Transaction on page 1- 2.
acquisition channel
MSC8101 support
package channel name
Required/Not required
for disassembly
Table 3 - 32: CPU to Mictor connections for Mictor C pins for 8101_MLT support
Logic analyzer
AMP mictor pin number
Mictor C pin 05CLOCK:3TS~Required
Mictor C pin 07C3:7CS4~Required
Mictor C pin 09C3:6ABB~Required
Mictor C pin 11C3:5BG~Required
Mictor C pin 13C3:4DP0~/EXT_BR2~Not required
Mictor C pin 15C3:3CS5~Required
Mictor C pin 17C3:2BR~Not required
Mictor C pin 19C3:1ALERequired
Mictor C pin 21C3:0DBG~Required
Mictor C pin 23C2:7DBB~Required
Mictor C pin 25C2:6TC2/DBG0~*Required
Mictor C pin 27C2:5DP3~/EXT_BR3~Not required
Mictor C pin 29C2:4CS6~Required
Mictor C pin 31C2:3CS7~Required
Mictor C pin 33C2:2DP1~/EXT_BG2~Required
Mictor C pin 35C2:1DP2~/EXT_DBG2~Required
Mictor C pin 37C2:0DP4~/EXT_BG3~Required
Mictor C pin 38C0:0TC1/BG0~*Required
Mictor C pin 36C0:1TC0/BR0~*Required for Internal Arbi-
Mictor C pin 34C0:2TEA~Required
Mictor C pin 32C0:3TA~Required
Mictor C pin 30C0:4TT4Required
acquisition channel
MSC8101 support
package channel name
Required/Not required
for disassembly
ter Mode
Not Required for External
Arbiter Mode
TMS708 MSC8101 Microprocessor Software Support
3- 27
Reference: Symbol and Channel Assignment Tables
Table 3 - 32: CPU to Mictor connections for Mictor C pins for 8101_MLT support (cont.)
Logic analyzer
AMP mictor pin number
Mictor C pin 28C0:5TT3Required
Mictor C pin 26C0:6TT2Required
Mictor C pin 24C0:7TT1Required
Mictor C pin 22C1:0TT0Required
Mictor C pin 20C1:1TSIZ3Required
Mictor C pin 18C1:2TSIZ2Required
Mictor C pin 16C1:3TSIZ1Required
Mictor C pin 14C1:4TSIZ0Required
Mictor C pin 12C1:5DP5~/EXT_DBG3~Required
Mictor C pin 10C1:6ARTRY~Required
Mictor C pin 08C1:7TBST~Required
Mictor C pin 06QUAL:1AACK~Required
*
When you use the 8101_MLT support for Internal Arbiter configuration, connect the signals TC0-TC2 to
C0:0, C0:0, and C2:6. For External Arbiter configuration, connect the signals BR0~, BG0~, and DBG0~
(request and grant signals from the fourth external master that is connected to the bus) to C0:1, C0:0,
and C2:6.
acquisition channel
MSC8101 support
package channel name
Required/Not required
for disassembly
Table 3 - 33: CPU to Mictor connections for Mictor D pins for 8101_MLT support
Logic analyzer
AMP mictor pin number
Mictor D pin 05QUAL:0CS2~Required
Mictor D pin 07D3:7D32Required
Mictor D pin 09D3:6D33Required
Mictor D pin 11D3:5D34Required
Mictor D pin 13D3:4D35Required
Mictor D pin 15D3:3D36Required
Mictor D pin 17D3:2D37Required
Mictor D pin 19D3:1D38Required
Mictor D pin 21D3:0D39Required
Mictor D pin 23D2:7D40Required
Mictor D pin 25D2:6D41Required
Mictor D pin 27D2:5D42Required
Mictor D pin 29D2:4D43Required
Mictor D pin 31D2:3D44Required
acquisition channel
MSC8101 support
package channel name
Required/Not required
for disassembly
3- 28
TMS708 MSC8101 Microprocessor Software Support
Reference: Symbol and Channel Assignment Tables
Table 3 - 33: CPU to Mictor connections for Mictor D pins for 8101_MLT support (cont.)
Logic analyzer
AMP mictor pin number
Mictor D pin 33D2:2D45Required
Mictor D pin 35D2:1D46Required
Mictor D pin 37D2:0D47Required
Mictor D pin 38D0:0D63Required
Mictor D pin 36D0:1D62Required
Mictor D pin 34D0:2D61Required
Mictor D pin 32D0:3D60Required
Mictor D pin 30D0:4D59Required
Mictor D pin 28D0:5D58Required
Mictor D pin 26D0:6D57Required
Mictor D pin 24D0:7D56Required
Mictor D pin 22D1:0D55Required
Mictor D pin 20D1:1D54Required
Mictor D pin 18D1:2D53Required
Mictor D pin 16D1:3D52Required
Mictor D pin 14D1:4D51Required
Mictor D pin 12D1:5D50Required
Mictor D pin 10D1:6D49Required
Mictor D pin 08D1:7D48Required
Mictor D pin 06CLOCK:2CS3~Required
acquisition channel
MSC8101 support
package channel name
Required/Not required
for disassembly
Table 3 - 34: CPU to Mictor connections for Mictor E pins for 8101_MLT support
Logic analyzer
AMP mictor pin number
Mictor E pin 05QUAL:3CS0~Required
Mictor E pin 07E3:7D0 (MSB)Required
Mictor E pin 09E3:6D1Required
Mictor E pin 11E3:5D2Required
Mictor E pin 13E3:4D3Required
Mictor E pin 15E3:3D4Required
Mictor E pin 17E3:2D5Required
Mictor E pin 19E3:1D6Required
Mictor E pin 21E3:0D7Required
acquisition channel
MSC8101 support
package channel name
Required/Not required
for disassembly
TMS708 MSC8101 Microprocessor Software Support
3- 29
Reference: Symbol and Channel Assignment Tables
Table 3 - 34: CPU to Mictor connections for Mictor E pins for 8101_MLT support (cont.)
Logic analyzer
AMP mictor pin number
Mictor E pin 23E2:7D8Required
Mictor E pin 25E2:6D9Required
Mictor E pin 27E2:5D10Required
Mictor E pin 29E2:4D11Required
Mictor E pin 31E2:3D12Required
Mictor E pin 33E2:2D13Required
Mictor E pin 35E2:1D14Required
Mictor E pin 37E2:0D15Required
Mictor E pin 38E0:0D31Required
Mictor E pin 36E0:1D30Required
Mictor E pin 34E0:2D29Required
Mictor E pin 32E0:3D28Required
Mictor E pin 30E0:4D27Required
Mictor E pin 28E0:5D26Required
Mictor E pin 26E0:6D25Required
Mictor E pin 24E0:7D24Required
Mictor E pin 22E1:0D23Required
Mictor E pin 20E1:1D22Required
Mictor E pin 18E1:2D21Required
Mictor E pin 16E1:3D20Required
Mictor E pin 14E1:4D19Required
Mictor E pin 12E1:5D18Required
Mictor E pin 10E1:6D17Required
Mictor E pin 08E1:7D16Required
Mictor E pin 06QUAL:2CS1~Required
acquisition channel
MSC8101 support
package channel name
Required/Not required
for disassembly
3- 30
TMS708 MSC8101 Microprocessor Software Support
Specifications
Specifications
Specification Tables
This section contains the specifications for the support.
Table 4--1 lists the electrical requirements the target system must produce for the
support to acquire correct data.
Table 4 - 1: Electrical specifications
CharacteristicsRequirements
Target system clock rate
8101_SNG specified clock rateMaximum 100 MHz
8101_SNG tested clock rateMaximum 50 MHz
8101_MLT specified clock rateMaximum 100 MHz
8101_MLT tested clock rateMaximum 66 MHz
Minimum setup time required2.5 ns
Minimum hold time required0ns
TMS708 MSC8101 Microprocessor Software Support
4- 1
Specifications
4- 2
TMS708 MSC8101 Microprocessor Software Support
Replaceable Parts List
Replaceable Parts Lists
This section contains a list of the replaceable components and modules for the
TMS708 MSC8101 support. Use this list to identify and order replacement parts.
Parts Ordering Information
Replacement parts are available through your local Tektronix field office or
representative.
Changes to Tektronix products are sometimes made to accommodate improved
components as they become available and to give you the benefit of the latest
improvements. Therefore, when ordering parts, it is important to include the
following information in your order:
HPart number
HInstrument type or model number
HInstrument serial number
HInstrument modification number, if applicable
If you order a part that has been replaced with a different or improved part, your
local Tektronix field office or representative will contact you concerning any
change in part number.
Using the Replaceable Parts List
The tabular information in the Replaceable Parts List is arranged for quick
retrieval. Understanding the structure and features of the list will help you find
all of the information you need for ordering replacement parts. The following
table describes the content of each column in the parts list.
TMS708 MSC8101 Microprocessor Software Support
5- 1
Replaceable Parts List
Parts list column descriptions
ColumnColumn nameDescription
1Figure & index numberItems in this section are referenced by figure and index numbers to the exploded view
illustrations that follow.
2Tektronix part numberUse this part number when ordering replacement parts from Tektronix.
3 and 4Serial numberColumn three indicates the serial number at which the part was first effective. Column four
indicates the serial number at which the part was discontinued. No entry indicates the part is
good for all serial numbers.
5QtyThis indicates the quantity of parts used.
6Name & descriptionAn item name is separated from the description by a colon (:). Because of space limitations, an
item name may sometimes appear as incomplete. Use the U.S. Federal Catalog handbook
H6-1 for further item name identification.
7Mfr. codeThis indicates the code of the actual manufacturer of the part.
8Mfr. part numberThis indicates the actual manufacturer’s or vendor’s part number.
Abbreviations
Chassis Parts
Mfr. Code to Manufacturer
Cross Index
Abbreviations conform to American National Standard ANSI Y1.1--1972.
Chassis-mounted parts and cable assemblies are located at the end of the
Replaceable Parts List.
The table titled Manufacturers Cross Index shows codes, names, and addresses
of manufacturers or vendors of components listed in the parts list.