Tektronix TMS708 Instruction Manual
Instruction Manual
TMS708
MSC8101 Microprocessor Software Support
071-1117-00
www.tektronix.com
Copyright © Tektronix, Inc. All rights reserved.
Tektronix products are covered by U.S. and foreign patents, issued and pending. Information in this public ation supercedes
that in all previously published material. Specifications and price c hange privileges reserved.
Tektronix, Inc., P.O. Box 500, Beaverton, OR 97077
TEKTRONIX and TEK are registered trademarks of Tektronix, Inc.
SOFTWARE WARRANTY
Tektronix warrants that the media on which this software product is furnished and the encoding of the programs on
the media will be free from defects in materials and workmanship for a period of three (3) months from the date of
shipment. If a medium or encoding proves defective during the warranty period, Tektronix will provide a
replacement in exchange for the defective medium. Except as to the media on which this software product is
furnished, this software product is provided “as is” without warranty of any kind, either express or implied.
Tektronix does not warrant that the functions contained in this software product will meet Customer’s
requirements or that the operation of the programs will be uninterrupted or error-free.
In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration
of the warranty period. If Tektronix is unable to provide a replacement that is free from defects in materials and
workmanship within a reasonable time thereafter, Customer may terminate the license for this software product
and return this software product and any associated materials for credit or refund.
THIS WARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER W ARRANTIES, EXPRESS
OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’
RESPONSIBILITY TO REPLACE DEFECTIVE MEDIA OR REFUND CUSTOMER’S PAYMENT IS
THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS
WARRANTY. TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT,
SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER
TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH
DAMAGES.
Table of Contents
Getting Started
Operating Basics
Preface vii...................................................
Manual Conventions vii..............................................
Contacting Tektronix viii.............................................
Support Package Description 1--1.......................................
Logic Analyzer Software Compatibility 1--1..............................
Logic Analyzer Configuration 1--2......................................
Requirements and Restrictions 1--2......................................
Timing Display Format 1--4...........................................
Functionality Not Supported 1--5.......................................
Functionality Supported But Not Tested 1--5..............................
Connecting the Logic Analyzer to a Target System 1--6.....................
Labeling P6434 Probes 1--6............................................
Setting Up the Support 2--1.....................................
Installing the Support Software 2--1.....................................
Channel Group Definitions 2--1.........................................
8101_SNG Support 2--2...........................................
8101_MLT Support 2--2...........................................
Clocking 2--3.......................................................
Acquisition Setup 2--3............................................
Clocking Options 2--3.............................................
Custom Cl ocking 2--3.............................................
Acquiring and Viewing Disassembled Data 2--5....................
Acquiring Data 2--5..................................................
Signal Acquisition 2--5............................................
Viewing Cycle Type Labels 2--8........................................
Hardware Display Format 2--9......................................
Changing How Labels are Displayed 2--13.................................
Optional Display Selections 2--14....................................
Micro-Specific Fields for 8101_SNG 2--14.............................
Micro-Specific Fields for 8101_MLT 2--17.............................
Marking Cycles 2--20..............................................
Displaying Exception Labels 2--21...................................
Viewing an Example of Cycle Type Labels 2--23............................
TMS708 MSC8101 Microprocessor Software Support
i
Table of Contents
Reference
Specifications
Replaceable Parts List
Reference: Symbol and Channel Assignment Tables 3--1.............
Symbol Tables 3--1..................................................
8101_SNG Support 3--1...........................................
8101_MLT Support 3--4...........................................
Channel Assignment Tables 3--7.......................................
8101_SNG Support 3--7...........................................
8101_MLT Support 3--13...........................................
CPU To Mictor Connections 3--20.......................................
8101_SNG Support 3--21...........................................
8101_MLT Support 3--26...........................................
Specification Tables 4--1..............................................
Parts Ordering Information 5--1.........................................
Using the Replaceable Parts List 5--1....................................
Index
ii
TMS708 MSC8101 Microprocessor Software Support
List of Figures
Table of Contents
Figure 2--1: Bus timing d iagram for SDRAM memory 2--6...........
Figure 2--2: Bus timing d iagram for GPCM memory 2--6............
Figure 2--3: Bus timing diagram for Multi Master mode 2--7.........
Figure 2--4: Example of the Hardware Display format in the
Single Master Mode 2--12....................................
Figure 2--5: Example of the Hardware Display format in the
Multi Master Mode 2--13.....................................
TMS708 MSC8101 Microprocessor Software Support
iii
Table of Contents
List of Tables
Table 2--1: Channel groups for the Single Master Mode 2--2.........
Table 2--2: Channel groups for the Multi Master Mode 2--2.........
Table 2--3: Sample points in Single Master Mode 2--7...............
Table 2--4: Sample points in Multi Master Mode 2--8...............
T able 2--5: Description of special characters in display 2--9..........
Table 2--6: Cycle type label definitions for the 8101_SNG
support 2--9..............................................
Table 2--7: Cycle type label definitions for the 8101_MLT
support 2--10..............................................
Table 2--8: General cycle type labels 2--11..........................
Table 2--9: Logic analyzer disassembly display options 2--14..........
Table 2--10: Mark selections and definitions for 8101_SNG
support 2--21...............................................
Table 2--11: Mark selections and definitions for 8101_MLT
support 2--21...............................................
Table 2--12: Interrupt and exception lab els 2--21....................
Table 3--1: 8101_SNG_Control group symbol table definitions 3--1....
Table 3--2: 8101_SNG_Chip_Sel group symbol table definitions 3--2..
Table 3--3: 8101_SNG_Byte_Enb group symbol table
definitions 3--2............................................
Table 3--4: 8101_MLT_Control group symbol table definitions 3--4...
Table 3--5: 8101_MLT_Chip_Sel group symbol table definitions 3--4..
Table 3--6: 8101_MLT_T_Type group symbol table definitions 3--5...
Table 3--7: 8101_MLT_T_Size group symbol table definitions 3--5....
Table 3--8: 8101_MLT_T_Code group symbol table definitions 3--6...
Table 3--9: 8101_MLT_Req_Grant group symbol table
definitions 3--6............................................
Table 3--10: Address group channel assignments for 8101_SNG
support 3--7..............................................
Table 3--11: Hi_Data group channel assignments for 8101_SNG
support 3--8..............................................
Table 3--12: Lo_Data group channel assignments for 8101_SNG
support 3--9..............................................
Table 3--13: Control group channel assignments for 8101_SNG
support 3--11..............................................
iv
TMS708 MSC8101 Microprocessor Software Support
Table of Contents
Table 3--14: Chip_Sel group channel assignments for 8101_SNG
support 3--11..............................................
Table 3--15: Byte_Enb group channel assignments for 8101_SNG
support 3--12..............................................
Table 3--16: Misc group channel assignments for 8101_SNG
support 3--12..............................................
Table 3--17: Address group channel assignments for 8101_MLT
support 3--13..............................................
Table 3--18: Hi_Data group channel assignments for 8101_MLT
support 3--14..............................................
Table 3--19: Lo_Data group channel assignments for 8101_MLT
support 3--15..............................................
Table 3--20: Control group channel assignments for 8101_MLT
support 3--16..............................................
Table 3--21: Chip_Sel group channel assignments for 8101_MLT
support 3--17..............................................
Table 3--22: T_Type group channel assignments for 8101_MLT
support 3--17..............................................
Table 3--23: T_Size group channel assignments for 8101_MLT
support 3--18..............................................
Table 3--24: T_Code group channel assignments for 8101_MLT
support 3--18..............................................
Table 3--25: Req_Grant group channel assignments for 8101_MLT
support 3--19..............................................
Table 3--26: Recommended pin assignments for a Mictor connector
(component side) 3--20.......................................
Table 3--27: CPU to Mictor connections for Mictor A pins for
8101_SNG support 3--21.....................................
Table 3--28: CPU to Mictor connections for Mictor C pins for
8101_SNG support 3--22.....................................
Table 3--29: CPU to Mictor connections for Mictor D pins for
8101_SNG support 3--23.....................................
Table 3--30: CPU to Mictor connections for Mictor E pins for
8101_SNG support 3--24.....................................
Table 3--31: CPU to Mictor connections for Mictor A pins for
8101_MLT support 3--26....................................
Table 3--32: CPU to Mictor connections for Mictor C pins for
8101_MLT support 3--27.....................................
Table 3--33: CPU to Mictor connections for Mictor D pins for
8101_MLT support 3--28.....................................
Table 3--34: CPU to Mictor connections for Mictor E pins for
8101_MLT support 3--29.....................................
TMS708 MSC8101 Microprocessor Software Support
v
Table of Contents
T able 4--1: Electrical specifications 4--1...........................
vi
TMS708 MSC8101 Microprocessor Software Support
Preface
This instruction manual contains information specific to the TMS708 MSC8101
microprocessor support package and is part of a set of information on how to
operate this product on compatible Tektronix logic analyzers.
If you are familiar with operating microprocessor support packages on the logic
analyzer for which the TMS708 MSC8101 support was purchased, you will
probably only need this instruction manual to set up and run the support.
If you are not familiar with operating microprocessor support packages, you will
need to supplement this instruction manual with information on basic operations
to set up and run the support.
Information on basic operations of microprocessor support packages is included
with each product. Each logic analyzer includes basic information that describes
how to perform tasks common to s upport packages on that platform. This
information can be in the form of online help, an installation manual, or a user
manual.
This manual provides detailed information on the following topics:
H Connecting the logic analyzer to the target system
Manual Conventions
H Setting up the logic analyzer to acquire data from the target system
H Acquiring and viewing cycle type labels
This manual uses the following conventions:
H The term “disassembler” refers to the software that decodes bus cycles and
displays cycle types.
H The phrase “information on basic operations” refers to the logic analyzer
online help, an installation manual, or a user manual covering the basic
operations of the microprocessor support.
H The term “logic analyzer” refers to the Tektronix logic analyzer for which
this product was purchased.
TMS708 MSC8101 Microprocessor Software Support
vii
Preface
Contacting Tektronix
Phone 1-800-833-9200*
Address Tektronix, Inc.
Department or name (if known)
14200 SW Karl Braun Dri ve
P.O. Box 500
Beaverton, OR 97077
USA
Web site www.tektronix.com
Sales support 1-800-833-9200, select option 1*
Service support 1-800-833-9200, select option 2*
Technical support Email: techsupport@tektronix.com
1-800-833-9200, select option 3*
6:00 a.m. -- 5:00 p.m. Pacific time
* This phone number is toll free in North America. After office hours, please leave a
voice mail message.
Outside North America, contact a Tektronix sales office or distributor; see the
Tektronix web site for a list of offices.
viii
TMS708 MSC8101 Microprocessor Software Support
Getting Started
Getting Started
This section contains information on the TMS708 MS C8101 microprocessor
support, and information on connecting your logic analyzer to your target
system.
Support Package Description
The TMS708 microprocessor support package displays the Cycle Type labels,
marks the Idle Cycles, and validates the data bus and the address bus. The
TMS708 does not display the instructions nor identify the Fetch cycles. The
Motorola MSC8101 16-bit Digital Signal Processor (DSP) is the first member of
the family of DSPs based on the Starcore SC140 DS P core.
The TMS708 installs two support packages 8101_SNG and 8101_MLT.
H 8101_SNG supports the Single Master mode of MSC8101 processor.
H 8101_MLT supports the Multi Master mode of MSC8101 processor. You can
use the 8101_MLT support for Internal and External Arbiter configurations.
In the Internal Arbiter configuration, the software supports three more
external masters on the same system bus. In the External Arbiter configuration, the software supports up to four masters. The software decodes the
cycles of all the masters.
The TMS708 microprocessor support package decodes the Cycle Types,
validates the data bus and identifies the Idle Cycles. The support does not decode
Instructions.
Refer to information on basic operations to determine how many modules and
probes your logic analyzer needs to meet the minimum channel requirements for
the TMS708 microprocessor support.
To use this support efficiently, you need the items listed in the information on
basic operations as well as the MSC8101 Microprocessor User Manual
(Motorola, April 2001, and Revision 0, MSC8101RM/D).
Logic Analyzer Software Compatibility
The label on the microprocessor support floppy disk states which version of
logic analyzer software this support is compatible with.
TMS708 MSC8101 Microprocessor Software Support
1- 1
Getting Started
Logic Analyzer Configuration
The TMS708 MSC8101 microprocessor support requires the following
minimum module configuration:
H One 136-channel, 100 MHz module for 8101_SNG support
H One 136-channel, 100 MHz module for 8101_MLT support
Requirements and Restrictions
Review the electrical specifications in the Specifications section in this manual
as they pertain to your target system, as well as the following descriptions of
other MSC8101 support requirements and restrictions.
Hardware Reset. If a hardware reset occurs in your MSC8101 system during an
acquisition, the disassembler application might acquire invalid samples.
System Clock Rate CLKOUT. The support can acquire data from the MSC8101
microprocessor operating at speeds of up to 100 MHz
has been tested for speeds up to 50 MHz and the 8101_MLT support up to
66MHz.
T_Code Group in 8101_MLT Group. The T_Code channel group consists of signals
TC0/BR0~, TC1/BG0~, and TC2/DBG0~. By default, this group is hidden in
the support package. If you want to use the support for Internal Arbiter Configuration, you must connect the signals TC0, TC1, and TC2 to the logic analyzer
channels C0:1, C0:0 and C2:6. To view the activities of TC[0-2] signals, add the
T_Code group to the listing using CTRL+L. If you want to use the support for
External Arbiter configuration, connect the signals BR0~, BG0~, and DBG0~ to
the logic analyzer channels C0:1,C0:0, and C2:6. The T_Code group is not valid
in External Arbiter Configuration.
Triggering on Address in a Burst Transaction. The signals BADDR[31--27]
generate the address increments to memory devices for burst accesses and these
are not visible when signals A[31--27] are connected to the logic analyzer
channels A0:[0--4]. You can trigger on an address within a burst transaction only
if signals BADDR[31--27] are connected to the logic analyzer channels A0:[0--4].
The disassembler displays the address increments for burst transactions even
though signals A[31--27] are probed.
1
. The 8101_SNG support
1- 2
1
Specification at time of printing. Contact your Tektronix sales representative for
current information on the fastest devices supported.
TMS708 MSC8101 Microprocessor Software Support
Getting Started
Signals Not Required in t he Channel Assignment. The TMS708 MSC8101 support
package decodes cycle types, validates address and data bus, and identifies the
idle cycles acquired by clock-by-clock acquisition. It does not decode instructions. The channel assignment contains signals that are not required to support
cycle type decoding, validate address and data bus, or identify idle cycles. If you
include the P6434 high-density probe interface in your design, we recommend
that you use these signals.
EAV Bit Setting in 8101_SNG Support. Set the EAV (Enable Address Visibility) bit
of the Bus Configuration Register (BCR) to 1 for correct disassembly. When the
EAV is set to 1, the Bank Select signals are not driven on the address bus.
During READ and WRITE commands to SDRAM devices, the full address is
driven on bus address lines. Therefore, when the EAV bit is set to 1, the full
address is valid at PSDCAS~ asserted and PSDRAS~ deasserted for SDRAM
accesses.
Qualifiers Used in 8101_MLT Support. The Multi Master support uses the internal
memory controller signals for validating Address and Data. The support uses the
ALE signal to qualify a valid Address and the PSDVAL~ signal to qualify a
valid data on the bus. The external masters connected to the system may be an
MSC8101 or a non-MSC8101processor. For an MSC 8101 processor, the ALE
and PSDVAL~ signals are the qualifiers. For a non-MSC8101 processor, the
ALE and TA~ signals are the qualifiers.
Address Pipelining. The TMS708 support is designed to support pipelining up to
one level. While acquiring data from systems with pipelining, you may at the
beginning acquire data tenures without any corresponding address tenures. The
support, by default, starts associating the first data with the first acquired address
tenure. This may cause incorrect Cycle Type decoding. In that case, you must
associate the first acquired address with the correct data tenure using the ‘Invalid
Data’ marking option. You must mark as ‘Invalid Data’ the first data tenure
without any corresponding address. Once you mark the Invalid Data, the support
package adjusts itself to associate the address and data correctly.
Nonintrusive Acquisition. Acquiring microprocessor bus cycles is nonintrusive to
the target system. That is, the TMS708 MSC8101 microprocessor does not
intercept, modify, or present back signals to the target system.
TMS708 MSC8101 Microprocessor Software Support
1- 3
Getting Started
Channel Groups. The channel groups required for clocking and cycle type
decoding in the 8101_SNG support are:
Address
Hi_Data
Lo_Data
Control
Chip_Sel
Byte_Enb
Misc
The channel groups required for clocking and cycle type decoding in the
8101_MLT support are:
Address
Hi_Data
Lo_Data
Control
Chip_Sel
T_Type
T_Size
T_Code
Req_Grant
Timing Display Format
The support has a Timing Display Format file. It sets up the display to show the
following waveforms:
For 8101_SNG Support:
CLKOUT
Address
Hi_Data
Lo_Data
PSDRAS~/POE~
PSDCAS~
PSDVAL~
Control
Chip_Sel
Byte_Enb
Misc
NOTE. The Address, Hi_Data, Lo_Data, Control, Chip_Sel, Byte_Enb, and Misc
groups are displayed in busform.
1- 4
TMS708 MSC8101 Microprocessor Software Support
For 8101_MLT S upport:
CLKOUT
Address
Hi_Data
Lo_Data
TS~
ALE
TA~
TEA~
AACK~
PSDVAL~
T_Type
T_Size
T_Code
Control
Chip_Sel
Req_Grant
Getting Started
NOTE. The Address,Hi_Data, Lo_Data, T_Type, T_Size, T_Code, Control,
Chip_Sel, and Req_Grant groups are displayed in busform.
Functionality Not Supported
The TMS708 software does not support the following functionalities:
H UPM cycles
H DMA cycles
H HDI16 cycles
H Multiple master mode with multiple memory controllers
H PowerPC
local bus cycles
Functionality Supported But Not Tested
The TMS708 software supports the following features, but are not tested.
H 60X system bus interface of the MSC8102 processor
H External Arbiter Configuration in 8101_MLT support
H Atomic bus operations (RAWA, WARA) in 8101_SNG support
TMS708 MSC8101 Microprocessor Software Support
1- 5
Getting Started
Connecting the Logic Analyzer to a Target System
You can use the channel probes, clock probes, and leadsets with a commercial
test clip (or adapter) to make the connections between the logic analyzer and
your target system.
To connect the probes to MSC8101 signals in the target system using a test clip,
follow the steps:
1. Power off your target system. You do not need to power off the logic
analyzer.
CAUTION. To prevent static damage, handle the microprocessor, probes, and the
logic analyzer module in a static-free environment. Static discharge can damage
these components.
Always wear a grounding wrist strap, heel strap, or similar device while
handling the microprocessor.
Labeling P6434 Probes
2. To discharge your stored static electricity, touch the ground connector
located on the back of the logic analyzer. If you are using a test clip, touch
any of the ground pins on the clip to discharge stored electricity from the test
clip.
CAUTION. To prevent permanent damage to the pins on the microprocessor, place
the target system on a horizontal surface before connecting the test clip.
3. Place the target system on a horizontal, static-free surface.
4. Use Tables 3--27 through 3--34 starting on page 3--21 to connect the channel
probes to MSC8101 signal pins on the test clip or in the target system.
5. Use leadsets to connect at least one ground lead from each channel and the
ground lead from each clock probe to the ground pins on your test clip.
The TMS708 MSC8101 software support package relies on the channel mapping
and labeling scheme for the P6434 Probes. Apply labels using the instructions
described in the P6434 Probe Instructions manual.
1- 6
TMS708 MSC8101 Microprocessor Software Support
Operating Basics
Setting Up the Support
This section provides information on how to set up the support and covers the
following topics:
H Installing the support software
H Channel group definitions
H Clocking options
The information in this section is specific to the operations and functions of the
TMS708 MSC8101 support on any Tektronix logic analyzer for which the
support can be purchased. Information on basic operations describes general
tasks and functions.
Before you acquire and display cycle type labels, you need to load the support
and specify the setups for clocking and triggering as described in the information
on basic operations. The support provides default values for each of these setups,
but you can change the default values as needed.
Installing the Support Software
NOTE. Before you install any software, you should verify that the microprocessor
support software is compatible with the logic analyzer software.
To install the TMS708 MSC8101 software on your Tektronix logic analyzer,
follow these steps:
1. Insert the floppy disk in the disk drive.
2. Click the Windows Start button, point to Settings, and click Control Panel.
3. In the Control Panel window, double-click Add/Remove Programs.
4. Follow the instructions on the screen for installing the software from the
To remove or uninstall software, follow the above instructions and select
Uninstall. You need to close all windows before you uninstall any software.
Channel Group Definitions
The software automatically defines channel groups for the support.
floppy disk.
TMS708 MSC8101 Microprocessor Software Support
2--1
Setting Up the Support
8101_SNG Support
8101_MLT Support
The channel groups for the TMS708 8101_SNG support are: Address, Hi_Data,
Lo_Data, Control, Chip_Sel, Byte_Enb, and Misc. Table 2--1 shows the channel
groups and the display radix for the 8101_SNG support.
Table 2--1: Channel groups for the Single Master
Mode
Group name Display radix
Address HEX
Hi_Data HEX
Lo_Data HEX
Mnemonics NONE (disassembler generated text)
Control SYM
Chip_Sel SYM
Byte_Enb SYM
Misc HEX (hidden by default)
The channel group for the TMS708 8101_MLT support are: Address, Hi_Data,
Lo_Data, T_Type, T_Size, T_Code, Control, Chip_Sel, and Req_Grant.
Table 2--2 shows the channel groups and the display radix for the 8101_MLT
support.
NOTE. The T_Code group is applicable only in Internal Arbiter Mode.
Table 2--2: Channel groups for the Multi Master Mode
Group name Display radix
Address HEX
Hi_Data HEX
Lo_Data HEX
Mnemonics NONE (disassembler generated text)
Control SYM (hidden by default)
Chip_Sel SYM
T_Type SYM
T_Size SYM
T_Code SYM (hidden by default)
Req_Grant SYM
2--2
TMS708 MSC8101 Microprocessor Software Support
Clocking
Setting Up the Support
If you want to know which signal is in which group, refer to the channel
assignment tables beginning on page 3--7.
Acquisition Setup
Clocking Options
Custom Clocking
The TMS708 MSC8101 affects the logic analyzer setup menus (and submenus)
by modifying existing fields and adding micro-specific fields.
On the logic analyzer, the TMS708 MSC8101 support adds the selection
‘8101_SNG’ and ‘8101_MLT’ to the Load Support Package dialog box, under
the File pulldown menu. Once ‘TMS708 MSC8101 support’ is loaded, the
‘Custom’ clocking mode selection in the logic analyzer module Setup menu is
also enabled.
The TMS708 support offers a microprocessor-specific clocking mode for the
MSC8101 microprocessor. This clocking mode is the default selection whenever
you load the MSC8101 support.
The disassembly will not be correct when using the Internal or External clocking
modes. Information on basic operations describes how to use these clock
selections for general purpose analysis.
A special clocking program is loaded to the module every time you load the
8101_SNG or 8101_MLT support. This special clocking is called Custom.
With Custom Clocking, the module logs in signals from the multiple channel
groups at every clock on the TMS708 MSC8101 bus. The module then sends all
the logged-in signals to the trigger machine and stores the signals in the
acquisition memory of the module.
When Custom is selected, the Custom Clocking Options menu adds the subtitle:
‘8101_SNG Microprocessor Clocking Support’ or ‘8101_MLT Microprocessor
Clocking Support’, and displays the clocking option—Standard. This is the only
custom clocking option available for this support.
TMS708 MSC8101 Microprocessor Software Support
2--3
Setting Up the Support
2--4
TMS708 MSC8101 Microprocessor Software Support
Acquiring and Viewing Disassembled Data
This section describes how to acquire and view data. The following information
covers these topics and tasks:
H Acquiring data
H Viewing cycle type labels
H Changing the way labels are displayed
H Timing diagrams
Acquiring Data
The TMS708 MSC8101 software package installs the 8101_SNG support for the
MSC8101 processor working in Single Master mode and the 8101_MLT for
MSC8101 processor working in Multi Master mode (for up to four masters on
the target system). Once you load the support, by default, the custom clocking
option is selected. Specify the trigger, if any, and you are ready to acquire and
disassemble data.
Signal Acquisition
If you have any problems acquiring data, refer to information on basic operations
in your online help or Appendix A: Error Messages and Disassembly Problems in
the user manual.
8101_SNG Support. The Custom Clock uses the falling edge of the CLKOUT
signal.
TMS708 MSC8101 Microprocessor Software Support
2--5
Acquiring and Viewing Disassembled Data
Figures 2--1 and 2--2 show the Bus Timing diagrams for SDRAM memory and
GPCM memory in the Single Master mode.
CLKOUT
ALE
CS
SDRAS
SDCAS
MA[0--11]
WE
DQM
Data
Z Column2
MMMMMMMMMMM
Column1
D0 D1 D0 D1
Figure 2--1: Bus timing diagram for SDRAM memory
CLKOUT
Address
PSDVAL
CSx
CSy
BCTLx
POE
Data
M
MM MM
Figure 2--2: Bus timing diagram for GPCM memory
2--6
TMS708 MSC8101 Microprocessor Software Support
Acquiring and Viewing Disassembled Data
Table 2--3 describes the sample points in 8101_SNG support.
Table 2--3: Sample points in Single Master Mode
Sample point Signals
Master sample point, M A[0--31], D[0--31], D[32--63], CS~[0--7],
PWE~[0--7], PSDCAS~, PSDRAS~/POE~,
PSDVAL~, CLKOUT, PSDWE~, PSDA10,
PGTA~, PSDAMUX, BCTL0~, BCTL1~,
NMI_OUT, HRESET~, SRESET~, PORESET~,
NMI~, DP6~/DACK3~, DP7~/DACK4~,
IRQ7~/INT_OUT~
The only sample point is M (Master). All the signals are logged and mastered at
every falling edge of the CLKOUT signal.
8101_MLT Support. The Custom Clock uses the rising edge of the CLKOUT.
Figure 2--3 shows the Bus Timing diagram for Multi Master mode.
CLKOUT
ADDR + ATTR
TS
AACK
DBG
TA
PSDVAL
D[0--63]
MMMMM M MM MMMM
D1 D2 D3
D0
Figure 2--3: Bus timing diagram for Multi Master mode
TMS708 MSC8101 Microprocessor Software Support
2--7
Loading...