Tektronix TMS562A Instruction Manual
Instruction Manual
TMS562A
MPC8260ITR Microprocessor
Software Support
071-0798-00
www.tektronix.com
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TEKTRONIX and TEK are registered trademarks of T ektronix, Inc.
SOFTWARE WARRANTY
T ektronix warrants that the media on which this software product is furnished and the encoding of the programs on
the media will be free from defects in materials and workmanship for a period of three (3) months from the date of
shipment. If a medium or encoding proves defective during the warranty period, T ektronix will provide a
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furnished, this software product is provided “as is” without warranty of any kind, either express or implied.
T ektronix does not warrant that the functions contained in this software product will meet Customer’s
requirements or that the operation of the programs will be uninterrupted or error-free.
In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration
of the warranty period. If T ektronix is unable to provide a replacement that is free from defects in materials and
workmanship within a reasonable time thereafter, Customer may terminate the license for this software product
and return this software product and any associated materials for credit or refund.
THIS WARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER WARRANTIES, EXPRESS
OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’
RESPONSIBILITY TO REPLACE DEFECTIVE MEDIA OR REFUND CUSTOMER’S PAYMENT IS
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TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH
DAMAGES.
Table of Contents
Getting Started
Operating Basics
Preface vii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Manual Conventions vii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contacting T ektronix viii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Support Package Description 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Analyzer Software Compatibility 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Analyzer Configuration 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Requirements and Restrictions 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functionality Not Supported 1–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features Not T ested 1–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard Accessories 1–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Options 1–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connecting the Logic Analyzer to a System Under T est 1–7. . . . . . . . . . . . . . . . . . .
Setting Up the Support 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Installing the Support Software 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Group Definitions 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Support Package Setups 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocking 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocking Options 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Acquisition 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acquiring and Viewing Disassembled Data 2–11. . . . . . . . . . . . . . . . . . . . .
Acquiring Data 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing Disassembled Data 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Display Format 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Display Format 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Flow Display Format 2–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subroutine Display Format 2–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Changing How Data is Displayed 2–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optional Display Selections 2–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Micro Specific Fields 2–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Marking Cycles 2–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Displaying Exception Labels 2–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing an Example of Disassembled Data 2–23. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Trace Reconstruction (ITR) 2–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifications
Specification T ables 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Replaceable Parts List
Parts Ordering Information 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the Replaceable Parts List 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS562A MPC8260ITR Microprocessor Support
i
Table of Contents
Reference
Index
Symbol Tables 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Assignments 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU To Mictor Connections 5–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ii
TMS562A MPC8260ITR Microprocessor Support
List of Figures
Table of Contents
Figure 2–1: Bus timing for 8260ITR_60X mode 2–5. . . . . . . . . . . . . . . . .
Figure 2–2: Bus timing for 8260 single mode of
SDRAM memory type 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2–3: Bus timing for 8260 single mode of nonSDRAM access 2–9.
Figure 2–4: Example of the hardware display format 2–14. . . . . . . . . . . . .
Figure 2–5: Listing window 2–27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2–6: Display showing Fetch Stream 2–28. . . . . . . . . . . . . . . . . . . . . .
Figure 2–7: Display showing Memory Image 2–29. . . . . . . . . . . . . . . . . . . .
TMS562A MPC8260ITR Microprocessor Support
iii
Table of Contents
List of Tables
Table 2–1: Signal acquisition for 8260ITR_60X mode 2–6. . . . . . . . . . . .
Table 2–2: Signal acquisition from SDRAM 2–8. . . . . . . . . . . . . . . . . . . .
Table 2–3: Signal acquisition from nonSDRAM 2–9. . . . . . . . . . . . . . . . .
Table 2–4: Description of special characters in the display 2–12. . . . . . . .
Table 2–5: Support cycle-type labels for sequences and definitions
(for 8260ITR_60X). 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2–6: Cycle-type labels for sequences and definitions for
8260ITR_SNG 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2–7: Mark selections and definitions 2–21. . . . . . . . . . . . . . . . . . . . .
Table 2–8: Marks available with TS~ asserted
(for 8260ITR_60X only) 2–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2–9: Interrupt and exception labels 2–22. . . . . . . . . . . . . . . . . . . . . .
Table 3–1: Electrical specifications 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–1: 8260ITR_60X _Ctrl group symbol table definitions 5–1. . . .
Table 5–2: 8260ITR_SNG Ctrl group symbol table definitions 5–2. . . . .
Table 5–3: 8260ITR_60X _Tsiz group symbol table definitions 5–2. . . . .
Table 5–4: 8260ITR_60X _Tc group symbol table definitions 5–3. . . . . .
Table 5–5: Address channel group assignments for 8260ITR_60X 5–5. .
Table 5–6: High_Data channel group assignments for 8260ITR_60X 5–6
Table 5–7: Low_Data channel group assignments for 8260ITR_60X 5–8
Table 5–8: Control channel group assignments for 8260ITR_60X 5–9. .
Table 5–9: Tsize channel group assignments for 8260ITR_60X 5–10. . . .
Table 5–10: TransferType channel group assignments for
8260ITR_60X 5–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–11: TC channel group assignments for 8260ITR_60X 5–10. . . . .
Table 5–12: Misc channel group assignments for 8260ITR_60X 5–11. . . .
Table 5–13: Clock and Qualifier channel assignments for
8260ITR_60X 5–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–14: Signals required for clocking and disassembly for
8260ITR_60X 5–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–15: Signals not required for clocking and disassembly for
8260ITR_60X 5–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–16: Address channel group assignments for 8260ITR_SNG 5–15
Table 5–17: High_Data channel group assignments for
8260ITR_SNG 5–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–18: Low_Data channel group assignments for
8260ITR_SNG 5–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
TMS562A MPC8260ITR Microprocessor Support
List of Tables (Cont)
Table of Contents
Table 5–19: Control channel group assignments for 8260ITR_SNG 5–19
Table 5–20: Misc channel group assignments for 8260ITR_SNG 5–20. . .
Table 5–21: Clock and Qualifier channel assignments for
8260ITR_SNG 5–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–22: Signals required for clocking and disassembly for
8260ITR_SNG 5–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–23: Signals not required for clocking and disassembly for
8260ITR_SNG 5–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–24: Recommended pin assignments for a Mictor connector
(component side) 5–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–25: CPU to Mictor connections for Mictor A pins for
8260ITR_60X 5–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–26: CPU to Mictor connections for Mictor C pins for
8260ITR_60X 5–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–27: CPU to Mictor connections for Mictor E pins for
8260ITR_60X 5–28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–28: CPU to Mictor connections for Mictor D pins for
8260ITR_60X 5–29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–29: CPU to Mictor connections for Mictor A pins for
8260ITR_SNG 5–31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–30: CPU to Mictor connections for Mictor C pins for
8260ITR_SNG 5–32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–31: CPU to Mictor connections for Mictor E pins for
8260ITR_SNG 5–34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–32: CPU to Mictor connections for Mictor D pins for
8260ITR_SNG 5–35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS562A MPC8260ITR Microprocessor Support
v
Table of Contents
vi
TMS562A MPC8260ITR Microprocessor Support
Preface
This instruction manual contains specific information about the
TMS562A MPC8260ITR microprocessor support package and is part of a set of
information on how to operate this product on compatible Tektronix logic
analyzers.
If you are familiar with operating microprocessor support packages on the logic
analyzer for which the TMS562A MPC8260ITR support was purchased, you will
probably only need this instruction manual to set up and run the support.
If you are not familiar with operating microprocessor support packages, you will
need to supplement this instruction manual with information on basic operations
to set up and run the support.
Information on basic operations of microprocessor support packages is included
with each product. Each logic analyzer includes basic information that describes
how to perform tasks common to support packages on that platform. This
information can be in the form of online help, an installation manual, or a user
manual.
This manual provides detailed information on the following topics:
Manual Conventions
H Connecting the logic analyzer to the system under test
H Setting up the logic analyzer to acquire data from the system under test
H Acquiring and viewing disassembled data
This manual uses the following conventions:
H The term “disassembler” refers to the software that disassembles bus cycles
into instruction mnemonics and cycle types.
H The phrase “information on basic operations” refers to logic analyzer online
help, an installation manual, or a user manual covering the basic operations
of microprocessor support.
TMS562A MPC8260ITR Microprocessor Support
vii
Preface
Contacting Tektronix
Phone 1-800-833-9200*
Address Tektronix, Inc.
Department or name (if known)
14200 SW Karl Braun Drive
P.O. Box 500
Beaverton, OR 97077
USA
Web site www.tektronix.com
Sales support 1-800-833-9200, select option 1*
Service support 1-800-833-9200, select option 2*
Technical support Email: techsupport@tektronix.com
1-800-833-9200, select option 3*
1-503-627-2400
6:00 a.m. – 5:00 p.m. Pacific time
* This phone number is toll free in North America. After office hours, please leave a
voice mail message.
Outside North America, contact a Tektronix sales office or distributor; see the
Tektronix web site for a list of offices.
viii
TMS562A MPC8260ITR Microprocessor Support
Getting Started
Getting Started
This section contains information on the TMS562A MPC8260ITR microprocessor support and information on connecting your logic analyzer to your system
under test.
Support Package Description
The TMS562A MPC8260ITR microprocessor support package displays
disassembled data from systems based on the Motorola MPC8260 microprocessor.
The TMS562A support includes the 8260ITR_60X software support for the 60x
Compatible Bus Mode (SDRAM, GPCM) and the 8260ITR_SNG software
support for the Single 8260 Mode (SDRAM, GPCM).
To use this support efficiently, refer to your logic analyzer online help and the
PowerQUICC II User’s Manual Rev. 1.0.
Logic Analyzer Software Compatibility
The label on the microprocessor support floppy disk states the version of logic
analyzer software the support is compatible with.
Logic Analyzer Configuration
The TMS562A support requires a minimum of one 136 module configuration
when using either the 8260ITR_60X support or the 8260ITR_SNG support.
Requirements and Restrictions
Review the electrical specifications in the Specifications chapter in this manual
as they pertain to your system under test, as well as the following descriptions of
other MPC8260ITR support requirements and restrictions. The following
information applies to both the 8260ITR_SNG and the 8260ITR_60X supports
unless specified otherwise.
Reset. If a hardware reset occurs in your MPC8260ITR system during an
acquisition, the application disassembler might acquire an invalid sample and
display the disassembled data incorrectly.
TMS562A MPC8260ITR Microprocessor Support
1–1
Getting Started
System Clock Rate. The operating speeds that the
TMS562A support can acquire
data from the MPC8260ITR microprocessor are listed on page 3–1. These
specifications were valid at the time this manual was printed. Please contact your
Tektronix Sales Representative for current information on the fastest devices
supported.
Disabling the Instruction Cache. To display disassembled acquired data, you must
disable the internal instruction cache. Disabling the cache makes all instruction
prefetches visible on the bus so that they can be acquired and displayed
disassembled.
Disabling the Data Cache. To display acquired data, you must disable the data
cache. Disabling the data cache makes visible all loads and stores to memory on
the bus, including data reads and writes, so the software can acquire and display
them.
Viewing Instruction Cache Activity. To see the Instruction cache activity, set the
disassembly option “Disassemble based on” to Memory Image. For further
details see the section Viewing Cache Activity on page 2–25.
Address Translation. The address translation must be turned off for proper
disassembly. The TMS562A support does not handle address translation.
NonIntrusive Acquisition. Acquiring microprocessor bus cycles is nonintrusive to
the system under test. That is, the MPC8260ITR support does not intercept,
modify, or present signals back to the system under test.
Memory Region. If the memory region of a PortWidth overlaps with another
PortWidth the disassembly may be incorrect.
Symbolic Display for Control group. The listed cycle types may be frequently
wrong for the Control group when using noncustom clocked data. This problem
occurs in waveform because the Control group is symbolic by default. To
overcome this problem, you must expand the group and look at the individual
lines.
Endian Mode for the Memory Image Option. The disassembly from the Memory
Image occurs correctly only for Big endian mode. Therefore, the Memory image
must be in Big Endian format.
1–2
TMS562A MPC8260ITR Microprocessor Support
Getting Started
8260ITR_SNG Support
EA V Bit. The EAV bit of the Bus Configuration Register (BCR) is required to be
set to 1 for correct disassembly. In this case, the Bank select signals are not
driven on the address bus. During READ and WRITE commands to SDRAM
devices, the full address is driven on bus address lines. Therefore, when the EAV
bit is set to 1, the full address is valid at PSDCAS~ asserted with PSDRAS~
deasserted for SDRAM accesses.
Memory Image Mode. In Memory Image Mode, NonMemory Image Cycles are
shown:
Fetches/Reads as (READ)
Writes as (WRITE)
SDRAM Address Multiplexing. The SDRAM address Multiplexing is not supported, for correct disassembly the Full address is required on the bus along with
the above requirement for the EAV bit.
Opcode Fetch/Opcode Read. The MPC8260 single mode microprocessor does not
provide a signal to distinguish between Data Read and Opcode Fetch. The
MPC8260ITR support adopts a heuristic approach and makes a reasonable
estimate when looking at the address values of a few sequences around the
current sequence. Yet, in some instances the support may fail, and then you need
to use the Marking Cycles option (see page 2–21).
Internal Cycles. Internal Cycles are detected, but not disassembled. These cycles
are shown as INTERNAL MEMORY CYCLE. Your input fields for entering the
start address of Internal Memory must be appropriate.
Branch Instructions. When the Trace Exception is enabled for branch instructions
the control goes to the Exception Handler. In that case the conditional branches
are not shown as taken (even if taken) and flushing is not done. You must use
Marking Cycles option for Flushing (see page 2–21).
Burst Cycles. There are no external signals available to indicate a burst transaction. The 8260ITR_SNG support adopts a heuristic approach and makes a
reasonable estimate by looking at the address values of a few sequences around
the current sequence to decide the burst. Yet, in some instances the support may
fail in doing so, and then you need to use the Marking Cycles option (see page
2-18).
Data for Memory Read and Write. There are no external signals to indicate the size
of the data in single 8260 mode. For memory reads and writes, all the data bytes
TMS562A MPC8260ITR Microprocessor Support
1–3
Getting Started
(on the data bus) starting from the address (indicated by Address group) are
shown as valid irrespective of the size of the data.
8260ITR_60X Support
Pipeline. If the following behavior is observed, the association of ADDRESS1 to
DATA 1 is handled correctly:
TRANSFER START
ADDRESS1
TRANSFER START
ADDRESS2
DATA 1
This behavior is basically a pipelined transaction. However, if ADDRESS1 is for
a READ cycle, then ADDRESS1 is associated with DATA 1 which is not
recommended. Such cycles are not observed normally and you may be requested
to mark DATA 1 again as Opcode (see Marking Cycles option on page 2–21).
Memory Image Mode. In Memory Image Mode, NonMemory Image Cycles are
shown in the following list when you set the Disassembly option Instruction
Fetch Indicator to TC[0:2] Bits:
Fetch as “–––Fetch Stream–––”
Reads as (READ)
Writes as (WRITE)
When a heuristic approach is chosen the 60x mode labels a NonMemory Image
cycles as “–––fetch Stream–––”.
1–4
TC[2:0] Encoding. When you set the disassembly option Instruction Fetch
Indicator to TC[2:0] Bits Fetches, Reads and Writes are distinguished by
encoding the TC[2:0] signals. The assumption is that each bus transaction has the
corresponding TC bits valid throughout the transaction.
Opcode Fetch/Opcode Read. Fetch is based on TC encoding or a Heuristic
approach. When a heuristic approach is selected, the MPC8260ITR support
makes a reasonable estimate for the address values of a few sequences around the
current sequence. Yet, in some instances the support may fail, and then you need
to use the Marking Cycles option on page 2–21.
Alternate Master Cycles. Alternative bus master transactions are acquired by the
MPC8260ITR support. The disassembler can distinguish between the
MPC8260ITR cycle and the alternate master cycle by looking at a qualified Bus
Grant. Alternate Cycles are not disassembled but shown as ALTERNATE
MASTER CYCLE.
TMS562A MPC8260ITR Microprocessor Support
Getting Started
The Alternate Master operates under the following assumptions:
H The data and address buses can only have one master. If a master owns the
address bus then the same master also owns the data bus. However, the
period the buses are granted may differ due to split bus transactions or
pipelining. In another words, if the BG~ and DBG~ signals are for the same
alternate master and not a different alternate master then the buses must be
granted to the requesting device.
H The arbiter type (external or internal) is determined at the time of system
reset and will not change dynamically during program execution. This means
that if the arbiter is configured as internal then BG~ and DBG~ signals are
the output signals from the 8260 microprocessor throughout the execution.
The signals BG~ and DBG~ are the inputs if the arbiter is external.
H If an alternate device asks for the bus (data / address) ownership and the
current master grants it, the alternate device becomes the bus master in the
next cycle. The alternate device continues to be the owner but for only one
bus transaction. If the alternate device wants to be the master again then it
must get bus grants from the original master again.
H If the BG~ is asserted before TS~ the address bus must be granted. This
means that alternate master cycles must be BG~ (qualified) for the TS~ to
grant the address bus to the requesting device. If there is a TS~ signal
without a BG~ signal (qualified) assertion then the following cycle belongs
to the original master. In the latter case when the address bus is not granted,
the data bus is also assumed to belong to the original master.
Internal Cycles. Internal Cycles are detected but not disassembled. Those cycles
are shown as INTERNAL MEMORY CYCLE. You must enter the appropriate
input in the field for the start address of Internal Memory.
Write Cycles Data. ITR operates with the assumption that Write cycles Data is
valid with ALE true, therefore, the corresponding address is valid.
Functionality Not Supported
Interrupt Signals
Not all interrupt signals are acquired by the TMS562A support software. The
interrupt signals that are acquired can be identified by the TMS562A support
software by looking at the address that is displayed for the interrupt service.
CPM Cycles
TMS562A MPC8260ITR Microprocessor Support
The communication processor module (CPM) is not supported.
1–5
Getting Started
DMA Cycles
UPM Cycles
Local Bus
Address Retry Cycles
Transfer Error Cycles
Features Not Tested
Exceptions
SDMA/IDMA cycles are not supported. DMA cycles are shown as ALTERNATE
MASTER CYCLE.
UPM cycles are not supported.
Only the 60x Compatible bus mode is supported. The local bus of the processor
is not supported.
Address Retry cycles are not supported.
Transfer Error cycles are not supported. However, some specific errors can be
detected based on available information: Bus Monitor Timeout error (using the
Time Stamp information), and Write protect error (by locating the address falling
in the memory region defined as read-only) etc.
All exceptions not tested (for both 8260ITR_60X and 8260ITR_SNG).
Symbol Table
8260ITR_60X
Setup
8260ITR_SNG Setup
The symbol table was checked for correct display only. Evaluation of the ability
to trigger using the symbols was not performed (for both 8260ITR_60X and
8260ITR_SNG).
Memory. Memory with 8, 16, 32 PortWidths
Little Endian Mode. PPC Little Endian Mode
ITR. Internal Trace Reconstruction (ITR)
Memory. Memory with 8, 16, 32 PortWidths (tested only through reference
memory editing)
Little Endian Mode. PPC Little Endian Mode (tested only through reference
memory editing)
ITR. Internal Trace Reconstruction (ITR) has been tested with only Assembly
Level Language source code and not with High Level Language.
1–6
TMS562A MPC8260ITR Microprocessor Support
Standard Accessories
Options
Getting Started
Memory Type. Only SDRAM and SRAM have been tested. DRAM is not tested.
The TMS562A Support is shipped with the following standard accessories:
H TMS562A Support SW Disk includes:
8260ITR_60X for the 60x Compatible Bus support
8260ITR_SNG
H TMS562A Support Instruction Manual
The following option is available when ordering the TMS562A Support:
H Option 21–Add P6434 Mass-Termination Probes
for the Single 8260 support
Connecting the Logic Analyzer to a System Under Test
You can use channel probes, clock probes, and leadsets with a commercial test
clip (or adapter) to make connections between the logic analyzer and your system
under test.
To connect the probes to MPC8260ITR signals in the system under test using a
test clip, follow these steps:
1. Power off your system under test. It is not necessary to power off the logic
analyzer.
CAUTION. To prevent static damage, handle the microprocessor, the probes, and
the logic analyzer module only in a static-free environment. Static discharge can
damage these components.
Always wear a grounding wrist strap, heel strap, or similar device while
handling the microprocessor.
2. To discharge your stored static electricity, touch the ground connector located
on the back of the logic analyzer. If you are using a test clip, touch any of the
ground pins on the clip to discharge stored static electricity from the test clip.
TMS562A MPC8260ITR Microprocessor Support
1–7
Getting Started
CAUTION. To prevent permanent damage to the pins on the microprocessor place
the system under test on a horizontal surface before connecting the test clip.
3. Place the system under test on a horizontal, static-free surface.
4. Use Table 5–5 through Table 5–20 starting on page 5–5 to connect the
channel probes to MPC8260ITR signal pins on the test clip or in the system
under test.
5. Use leadsets to connect at least one ground lead from each channel probe and
the ground lead from each clock probe to ground pins on your test clip.
1–8
TMS562A MPC8260ITR Microprocessor Support
Operating Basics
Setting Up the Support
This section provides information on how to set up the support. The information
gives an overview of channel groups definitions, support package setups, and
clocking options.
The information in this section is specific to the operations and functions of the
TMS562A MPC8260ITR support on any Tektronix logic analyzer for which it
can be purchased.
Before you acquire and display disassembled data, you need to load the support
and specify the setups for clocking and triggering as described in the information
on basic operations. The support provides default values for each of these setups,
but you can change them as needed.
Installing the Support Software
NOTE. Before you install any software, it is recommended that you verify that the
microprocessor support software is compatible with the logic analyzer software.
To install the TMS562A software on your Tektronix logic analyzer, follow these
steps:
1. Insert the floppy disk in the disk drive.
2. Click the Windows Start button, point to Settings, and click Control Panel.
3. In the Control Panel window, double-click Add/Remove Programs.
4. Follow the instructions on the screen for installing the software from the
floppy disk.
To remove or uninstall software, close all windows, and then follow the above
instructions and select Uninstall.
TMS562A MPC8260ITR Microprocessor Support
2–1
Setting Up the Support
Channel Group Definitions
The software automatically defines channel groups for the support. The channel
groups for the TMS562A support is listed in the following tables and displayed
in this order:
8260ITR_SNG support
Address Hexadecimal
High_Data Hexadecimal
Low_Data Hexadecimal
TraceAddr Hexadecimal (Synthesized Group)
Mnemonics None (Disassembly text generated by
Control Symbol
PortWidth Hexadecimal (Synthesized Group)
Misc OFF
Default display radix
PDL)
8260ITR_60X support Default display radix
Address Hexadecimal
High_Data Hexadecimal
Low_Data Hexadecimal
Trace Address Hexadecimal (Synthesized group)ББББББ
2–2
Mnemonics None (Disassembly text generated by
PDL)
ControlÁ Symbolic
Tsize Symbolic
TransferTypeÁÁ Hexadecimal
TCÁ Hexadecimal
Misc OFF
The channel group tables begin on page 5–1.
TMS562A MPC8260ITR Microprocessor Support
Support Package Setups
The TMS562A software installs MPC8260ITR support package setup file.
Setting Up the Support
8260ITR_60X Setup
8260ITR_SNG Setup
This setup provides disassembly support for an alternate master, for example, an
L2 cache, an ASIC DMA, a high-end PowerPC processor, or an MPC8260ITR
microprocessor. Signals are displayed as they appear electrically on the front side
bus.
This setup provides disassembly support for a single MPC8260ITR bus mode.
Signals are displayed as they appear electrically on the front side bus.
TMS562A MPC8260ITR Microprocessor Support
2–3
Setting Up the Support
Clocking
This section provides information on clocking options for the MPC8260ITR
support.
Custom Clocking
Clocking Options
A special clocking program is loaded to the module every time you load the
MPC8260ITR support. This special clocking is called Custom.
When Custom is selected, the Custom Clocking Options menu has the following
subtitles added:
H 8260ITR_60X Microprocessor Clocking Support
H 8260ITR_SNG Microprocessor Clocking Support
The TMS562A support offers a microprocessor-specific clocking mode for the
MPC8260ITR microprocessor. This clocking mode is the default selection
whenever you load the MPC8260ITR support.
Disassembly is not correct when using the Internal or External clocking modes.
Information in your logic analyzer online help describes how to use these clock
selections for general-purpose analysis.
Setup and Hold Time. You can change the Setup and Hold time window of all the
signal groups. The default Setup time is 2.5 ns and the Hold time is 0 ns. The
user defined Setup and Hold has precedence over default Setup and Hold times.
2–4
TMS562A MPC8260ITR Microprocessor Support
Signal Acquisition
Setting Up the Support
The following section shows timing diagrams and tables that list details about
how you acquire the relevant address, data, and control signals from various
memory types.
Figures 2–1 shows bus timing for the 8260ITR_60X mode.
CLKIN
ADDR
DATA
BG
TS
ALE
DBG
PSDVAL
AACK
Address 1 Address 2
D0 D0
ABCD E
Figure 2–1: Bus timing for 8260ITR_60X mode
TMS562A MPC8260ITR Microprocessor Support
2–5
Setting Up the Support
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8260ITR_60X Mode. The Custom Clock is the rising edge of CLKIN Clock.
Table 2–1 lists the acquisition of signals for 8260ITR_60X mode.
H Sample points:
BUS_GRANT =
{”BG~”,”DBG~”,”ABB~/IRQ2~”,”DBB~/IRQ3~”,”ARTRY~”};
TS_ATRIB = {”TS~”, ”TBST~”, ”TSIZ0”, ”TSIZ1”, ”TSIZ2”,”TSIZ3”,
BNKSEL0/TC0/AP1/MODCK1~”,
”BNKSEL1/TC1/AP2/MODCK2~”,
“BNKSEL2/TC2/AP3/MODCK3~”, ”TT0”, ”TT1”, ”TT2”,
”TT3”, ”TT4”, ,}
H Master sample points:
Master sample_pt M = {”PSDA10/PGPL0”, ”HRESET~”, ”SRESET~”,
”PSDAMUX/PGPL5”, ”L2_HIT~/IRQ4~”, ”CS3~”, ”CS1~”, ”CS0~”,
LOGA7, LOGA6, LOGA5, LOGA4, LOGA3, LOGA2, LOGA1, LOGA0,
LOGE7, LOGE6, LOGE5, LOGE4, LOGE3, LOGE2, LOGE1, LOGE0,
LOGD7, LOGD6, LOGD5, LOGD4, LOGD3, LOGD2, LOGD1, LOGD0,
”PSDVAL~”, ”TA~”, ”BCTL0~”, ”AACK~”, ”BR~”}
T able 2–1: Signal acquisition for 8260ITR_60X mode
2–6
Qualifiers
BG~
ÁÁ
ÁÁ
ÁÁ
TS~
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ALE
ÁÁ
ÁÁ
= Low
= Low
= High
Operation
Sample BUS_GRANT and
Master
Á
Á
Á
БББББББ
БББББББ
БББББББ
Sample TS_A TRIB and Master
Á
Á
Á
Á
Á
БББББББ
БББББББ
БББББББ
БББББББ
БББББББ
Master
Á
Á
БББББББ
БББББББ
Signals
BG~, DBG~, ABB~/IRQ2~, DBB~/IRQ3~, ARTRY~
PSDA10/PGPL0, HRESET~, SRESET~, PSDAMUX/PGPL5,
БББББББББББББББ
L2_HIT~/IRQ4~, CS3~, CS1~, CS0~, A[0–26], D[0–31],
БББББББББББББББ
D[32–63],
БББББББББББББББ
BADDR[27–31], PSDVAL~, T A~, BCTL0~, AACK~, BR~
TS~, TBST~, TSIZ0, TSIZ1, TSIZ2, TISZ3,
BNKSEL0/TC0/AP1/MODCK1~, BNKSEL1/TC1/AP2/MODCK2~,
БББББББББББББББ
BNKSEL2/TC2/AP3/MODCK3~,
БББББББББББББББ
TT0, TT1, TT2, TT3, TT4PSDA10/PGPL0, HRESET~, SRESET~,
БББББББББББББББ
PSDAMUX/PGPL5,
L2_HIT~/IRQ4~, CS3~, CS1~, CS0~, A[0–26], D[0–31],
БББББББББББББББ
D[32–63], BADDR[27–31], PSDV AL~, TA~, BCTL0~, AACK~,
БББББББББББББББ
BR~
PSDA10/PGPL0, HRESET~, SRESET~, PSDAMUX/PGPL5,
БББББББББББББББ
L2_HIT~/IRQ4~, CS3~, CS1~, CS0~, A[0–26], D[0–31],
D[32–63], BADDR[27–31], PSDV AL~, TA~, BCTL0~, AACK~,
БББББББББББББББ
BR~
TMS562A MPC8260ITR Microprocessor Support
Position
Position A
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Position B
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Position C
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T able 2–1: Signal acquisition for 8260ITR_60X mode (Cont.)
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Setting Up the Support
Qualifiers
DBG~
ÁÁÁ
ÁÁÁ
ÁÁÁ
PSDVAL~
ÁÁÁ
ÁÁÁ
ÁÁÁ
= Low
Á
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= Low
Á
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Á
Operation
Sample TS_ATRIB and
БББББББ
BUS_GRANT
БББББББ
БББББББ
Master
БББББББ
БББББББ
БББББББ
Figures 2–2 shows that at the raising edge of the clock and on
PSDCAS~/PGPL3, asserted and POE~/PSDRAS~/PGPL2 deasserted, ADDR is
logged in. Finally at the raising edge of the clock and on PSDVAL~ assertion the
data is sampled and master strobed.
CLKIN
ADDRESS
Signals
TS~, TBST~, TSIZ0, TSIZ1, TSIZ2, TISZ3,
БББББББББББББББ
BNKSEL0/TC0/AP1/MODCK1~, BNKSEL1/TC1/AP2/MODCK2~,
BNKSEL2/TC2/AP3/MODCK3~,
БББББББББББББББ
TT0, TT1, TT2, TT3, TT4BG~,
БББББББББББББББ
DBG~, ABB~/IRQ2~, DBB~/IRQ3~, ARTRY~
PSDA10/PGPL0, HRESET~, SRESET~, PSDAMUX/PGPL5,
БББББББББББББББ
L2_HIT~/IRQ4~,
БББББББББББББББ
CS3~, CS1~, CS0~, A[0–26], D[0–31], D[32–63], BADDR[27–31],
БББББББББББББББ
PSDV AL~, TA~, BCTL0~, AACK~, BR~
Position
Position D
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Position E
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POE/PSDRAS/PGPL2
PSDCAS/PGPL3
DATA
PSDVAL
PSDWE/PGPL1
BCTL0
Figure 2–2: Bus timing for 8260 single mode of SDRAM memory type
Login Address (Login Strobe=ADDR)
Master (Master Strobe=M)
A
Note: PSDWE~indicates whether the transaction is read or write.
B
TMS562A MPC8260ITR Microprocessor Support
2–7
Setting Up the Support
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8260ITR_SNG Mode (SDRAM Acquisition). The Custom Clock is the rising edge of
CLKIN Clock. Table 2–2 lists the acquisition of signals from SDRAM.
H Sample points:
ADDR = {PSDCAS~/PGPL3, POE~/PSDRAS~/PGPL2, A3:7–0, A2:7–0,
A1:7–0, A0:7–0}
H Master sample points:
Master sample_pt M = {Master sample points include all other signals except
those in ADDR sample point}
T able 2–2: Signal acquisition from SDRAM
Qualifiers
PSDCAS~
ÁÁ
& PSDRAS~
PSDVAL~
ÁÁ
ÁÁ
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= Low
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= High
= Low
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Operation
Sample ADDR
ÁÁÁÁ
Master
ÁÁÁÁ
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ÁÁÁÁ
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ÁÁÁÁ
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ÁÁÁÁ
NON-SDRAM Acquisition. The Custom Clock is the rising edge of the CLKIN
Clock. Table 2–3 lists signal acquisition from nonSDRAM.
Signal
PSDCAS~/PGPL3, POE~/PSDRAS~/PGPL2,
ББББББББББББББББББ
A3:7–0, A2:7–0, A1:7–0, A0:7–0
PSDCAS~/PGPL3, POE~/PSDRAS~/PGPL2,
ББББББББББББББББББ
A3:7–0, A2:7–0, A1:7–0, A0:7–0CLKIN,
PSDA10/PGPL0, HRESET~, SRESET~, PSDAMUX/PGPL5,
ББББББББББББББББББ
L2_HIT~/IRQ4~, CS3~, CS1~, CS0~, BR~,
ББББББББББББББББББ
BNKSEL0/TC0/AP1/MODCK1~,
ББББББББББББББББББ
BNKSEL1/TC1/AP2/MODCK2~,
BNKSEL2/TC2/AP3/MODCK3~,
ББББББББББББББББББ
TT0, TT1, TT2, TT3, TT4, TBST~, TSIZ0, TSIZ1, TSIZ2,TSIZ3TS~,
ББББББББББББББББББ
ALE, PSDVAL~, AACK~, AR TR Y~, DBB~/IRQ3~, BCTL0~, TA~,
ББББББББББББББББББ
PSDWE~/PGPL1, TEA~A[0–31], D[0–31], D[32–63]
Position
Position A
ÁÁ
Position B
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2–8
TMS562A MPC8260ITR Microprocessor Support
Setting Up the Support
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Figure 2–3 timing waveforms show when the address, data and other signals are
logged in.
The login strobe:
ADDR = {”PSDCAS~/PGPL3”, ”POE~/PSDRAS~/PGPL2”, A3: 7–0,A2:
7–0,A1: 7–0,A0: 7–0};
The Master strobe M includes all other signals except the one in ADDR.
In this case at the rising edge of the clock and on PSDVAL~ assertion, all the
signals are sampled and master strobed.
CLKIN
ADDRESS
DATA
PSDVAL
PSDWE/PGPL1
BCTL0
Figure 2–3: Bus timing for 8260 single mode of nonSDRAM access
T able 2–3: Signal acquisition from nonSDRAM
Qualifiers
PSDVAL~
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
TMS562A MPC8260ITR Microprocessor Support
= Low
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
Operation
Sample ADDR and
ÁÁÁÁ
Master
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Login Address (Login Strobe=ADDR)
and a master strobed (Master Strobe=M)
Note: BCTL0~ indicates whether the transaction is read or write.
Signal
PSDCAS~/PGPL3, POE~/PSDRAS~/PGPL2,
БББББББББББББББББ
A3:7–0, A2:7–0, A1:7–0, A0:7–0CLKIN,
PSDA10/PGPL0, HRESET~, SRESET~, PSDAMUX/PGPL5,
БББББББББББББББББ
L2_HIT~/IRQ4~, CS3~, CS1~, CS0~, BR~,
БББББББББББББББББ
BNKSEL0/TC0/AP1/MODCK1~
BNKSEL1/TC1/AP2/MODCK2~
БББББББББББББББББ
BNKSEL2/TC2/AP3/MODCK3~
БББББББББББББББББ
TT0, TT1, TT2, TT3, TT4, TBST~, TSIZ0, TSIZ1, TSIZ2,TSIZ3TS~,
БББББББББББББББББ
ALE, PSDVAL~, AACK~, ABB~/IRQ2~, AR TR Y~, DBB~/IRQ3~, BCTL0~,
TA~, PSDWE~/PGPL1, TEA~A[0–31], D[0–31], D[32–63]
БББББББББББББББББ
A
Position
Position A
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2–9
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