Instruction Manual
TMS 545A
PPC7400ITR Microprocessor Support
071-0797-00
Warning
The servicing instructions are for use by qualified
personnel only. To avoid personal injury, do not
perform any servicing unless you are qualified to
do so. Refer to all safety summaries prior to
performing service.
www.tektronix.com
Copyright © T ektronix, Inc. All rights reserved. Licensed software products are owned by Tektronix or its suppliers and
are protected by United States copyright laws and international treaty provisions.
Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the
Rights in T echnical Data and Computer Software clause at DFARS 252.227-7013, or subparagraphs (c)(1) and (2) of the
Commercial Computer Software – Restricted Rights clause at F AR 52.227-19, as applicable.
T ektronix products are covered by U.S. and foreign patents, issued and pending. Information in this publication supercedes
that in all previously published material. Specifications and price change privileges reserved.
T ektronix, Inc., P.O. Box 500, Beaverton, OR 97077
TEKTRONIX and TEK are registered trademarks of T ektronix, Inc.
SOFTWARE WARRANTY
T ektronix warrants that the media on which this software product is furnished and the encoding of the programs on
the media will be free from defects in materials and workmanship for a period of three (3) months from the date of
shipment. If a medium or encoding proves defective during the warranty period, T ektronix will provide a
replacement in exchange for the defective medium. Except as to the media on which this software product is
furnished, this software product is provided “as is” without warranty of any kind, either express or implied.
T ektronix does not warrant that the functions contained in this software product will meet Customer’s
requirements or that the operation of the programs will be uninterrupted or error-free.
In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration
of the warranty period. If T ektronix is unable to provide a replacement that is free from defects in materials and
workmanship within a reasonable time thereafter, Customer may terminate the license for this software product
and return this software product and any associated materials for credit or refund.
THIS WARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER WARRANTIES, EXPRESS
OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’
RESPONSIBILITY TO REPLACE DEFECTIVE MEDIA OR REFUND CUSTOMER’S PAYMENT IS
THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS
WARRANTY. TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT,
SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER
TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH
DAMAGES.
HARDWARE WARRANTY
T ektronix warrants that the products that it manufactures and sells will be free from defects in materials and
workmanship for a period of one (1) year from the date of shipment. If a product proves defective during this
warranty period, T ektronix, at its option, either will repair the defective product without charge for parts and labor,
or will provide a replacement in exchange for the defective product.
In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration
of the warranty period and make suitable arrangements for the performance of service. Customer shall be
responsible for packaging and shipping the defective product to the service center designated by T ektronix, with
shipping charges prepaid. Tektronix shall pay for the return of the product to Customer if the shipment is to a
location within the country in which the T ektronix service center is located. Customer shall be responsible for
paying all shipping charges, duties, taxes, and any other charges for products returned to any other locations.
This warranty shall not apply to any defect, failure or damage caused by improper use or improper or inadequate
maintenance and care. T ektronix shall not be obligated to furnish service under this warranty a) to repair damage
resulting from attempts by personnel other than T ektronix representatives to install, repair or service the product;
b) to repair damage resulting from improper use or connection to incompatible equipment; c) to repair any
damage or malfunction caused by the use of non-T ektronix supplies; or d) to service a product that has been
modified or integrated with other products when the effect of such modification or integration increases the time
or difficulty of servicing the product.
THIS WARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER WARRANTIES, EXPRESS
OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’
RESPONSIBILITY TO REPAIR OR REPLACE DEFECTIVE PRODUCTS IS THE SOLE AND
EXCLUSIVE REMEDY PROVIDED TO THE CUST OMER FOR BREACH OF THIS WARRANTY.
TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT , SPECIAL,
INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER TEKTRONIX OR
THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.
Table of Contents
Getting Started
Operating Basics
General Safety Summary v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preface vii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Manual Conventions vii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Analyzer Documentation viii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contacting T ektronix ix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Support Package Description 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Options 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Analyzer Software Compatibility 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Analyzer Configuration 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Requirements and Restrictions 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Display Format 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functionality Not Supported 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Assignments 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU To Mictor Connections 1–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Charts 1–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Up the Support 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Group Definitions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocking 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocking Options 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Custom Clocking 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Symbols 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Range Symbols 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acquiring and Viewing Disassembled Data 2–9. . . . . . . . . . . . . . . . . . . . .
Acquiring Data 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing Disassembled Data 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Display Format 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Display Format 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Flow Display Format 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subroutine Display Format 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Changing How Data is Displayed 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optional Display Selections 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Marking Cycles 2–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Displaying Exception Labels 2–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disassembly Display Options 2–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Micro Specific Fields 2–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Trace Reconstruction (ITR) 2–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing an Example of Disassembled Data 2–28. . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS 545A PPC7400ITR Microprocessor Support
i
Table of Contents
Specifications
Replaceable Parts List
Index
ii
TMS 545A PPC7400ITR Microprocessor Support
List of Figures
Table of Contents
Figure 1–1: Pin assignments for a Mictor connector
(component side) 1–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2–1: PPC 7400/PPC 740/750 support bus timing diagram 2–4. . .
Figure 2–2: Example of the hardware display format 2–13. . . . . . . . . . . . .
Figure 2–3: Listing window 2–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2–4: Display showing Fetch Stream 2–27. . . . . . . . . . . . . . . . . . . . . .
Figure 2–5: Display showing Memory Image 2–27. . . . . . . . . . . . . . . . . . . .
TMS 545A PPC7400ITR Microprocessor Support
iii
Table of Contents
List of Tables
Table 1–1: TLA Address group channel assignments 1–4. . . . . . . . . . . . .
Table 1–2: TLA Hi_Data group channel assignments 1–5. . . . . . . . . . . .
Table 1–3: TLA Lo_Data group channel assignments 1–6. . . . . . . . . . . .
Table 1–4: TLA Control group channel assignments 1–7. . . . . . . . . . . . .
Table 1–5: TLA Transfer group channel assignments 1–8. . . . . . . . . . . .
Table 1–6: TLA Tsiz group channel assignments 1–8. . . . . . . . . . . . . . . .
Table 1–7: TLA Misc group channel assignments 1–8. . . . . . . . . . . . . . . .
Table 1–8: Clock channel assignments 1–9. . . . . . . . . . . . . . . . . . . . . . . . .
Table 1–9: TLA CPU to Mictor connections for Mictor A pins 1–11. . . . .
Table 1–10: TLA CPU to Mictor connections for Mictor C pins 1–12. . . .
Table 1–11: CPU to Mictor connections for Mictor D pins 1–13. . . . . . . .
Table 1–12: TLA CPU to Mictor connections for Mictor E pins 1–15. . . .
Table 1–13: Clock channels 1–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1–14: Qualifier channels 1–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1–15: Address channels 1–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1–16: Data channels 1–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1–17: Control channels 1–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1–18: Control channels 1–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1–19: Extended channels 1–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2–1: PPC7400ITR_Transfer group symbol table definitions 2–5. .
Table 2–2: PPC7400ITR_Tsiz group symbol table definitions 2–5. . . . . .
Table 2–3: PPC7400ITR_Ctrl Control group symbol table
definitions 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2–4: Description of special characters in the display 2–10. . . . . . . .
Table 2–5: Cycle type labels for Address sequences and definitions 2–10.
Table 2–6: Cycle type labels for Data sequences and definitions 2–11. . . .
Table 2–7: Cycle type labels for ARTRY, DRTRY, and Data
Error cycles 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2–8: General cycle type labels definitions 2–12. . . . . . . . . . . . . . . . .
Table 2–9: Mark selections and definitions 2–17. . . . . . . . . . . . . . . . . . . . .
Table 2–10: Interrupt and exception labels 2–19. . . . . . . . . . . . . . . . . . . . .
Table 2–11: TLA disassembly display options 2–20. . . . . . . . . . . . . . . . . . .
Table 3–1: Electrical specifications 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
TMS 545A PPC7400ITR Microprocessor Support
General Safety Summary
Review the following safety precautions to avoid injury and prevent damage to
this product or any products connected to it. To avoid potential hazards, use this
product only as specified.
Only qualified personnel should perform service procedures.
While using this product, you may need to access other parts of the system. Read
the General Safety Summary in other system manuals for warnings and cautions
related to operating the system.
To Avoid Fire or Personal Injury
Connect and Disconnect Properly . Do not connect or disconnect probes or test
leads while they are connected to a voltage source.
Ground the Product. This product is grounded through the grounding conductor
of the power cord. To avoid electric shock, the grounding conductor must be
connected to earth ground. Before making connections to the input or output
terminals of the product, ensure that the product is properly grounded.
Observe All Terminal Ratings. To avoid fire or shock hazard, observe all ratings
and marking on the product. Consult the product manual for further ratings
information before making connections to the product.
Do Not Operate Without Covers. Do not operate this product with covers or panels
removed.
Avoid Exposed Circuitry. Do not touch exposed connections and components
when power is present.
Do Not Operate With Suspected Failures. If you suspect there is damage to this
product, have it inspected by qualified service personnel.
Do Not Operate in Wet/Damp Conditions.
Do Not Operate in an Explosive Atmosphere.
Keep Product Surfaces Clean and Dry .
TMS 545A PPC7400ITR Microprocessor Support
v
General Safety Summary
Symbols and Terms
T erms in this Manual. These terms may appear in this manual:
WARNING. Warning statements identify conditions or practices that could result
in injury or loss of life.
CAUTION. Caution statements identify conditions or practices that could result in
damage to this product or other property.
T erms on the Product. These terms may appear on the product:
DANGER indicates an injury hazard immediately accessible as you read the
marking.
WARNING indicates an injury hazard not immediately accessible as you read the
marking.
CAUTION indicates a hazard to property including the product.
vi
TMS 545A PPC7400ITR Microprocessor Support
Preface
This instruction manual contains specific information about the TMS 545A
PPC7400ITR microprocessor support package and is part of a set of information
on how to operate this product on compatible Tektronix logic analyzers.
If you are familiar with operating TMS 545A PPC7400ITR microprocessor
support package on the logic analyzer for which the TMS 545A PPC7400ITR
support was purchased, you will probably only need this instruction manual to set
up and run the support.
If you are not familiar with operating microprocessor support packages, you will
need to supplement this instruction manual with information on basic operations
in your online help to set up and run the support.
Information on basic operations of PPC7400ITR microprocessor support package
is included with each product. Each logic analyzer includes basic information
that describes how to perform tasks common to support packages on that
platform. This information can be in the form of online help, an installation
manual, or a user manual.
This manual provides detailed information on the following topics:
Manual Conventions
H Connecting the logic analyzer to the system under test
H Setting up the logic analyzer to acquire data from the system under test
H Acquiring and viewing disassembled data
This manual uses the following conventions:
H The term “disassembler” refers to the software that disassembles bus cycles
into instruction mnemonics and cycle types.
H The phrase “information on basic operations” refers to online help, an
installation manual, or a user manual covering the basic operations of
PPC7400ITR microprocessor support.
H In the information on basic operations, the term “XXX” or “P54C” appearing
in field selections and file names must be replaced with PPC7400ITR. This
term is the name of the PPC7400ITR microprocessor in field selections and
file names you must use to operate the PPC7400ITR support.
H The term SUT (system under test) refers to the PPC7400ITR microprocessor-
based system from which data will be acquired.
TMS 545A PPC7400ITR Microprocessor Support
vii
Preface
H The term “HI module” refers to the module in the higher-numbered slot and
the term “LO module” refers to the module in the lower-numbered slot.
H PPC7400ITR refers to all supported variations of the PPC750 or PPC740
PPC7400 microprocessors unless otherwise noted.
H An underscore (_) following a signal name indicates an active low signal.
Logic Analyzer Documentation
A description of other documentation available for each type of Tektronix logic
analyzer is located in the user manual of the corresponding module. The manual
set provides the information necessary to install, operate, maintain, and service
the logic analyzer and associated products.
viii
TMS 545A PPC7400ITR Microprocessor Support
Contacting Tektronix
Preface
Phone 1-800-833-9200*
Address Tektronix, Inc.
Department or name (if known)
14200 SW Karl Braun Drive
P.O. Box 500
Beaverton, OR 97077
USA
Web site www.tektronix.com
Sales support 1-800-833-9200, select option 1*
Service support 1-800-833-9200, select option 2*
Technical support Email: support@tektronix.com
1-800-833-9200, select option 3*
1-503-627-2400
6:00 a.m. – 5:00 p.m. Pacific time
* This phone number is toll free in North America. After office hours, please leave a
voice mail message.
Outside North America, contact a Tektronix sales office or distributor; see the
Tektronix web site for a list of offices.
TMS 545A PPC7400ITR Microprocessor Support
ix
Preface
x
TMS 545A PPC7400ITR Microprocessor Support
Getting Started
Getting Started
This chapter contains information on the TMS 545A PPC7400ITR microprocessor support and information on connecting your logic analyzer to your system
under test.
Support Package Description
The TMS 545A PPC7400ITR microprocessor support package disassembled data
from systems based on the PPC7400ITR microprocessor.
The TMS 545A Support is comprised of the following:
H TMS 545A PPC7400ITR Support SW Disk
H TMS 545A PPC7400ITR microprocessor Support Instruction Manual
Refer to information on basic operations to determine how many modules and
probes your logic analyzer needs to meet the minimum channel requirements for
the TMS 545A PPC7400ITR microprocessor support.
To use this support efficiently, you need the items listed in the information on
basic operations as well as:
H MPC 750 RISC Microprocessor User’s Manual, 1997
H PowerPC Max Microprocessor Implementation Definition Book 1V Version
2.0, Motorola, 1998.
Options
The following options are available when ordering the TMS 545A Support:
H Option 21 (adds 4 P6434 Probes)
Logic Analyzer Software Compatibility
The label on the PPC7400ITR microprocessor support floppy disk states with
which version of logic analyzer software the support is compatible.
Logic Analyzer Configuration
For use with a logic analyzer, the TMS 545A support requires a minimum of one
136-channel module.
TMS 545A PPC7400ITR Microprocessor Support
1–1
Getting Started
Requirements and Restrictions
Review electrical specifications in the Specifications chapter in this manual as
they pertain to your system under test, as well as the following descriptions of
other PPC7400ITR support requirements and restrictions.
Hardware Reset. If a hardware reset occurs in your PPC7400ITR microprocessor
system during an acquisition, the disassembler might acquire an invalid sample.
System Clock Rate. The PPC7400ITR microprocessor support can acquire data
from the PPC7400ITR microprocessor operating at speeds of up to 133 MHz.
The PPC7400ITR microprocessor support has been tested to 100 MHz.
Channel Groups. The channel groups required for clocking and disassembly are
the Address Group, Hi_Data Group, Lo_Data Group, Control Group, Transfer
Group, and Tsiz Group.
Timing Display Format
The channel group not required for clocking and disassembly is the Misc Group.
Disabling the Instruction Cache. To disassemble acquired data, you must disable
the internal instruction cache. Disabling the cache makes all instruction
prefetches visible on the bus so that they can be acquired and disassembled. To
see acquired data with the cache enabled, see Instruction Trace Reconstruction
on page 2–23.
Disabling the Data Cache. To display acquired data, you must disable the data
cache. Disabling the data cache makes visible on the bus all of the loads and
stores to memory, including data reads and writes, so that the software can
acquire and display them.
A Timing Display Format file is provided. It sets up the display to show the
following waveforms:
CLK, BR_, Address, TS_, ABB_, BG_, AACK_, ARTRY_, TBST_,
Hi_Data, Lo_Data, TA_, DBB_, DBG_, TEA_, DTI[1]/DRTRY_, Control,
Tsiz, Transfer.
1–2
NOTE. Address, Hi_Data, Lo_Data, Control, Tsiz, and Transfer are displayed in
bus form.
The method of selecting or restoring the Timing Display Format file is different
for each platform and will be ignored in this document.
TMS 545A PPC7400ITR Microprocessor Support
Functionality Not Supported
Interrupt Signals. Not all of the interrupt signals are acquired by the TMS 545A
support software. The interrupts that are acquired can be identified by the
TMS 545A support software by looking at the address that is displayed for the
interrupt service.
Microprocessor. The TMS 545A support acquires all the address and data cycles
on the bus and does not differentiate between potential master and alternate
master.
L2 cache. L2 cache transactions are not supported for the PPC7400ITR support.
Extra Acquisition Channels. Extra Acquisition Channels are not available on the
logic analyzer.
Getting Started
Alternate Bus Master. Alternate bus master transactions are not processed in the
disassembly.
Address Pipelining. If address pipelining continues for several sequences (those
longer than approximately 1 K), performance might be degraded when you scroll
data by entering a sequence number in the cursor field.
If address pipelining continues for additional sequences of 1 K or greater,
erroneous address and data association might occur. You can use the Mark Cycles
function to correct the interpretation of erroneous address and data association.
See Marking Cycles on page 2–16 for information on how to correct improper
address and data association.
TMS 545A PPC7400ITR Microprocessor Support
1–3
Getting Started
Channel Assignments
Channel assignments shown in Table 1–1 through Table 1–8 use the following
conventions:
H All signals are required by the support unless indicated otherwise.
H Channels are shown starting with the most significant bit (MSB) descending
to the least significant bit (LSB).
H Channel group assignments are for all modules unless otherwise noted.
H An underscore (_) following a signal name indicates an active low signal.
Table 1–1 shows the probe section and channel assignments for the Tektronix
logic analyzer (TLA) Address group and the PPC7400ITR microprocessor signal
to which each channel connects. By default, this channel group is displayed in
hexadecimal.
T able 1–1: TLA Address group channel assignments
Bit order Section:channel PPC7400ITR signal name
31 A3:7 A0
30 A3:6 A1
29 A3:5 A2
28 A3:4 A3
27 A3:3 A4
26 A3:2 A5
25 A3:1 A6
24 A3:0 A7
23 A2:7 A8
22 A2:6 A9
21 A2:5 A10
20 A2:4 A11
19 A2:3 A12
18 A2:2 A13
17 A2:1 A14
16 A2:0 A15
15 A1:7 A16
14 A1:6 A17
13 A1:5 A18
12 A1:4 A19
11 A1:3 A20
1–4
TMS 545A PPC7400ITR Microprocessor Support
T able 1–1: TLA Address group channel assignments (cont.)
Bit order PPC7400ITR signal nameSection:channel
10 A1:2 A21
9 A1:1 A22
8 A1:0 A23
7 A0:7 A24
6 A0:6 A25
5 A0:5 A26
4 A0:4 A27
3 A0:3 A28
2 A0:2 A29
1 A0:1 A30
0 A0:0 A31
Getting Started
Table 1–2 shows the probe section and channel assignments for the TLA Hi_Data
group and the PPC7400ITR microprocessor signal to which each channel
connects. By default, this channel group is displayed in hexadecimal.
T able 1–2: TLA Hi_Data group channel assignments
Bit order Section:channel PPC7400ITR signal name
31 E3:7 D0
30 E3:6 D1
29 E3:5 D2
28 E3:4 D3
27 E3:3 D4
26 E3:2 D5
25 E3:1 D6
24 E3:0 D7
23 E2:7 D8
22 E2:6 D9
21 E2:5 D10
20 E2:4 D11
19 E2:3 D12
18 E2:2 D13
17 E2:1 D14
16 E2:0 D15
15 E1:7 D16
14 E1:6 D17
TMS 545A PPC7400ITR Microprocessor Support
1–5
Getting Started
T able 1–2: TLA Hi_Data group channel assignments (cont.)
Bit order PPC7400ITR signal nameSection:channel
13 E1:5 D18
12 E1:4 D19
11 E1:3 D20
10 E1:2 D21
9 E1:1 D22
8 E1:0 D23
7 E0:7 D24
6 E0:6 D25
5 E0:5 D26
4 E0:4 D27
3 E0:3 D28
2 E0:2 D29
1 E0:1 D30
0 E0:0 D31
Table 1–3 shows the probe section and channel assignments for the TLA
Lo_Data group and the PPC7400ITR microprocessor signal to which each
channel connects. By default, this channel group is displayed in hexadecimal.
T able 1–3: TLA Lo_Data group channel assignments
Bit order Section:channel PPC7400ITR signal name
31 D3:7 D32
30 D3:6 D33
29 D3:5 D34
28 D3:4 D35
27 D3:3 D36
26 D3:2 D37
25 D3:1 D38
24 D3:0 D39
23 D2:7 D40
22 D2:6 D41
21 D2:5 D42
20 D2:4 D43
19 D2:3 D44
18 D2:2 D45
17 D2:1 D46
1–6
TMS 545A PPC7400ITR Microprocessor Support
T able 1–3: TLA Lo_Data group channel assignments (cont.)
Bit order PPC7400ITR signal nameSection:channel
16 D2:0 D47
15 D1:7 D48
14 D1:6 D49
13 D1:5 D50
12 D1:4 D51
11 D1:3 D52
10 D1:2 D53
9 D1:1 D54
8 D1:0 D55
7 D0:7 D56
6 D0:6 D57
5 D0:5 D58
4 D0:4 D59
3 D0:3 D60
2 D0:2 D61
1 D0:1 D62
0 D0:0 D63
Getting Started
Table 1–4 shows the probe section and channel assignments for the TLA Control
group and the PPC7400ITR microprocessor signal to which each channel
connects. By default, this channel group is displayed as symbols.
T able 1–4: TLA Control group channel assignments
Bit order Section:channel PPC7400ITR signal name
10 C2:2 TS_
9 C3:4 BG_
8 C1:4 DBG_
7 C2:0 ARTRY_
5 C2:1 AACK_
4 Clock:1 TA_
3 Clock:0 TEA_
2 C2:4 ABB_
1 C0:4 DTI[O]
0 Clock:2 DBB_
TMS 545A PPC7400ITR Microprocessor Support
1–7
Getting Started
Table 1–5 shows the probe section and channel assignments for the TLA Transfer
group and the PPC7400ITR microprocessor signal to which each channel
connects. By default, this channel group is displayed as symbols.
T able 1–5: TLA Transfer group channel assignments
Bit order Section:channel PPC7400ITR signal name
5 C3:1 TT0
4 C0:7 TT1
3 C3:6 TT2
2 C3:7 TT3
1 C1:2 TT4
0 C1:7 WT_
Table 1–6 shows the probe section and channel assignments for the TLA Tsiz
group and the PPC7400ITR microprocessor signal to which each channel
connects. By default, this channel group is displayed in symbols.
T able 1–6: TLA Tsiz group channel assignments
Bit order Section:channel PPC7400ITR signal name
3 C3:3 TSIZ2
2 C2:7 TSIZ1
1 C2:6 TSIZ0
0 C3:2 TBST_
Table 1–7 shows the probe section and channel assignments for the TLA Misc
group and the PPC7400ITR microprocessor signal to which each channel
connects. By default, this channel group is not visible.
T able 1–7: TLA Misc group channel assignments
Bit order Section:channel PPC7400ITR signal name
2 Clock:3 CLK
1 C1:5 BR_
0 C0:5 GBL_
1–8
TMS 545A PPC7400ITR Microprocessor Support
Getting Started
Logic Analyzer. Extra channels that are not connected in the PPC7400ITR
support:
C1:3
C1:5
C0:5
NonIntrusive Acquisition. Acquiring microprocessor bus cycles will be nonintrusive to the system under test. That is, the PPC7400ITR support will not intercept,
modify, or present back signals to the system under test.
Acquisition Setup. The PPC7400ITR support will affect the logic analyzer setup
menus (and submenus) by modifying existing fields and adding micro-specific
fields.
On the logic analyzer, the PPC7400ITR support will add the selection
“PPC7400ITR” to the Load Support Package dialog box, under the File pulldown
menu. Once that “PPC7400ITR support” has been loaded, the “Custom” clocking
mode selection in the logic analyzer module Setup menu is also enabled.
Table 1–8 shows the probe section and channel assignments for the clock probes
(not part of any group), and the PPC7400ITR signal to which each channel
connects.
T able 1–8: Clock channel assignments
TLA
section & probe
CLK:3 CLK Clock
CLK:2 DBB_ Used as qualifier
CLK:1 TA_ Used as qualifier
CLK:0 TEA_ Used as qualifier
C2:0 ARTRY_ Used as qualifier
C2:1 AACK_ Used as qualifier
C2:2 TS_ Used as qualifier
C2:3 DTI[1]/DRTRY_* Used as qualifier
* This signal occurs as DTI[1] in 7400 and as DRTRY_ in 750
PPC7400ITR signal
name
Description
TMS 545A PPC7400ITR Microprocessor Support
1–9
Getting Started
CPU To Mictor Connections
To probe the microprocessor you will need to make connections between the
CPU and the Mictor pins of the P6434 Mass Termination Probe. Refer to the
P6434 Mass Termination Probe manual, Tektronix part number 070-9793-xx, for
more information on mechanical specifications. Table 1–9 through Table 1–11
show the CPU pin to Mictor pin connections.
Tektronix uses a counter clockwise pin assignment. Pin 1 is located at the top
left, and pin 2 is located directly below it. Pin 20 is located on the bottom right,
and pin 21 is located directly above it.
AMP uses an odd side-even side pin assignment. Pin 1 is located at the top left,
and pin-3 is located directly below it. Pin 2 is located on the top right, and pin 4
is located directly below it.
NOTE. When designing Mictor connectors into your SUT, always follow the
Tektronix pin assignment.
Tektronix Pinout AMP Pinout
Pin 1
Pin 19
Pin 38
Pin 20
Pin 1
Pin 37
Pin 2
Pin 38
Figure 1–1: Pin assignments for a Mictor connector (component side)
Please pay close attention to the caution below.
CAUTION. To protect the CPU and the inputs of the module, it is recommended
that a 180 W resistor is connected in series between each ball pad of the CPU
and each pin of the Mictor connector. The resistor must be no farther away from
the ball pad of the CPU than 1/2-inch.
1–10
TMS 545A PPC7400ITR Microprocessor Support
T able 1–9: TLA CPU to Mictor connections for Mictor A pins
Getting Started
Tektronix
Mictor A
pin number
1 1 NC NC NC
2 3 NC NC NC
3 5 TEA_ J1 H13
4 7 A0 A13 C16
5 9 A1 D2 E4
6 11 A2 H11 D13
7 13 A3 C1 F2
8 15 A4 B13 D14
9 17 A5 F2 G1
10 19 A6 C13 D15
11 21 A7 E5 E2
12 23 A8 D13 D16
13 25 A9 G7 D4
14 27 A10 F12 E13
15 29 A11 G3 G2
16 31 A12 G6 E15
17 33 A13 H2 H1
18 35 A14 E2 E16
19 37 A15 L3 H2
20 38 A31 L2 P1
21 36 A30 K2 J15
22 34 A29 K3 M1
23 32 A28 J6 H16
24 30 A27 J2 K2
25 28 A26 H3 G15
26 26 A25 M3 K1
27 24 A24 J7 G13
28 22 A23 F3 F4
29 20 A22 G2 F16
30 18 A21 E1 H3
31 16 A20 H7 F15
32 14 A19 J4 J2
33 12 A18 G4 F14
34 10 A17 L4 J1
35 8 A16 G5 F13
AMP
Mictor A
pin number
PPC7400ITR
signal name
PPC 7400/750
socket
PPC 740
socket
TMS 545A PPC7400ITR Microprocessor Support
1–11
Getting Started
T able 1–9: TLA CPU to Mictor connections for Mictor A pins (cont.)
Tektronix
Mictor A
pin number
36 6 TA_ F1 H14
37 4 NC NC NC
38 2 NC NC NC
39 39 GND NC NC
40 40 GND NC NC
41 41 GND NC NC
42 42 GND NC NC
43 43 GND NC NC
AMP
Mictor A
pin number
PPC7400ITR
signal name
PPC 7400/750
socket
PPC 740
socket
T able 1–10: TLA CPU to Mictor connections for Mictor C pins
Tektronix
Mictor C
pin number
1 1 NC
2 3 NC NC NC
3 5 CLK H9 C9
4 7 TT3 C12 C14
5 9 TT2 B12 B16
6 11 TEA_ J1 H13
7 13 BG_ H1 L1
8 15 TSIZ2 C9 B12
9 17 TBST_ A11 A14
10 19 TT0 C10 B13
11 21 NC
12 23 TSIZ1 B9 D10
13 25 TSIZ0 A9 A13
14 27 DBB_ K5 J14
15 29 ABB_ L7 K4
16 31 DTI[1]/DRTRY_* H6 G16
17 33 TS_ K7 J13
18 35 AACK_ N3 L2
19 37 ARTRY_ L6 J4
20 38 ARTRY_DATA_ L6 J4
AMP
Mictor C
pin number
PPC7400ITR signal
name
PPC 7400/750 PPC 740
NC
NC
NC
NC
1–12
TMS 545A PPC7400ITR Microprocessor Support
T able 1–10: TLA CPU to Mictor connections for Mictor C pins (cont.)
Getting Started
Tektronix
Mictor C
pin number
21 36 AACK_ N3 L2
22 34 TS_ K7 J13
23 32 DTI[1]/DRTRY_* H6 G16
24 30 DTI[0] D1 G4
25 28 GBL_ B1 F1
26 26 TA_ F1 H14
27 24 TT1 D11 A15
28 22 NC NC NC
29 20 HRESET_ B6 A7
30 18 TT4 F11 C15
31 16 SYSCLK H9 C9
32 14 DBG_ K1 N1
33 12 BR_ E7 B6
34 10 ARTRY_ L6 J4
35 8 WT C3 D2
36 6 NC NC NC
37 4 NC NC NC
38 2 NC NC NC
39 39 GND NC NC
40 40 GND NC NC
41 41 GND NC NC
42 42 GND NC NC
43 43 GND NC NC
* This signal occurs as DTI[1] in 7400 and as DRTRY_ in 750
AMP
Mictor C
pin number
PPC7400ITR signal
name
PPC 740PPC 7400/750
T able 1–11: CPU to Mictor connections for Mictor D pins
Tektronix
Mictor D
pin number
1 1 NC NC NC
2 3 NC NC NC
3 5 NC NC NC
AMP
Mictor D
pin number
TMS 545A PPC7400ITR Microprocessor Support
PPC7400ITR signal
name
PPC 7400/750 PPC 740
1–13
Getting Started
T able 1–11: CPU to Mictor connections for Mictor D pins (cont.)
Tektronix
Mictor D
pin number
4 7 DL0 M6 K13
5 9 DL1 P3 K15
6 11 DL2 N4 K16
7 13 DL3 N5 L16
8 15 DL4 R3 L15
9 17 DL5 M7 L13
10 19 DL6 T2 L14
11 21 DL7 N6 M16
12 23 DL8 U2 M15
13 25 DL9 N7 M13
14 27 DL10 P11 N16
15 29 DL11 V13 N15
16 31 DL12 U12 N13
17 33 DL13 P12 N14
18 35 DL14 T13 P16
19 37 DL15 W13 P15
20 38 DL31 W2 R4
21 36 DL30 U3 T3
22 34 DL29 V3 P4
23 32 DL28 R2 T2
24 30 DL27 N1 T1
25 28 DL26 U1 R3
26 26 DL25 V1 N4
27 24 DL24 P1 N3
28 22 DL23 T1 P3
29 20 DL22 V8 T13
30 18 DL21 V12 N12
31 16 DL20 U11 P13
32 14 DL19 T11 N10
33 12 DL18 W8 T14
34 10 DL17 V10 R14
35 8 DL16 U13 R16
36 6 DBB_ K5 J14
37 4 NC NC NC
38 2 NC NC NC
AMP
Mictor D
pin number
PPC7400ITR signal
name
PPC 740PPC 7400/750
1–14
TMS 545A PPC7400ITR Microprocessor Support
T able 1–11: CPU to Mictor connections for Mictor D pins (cont.)
Getting Started
Tektronix
Mictor D
pin number
39 39 GND NC NC
40 40 GND NC NC
41 41 GND NC NC
42 42 GND NC NC
43 43 GND NC NC
AMP
Mictor D
pin number
PPC7400ITR signal
name
PPC 740PPC 7400/750
T able 1–12: TLA CPU to Mictor connections for Mictor E pins
Tektronix
Mictor E
pin number
1 1 NC NA NA
2 3 NC NA NA
3 5 NC NC NC
4 7 DH0 W12 P14
5 9 DH1 W11 Y16
6 11 DH2 V11 R15
7 13 DH3 T9 T15
8 15 DH4 W10 R13
9 17 DH5 U9 R12
10 19 DH6 U10 P11
11 21 DH7 M11 N11
12 23 DH8 M9 R11
13 25 DH9 P8 T12
14 27 DH10 W7 T11
15 29 DH11 P9 R10
16 31 DH12 W9 P9
17 33 DH13 R10 N9
18 35 DH14 W6 T10
19 37 DH15 V7 V7
20 38 DH31 R5 T4
21 36 DH30 U4 T5
22 34 DH29 W3 N5
AMP
Mictor E
pin number
PPC7400ITR signal
name
PPC 7400/750 PPC 740
TMS 545A PPC7400ITR Microprocessor Support
1–15
Getting Started
T able 1–12: TLA CPU to Mictor connections for Mictor E pins (cont.)
Tektronix
Mictor E
pin number
23 32 DH28 V4 R5
24 30 DH27 V5 T6
25 28 DH26 P7 R6
26 26 DH25 W4 N6
27 24 DH24 U5 P6
28 22 DH23 W5 T7
29 20 DH22 U6 R7
30 18 DH21 R7 N7
31 16 DH20 U7 T8
32 14 DH19 T7 R8
33 12 DH18 V9 N8
34 10 DH17 U8 P8
35 8 DH16 V6 T9
36 6 NC
37 4 NC NC NC
38 2 NC NC NC
39 39 GND NC NC
40 40 GND NC NC
41 41 GND NC NC
42 42 GND NC NC
43 43 GND NC NC
AMP
Mictor E
pin number
PPC7400ITR signal
name
NC
PPC 740PPC 7400/750
NC
1–16
TMS 545A PPC7400ITR Microprocessor Support
Channel Charts
Getting Started
Tables 1–13 through 1–19 identify the signal names assigned to the acquisition
channel numbers on the logic analyzer.
T able 1–13: Clock channels
TLA clock
channel
CLK:3 CLK Rising M CLK
CLK:2 M DBB_
CLK:1 Qual M TA_
CLK:0 Qual M TEA_
CLK or Qual
Active CLK
edge
Login strobe
PPC7400ITR
signal name
Table 1–14 identifies the QUAL channel numbers on the logic analyzer.
T able 1–14: Qualifier channels
TLA qualifier
channel
QUAL:3 M
QUAL:2 M
QUAL:1 M
QUAL:0 M
Qual only Login strobe
PPC7400ITR
signal name
TMS 545A PPC7400ITR Microprocessor Support
1–17
Getting Started
T able 1–15: Address channels
TLA acquisition
channel
A3:7 LOGA7 M A0
A3:6 LOGA7 M A1
A3:5 LOGA7 M A2
A3:4 LOGA7 M A3
A3:3 LOGA6 M A4
A3:2 LOGA6 M A5
A3:1 LOGA6 M A6
A3:0 LOGA6 M A7
A2:7 LOGA5 M A8
A2:6 LOGA5 M A9
A2:5 LOGA5 M A10
A2:4 LOGA5 M A11
A2:3 LOGA4 M A12
A2:2 LOGA4 M A13
A2:1 LOGA4 M A14
A2:0 LOGA4 M A15
A1:7 LOGA3 M A16
A1:6 LOGA3 M A17
A1:5 LOGA3 M A18
A1:4 LOGA3 M A19
A1:3 LOGA2 M A20
A1:2 LOGA2 M A21
A1:1 LOGA2 M A22
A1:0 LOGA2 M A23
A0:7 LOGA1 M A24
A0:6 LOGA1 M A25
A0:5 LOGA1 M A26
A0:4 LOGA1 M A27
A0:3 LOGA0 M A28
A0:2 LOGA0 M A29
A0:1 LOGA0 M A30
A0:0 LOGA0 M A31
Login
group
Login
strobe
PPC7400ITR signal name
1–18
TMS 545A PPC7400ITR Microprocessor Support
T able 1–16: Data channels
Getting Started
TLA acquisition
channel
D3:7 LOGD7 M D32
D3:6 LOGD7 M D33
D3:5 LOGD7 M D34
D3:4 LOGD7 M D35
D3:3 LOGD6 M D36
D3:2 LOGD6 M D37
D3:1 LOGD6 M D38
D3:0 LOGD6 M D39
D2:7 LOGD5 M D40
D2:6 LOGD5 M D41
D2:5 LOGD5 M D42
D2:4 LOGD5 M D43
D2:3 LOGD4 M D44
D2:2 LOGD4 M D45
D2:1 LOGD4 M D46
D2:0 LOGD4 M D47
D1:7 LOGD3 M D48
D1:6 LOGD3 M D49
D1:5 LOGD3 M D50
D1:4 LOGD3 M D51
D1:3 LOGD2 M D52
D1:2 LOGD2 M D53
D1:1 LOGD2 M D54
D1:0 LOGD2 M D55
D0:7 LOGD1 M D56
D0:6 LOGD1 M D57
D0:5 LOGD1 M D58
D0:4 LOGD1 M D59
D0:3 LOGD0 M D60
D0:2 LOGD0 M D61
D0:1 LOGD0 M D62
D0:0 LOGD0 M D63
Login
group
Login
strobe
PPC7400ITR signal name
TMS 545A PPC7400ITR Microprocessor Support
1–19
Getting Started
T able 1–17: Control channels
TLA acquisition
channel
C3:7 LOGC7 M TT3
C3:6 LOGC6 M TT2
C3:5 LOGC5 M
C3:4 LOGC4 M BG_
C3:3 LOGC7 M TSIZ2
C3:2 LOGC6 M TBST_
C3:1 LOGC5 M TT0
C3:0 LOGC4 M
C2:7 LOGC7 M TSIZ1
C2:6 LOGC6 M TSIZ0
C2:5 LOGC5 M
C2:4 LOGC4 M ABB_
C2:3 LOGC7 M DTI[1]/DRTRY_*
C2:2 LOGC6 M TS_
C2:1 LOGC5 M AACK_
C2:0 LOGC4 M ARTRY_
C1:7 LOGC3 M WT_
C1:6 LOGC2 M ARTRY_1
C1:5 LOGC1 M BR_
C1:4 LOGC0 M DBG_
C1:3 LOGC3 M SYSCLK
C1:2 LOGC2 M TT4
C1:1 LOGC1 M HRESET_
C1:0 LOGC0 M
C0:7 LOGC3 M TT1
C0:6 LOGC2 M
C0:5 LOGC1 M GBL_
C0:4 LOGC0 M DTI[0]
C0:3 LOGC3 M
C0:2 LOGC2 M
C0:1 LOGC1 M
C0:0 LOGC0 M ARTRY_DATA_
* This signal occurs as DTI[1] in 7400 and as DRTRY_ in 750
Login
group
Login
strobe
PPC7400ITR signal name
1–20
TMS 545A PPC7400ITR Microprocessor Support
T able 1–18: Control channels
Getting Started
TLA acquisition
channel
C3:7 LOGC7 M TT3
C3:3 LOGC7 M TSIZ2
C2:7 LOGC7 M TSIZ1
C2:3 LOGC7 M DTI[1]/DRTRY_*
C3:6 LOGC6 M TT2
C3:2 LOGC6 M TBST_
C2:6 LOGC6 M TSIZ0
C2:2 LOGC6 M TS_
C3:5 LOGC5 M
C3:1 LOGC5 M TT0
C2:5 LOGC5 M
C2:1 LOGC5 M AACK_
C3:4 LOGC4 M BG_
C3:0 LOGC4 M
C2:4 LOGC4 M ABB_
C2:0 LOGC4 M ARTRY_
C1:7 LOGC3 M WT_
C1:3 LOGC3 M SYSCLK
C0:7 LOGC3 M TT1
C0:3 LOGC3 M
C1:6 LOGC2 M ARTRY_
C1:2 LOGC2 M TT4
C0:6 LOGC2 M
C0:2 LOGC2 M
C1:5 LOGC1 M BR_
C1:1 LOGC1 M HRESET_
C0:5 LOGC1 M GBL_
C0:1 LOGC1 M
C1:4 LOGC0 M DBG_
C1:0 LOGC0 M
C0:4 LOGC0 M DTI[0]
C0:0 LOGC0 M ARTRY_DATA_
* This signal occurs as DTI[1] in 7400 and as DRTRY_ in 750
Login
group
Login
strobe
PPC7400ITR signal name
TMS 545A PPC7400ITR Microprocessor Support
1–21
Getting Started
T able 1–19: Extended channels
TLA acquisition
channel
E3:7 LOGE7 M D0
E3:6 LOGE7 M D1
E3:5 LOGE7 M D2
E3:4 LOGE7 M D3
E3:3 LOGE6 M D4
E3:2 LOGE6 M D5
E3:1 LOGE6 M D6
E3:0 LOGE6 M D7
E2:7 LOGE5 M D8
E2:6 LOGE5 M D9
E2:5 LOGE5 M D10
E2:4 LOGE5 M D11
E2:3 LOGE4 M D12
E2:2 LOGE4 M D13
E2:1 LOGE4 M D14
E2:0 LOGE4 M D15
E1:7 LOGE3 M D16
E1:6 LOGE3 M D17
E1:5 LOGE3 M D18
E1:4 LOGE3 M D19
E1:3 LOGE2 M D20
E1:2 LOGE2 M D21
E1:1 LOGE2 M D22
E1:0 LOGE2 M D23
E0:7 LOGE1 M D24
E0:6 LOGE1 M D25
E0:5 LOGE1 M D26
E0:4 LOGE1 M D27
E0:3 LOGE0 M D28
E0:2 LOGE0 M D29
E0:1 LOGE0 M D30
E0:0 LOGE0 M D31
Login
group
Login
strobe
PPC7400ITR signal name
1–22
TMS 545A PPC7400ITR Microprocessor Support
Operating Basics
Setting Up the Support
This section provides information on how to set up the support. The information
covers the following topics:
H Channel group definitions
H Clocking options
H Symbol table files
The information in this section is specific to the operations and functions of the
TMS 545A PPC7400ITR microprocessor support on any Tektronix logic
analyzer for which the support can be purchased. Information on basic operations
describes general tasks and functions.
Before you acquire and disassemble data, you need to load the support and
specify the setups for clocking and triggering as described in the information on
basic operations. The support provides default values for each of these setups,
but you can change them as needed.
Channel Group Definitions
Clocking
Clocking Options
The software automatically defines channel groups for the support. The channel
groups for the PPC7400ITR support are Address, Hi_Data, Lo_Data, Control,
Transfer (Tran), Tsiz, and Misc. If you want to know which signal is in which
group, refer to the channel assignment tables beginning on page 1–4.
The PPC7400ITR support offers a PPC7400ITR microprocessor-specific
clocking mode for the PPC7400ITR microprocessor. This clocking mode is the
default selection whenever you load the PPC7400ITR support.
Disassembly will not be correct with the Internal or External clocking modes.
Information on basic operations describes how to use these clock selections for
general purpose analysis.
TMS 545A PPC7400ITR Microprocessor Support
2–1
Setting Up the Support
Custom Clocking
A special clocking program is loaded to the module every time you load the
PPC7400ITR support. This special clocking is called Custom.
With Custom clocking, the module logs in signals from multiple channel groups
at different times when the signals are valid on the PPC7400ITR bus. The
module then sends all the logged-in signals to the trigger machine and to the
acquisition memory of the module for storage.
In Custom clocking, the module clocking state machine (CSM) generates one
master sample for each PPC7400ITR microprocessor bus cycle, no matter how
many clock cycles are contained in the bus cycle.
When Custom is selected, the Custom Clocking Options menu will have the
subtitle “PPC7400ITR microprocessor Clocking Support” added, and the
clocking options will also be displayed.
The following clocking options are provided:
Select Processor. This clocking option allows the user to select the processor for
which disassembly is required. The processors provided in the options are:
H PPC7400ITR microprocessor: This is the default option. This option can be
selected when the processor for which support is required is PPC7400ITR.
H PPC 740/750 microprocessor: This option enables the user to acquire and use
the disassembly support for PPC 750/740 processors.
Pipeline Depth. This clocking option is provided so as to enable the user to select
the depth of address pipelining carried out by the microprocessor.
Two options are provided:
H One: This option can be selected when Address pipelining is occuring on the
bus. This is the default option.
H Zero: This can be selected by the user when there is no address pipelining is
carried out by the microprocessor.
NOTE. Pipeline Zero Option should be selected only when the Address and Data
cycle of a transaction are completed before the next Address-Data Transaction.
This holds true when the number of processors being used in a multiprocessor
environment is more than 1.
For Multiprocessor environments it is always preferable to use the Pipeline One
Option.
2–2
TMS 545A PPC7400ITR Microprocessor Support
Setting Up the Support
Bus timing diagram. All the data signals D[0–63] are logged in during “D” strobe
and DBG_ and DBWO_ are logged in during “DBB” strobe. All the address
signals A[0–31] and the remaining signals are strobed in during “A” strobe. See
Figure 2–1.
NOTE. BG_ logged in by the “A” strobe is the state during the previous cycle.
An “M” strobe is done if one or more of the following conditions are met:
TA_ is asserted
TS_ is asserted
ARTRY_ is asserted on the second clock after the assertion of AACK_
DRTRY_ is asserted (if the processor selected is PPC 740/750) OR
TEA_ is asserted
TMS 545A PPC7400ITR Microprocessor Support
2–3
Setting Up the Support
CLK
BR_
BG_
ABB_
TS_
1 2 3 4 5 6 7 10 11
12
13
A [0:31]
AACK_
ARTRY_
DBG_
DBB_
TA_
D [0:63]
TEA_
DBB DBB AD
DBB
M
Addr Addr Addr
D1 D2 D3 D0 D1
D0
AD
M
DBB ADMADMAD
M
DBBADMADMAD
DBB
M
2–4
Figure 2–1: PPC 7400/PPC 740/750 support bus timing diagram
TMS 545A PPC7400ITR Microprocessor Support
Symbols
Setting Up the Support
The TMS 545A support supplies three symbol-table files: PPC7400ITR_Transfer, PPC7400ITR_Tsiz, and PPC7400ITR_Ctrl. The PPC7400ITR_Ctrl file
replaces specific Control-channel group values with symbolic values when
Symbolic is the radix for the channel group.
Symbol tables are generally not for use in timing or PPC7400ITR_T support
disassembly.
Table 2–1 shows the definitions for name, bit pattern, and meaning of the
Transfer group symbols in file PPC7400ITR_Transfer.
T able 2–1: PPC7400ITR_Transfer group symbol table definitions
Control group value
TT0 TT2
Symbol
FETCH
DATA_READ
DATA_WRT
ADDR_ONLY
UNKNOWN
TT1 TT3
01 0101
X1 X1X1
X0 X1XX
XX X0XX
XX XXXX
TT4
WT
Description
Instruction fetch cycle
Read cycle
Write cycle
Address only cycle
Unknown transfer cycle
Table 2–2 shows the definitions for name, bit pattern, and meaning of the Tsiz
group symbols in file PPC7400ITR_Tsiz.
T able 2–2: PPC7400ITR_Tsiz group symbol table definitions
Control group value
TSIZ0
TSIZ1
Symbol
BURST
8_BYTE
1_BYTE
2_BYTE
3_BYTE
4_BYTE
5_BYTE
6_BYTE
TSIZ2
TBST_
0100
0001
0011
0101
0111
1001
1011
1101
Description
Burst transaction
Single beat 8-Byte transaction
Single beat 1-Byte transaction
Single beat 2-Byte transaction
Single beat 3-Byte transaction
Single beat 4-Byte transaction
Single beat 5-Byte transaction
Single beat 6-Byte transaction
TMS 545A PPC7400ITR Microprocessor Support
2–5
Setting Up the Support
T able 2–2: PPC7400ITR_Tsiz group symbol table definitions (cont.)
Control group value
TSIZ0
TSIZ1
TSIZ2
Symbol Description
7_BYTE
UNKNOWN
1111
XXXX
TBST_
Table 2–3 shows the definitions for name, bit pattern, and meaning of the Control
group symbols in file PPC7400ITR_Ctrl.
T able 2–3: PPC7400ITR_Ctrl Control group symbol table definitions
Control group value
TS_ DTI[1]/DRTRY_* ABB_
BG_ AACK_ DBWO_
Symbol
ARTRY_P0E
ARTRY_P1E
ARTRY_DRTRY
ARTRY_P0D
ARTRY_P1D
P0A_P0E
P0A_P1E
P1A_P0E
P1A_P1E
P0A_P0D
P0A_P1D
P1A_P0D
P1A_P1D
P0_A
P1_A
P0_E
P1_E
P0_D
P1_D
ARTRY
P0A_DRTRY
DBG_ TA_ DBB_
ARTRY_ TEA_
XX00 XXX0 XXX
XXX0 XXX0 XXX
XXX0 0XXX XXX
XX00 XX0X XXX
XXX0 XX0X XXX
0001 XXX0 XXX
00X1 XXX0 XXX
0X01 XXX0 XXX
0XX1 XXX0 XXX
0001 XX0X XXX
00X1 XX0X XXX
0X01 XX0X XXX
0XX1 XX0X XXX
00X1 XXXX XXX
0XX1 XXXX XXX
XX0X XXX0 XXX
XXXX XXX0 XXX
XX0X XX0X XXX
XXXX XX0X XXX
XXX0 XXXX XXX
XX0X 0XXX XXX
Single beat 7-Byte transaction
Unknown tsiz cycle
Description
ARTRY Cycle and Data Error
ARTRY Cycle and Alternate Master Data Error
ARTRY Cycle
ARTRY Cycle and Data
ARTRY Cycle and Alternate Master Data
PPC0 Address and PPC0’s Data Error
PPC0 Address and PPC1’s Data Error
PPC1 Address and PPC0’s Data Error
PPC1 Address and PPC1’s Data Error
Address and Data
Current Master Address and Alternate Master Data
Alternate Master Address and Current Master Data
Alternate Master Address and Data
Address Cycle
Alternate Master Address Cycle
Data Error
Alternate Master Data Error
Data Cycle
Alternate Master Data Cycle
ARTRY Cycle
DRTRY Cycle
2–6
TMS 545A PPC7400ITR Microprocessor Support
T able 2–3: PPC7400ITR_Ctrl Control group symbol table definitions (cont.)
Control group value
TS_ DTI[1]/DRTRY_* ABB_
BG_ AACK_ DBWO_
DBG_ TA_ DBB_
Symbol Description
P1A_DRTRY
UNKNOWN
* This signal occurs as DTI[1] in 7400 and as DRTRY_ in 750
XXXX 0XXX XXX
XXXX XXXX XXX
ARTRY_ TEA_
Alternate Master DRTRY Cycle
Unknown Cycle
Information on basic operations describes how to use symbolic values for
triggering and for displaying other channel groups symbolically, such as for the
Address channel group.
Setting Up the Support
Range Symbols
The TMS 545A design supports range symbols in a manner similar to pattern
symbols. Both types of symbols are accessed in the same manner (by the user).
Range symbols associate a range of data values with a symbol “name”. When a
range symbol table is selected for the radix of the Address group, all address
values (both in the Address column and in the disassembly Mnemonics column)
will be replaced with their corresponding symbol name plus an offset, if the
value falls within one of the defined ranges. If no symbol is defined, the address
value will be displayed in HEX or OCT, depending upon the output radix
selection for that symbol table. If the output radix selection is anything but HEX
or OCT, addresses will be displayed in HEX. The offset (the difference between
the value and the lower bound of the range) will also be displayed in that radix
(HEX or OCT).
NOTE. The various ranges must not overlap.
For example, given the following disassembled code fragment:
Address Mnemonic
.
00009700 ba 0000A00F
. .
. .
0000A00F .
.
TMS 545A PPC7400ITR Microprocessor Support
2–7
Setting Up the Support
and given the Address group range symbol:
mysub 0000A000 0000AFFF
then displaying disassembly in Hardware mode and selecting symbolic radix for
the Address group will cause the following disassembled code fragment to be
displayed:
Address Mnemonic
.
00009700 ba mysub+f
. .
. .
mysub+f .
.
If the output radix of the symbol table is changed to OCTAL then the code
fragment will look like:
Address Mnemonic
.
00000113400 ba mysub+17
. .
. .
mysub+17 .
.
Users can also load their own user-defined range symbols if the file follows the
conventions of the logic analyzer symbol table file format.
2–8
TMS 545A PPC7400ITR Microprocessor Support
Acquiring and Viewing Disassembled Data
This section describes how to acquire data and view it disassembled. Information
covers the following topics and tasks:
H Acquiring data
H Viewing disassembled data in various display formats
H Cycle type labels
H Changing the way data is displayed
H Changing disassembled cycles with the mark cycles function
Acquiring Data
Once you load the PPC7400ITR support, choose a clocking mode, and specify
the trigger, you are ready to acquire and disassemble
If you have any problems acquiring data, refer to information on basic operations
in your online help or Appendix A: Error Messages and Disassembly Problems in
the basic operations user manual.
data.
Viewing Disassembled Data
You can view disassembled data in four display formats: Hardware, Software,
Control Flow, and Subroutine. The information on basic operations describes
how to select the disassembly display formats.
NOTE. Selections in the Disassembly property page (the Disassembly Format
Definition overlay) must be set correctly for your acquired data to be disassembled correctly. Refer to Changing How Data is Displayed on page 2–14.
The default display format shows the Address, HI_Data, LO_Data, Control,
Transfer and Tsiz channel group values for each sample of acquired data.
If a channel group is not visible, you must use the Disassembly property page to
make the group visible.
The disassembler displays special characters and strings in the instruction
mnemonics to indicate significant events. Table 2–4 shows these special
characters and strings, and gives a definition of what they represent.
TMS 545A PPC7400ITR Microprocessor Support
2–9
Acquiring and Viewing Disassembled Data
T able 2–4: Description of special characters in the display
Character or string displayed Description
>> On the TLA. The instruction was manually marked
Hardware Display Format
#
-ā-ā-ā-ā-ā-ā-ā-
-ā-ā-ā-ā-ā-ā-ā-
-ā-ā-ā-ā-ā-ā-ā-
-ā-
-ā-ā-ā-ā-ā-ā-ā-
<Hex value>
Indicates an immediate value
In the Address channel group, this indicates that the
sequence did not have information that could be disassembled
In the HI_Data and LO_Data groups, this indicates that the
sequence does not contain valid data
In the LO_Data group, this indicates that the bus configuration is 32-Bits
In the invalidate byte lanes, this indicates a Data Read or
Data Write transaction
Indicates a flushed instruction when only one of the
instructions fetched is executed
In whole bytes that are not valid, this indicates invalidated
data; the value for invalidated data is hexadecimal
In Hardware display format, the disassembler displays certain cycle type labels in
parentheses.
If a single sequence has both an Address/Direct Store Access cycle and a Data
cycle, then a combination of cycle type labels described in Tables 2–5, 2–6, and
2–7 is displayed. For example, if Alternate Master Address and Alternate Master
Data are acquired in one sample, the disassembler would display the cycle type
label ( ALT ADDRS AND ALT DATA ).
2–10
T able 2–5: Cycle type labels for Address sequences and definitions
Cycle type label Definition
( 7400 ADDRESS )
( 7400 ARTRY ADDRESS )
( 740/750 ADDRESS )
( 740/750 ARTRY ADDRESS)
( 7400 ADDRESS ) &
( ALTERNATE MASTER )
( 740/750 ADDRESS ) &
( ALTERNATE MASTER )
Address cycle with selected processor mastership
Selected processor Address retried
Address cycle for the selected 740/750 processor mastership
Selected 740/750 processor Address retried
Address cycle when the processor selected is PPC 7400 and
the option selected under “Processors Used” is less than 3.
This is relevant when simultaneous disassembly is done for a
max of 2 processors.
Address cycle when the processor selected is PPC 740/750
and the option selected under “Processors Used” is less than
3. This is relevant when simultaneous disassembly is done
for a max of 2 processors.
TMS 545A PPC7400ITR Microprocessor Support
Acquiring and Viewing Disassembled Data
T able 2–5: Cycle type labels for Address sequences and definitions (cont.)
Cycle type label Definition
( ALTERNATE MASTER
ADDRESS )
Alternate master address. This is relevant when the option
selected under “Processors used” is greater than 2. This
implies that simultaneous disassembly would not be done
when the number of processors in a multiprocessing
environment is more than 2.
( INVALID ADDRESS )
Invalid selected processor Address which cannot associate
with any data
T able 2–6: Cycle type labels for Data sequences and definitions
Cycle type label Definition
( 7400 DATA ) Data cycle with selected processor mastership
( 740/750 DATA ) Data cycle with selected processor mastership
( ALTERNATE MASTER
DATA )
( INVALID DATA ) Invalid selected processor Data does not associate with address.
Alternate Master Data. This is applicable when the option selected
under “Processors Used” is greater than 2.
T able 2–7: Cycle type labels for ARTRY, DRTRY, and Data Error cycles
Cycle type label Definition
( 7400 DATA ERROR )
Data error in selected processor data – Assertion of TEA. This is
applicable only in the case where the option selected under
“Processors Used” is less than 3 and the processor being used is
PPC7400.
( 740/750 DATA ERROR )
( ALTERNATE DATA
ERROR )
( ARTRY_CYCLE ) Sequence having ARTRY* asserted
( UNKNOWN ) Cycle does not carry valid information
If a sequence contains both Address and Data, then a combination of labels
described above can be expected. For example, Alternate Masters address and
data if acquired in a single sequence, that sequence would be labeled as
( ALTERNATE ADDRESS AND ALTERNATE DATA ).
TMS 545A PPC7400ITR Microprocessor Support
Data error in selected processor data – Assertion of TEA. This is
applicable only in the case where the option selected under
“Processors Used” is less than 3 and the processor being used is
PPC 740/750.
Data error in Alternate Master Data
2–11
Acquiring and Viewing Disassembled Data
The processor performing a transaction on the bus in a multiprocessor environment would be treated as an Alternate master only when the option selected
under “Processors Used” is greater than 2. Hence, even if the number of
processors in the multiprocessor environment is 2 and if the above mentioned
option is selected, then all the transactions of the second processor would still be
treated as Alternate Master Transactions.
A sequence containing data may also be labeled as shown in Table 2–8.
T able 2–8: General cycle type labels definitions
Cycle type label Definition
( FLUSH ) An instruction is fetched but not executed; it is labeled as FLUSH
( FLUSH: PREDICTION FAIL ) An instruction was fetched based on the prediction bit, but the
( CACHE FILL ) Burst read transfer that occurs after wrap around of the end of
( CLEAN BLOCK ) Clean Block transaction
prediction was incorrect
the cache line
( FLUSH BLOCK ) Flush Block transaction
( SYNC ) Address Only transaction due to the execution of Sync instruction
( KILL BLOCK ) Kill Block transaction
( EIEIO ) Enforce In-Order Execution of I/O cycle
( LARX RSRV SET ) Reservation Set
TLBSYNC Translation Lookaside Buffer Synchronization
ICBI Instruction Cache Block Invalidate
( GRAPHICS WRITE ) External Control Word Write transaction
( GRAPHICS READ ) External Control Word Read transaction
( WRT WITH FLUSH ) Write-with-Flush operation issued by the processor
( WRT WITH KILL ) W rite with Kill operation
( DATA READ ) Single Beat Read or Burst Read operation
( RWITM ) Read-With-Intent-To-Modify transaction
( WWF-AT OMIC ) Write-With-Flush-Atomic operations issued by the processor
( READ-AT OMIC ) Read-Atomic operation
( RWITM-ATOMIC ) Read-With-Intent-To-Modify-Atomic transaction
( RWNITC ) Read With No Intent To Cache
2–12
( RCLAIM ) Read Claim (Applicable only in the MaxBus mode which is not
supported)
( RESERVED ) Reserved Transaction type match any of the defined patterns
TMS 545A PPC7400ITR Microprocessor Support
Acquiring and Viewing Disassembled Data
Software Display Format
Control Flow Display
Format
Figure 2–2: Example of the hardware display format
The Software display format shows only the first fetch of executed instructions.
Flushed cycles and extensions are not shown, even though they are part of the
executed instruction. Data reads and writes are not displayed.
The Control Flow display format shows only the first fetch of instructions that
change the flow of control.
Instructions that generate a change in the flow of control in the PPC7400ITR microprocessor are as follows:
bblsc
ba bla rfi
Instructions that might generate a change in the flow of control in the
PPC7400ITR microprocessor are as follows:
bc bcla bcctr tdi
bca bclr bcctrl tw
bcl bclrl td twi
TMS 545A PPC7400ITR Microprocessor Support
2–13
Acquiring and Viewing Disassembled Data
The disassembler displays some instructions that cause traps or interrupts, as well
as exception vector reads that are taken and the message" ( **BAD CYCLE
TYPE** ). Mnemonics misinterpreted by the disassembler are also displayed.
Subroutine Display
Format
The Subroutine display format shows only the first fetch of subroutine call and
return instructions. It will display conditional subroutine calls if they are
considered to be taken.
Instructions that generate a subroutine call or a return in the PPC7400ITR microprocessor are as follows:
sc rfi
Instructions that might generate a subroutine call or a return in the
PPC7400ITR microprocessor are as follows:
td tdi tw twi
The disassembler displays some instructions that cause traps or interrupts, as well
as exception vector reads that are taken and the message" ( **BAD CYCLE
TYPE** ). Mnemonics misinterpreted by the disassembler are also displayed.
Changing How Data is Displayed
There are common fields and features that allow you to further modify displayed
data to suit your needs. You can make common and optional display selections in
the Disassembly property page (the Disassembly Format Definition overlay).
2–14
Optional Display
Selections
You can make selections unique to the PPC7400ITR support to do the following
tasks:
H Change how data is displayed across all display formats
H Change the interpretation of disassembled cycles
H Display exception cycles
You can make optional selections for disassembled
common selections (described in the information on basic operations), you can
change the displayed data in the following ways:
H Select the prefetch byte order
H Select the alternate byte order low and high bounds
H Select the exception byte order
H Specify the exception prefix
TMS 545A PPC7400ITR Microprocessor Support
data. In addition to the
Acquiring and Viewing Disassembled Data
The PPC7400ITR support product has five additional fields: Prefetch Byte Ord,
Alt-Byte Ord-Lo Bound, Alt-Byte Ord-Hi Bound, Exception Byte Ord, and
Exception Prefix. These fields appear in the area indicated in the basic operations
user manual.
Prefetch Byte Order. You can select the byte ordering for the predominant
instruction fetches as Big- or Little-Endian.
Alt Byte Ord - Lo Bound and Alt Byte Ord - Hi Bound. You can enter the low and
high bounds for the alternate byte ordering range. The default is 00000000.
You should enter alternate values on double-word boundaries. If the value is not
on a double-word boundary, the disassembler assumes the value to be the nearest
double-word.
If you do not enter a value in the field, the data is acquired and disassembled
according to the selection in the Prefetch Byte Ord field.
NOTE. The alternate high bound value must be greater than the alternate low
bound value or disassembly will be incorrect.
Exception Byte Order. You can select the byte ordering for exception processing
as Big- or Little-Endian.
Exception Prefix. You can enter the prefix value of the exception table as 000 to
FFF. The default prefix value is 000. The exception table must reside in external
memory for interrupt and exception cycles to be visible to the disassembler.
NOTE. If an address is in the Exception processing region and in the range
selected for the alternate byte ordering, the disassembler uses the byte ordering
selected for the Exception processing.
TMS 545A PPC7400ITR Microprocessor Support
2–15
Acquiring and Viewing Disassembled Data
Marking Cycles
The disassembler has a Mark Opcode function that allows you to change the
interpretation of a cycle type. Using this function, you can select a cycle and
change it.
Marks are placed by using the Mark Opcode button. The Mark Opcode button
will always be available. If the sample being marked is not an Address cycle or
Data cycle of the potential bus master, the Mark Opcode selections will be
replaced by a note indicating that “An Opcode Mark cannot be placed at the
selected data sample.”
When a cycle is marked, the character “>>” is displayed immediately to the left
of the Mnemonics column. Cycles can be unmarked by using the “Undo Mark”
selection, which will remove the character “>>”.
The list of selections varies depending on the selection in the Bus Processor
Select field in the Disassembly property page (Disassembly Format Definition
overlay).
Mark selections available on data sequences without an address and data cycle
associated with a fetch cycle when the PPC7400ITR microprocessor is operating
in 64-bit mode are as follows:
Opcode - Opcode
Opcode - Flush
Flush - Opcode
Flush - Flush
Invalid_Data
Undo Mark
Mark selections available on sequences with only an Address cycle are as
follows:
Invalid_Address
Undo Mark
The following two extra marking options are provided when the Heuristic
Method is chosen for Instruction Fetch and Data Read differentiation.
Not an Instruction Fetch
Instruction Fetch
Mark selections available on sequences with both data and address cycles (if the
data cycle is associated with a fetch cycle) and the PPC7400ITR microprocessor
is operating in 64-bit mode are as follows:
Opcode - Opcode
Opcode - Flush
Flush - Opcode
Flush - Flush
Invalid_Data
2–16
TMS 545A PPC7400ITR Microprocessor Support
Invalid_Address
Opcode - Opcode Invalid_Address
Opcode - Flush Invalid_Address
Flush - Opcode Invalid_Address
Flush - Flush Invalid_Address
Invalid_Address Invalid_Data
Undo Mark
Mark selections available on sequences with data that is not associated with a
Fetch cycle are as follows:
Invalid_Data
Undo Mark
Table 2–9 describes the various combinations of mark selections.
T able 2–9: Mark selections and definitions
Mark selection or combination * Definition
Opcode - Opcode
HI_Data and LO_Data are disassembled
Acquiring and Viewing Disassembled Data
Opcode - Flush
Flush - Opcode
Flush - Flush Instructions not disassembled and labeled as ( FLUSH )
Invalid_Address Valid PPC 7400 address is invalidated and labeled as ( Incom_Addrs )
Instruction Fetch
Not an Instruction Fetch
Opcode - Opcode Invalid_Address
Opcode - Flush Invalid_Address
Flush - Opcode Invalid_Address
Flush - Flush Invalid_Address Instructions not disassembled and labeled as ( FLUSH ); the address is invalidated
Invalid_Address
Invalid_Data
Invalid_Address Invalid_Data
Undo Mark
Only HI_Data is disassembled in Big-Endian mode or only LO_Data is disassembled in
Little-Endian mode
Only LO_Data is disassembled in Big-Endian mode or only HI_Data is disassembled in
Little-Endian mode
The data corresponding to the address is decoded as an instruction fetch
The data corresponding to the address is decoded as a data read
Use to mark a sequence with PPC7400ITR address and data from different
transactions; HI_Data and LO_Data are disassembled; the address is invalidated
HI_Data is disassembled only in Big-Endian mode or LO_Data is disassembled only in
Little-Endian mode; the address is invalidated
LO_Data is disassembled only in Big-Endian mode or HI_Data is disassembled only in
Little-Endian mode; the address is invalidated
Address is invalidated
HI_Data and LO_Data are invalidated
Address, HI_Data, and LO_Data are invalidated
Removes all marks on the selected sample
* Mark selections intended to be used on sequences with data are not available for noninstructions.
TMS 545A PPC7400ITR Microprocessor Support
2–17
Acquiring and Viewing Disassembled Data
The Invalid_Address mark invalidates the address from being associated with the
wrong data. You can use this mark if you determine that the data for the address
was not acquired.
A1
–––T–––––––A2–––––
D2
Here, data for the address A1 was not acquired. But the disassembler will
associate the address A1 with the data D2. Hence, A1 has to be marked as
Invalid_Address to invalidate A1.
The Invalid_Data mark invalidates the data from being associated with the wrong
address. You can use this mark if you determine that the address for the data was
not acquired. For example:
A1
D0
A2
D1
For example:
Displaying Exception
Labels
Here, Address for Data D0 was not acquired or the disassembler has failed to
associate Data D0 with Address A0 for some reason. The resulting display
associates Data D0 with Address A1 and Data D1 with Address A2 which is
wrong. To correct the disassembly, data D0 may have to be marked as Invalid_Data so that Address A1 will associate with Data D1.
Not an Instruction Fetch. This marking option primarily allows the user to correct
any data that has wrongly been decoded as an instruction fetch. Such a wrong
decoding is possible sometimes in the Heuristic Method since the TT encodings
along with WT_ pin does not provide a clear distinction between Instruction
Fetches and Data Reads as in PPC 740/750. Hence the Heuristic Algorithm is
used to perform the necessary distinction, which is again approximate.
This marking option has to be used on the address of the data that has been
wrongly decoded as instruction fetch.
The same explanation, though in the reverse context, is true for the marking
option Instruction Fetch.
Information on basic operations contains more details on marking cycles.
The disassembler can display PPC7400ITR exception labels. The exception table
must reside in external memory for interrupt and exception cycles to be visible to
the disassembler.
2–18
You can enter the table prefix in the Exception Prefix field. The Exception Prefix
field provides the disassembler with the offset address; enter a three-digit
hexadecimal value corresponding to the prefix of the exception table.
TMS 545A PPC7400ITR Microprocessor Support
Acquiring and Viewing Disassembled Data
These fields are located in the Disassembly property page (Disassembly Format
Definition overlay).
Table 2–10 lists the PPC7400ITR interrupt and exception labels.
T able 2–10: Interrupt and exception labels
Offset Displayed interrupt or exception name
0x00000 ( RESERVED )
0x00100 ( SYSTEM RESET )
0x00200 ( MACHINE CHECK EXPN )
0x00300 ( DSI EXPN)
0x00400 ( ISI EXPN)
0x00500 ( EXTERNAL INTRPT )
0x00600 ( ALIGNMENT EXPN )
0x00700 ( PROGRAM EXPN )
0x00800 ( FLOATING-POINT UNAVLBL EXPN )
0x00900 ( DECREMENTER EXPN )
0x00A00 to 0x00BFF ( RESERVED )
0x00C00 ( SYSTEM CALL )
0x00D00 ( TRACE EXPN )
0x00E00 ( RESERVED )
0x00F00 ( PERFORMANCE MONITOR EXPN )
0x01000 ( RESERVED )
0x01100 ( RESERVED )
0x01200 ( RESERVED )
0x01300 ( INST ADDRESS BREAKPOINT EXPN )
0x01400 ( SYS MGMT INTERRUPT EXPN )
0x1500 ( RESERVED )
0x1600 ( VMX ASSIST INTERRUPT )
0x01700 ( THERMAL MGMT INTRPT )
0xF200 ( ALTIVEC UNAV AILABLE EXPN )
0x01800 to 0x02FFF ( RESERVED )
TMS 545A PPC7400ITR Microprocessor Support
2–19
Acquiring and Viewing Disassembled Data
Disassembly Display Options
T able 2–11: TLA disassembly display options
Description Option
Show: Hardware (Default)
Highlight: Software (Default)
Disasm Across Gaps: Yes (Default)
Software
Control Flow
Subroutine
Control Flow
Subroutine
None
No
Micro Specific Fields
This submenu will have the title:“PPC7400ITR Controls”.
Select Processor. The processor for which disassembly is to be done has to be
selected through this option. This consists of the following two options:
H PPC 7400: This option has to be selected when the processor for which
disassembly has to be carried out is PPC 7400.
H PPC 740/750: This option has to be selected when the processor for which
the disassembly has to be done is PPC 740 or PPC 750.
Processors Used. The TMS 545A support provides simultaneous disassembly for
a maximum of 2 processors. If there are more than two processors used, then the
transaction by the processors other than the one that is being probed are labeled
as Alternate Master Transactions. This consists of the following two options:
H Less Than 3: This option should be selected when the number of processors
being used in a mutiprocessor environment is less than 3. The usage of this
option causes simultaneous disassembly to be carried out for a maximum of
two processors.
2–20
H Greater Than 2: This option should be selected when the number of
processors being used is greater than 2. The selection of this option causes all
the transactions caused by the other processors to be labeled as Alternate
Master Transactions.
TMS 545A PPC7400ITR Microprocessor Support
Acquiring and Viewing Disassembled Data
NOTE. NOTE: The above mentioned limitation for simultaneous disassembly is
because the memory controller used in a multiprocessor environment is always
external with respect to any of the processors. Hence, for a given processor it is
possible to determine whether the processor being probed is the Master or not.
This limits the number of processors as candidates for simultaneous disassembly
to 2.
Prefetch Byte Ordering. Byte ordering for the Predominant Instruction Fetches is
selected from one of the two available options.
Prefetch Byte Ord: Big Endian (default)
Lit Endian
Alternate Byte ordering range is supplied by entering the proper 32 bit hexadecimal values in the fill-in fields:
Alt Byte Ord – Lo Bound 00000000 (default)
Alt Byte Ord – Hi Bound 00000000 (default)
H Hi Bound Value must be greater than Lo Bound Value, otherwise an
erroneous display may result.
H Values entered are preferred on Double word boundary — if any other value
is entered, it defaults to the nearest double word value. If nothing is entered
in these fields, then the byte ordering that is selected under Prefetch Byte
ordering is assumed for the entire acquisition.
H The range supplied for alternate byte ordering, which is the byte ordering
opposite to that selected for Prefetch Byte Ordering, is assumed.
Exception Byte Ordering. Byte ordering selected for Exception processing must be
selected by selecting one of the two options.
Exception Byte Ord: Big Endian (default)
Lit Endian
Exception Prefix. Valid Exception Prefix is selected by selecting one of the
following two options depending on the system he has used.
Exception Prefix: 000 (default) Option 1
FFF Option 2
TMS 545A PPC7400ITR Microprocessor Support
2–21
Acquiring and Viewing Disassembled Data
NOTE. If an address happens to be in both the Exception processing region of the
processor and in the range selected for the alternate byte ordering, then the byte
ordering selected for the Exception processing will be assumed for that address.
Instruction Fetch Indicator Provides two options to the user:
H Transfer Group
H By Heuristic Method
The Transfer Group option should be selected by the user only when TT[0–4]
signals distinguish between Instruction Fetches and Data reads. This is possible
only when the IFTT bit in the HID0 register is set.
The By Heuristic Method option should be chosen only when the TT[0–4]
signals do not differentiate between Instruction Fetches and Data Reads. Now a
Heuristic algorithm is used to differentiate between the two types of transactions.
Note that this algorithm provides only an approximate differentiation between the
two types of transactions. In cases where the differentiation is incorrect marking,
options have to be used to do the necessary correction.
Disassemble based on. This option lets the user select the basis for disassembly.
Fetch Stream (Default)
Memory Image
When the option Fetch Stream is selected normal disassembly occurs. But when
the Memory Image option is selected disassembly is based on the image file, for
example, S-record file.
Address for Trace Writes. This field contains the address to which the Branch
Trace Exception handler needs to write the branch target address (SRR0 value).
0x00000000 (default)
Maximum Instructions. Here the user needs to enter the number of instructions to
be displayed (from the image file each time a BTE is encountered) in the
property for Maximum Instructions.
40 (default)
The user needs to enter the number of instructions to be displayed (from the
image file each time a BTE is encountered). This number is the maximum
number of instructions that will be taken from the image file to show each time a
control flow change occurs.
2–22
TMS 545A PPC7400ITR Microprocessor Support
Image file path. The user needs to enter the complete path to the S-record file in
the property for Image file path. The Browse button can be used for this.
C:\Program Files\TLA 700\Supports\PPC7400ITR\Demo.src (Default)
Address Offset in Hex. This is the address offset (in hex) from the starting address
(as indicated by the S-record) where the user program will be loaded in memory.
0x00000000 (default)
Suppose the linker output and the corresponding S-record file have a starting
address of 0x0, but the user loads at a different address. For example, 0x50, then
the user will need to specify the offset 0x50 in this field.
Instruction Trace Reconstruction (ITR)
The logic Analyzer acquires data, which appears on the external bus of the
microprocessor. When the internal instruction cache is enabled, most of the
instruction fetches happen from the cache for which no external bus activity
occurs. This severely limits the information that a logic analyzer can display for
the user. To address this problem, some indirect methods are used to logically
track the program flow even though instruction fetches are happening from
internal cache. Following is brief explanation with examples showing ways you
can use the ITR method with this support.
Acquiring and Viewing Disassembled Data
Memory Image (S-record)
Image Reader
It is possible to reconstruct the program execution. That is, the portions of the
program which get executed inside the cache can be read from the Image File
and shown on the display. This can occur if both a program image (or Image
File) that is being executed is available externally (in S-record format for
example), and if the processor provides information about the control flow
instructions being executed and they can be acquired.
The memory image is a hexadecimal form of the program being executed by the
processor; therefore, it is the output of the Compiler/Assembler and Linker.
Linker output is normally available in one of the industry standard formats like
Intel Hex format, S-record format, or a proprietary format used by the software
development system. This support requires the external Image file to be in the
Motorola S-record format. Usually, tools are available to convert proprietary
output formats into Motorola S-record. The usage of one particular tool to
convert a source file into a S-record file (Image file) is also explained in a later
section.
The Motorola MPC7400 processor provides a Branch Trace Exception (BTE),
which can generate an exception on change of control flow, whenever a branch
instruction is encountered. Branch Trace Exception is a feature available in the
TMS 545A PPC7400ITR Microprocessor Support
2–23
Acquiring and Viewing Disassembled Data
processor used for collecting information about the program flow inside the
cache. The BTE is used to provide information about the target address,
whenever a change in control flow takes place. This in conjunction with the
external image file is used to display cache activity. TMS 545A supports only the
S-record format so it requires that the image file be available in Motorola
S-record format.
Basically, whenever a gap occurs in the acquisition because fetches take place
from internal cache, instructions are taken from the external image file and
displayed.
Viewing Cache Activity
This section on Viewing Cache Activity on the Tektronix logic analyzer consists
of a three-part procedure and a section showing the limits to using this procedure
when using self-modifying code (see page 2–29).
This procedure uses Green Hills software and SDS (Software Development
Solutions) Compiler for Embedded PCs. If you do not have this software, you
will need to find an alternative. Contact your Tektronix sales representative if
you need support.
Three-part procedure:
H Retrieving Control Flow Information
H Converting an Image file to S-record format
H Configuring the Tektronix logic analyzer
Retrieving Control Flow Information. Follow this procedure to retrieve information
about the Control flow from the Processor:
1. Enable the Branch Trace Exception bit of the Processor.
The Branch Trace enable bit is part of the register MSR. Once this bit is
enabled whenever a branch occurs in the program, a BTE is generated. This
exception is used to discover that a branch instruction has occurred and to
make target address available.
2–24
TMS 545A PPC7400ITR Microprocessor Support
Acquiring and Viewing Disassembled Data
2. Write the exception handler routine.
Whenever a branch is encountered, the program flows to the exception
handling routine, which for MPC7400 is at D00. You have to write your
exception handler routine here. A sample is shown below.
mfsrr0 r2 // r2 and r4 are assumed not to be modified by the user’s
program. The user is advised to use registers which are not
used in their main program.
xor r4,r4,r4
addi r4,r4,NonĆcacheable address //The user has to enter the required
noncacheable address.
stw r2,0(r4)
rfi
The exception handler routine for the PPC7400ITR support needs the starting
address to look into the code in the image file. This address will be available as
the “return address from a BTE / branch target address” in the register SRR0.
The value of SRR0 must be written onto a noncacheable region of memory so
that it appears on the external bus. The Image reader reads this value and the
cache activity is filled in. In the above code, the value of SRR0 is moved to a
register (R2) and this value is written onto a noncacheable region of the memory
so that it is available on theexternal bus.
Converting an Image File to S-Record Format. The source code must be converted
to S-record format. For example:
FileName.s (the source file with the mnemonics) to FileName.src
Follow these steps to convert an image file into S-record format using Green
Hills software:
a. Open the Green Hills command line
b. Change the working directory to the directory with FileName.s, which
for this example is c:\test
c. Type cd c:\test
d. Type asppc ćo FileName.o FileName.s
This command will generate a FileName.o file
e. Type lx ćo FileName.out FileName.o
This command will generate a FileName.out file
TMS 545A PPC7400ITR Microprocessor Support
2–25
Acquiring and Viewing Disassembled Data
Execute step f at an MS Windows command prompt, not a Green Hills command
prompt. You can either go to the directory c:\sds73\hcppc\bin and type the
following:
f. elf2hex ćo c:\test\FileName.src ćm c:\test\FileName.out
Or you can go to the directory where FileName.s is present for example, c:\test
and type the following:
g. c:\sds73\hcppc\bin\elf2hex -o FileName.src ćm FileName.out
The elf2hex utility used in this example is part of SDS (Software Development
Solutions) Compiler for Embedded PCs.
This will generate a FileName.src file in the same directory as the FileName.s
file, which for this example is c:\test.
Configuring the TLA. Follow these steps to configure your Tektronix logic
analyzer.
1. In the TLA software, load the support package.
2. Click on Setup, and then, on Trigger. Set the trigger for the address D00,
which is the Exception handler routine address.
3. Modify the TLA listing window properties as shown in Figure 2–3.
2–26
Figure 2–3: Listing window
TMS 545A PPC7400ITR Microprocessor Support
Acquiring and Viewing Disassembled Data
a. Change the Disassemble based on property to Memory Image.
b. Enter the noncacheable address used in the exception routine in the
property for Address for Trace Writes.
c. Enter the number of instructions to be displayed (from the image file
each time a BTE is encountered) in the property for Maximum Instructions. The default value is 40. This number is the maximum number of
instructions that will be taken from the image file to show each time a
control flow change occurs.
The number of instructions displayed is limited by two conditions:
H Number of instructions entered by the user.
H Another branch instruction encountered in the Image file will stop the
display.
The Image reader displays instructions from the cache until the number of
instructions entered by the user is completed or another branch instruction is
encountered.
d. Enter the complete path to the S-record file in the property for Image file
path. Either type in the path name or select the path name by pressing the
menu button to the right of the property for Image file path.
e. Enter the address offset in the field corresponding to Address Offset in
Hex. This is the address offset (in hex) from the starting address (as
indicated by the S-record) where the user program will be loaded in
memory.
Suppose the linker output and the corresponding S-record file have a
starting address of 0x0, but the user loads at a different address, for
example, 0x50, then the user needs to specify the offset 0x50 in this
field.
When all three sections of the procedure are completed, press ok/apply to view
the cache data on the display. To revert back to the original Fetch Stream data,
change the property for “Disassemble based on” back to Fetch Stream. Figures
2–4 and 2–5 show the effect of changing the property for “Disassemble based
on” from Fetch Stream data to Memory Image.
Figure 2–4 shows that the property for Fetch Stream is enabled. The exception
handler was written to make the value of SRR0 appear on the bus thus enabling
the Image reader to access the Image file. Figure 2–5 shows that the property for
Memory Image is enabled. In this case, the fetch stream is not disassembled and
is shown as “Instruction from fetch”.
TMS 545A PPC7400ITR Microprocessor Support
2–27
Acquiring and Viewing Disassembled Data
Figure 2–4: Display showing Fetch Stream
Figure 2–5: Display showing Memory Image
2–28
TMS 545A PPC7400ITR Microprocessor Support
Acquiring and Viewing Disassembled Data
The limitation of this procedure is that it will not work correctly with self-modifying code.
Error Messages Specific to the ITR support. The following are error messages
which are relevant to the ITR support.
1. Could Not Open File — This error message is displayed if the system is
unable to open the specified file.
2. Specified File is Not a Valid SĆRecord File — This message is
displayed if the file is not a valid S-record file. This might occur if:
H The file is corrupted.
H The format is not in the Motorola S-record format.
3. Insufficient Memory — This error occurs if problems are encountered
with allocating memory for the different buffers.
4. Error in Processing File — Unspecified error occurred while proces-
sing the file.
5. Invalid Address: No Associated Data — This error implies that the
data is not corresponding to the address passed to the Image reader. This
might occur when the wrong .src file has been given as input to the Image
reader or when there is an error in the flow of code.
Viewing an Example of Disassembled Data
A demonstration system file (or demonstration reference memory) is provided so
that you can see an example of how your PPC7400ITR microprocessor bus
cycles and instruction mnemonics look when they are disassembled. Viewing the
system file is not a requirement for preparing the module for use, and you can
view it without connecting the logic analyzer to your system under test.
Information on basic operations describes how to view the file.
TMS 545A PPC7400ITR Microprocessor Support
2–29
Acquiring and Viewing Disassembled Data
2–30
TMS 545A PPC7400ITR Microprocessor Support
Specifications
Specifications
Specification Tables
This chapter contains information regarding the specifications of the support.
Table 3–1 lists the electrical requirements the system under test must produce for
the support to acquire correct data.
T able 3–1: Electrical specifications
Characteristics Requirements
SUT clock rate
PPC7X0 specified clock rate Max 133 MHz
PPC7X0 tested clock rate Max 100 MHz
Minimum setup time required
TLA 700 2.5 ns
Minimum hold time required
TLA 700 0 ns
TMS 545A PPC7400ITR Microprocessor Support
3–1
Specifications
3–2
TMS 545A PPC7400ITR Microprocessor Support
Replaceable Parts List
Replaceable Parts List
This section contains a list of the replaceable parts for the
TMS 545A PPC7400ITR microprocessor support product.
Parts Ordering Information
Replacement parts are available through your local Tektronix field office or
representative.
Changes to Tektronix products are sometimes made to accommodate improved
components as they become available and to give you the benefit of the latest
improvements. Therefore, when ordering parts, it is important to include the
following information in your order.
H Part number
H Instrument type or model number
H Instrument serial number
H Instrument modification number, if applicable
Abbreviations
Mfr. Code to Manufacturer
Cross Index
If you order a part that has been replaced with a different or improved part, your
local Tektronix field office or representative will contact you concerning any
change in part number.
Abbreviations conform to American National Standard ANSI Y1.1–1972.
The table titled Manufacturers Cross Index shows codes, names, and addresses
of manufacturers or vendors of components listed in the parts list.
TMS 545A PPC7400ITR Microprocessor Support
4–1
Replaceable Parts Lists
Manufacturers cross index
Mfr.
code
80009 TEKTRONIX INC 14150 SW KARL BRAUN DR
Manufacturer Address City, state, zip code
PO BOX 500
BEAVERT ON, OR 97077–0001
Replaceable parts list
Fig. &
index
number
––– 071-0797-00 1 MANUAL,TECH INSTRUCTIONS,PPC 7400_ITR;TMS
Tektronix
part number
Serial no.
effective
Serial no.
discont’d
Qty Name & description Mfr. code Mfr. part number
STANDARD ACCESSORIES
545A
80009
071-0797-00
4–2
TMS 545A PPC7400ITR Microprocessor Support
Index
Index
A
about this manual set, vii
acquiring data, 2–9
Address, T ektronix, ix
Address group, channel assignments, 1–4
Address Pipelining, 1–3
address pipelining, 1–3
Alt Byte Ord - Hi Bound field, 2–15
Alt Byte Ord - Lo Bound field, 2–15
Alternate bus master, 1–3
application, logic analyzer configuration, 1–1
B
basic operations, where to find information, vii
Big-Endian byte order, 2–15
bus cycles
AR TRY, DRTRY, and Data Error, 2–11
Data cycle types, 2–11
displayed cycle types, 2–10
displayed general cycle types, 2–12
C
channel assignments
Address group, 1–4
clocks, 1–9
Control group, 1–7
Data group, 1–5, 1–6
DataSize group, 1–8
Misc group, 1–8
channel groups, 2–1
visibility , 2–9
clock channel assignments, 1–9
clock rate, 1–2
SUT, 3–1
clocking, Custom, 2–1
how data is acquired, 2–2
connections, CPU to Mictor, 1–10
Contacting T ektronix, ix
Control Flow display format, 2–13
Control group
channel assignments, 1–7
symbol table, 2–5, 2–6
CPU to Mictor connections, 1–10
Custom clocking, 2–1
how data is acquired, 2–2
cycle types, 2–10
AR TRY, 2–11
combined labels, 2–10
Data, 2–11
Data Error, 2–11
DR TRY, 2–11
general, 2–12
D
data
acquiring, 2–9
disassembly formats
Control Flow, 2-13
Hardware, 2-10
Software, 2-13
Subroutine, 2-14
data cache, 1–2
data display , changing, 2–14
Data group, channel assignments, 1–5, 1–6
DataSize group, channel assignments, 1–8
definitions
disassembler, vii
HI module, viii
information on basic operations, vii
LO module, viii
P54C, vii
SUT, vii
XXX, vii
demonstration file, 2–28
disassembled data
AR TRY, DRTRY, and Data Error cycle types, 2–11
cycle type definitions, 2–10
Data cycle types, 2–11
general cycle type definitions, 2–12
viewing, 2–9
viewing an example, 2–28
disassembler
definition, vii
logic analyzer configuration, 1–1
setup, 2–1
Disassembly Format Definition overlay, 2–14
Disassembly property page, 2–14
display formats
Control Flow, 2–13
Hardware, 2–10
Software, 2–13
special characters, 2–9
Subroutine, 2–14
TMS 545A PPC7400ITR Microprocessor Support
Index–1
Index
E
electrical specifications, 3–1
clock rate, 3–1
Exception Byte Ord field, 2–15
Exception Byte Ordering, 2–21
exception labels, 2–18
Exception Prefix field, 2–15
Extra Acquisition Channels, 1–3
F
functionality not supported, 1–3
interrupt signals, 1–3
H
Hardware display format, 2–10
AR TRY, DRTRY, and Data Error cycle types, 2–11
cycle type definitions, 2–10
Data cycle types, 2–11
general cycle type definitions, 2–12
HI module, definition, viii
hold time, minimum, 3–1
Mark Opcode function, 2–16
marking cycles, definition of, 2–16
Micro Specific Fields
Exception Byte Ordering, 2–21
Prefetch Byte Ordering, 2–21
Microprocessor, 1–3
microprocessor, specific clocking and how data is
acquired, 2–2
Mictor to CPU connections, 1–10
Misc group, channel assignments, 1–8
P
P54C, definition, vii
Phone number, Tektronix, ix
pipelining address, 1–3
Prefetch Byte Ord field, 2–15
Prefetch Byte Ordering, 2–21
Product support, contact information, ix
R
reference memory, 2–28
Reset, SUT hardware, 1–2
restrictions, 1–2
I
Instruction Cache, 1–2
Instruction Trace Reconstruction
overview , 2–22
procedure to view cache activity, 2–23
interrupt signals, functionality not supported, 1–3
L
L2 Cache, 1–3
Little-Endian byte order, 2–15
LO module, definition, viii
logic analyzer
configuration for disassembler, 1–1
configuration for the application, 1–1
with a TLA 700 series, 1-1
software compatibility, 1–1
M
manual
conventions, vii
how to use the set, vii
Mark Cycle function, 2–16
S
Service support, contact information, ix
set up time, minimum, 3–1
setups, disassembler, 2–1
signals, active low sign, viii
Software display format, 2–13
special characters displayed, 2–9
specifications
channel assignments, 1–4
electrical, 3–1
Subroutine display format, 2–14
support setup, 2–1
SUT, definition, vii
SUT hardware Reset, 1–2
symbol table, Control channel group, 2–5, 2–6
system file, demonstration, 2–28
T
T echnical support, contact information, ix
T ektronix, contacting, ix
terminology, vii
Timing Display Format, 1–2
Index–2
TMS 545A PPC7400ITR Microprocessor Support
Index
U
URL, Tektronix, ix
V
viewing disassembled data, 2–9
W
Web site address, Tektronix, ix
X
XXX, definition, vii
TMS 545A PPC7400ITR Microprocessor Support
Index–3
Index
Index–4
TMS 545A PPC7400ITR Microprocessor Support
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