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Instruction Manual
TMS 540
PowerPC 60X Microprocessor Support
070-9829-00
There are no current European directives that
apply to this product. This product provides
cable and test lead connections to a test object of
electronic measuring and test equipment.
Warning
The servicing instructions are for use by
qualified personnel only. To avoid personal
injury, do not perform any servicing unless you
are qualified to do so. Refer to all safety
summaries prior to performing service.
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Copyright T ektronix, Inc. All rights reserved. Licensed software products are owned by Tektronix or its suppliers and are
protected by United States copyright laws and international treaty provisions.
Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the
Rights in T echnical Data and Computer Software clause at DFARS 252.227-7013, or subparagraphs (c)(1) and (2) of the
Commercial Computer Software – Restricted Rights clause at F AR 52.227-19, as applicable.
T ektronix products are covered by U.S. and foreign patents, issued and pending. Information in this publication supercedes
that in all previously published material. Specifications and price change privileges reserved.
Printed in the U.S.A.
T ektronix, Inc., P.O. Box 1000, Wilsonville, OR 97070–1000
TEKTRONIX and TEK are registered trademarks of T ektronix, Inc.
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SOFTWARE WARRANTY
T ektronix warrants that the media on which this software product is furnished and the encoding of the programs on
the media will be free from defects in materials and workmanship for a period of three (3) months from the date of
shipment. If a medium or encoding proves defective during the warranty period, T ektronix will provide a
replacement in exchange for the defective medium. Except as to the media on which this software product is
furnished, this software product is provided “as is” without warranty of any kind, either express or implied.
T ektronix does not warrant that the functions contained in this software product will meet Customer’s
requirements or that the operation of the programs will be uninterrupted or error-free.
In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration
of the warranty period. If T ektronix is unable to provide a replacement that is free from defects in materials and
workmanship within a reasonable time thereafter, Customer may terminate the license for this software product
and return this software product and any associated materials for credit or refund.
THIS WARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER WARRANTIES, EXPRESS
OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’
RESPONSIBILITY TO REPLACE DEFECTIVE MEDIA OR REFUND CUSTOMER’S PAYMENT IS
THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS
WARRANTY. TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT,
SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER
TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH
DAMAGES.
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HARDWARE WARRANTY
T ektronix warrants that the products that it manufactures and sells will be free from defects in materials and
workmanship for a period of one (1) year from the date of shipment. If a product proves defective during this
warranty period, T ektronix, at its option, either will repair the defective product without charge for parts and labor,
or will provide a replacement in exchange for the defective product.
In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration
of the warranty period and make suitable arrangements for the performance of service. Customer shall be
responsible for packaging and shipping the defective product to the service center designated by T ektronix, with
shipping charges prepaid. Tektronix shall pay for the return of the product to Customer if the shipment is to a
location within the country in which the T ektronix service center is located. Customer shall be responsible for
paying all shipping charges, duties, taxes, and any other charges for products returned to any other locations.
This warranty shall not apply to any defect, failure or damage caused by improper use or improper or inadequate
maintenance and care. T ektronix shall not be obligated to furnish service under this warranty a) to repair damage
resulting from attempts by personnel other than T ektronix representatives to install, repair or service the product;
b) to repair damage resulting from improper use or connection to incompatible equipment; c) to repair any
damage or malfunction caused by the use of non-T ektronix supplies; or d) to service a product that has been
modified or integrated with other products when the effect of such modification or integration increases the time
or difficulty of servicing the product.
THIS WARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER WARRANTIES, EXPRESS
OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’
RESPONSIBILITY TO REPAIR OR REPLACE DEFECTIVE PRODUCTS IS THE SOLE AND
EXCLUSIVE REMEDY PROVIDED TO THE CUST OMER FOR BREACH OF THIS WARRANTY.
TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT , SPECIAL,
INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER TEKTRONIX OR
THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.
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Table of Contents
Getting Started
Operating Basics
General Safety Summary v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Service Safety Summary vii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preface: Microprocessor Support Documentation ix. . . . . . . . . . . . . . . .
Manual Conventions ix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Analyzer Documentation x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contacting T ektronix x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Support Description 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Analyzer Software Compatibility 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Analyzer Configuration 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Requirements and Restrictions 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuring the Probe Adapter 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connecting to a System Under T est 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPC601, PPC601, MPC603, and PPC603 Converter Clips 1–4. . . . . . . . . . . .
Without a Probe Adapter 1–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Applying and Removing Power 1–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifications
Setting Up the Support 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Group Definitions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocking Options 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DR TRY Cycles 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Symbols 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acquiring and Viewing Disassembled Data 2–7. . . . . . . . . . . . . . . . . . . . .
Acquiring Data 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing Disassembled Data 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Display Format 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Display Format 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Flow Display Format 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subroutine Display Format 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Changing How Data is Displayed 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optional Display Selections 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Marking Cycles 2–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Displaying Exception Labels 2–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing an Example of Disassembled Data 2–18. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Probe Adapter Description 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifications 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Assignments 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
How Data is Acquired 3–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Custom Clocking 3–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocking Options 3–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Table of Contents
Alternate Microprocessor Connections 3–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signals Not On the Probe Adapter 3–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extra Channels 3–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PPC60X Microprocessor Signal Names to PGA Socket Pin Numbers 3–16. . . . . . . .
Maintenance
Probe Adapter Circuit Description 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Replacing Signal Leads 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Replacing Protective Sockets 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Replacing the Fuse 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Replaceable Electrical Parts
Parts Ordering Information 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the Replaceable Electrical Parts List 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Replaceable Mechanical Parts
Parts Ordering Information 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the Replaceable Mechanical Parts List 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . .
Index
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TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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List of Figures
Table of Contents
Figure 1–1: Adjusting the friction of the O-ring in
the converter clip 1–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1–2: Placing the PGA-to-QFP converter clip onto the
microprocessor 1–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1–3: Tie-down hole placement on the MPC601 or PPC601
converter clips 1–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1–4: Tie-down hole placement on the MPC603 or PPC603
converter clips 1–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1–5: Using an alternate method to secure the PGA-to-QFP
converter clip 1–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1–6: Placing the probe adapter onto the PGA-to-QFP
converter clip 1–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1–7: Connecting probes to a high-density probe 1–10. . . . . . . . . . .
Figure 1–8: Connecting cables to a high-density probe 1–11. . . . . . . . . . . .
Figure 1–9: Location of the power jack 1–20. . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables
Figure 2–1: Disassembled data in the Hardware display format 2–11. . . .
Figure 3–1: Dimensions of the probe adapter and converter clips 3–3. . .
Figure 3–2: PowerPC 60X bus timing 3–14. . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3–3: Grid row and column labels for the pin numbers on the
PGA socket 3–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4–1: Location of the fuse 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1–1: Supported microprocessors 1–1. . . . . . . . . . . . . . . . . . . . . . . .
Table 1–2: High-density probe exceptions for the 136-channel
module 1–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1–3: 136-channel: PowerPC 60X connections for channel
probes 1–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1–4: 192-channel: PowerPC 60X connections for the HI
module 1–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1–5: 192-channel: PowerPC 60X connections for the LO
module 1–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1–6: PowerPC 60X connections for the clock channels 1–18. . . . . . .
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Table of Contents
Table 2–1: Control group symbol table definitions 2–3. . . . . . . . . . . . . . .
Table 2–2: Transfer group symbol table definitions 2–4. . . . . . . . . . . . . .
Table 2–3: Transfer Size group symbol table definitions 2–5. . . . . . . . . .
Table 2–4: Meaning of special characters in the display 2–8. . . . . . . . . .
Table 2–5: Cycle type labels for Address sequences and
definitions 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2–6: Cycle type labels for Direct Store Access sequences and
definitions 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2–7: Cycle type labels for Data sequences and definitions 2–9. . . .
Table 2–8: Cycle type labels for ARTRY, DRTRY, and Data
Error cycles 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2–9: General cycle type labels definitions 2–10. . . . . . . . . . . . . . . . .
Table 2–10: Mark selections and definitions 2–16. . . . . . . . . . . . . . . . . . . .
Table 2–11: Interrupt and exception labels 2–17. . . . . . . . . . . . . . . . . . . . .
Table 3–1: Electrical specifications 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3–2: Environmental specifications 3–2. . . . . . . . . . . . . . . . . . . . . . .
Table 3–3: Certifications and compliances 3–2. . . . . . . . . . . . . . . . . . . . . .
Table 3–4: Address group channel assignments 3–5. . . . . . . . . . . . . . . . . .
Table 3–5: Hi_Data group channel assignments 3–6. . . . . . . . . . . . . . . . . .
Table 3–6: Lo_Data group channel assignments 3–7. . . . . . . . . . . . . . . . .
Table 3–7: Control group channel assignments 3–8. . . . . . . . . . . . . . . . . .
Table 3–8: Transfer group channel assignments 3–9. . . . . . . . . . . . . . . . .
Table 3–9: Tsiz group channel assignments 3–9. . . . . . . . . . . . . . . . . . . . .
Table 3–10: Misc group channel assignments 3–9. . . . . . . . . . . . . . . . . . .
Table 3–11: 192-channel: Com_60X group channel assignments 3–10. . . .
Table 3–12: 192-channel: PPC601_4 group channel assignments 3–11. . .
Table 3–13: 192-channel: PPC603_4 group channel assignments 3–11. . .
Table 3–14: 192-channel: PPC604 group channel assignments 3–12. . . . .
Table 3–15: Clock channel assignments (not a group) 3–13. . . . . . . . . . . . .
Table 3–16: Extra module sections and channels 3–16. . . . . . . . . . . . . . . .
Table 3–17: PGA socket pin numbers to PPC60X signal names 3–16. . . .
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TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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General Safety Summary
Review the following safety precautions to avoid injury and prevent damage to
this product or any products connected to it. To avoid potential hazards, use this
product only as specified.
Only qualified personnel should perform service procedures.
While using this product, you may need to access other parts of the system. Read
the General Safety Summary in other system manuals for warnings and cautions
related to operating the system.
To Avoid Fire or
Personal Injury
Use Proper Power Cord. Use only the power cord specified for this product and
certified for the country of use.
Connect and Disconnect Properly . Do not connect or disconnect probes or test
leads while they are connected to a voltage source.
Ground the Product. This product is grounded through the grounding conductor
of the power cord. To avoid electric shock, the grounding conductor must be
connected to earth ground. Before making connections to the input or output
terminals of the product, ensure that the product is properly grounded.
Observe All Terminal Ratings. To avoid fire or shock hazard, observe all ratings
and marking on the product. Consult the product manual for further ratings
information before making connections to the product.
Do not apply a potential to any terminal, including the common terminal, that
exceeds the maximum rating of that terminal.
Use Proper AC Adapter. Use only the AC adapter specified for this product.
Do Not Operate Without Covers. Do not operate this product with covers or panels
removed.
Use Proper Fuse. Use only the fuse type and rating specified for this product.
Avoid Exposed Circuitry. Do not touch exposed connections and components
when power is present.
Do Not Operate With Suspected Failures. If you suspect there is damage to this
product, have it inspected by qualified service personnel.
Do Not Operate in Wet/Damp Conditions.
Do Not Operate in an Explosive Atmosphere.
Keep Product Surfaces Clean and Dry .
Provide Proper Ventilation. Refer to the manual’s installation instructions for
details on installing the product so it has proper ventilation.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Page 10
General Safety Summary
Symbols and Terms
T erms in this Manual. These terms may appear in this manual:
WARNING. Warning statements identify conditions or practices that could result
in injury or loss of life.
CAUTION. Caution statements identify conditions or practices that could result in
damage to this product or other property.
T erms on the Product. These terms may appear on the product:
DANGER indicates an injury hazard immediately accessible as you read the
marking.
WARNING indicates an injury hazard not immediately accessible as you read the
marking.
CAUTION indicates a hazard to property including the product.
Symbols on the Product. The following symbols may appear on the product:
WARNING
High Voltage
Protective Ground
(Earth) T erminal
CAUTION
Refer to Manual
Double
Insulated
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TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Service Safety Summary
Only qualified personnel should perform service procedures. Read this Service
Safety Summary and the General Safety Summary before performing any service
procedures.
Do Not Service Alone. Do not perform internal service or adjustments of this
product unless another person capable of rendering first aid and resuscitation is
present.
Disconnect Power. To avoid electric shock, disconnect the main power by means
of the power cord or, if provided, the power switch.
Use Care When Servicing With Power On. Dangerous voltages or currents may
exist in this product. Disconnect power, remove battery (if applicable), and
disconnect test leads before removing protective panels, soldering, or replacing
components.
To avoid electric shock, do not touch exposed connections.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Preface: Microprocessor Support Documentation
This instruction manual contains specific information about the TMS 540
PowerPC 60X microprocessor support package and is part of a set of information
on how to operate this product on compatible Tektronix logic analyzers.
If you are familiar with operating microprocessor support packages on the logic
analyzer for which the TMS 540 PowerPC 60X support was purchased, you will
probably only need this instruction manual to set up and run the support.
If you are not familiar with operating microprocessor support packages, you will
need to supplement this instruction manual with information on basic operations
to set up and run the support.
Information on basic operations of microprocessor support packages is included
with each product. Each logic analyzer has basic information that describes how
to perform tasks common to support packages on that platform. This information
can be in the form of online help, an installation manual, or a user manual.
This manual provides detailed information on the following topics:
H Connecting the logic analyzer to the system under test
Manual Conventions
H Setting up the logic analyzer to acquire data from the system under test
H Acquiring and viewing disassembled data
H Using the probe adapter
This manual uses the following conventions:
H The term disassembler refers to the software that disassembles bus cycles
into instruction mnemonics and cycle types.
H The phrase “information on basic operations” refers to online help, an
installation manual, or a basic operations of microprocessor supports user
manual.
H In the information on basic operations, the term XXX or P54C used in field
selections and file names must be replaced with PPC60X. This is the name of
the microprocessor in field selections and file names you must use to operate
the PowerPC 60X support.
H The term system under test (SUT) refers to the microprocessor-based system
from which data will be acquired.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Page 13
Preface: Microprocessor Support Documentation
H The term logic analyzer refers to the Tektronix logic analyzer for which this
product was purchased.
H The term module refers to a 136-channel or a 192-channel module.
H PPC60X refers to all supported variations of the PowerPC 60X microproces-
sor unless otherwise noted.
H An asterisk (*) following a signal name indicates an active low signal.
Logic Analyzer Documentation
A description of other documentation available for each type of Tektronix logic
analyzer is located in the corresponding module user manual. The manual set
provides the information necessary to install, operate, maintain, and service the
logic analyzer and associated products.
Contacting Tektronix
Product
Support
Service
Support
For other
information
To write us Tektronix, Inc.
For application-oriented questions about a Tektronix measurement product, call toll free in North America:
1-800-TEK-WIDE (1-800-835-9433 ext. 2400)
6:00 a.m. – 5:00 p.m. Pacific time
Or, contact us by e-mail:
tm_app_supp@tek.com
For product support outside of North America, contact your
local Tektronix distributor or sales office.
Contact your local Tektronix distributor or sales office. Or, visit
our web site for a listing of worldwide service locations.
http://www.tek.com
In North America:
1-800-TEK-WIDE (1-800-835-9433)
An operator will direct your call.
P.O. Box 1000
Wilsonville, OR 97070-1000
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TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Getting Started
Support Description
This chapter provides information on the following topics and tasks:
H A description of the TMS 540 microprocessor support package
H Logic analyzer software compatibility
H Your system under test requirements
H Support restrictions
H How to connect to the system under test (SUT)
H How to apply power to and remove power from the probe adapter
The TMS 540 microprocessor support package disassembles data from systems
that are based on Motorola MPC601, MPC603, and MPC604 microprocessors,
and IBM PPC601, PPC603 and PPC604 microprocessors. The Motorola
MPC604 and IBM PPC604 microprocessors are only supported through the
software setup and disassembler.
The support runs on a compatible Tektronix logic analyzer equipped with a
136-channel module or a 192-channel module.
Refer to information on basic operations to determine how many modules and
probes your logic analyzer needs to meet the minimum channel requirements for
the TMS 540 microprocessor support.
Table 1–1 shows the microprocessors and packages from which the TMS 540
support can acquire and disassemble data.
T able 1–1: Supported microprocessors
Name Package
Motorola MPC601 304-pin QFP
Motorola MPC603 240-pin QFP
Motorola MPC604* 304-pin QFP
IBM PPC601 304-pin QFP
IBM PPC603 240-pin QFP
IBM PPC604* 304-pin QFP
* Contact Tektronix for availability of the MPC604 or PPC604 microprocessor support.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
1–1
Page 15
Getting Started
A complete list of standard and optional accessories is provided at the end of the
parts list in the Replaceable Mechanical Parts chapter.
To use this support efficiently, you need to have the items listed in the information on basic operations as well as the following documents:
H The PowerPC System Architecture Manual, Mindshare, Inc.,1995
H The PowerPC Microprocessor Family: The Programming Environments
Manual, Motorola, Inc., 1993
H The PowerPC 601 RISC Microprocessor User’s Manual, Motorola, Inc., 1993
H The MPC601 data sheet, Motorola, Inc., 1993
H The PowerPC 603 RISC Microprocessor User’s Manual, IBM Microelec-
tronics, and Motorola, Inc., 1993
H The PowerPC 603 RISC Microprocessor Hardware Specification, IBM
Microelectronics, and Motorola, Inc., 1993
H The PowerPC 604 RISC Microprocessor User’s Manual, IBM Microelec-
tronics, and Motorola, Inc., 1993
Information on basic operations also contains a general description of supports.
Logic Analyzer Software Compatibility
The label on the microprocessor support floppy disk states which version of logic
analyzer software the support is compatible with.
Logic Analyzer Configuration
To use the PowerPC 60X support, the Tektronix logic analyzer must be equipped
with either a 136-channel module, or a 192-channel module at a minimum. The
module must be equipped with enough probes to acquire channel and clock data
from signals in your PowerPC 60X-based system.
Refer to information on basic operations to determine how many modules and
probes the logic analyzer needs to meet the channel requirements.
Requirements and Restrictions
You should review the general requirements and restrictions of microprocessor
supports in the information on basic operations as they pertain to your SUT.
1–2
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 16
Getting Started
You should also review electrical, environmental, and mechanical specifications
in the Specifications chapter in this manual as they pertain to your system under
test, as well as the following descriptions of other PowerPC 60X support
requirements and restrictions.
System Clock Rate. The TMS 540 support can acquire data from the PowerPC
60X microprocessor at speeds of up to 66 MHz
1
.
SUT Power. Whenever the SUT is powered off, be sure to remove power from
the probe adapter. Refer to Applying and Removing Power at the end of this
chapter for information on how to remove power from the probe adapter.
PPC601 SYSCLK Signal. When connecting to a PPC601 microprocessor system
under test, the HI_C3:3, HI_CK3, and LO_CK3 podlets must connect to a 1X
clock. When using the TMS 540 product, the application assumes that the
BCLK_EN* signal is a 1X clock. If it is not, you must remove the jumper on
J300 on the probe adapter and connect a 1X clock to pin 2 of J300.
For the relationship between the clock and signals to be correct, you need to
compare the 1X clock to the TS* and TA* signals with a 200 MHz oscilloscope.
There should be 6 ns setup time between the assertion of TS* and TA* (going
low) and the rising clock edge of the 1X clock. To improve the clock trace, you
can add a small ferrite bead to the wire connecting the 1X clock to pin 2 of J300.
MPC604 and PPC604 Microprocessor Support. The Motorola MPC604 and IBM
PPC604 microprocessors are only supported through the application setup and
disassembler. You can, however, use a commercial test clip and the PPC60X
probe adapter to connect to the signals in you SUT. Refer to the connection
procedure beginning on page 1–11.
Address Pipelining. If address pipelining sustains for many sequences (approximately 1 K), there might be performance degradation when scrolling data by
entering a sequence number in the Cursor field.
If address pipelining sustains for additional sequences (1 K or greater), there
might be erroneous address and data association. You can use the Mark Cycles
function to correct the interpretation of erroneous address and data association.
Configuring the Probe Adapter
The probe adapter does not require any configuration.
1
Specification at time of printing. Contact your Tektronix sales representative for
current information on the fastest devices supported.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
1–3
Page 17
Getting Started
Connecting to a System Under Test
Before you connect to the SUT, you must connect the probes to the module.
Your SUT must also have a minimum amount of clear space surrounding the
microprocessor to accommodate the probe adapter. Refer to the Specifications
chapter in this manual for the required clearances.
The channel and clock probes shown in this chapter are for a 136-channel
module. The probes will look different if you are using a 192-channel module.
The general requirements and restrictions of microprocessor supports in the
information on basic operations shows the vertical dimensions of a channel or
clock probe connected to square pins on a circuit board.
MPC601, PPC601,
MPC603, and PPC603
Converter Clips
This procedure requires contact lubricant and thermal joint compound. To
connect the logic analyzer to a SUT using a QFP probe adapter and PGA-to-QFP
converter clip, follow these steps:
1. Turn off power to your SUT. It is not necessary to turn off the logic analyzer.
CAUTION. Static discharge can damage the microprocessor, the probe adapter,
the acquisition probes, or the module. To prevent static damage, handle all the
above only in a static-free environment.
Always wear a grounding wrist strap or similar device while handling the
microprocessor and probe adapter.
2. To discharge your stored static electricity, touch the ground connector located
on the back of the logic analyzer. Then, touch the black foam on the
underside of the probe adapter to discharge stored static electricity from the
probe adapter.
CAUTION. Failure to place the SUT on a horizontal surface before connecting the
probe adapter might permanently damage the pins on the microprocessor.
1–4
3. Place the SUT on a horizontal surface.
4. Use a magnifying glass to examine the pins of the microprocessor soldered
into the SUT. Check for the following characteristics:
a. The pins are cleanly soldered to the board without excess solder or
deformity.
b. The bends of the pins are uniform (consistent and even).
5. Apply contact lubricant to the pins of the converter clip to improve the
connection to the microprocessor.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 18
Getting Started
6. Check that the heat sink moves easily, and yet stays in position when not
being moved.
If the heat sink is very difficult to move or does not stay in position, you
need to adjust the friction of the O-ring in the PGA-to-QFP converter clip. To
adjust the friction, refer to Figure 1–1 and follow these steps:
a. If you have difficulty moving the heat sink, loosen each of the four
O-ring screws a little until the heat sink is moveable, and yet will stay in
position.
b. If the heat sink does not stay in position, tighten each of the four O-ring
screws a little until the heat sink is moveable, and yet will stay in
position.
CAUTION. Do not loosen or tighten the four screws closest to the corners of the
PGA-to-QFP converter clip. These are set by the manufacturer.
Do not adjust
outside screws
O-ring
adjustment
screws
Figure 1–1: Adjusting the friction of the O-ring in the converter clip
7. Pull up the heat sink on the converter clip to allow vertical clearance for the
microprocessor.
8. Apply a small amount of thermal joint compound to the end of the heat sink
that faces the microprocessor (the end that will contact the microprocessor).
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
1–5
Page 19
Getting Started
CAUTION. Failure to correctly place the PGA-to-QFP converter clip onto the
microprocessor might permanently damage the microprocessor and converter
clip once power is applied.
9. Line up the pin E1 indicator on the converter clip with the pin 1 indicator on
the microprocessor.
10. Place the converter clip onto the microprocessor as shown in Figure 1–2.
Center the clip on the microprocessor and press the clip down while slightly
rocking the clip.
PGA-to–QFP converter clip*
Pin E1
Microprocessor
Pin 1
SUT
Figure 1–2: Placing the PGA-to-QFP converter clip onto the microprocessor
11. Measure the resistance between Vcc and ground to verify that they are not
shorted together. If you detect a short, determine the source and repair the
problem before applying power (described at the end of this chapter).
12. If there are tie-down holes in your SUT that match the tie-down holes on the
converter clip, you can use screws to secure the clip (and probe adapter) to
the SUT.
Figure 1–3 shows the placement of the tie-down holes on the MPC601 or
PPC601 clips. Figure 1–4 shows the placement of the tie-down holes on the
MPC603 or PPC603 clips.
1–6
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 20
60 mm
(2.350 in)
Getting Started
53 mm
(2.080 in)
3 mm
(.135 in)
53 mm
(2.080 in)
Figure 1–3: Tie-down hole placement on the MPC601 or PPC601 converter clips
60 mm
(2.350 in)
46 mm
(1.800 in)
7 mm
(.275 in)
46 mm
(1.800 in)
Figure 1–4: Tie-down hole placement on the MPC603 or PPC603 converter clips
13. Gently press down and turn the heat sink in the converter clip until it just
makes contact with the microprocessor.
14. If you cannot secure the clip through tie-down holes and screws, you can use
a nonconductive retention device around the clip and SUT circuit board to
make sure the clip is secure. Figure 1–5 shows an example of this method.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
1–7
Page 21
Getting Started
Nonconductive
retention device
Figure 1–5: Using an alternate method to secure the PGA-to-QFP converter clip
CAUTION. Failure to correctly place the probe adapter onto the PGA-to-QFP
converter clip might permanently damage the microprocessor, probe adapter, and
clip once power is applied.
15. Remove the black foam from the underside of the probe adapter.
16. Line up the pin E1 indicator on the probe adapter with the pin E1 indicator
on the PGA-to-QFP clip.
17. Place the probe adapter onto the PGA-to-QFP clip as shown in Figure 1–6.
1–8
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 22
Getting Started
Pin E1
Pin 1
SUT
Pin E1
Probe adapter
PGA–to–QFP clip*
* Earlier versions of some clips might not have a heat sink.
Figure 1–6: Placing the probe adapter onto the PGA-to-QFP converter clip
18. Connect the clock and channel probes to the high-density probe as shown in
Figure 1–7. For the 192-channel module, match the channel groups and
numbers on the probe labels to the corresponding HI_ and LO_pins on the
high-density probe. Match the ground pins on the probes to the corresponding pins on the probe adapter.
For the 136-channel module, match the channel groups and numbers on the
probe labels to the corresponding LO_ pins on the high-density probe. There
are some exceptions; they are shown in Table 1–2.
T able 1–2: High-density probe exceptions for the 136-channel module
Section Connect to high-density probe pins
E3, E2, E1, E0 HI_A3, HI_A2, HI_A1, HI_A0
C1, C0 HI_C3, HI_C2
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
1–9
Page 23
Getting Started
Clock probe
Hold the channel probes by the podlet
holder when connecting them to the
high-density probe. Do not hold them
by the cables or necks of the podlets.
Channel probe
and podlet holder
Channels connect to
the logic analyzer
High-density probe
Figure 1–7: Connecting probes to a high-density probe
19. Align pin 1 on the LO cable connector, the end on the narrowest cable strip
of the cable, with pin 1 on the LO connector on the high-density probe.
Connect the cable to the connector as shown in Figure 1–8.
NOTE. The LO cable is 12 inches long; the HI cable is 13 inches long.
20. Align pin 1 on the HI cable connector, the end on the narrowest cable strip of
the cable, with pin 1 on the HI connector on the high-density probe. Connect
the cable to the connector as shown in Figure 1–8.
1–10
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 24
HI cable
Pin 1 side
Getting Started
Probe adapter
LO cable
SUT
High-density probe
Figure 1–8: Connecting cables to a high-density probe
Without a Probe Adapter
You can use channel probes, clock probes, and leadsets with a commercial test
clip (or adapter) to make connections between the logic analyzer and your SUT.
To connect the probes to PowerPC 60X signals in the SUT using a test clip,
follow these steps:
1. Turn off power to your SUT. It is not necessary to turn off power to the logic
analyzer.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
1–11
Page 25
Getting Started
CAUTION. Static discharge can damage the microprocessor, the probes, or the
module. To prevent static damage, handle all of the above only in a static-free
environment.
Always wear a grounding wrist strap or similar device while handling the
microprocessor.
2. To discharge your stored static electricity, touch the ground connector located
on the back of the logic analyzer. If you are using a test clip, touch any of the
ground pins on the clip to discharge stored static electricity from it.
CAUTION. Failure to place the SUT on a horizontal surface before connecting the
test clip might permanently damage the pins on the microprocessor.
3. Place the SUT on a horizontal static-free surface.
4. For the 136-channel module, use Tables 1–3 and 1–6 to connect the channel
and clock probes to PowerPC 60X signal pins on a test clip or in the SUT.
Use leadsets to connect at least one ground lead from each channel probe and
the ground lead from each clock probe to ground pins in your SUT or on
your test clip.
T able 1–3: 136-channel: PowerPC 60X connections for channel probes
Section:channel PowerPC 60X signal Section:channel PowerPC 60X signal
A3:7 A0 D3:7 DL0
A3:6 A1 D3:6 DL1
A3:5 A2 D3:5 DL2
A3:4 A3 D3:4 DL3
A3:3 A4 D3:3 DL4
A3:2 A5 D3:2 DL5
A3:1 A6 D3:1 DL6
A3:0 A7 D3:0 DL7
A2:7 A8 D2:7 DL8
A2:6 A9 D2:6 DL9
A2:5 A10 D2:5 DL10
A2:4 A1 1 D2:4 DL11
A2:3 A12 D2:3 DL12
A2:2 A13 D2:2 DL13
A2:1 A14 D2:1 DL14
A2:0 A15 D2:0 DL15
1–12
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 26
Getting Started
T able 1–3: 136-channel: PowerPC 60X connections for channel probes (cont.)
Section:channel PowerPC 60X signalSection:channelPowerPC 60X signal
A1:7 A16 D1:7 DL16
A1:6 A17 D1:6 DL17
A1:5 A18 D1:5 DL18
A1:4 A19 D1:4 DL19
A1:3 A20 D1:3 DL20
A1:2 A21 D1:2 DL21
A1:1 A22 D1:1 DL22
A1:0 A23 D1:0 DL23
A0:7 A24 D0:7 DL24
A0:6 A25 D0:6 DL25
A0:5 A26 D0:5 DL26
A0:4 A27 D0:4 DL27
A0:3 A28 D0:3 DL28
A0:2 A29 D0:2 DL29
A0:1 A30 D0:1 DL30
A0:0 A31 D0:0 DL31
E3:7 DH0 C3:7 TT3
E3:6 DH1 C3:6 TT2
E3:5 DH2 C3:5
E3:4 DH3 C3:4 BG*
E3:3 DH4 C3:3 TSIZ2
E3:2 DH5 C3:2 TBST*
E3:1 DH6 C3:1 TT0
E3:0 DH7 C3:0 XA TS_B2* (Delayed XATS*)
E2:7 DH8 C2:7 TSIZ1
E2:6 DH9 C2:6 TSIZ0
E2:5 DH10 C2:5 DBB*
E2:4 DH1 1 C2:4 ABB*
E2:3 DH12 C2:3 XA TS*
E2:2 DH13 C2:2 TS*
E2:1 DH14 C2:1 AACK*
E2:0 DH15 C2:0 ARTRY_ERLY*
E1:7 DH16 C1:7 TC0
E1:6 DH17 C1:6 ARTRY*
TEA*[
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
1–13
Page 27
Getting Started
T able 1–3: 136-channel: PowerPC 60X connections for channel probes (cont.)
Section:channel PowerPC 60X signalSection:channelPowerPC 60X signal
E1:5 DH18 C1:5
E1:4 DH19 C1:4 DBG*
E1:3 DH20 C1:3
E1:2 DH21 C1:2 DRTRY*
E1:1 DH22 C1:1
E1:0 DH23 C1:0 DRTRY_ERLY*
E0:7 DH24 C0:7 TT1
E0:6 DH25 C0:6 TA*#
E0:5 DH26 C0:5 GBL*
E0:4 DH27 C0:4 DBWO*
E0:3 DH28 C0:3 XA TS*=
E0:2 DH29 C0:2 TS*=
E0:1 DH30 C0:1 AACK*=
E0:0 DH31 C0:0 ARTRY_DATA*
[ TEA* is also probed by CK:0.
] Signal not required for disassembly.
w BR* signal on the 603 microprocessor; SHD* signal on the 601 microprocessor.
W SYSCLK* is also probed by CK:3.
# TA* is also probed by CK:1.
BR_SHD*]w
SYSCLK]W
HRESET*]
1–14
5. For the 192-channel module, use Tables 1–4, 1–5, and 1–6 to connect the HI
and LO module probes to PowerPC 60X signal pins on a test clip or in the
SUT.
For both modules, use leadsets to connect at least one ground lead from each
channel probe and the ground lead from each clock probe to ground pins in
your SUT or on your test clip.
Table 1–4 shows the 192-channel HI module probes and the PPC60X signals
to which they must connect for disassembly to be correct.
T able 1–4: 192-channel: PowerPC 60X connections for the HI module
Section:
channel
A3:7 DH0 D3:7
A3:6 DH1 D3:6
Connect to PPC60X signal
Section:
channel
Connect to PPC60X signal
DPE*[
DP7[
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 28
Getting Started
T able 1–4: 192-channel: PowerPC 60X connections for the HI module (cont.)
Section:
channel
A3:5 DH2 D3:5
A3:4 DH3 D3:4
A3:3 DH4 D3:3
A3:2 DH5 D3:2
A3:1 DH6 D3:1
A3:0 DH7 D3:0
A2:7 DH8 D2:7
A2:6 DH9 D2:6
A2:5 DH10 D2:5
A2:4 DH1 1 D2:4
A2:3 DH12 D2:3
A2:2 DH13 D2:2
A2:1 DH14 D2:1
A2:0 DH15 D2:0
A1:7 DH16 D1:7
A1:6 DH17 D1:6
Connect to PPC60X signal
Section:
channel
Connect to PPC60X signal
DP6[
DP5[
DP4[
DP3[
DP2[
DP1[
DP0[
RSRV*[
TC1[
WT*[
TT4[
SRESET*[
INT*[
APE*[
AP3[
AP2[
A1:5 DH18 D1:5
A1:4 DH19 D1:4
A1:3 DH20 D1:3
A1:2 DH21 D1:2
A1:1 DH22 D1:1
A1:0 DH23 D1:0
A0:7 DH24 D0:7
A0:6 DH25 D0:6
A0:5 DH26 D0:5
A0:4 DH27 D0:4
A0:3 DH28 D0:3
A0:2 DH29 D0:2
A0:1 DH30 D0:1
A0:0 DH31 D0:0
C3:7 TC0 C1:7
C3:6
ARTRY*]
C1:6
AP1[
AP0[
CI*[
SCAN_CTL (601) [
SCAN_SIN (601) [
SCAN_CLK (601) [
SC_DRIVE (601) [
CSE1 (601 and 604) [
CSE2 (601) [
CSE0 (601 and 604) [
BSCAN_EN* (601) [
PCLK_EN* (601) [
RESUME (601) [
ESP_EN* (601) [
RTC (601) [
SYS_QUIESC* (601) [
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
1–15
Page 29
Getting Started
T able 1–4: 192-channel: PowerPC 60X connections for the HI module (cont.)
Section:
channel
C3:5
C3:4 DBG* C1:4
C3:3
C3:2 DRTR Y* C1:2
C3:1
C3:0 DRTRY* C1:0
C2:7 TT1 C0:7
C2:6
C2:5 GBL* C0:5
C2:4 DBWO* C0:4
C2:3 XATS*# C0:3
C2:2 TS*% C0:2
C2:1 AACK*@ C0:1
C2:0
[ Not required for disassembly.
] ARTRY* is also probed by LO_C2:0.
Connect to PPC60X signal
BR* (603 and 604), SHD* (601) [
SYSCLK[w
HRESET*[
TA*W
ARTRY*]
Section:
channel
C1:5
C1:3
C1:1
C0:6
C0:0
Connect to PPC60X signal
CKSTP_IN* (601) [
QUIESC_REQ (601) [
HP_SNP_REQ* (601) [
SCAN_OUT (601) [
RUN_NSTOP (601) [
CKSTP_OUT* (601) [
DBDIS* (603 and 604) [
TLBISYNC* (603) [
TBEN (603 and 604) [
QACK* (603) [
QREQ* (603) [
CSE (603) [
CLK_OUT (603 and 604) [
TCK (603 and 604) [
w SYSCLK is also probed by HI_CLK:3 and LO_CLK:3.
W TA* is also probed by HI_CLK:1 and LO_CLK:1.
# XA TS* is also probed by LO_C3:0 and LO_C2:3.
% TS* is also probed by LO_C2:2.
@ AACK* is also probed by LO_C2:1.
Table 1–5 shows the 192-channel LO module probes and the PPC60X signals to
which they must connect for disassembly to be correct.
T able 1–5: 192-channel: PowerPC 60X connections for the LO module
Section:
channel
A3:7 A0 D3:7 DL0
A3:6 A1 D3:6 DL1
A3:5 A2 D3:5 DL2
A3:4 A3 D3:4 DL3
Connect to PPC60X signal
Section:
channel
Connect to PPC60X signal
1–16
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 30
Getting Started
T able 1–5: 192-channel: PowerPC 60X connections for the LO module (cont.)
Section:
channel
A3:3 A4 D3:3 DL4
A3:2 A5 D3:2 DL5
A3:1 A6 D3:1 DL6
A3:0 A7 D3:0 DL7
A2:7 A8 D2:7 DL8
A2:6 A9 D2:6 DL9
A2:5 A10 D2:5 DL10
A2:4 A1 1 D2:4 DL11
A2:3 A12 D2:3 DL12
A2:2 A13 D2:2 DL13
A2:1 A14 D2:1 DL14
A2:0 A15 D2:0 DL15
A1:7 A16 D1:7 DL16
A1:6 A17 D1:6 DL17
A1:5 A18 D1:5 DL18
A1:4 A19 D1:4 DL19
Connect to PPC60X signal
Section:
channel
Connect to PPC60X signal
A1:3 A20 D1:3 DL20
A1:2 A21 D1:2 DL21
A1:1 A22 D1:1 DL22
A1:0 A23 D1:0 DL23
A0:7 A24 D0:7 DL24
A0:6 A25 D0:6 DL25
A0:5 A26 D0:5 DL26
A0:4 A27 D0:4 DL27
A0:3 A28 D0:3 DL28
A0:2 A29 D0:2 DL29
A0:1 A30 D0:1 DL30
A0:0 A31 D0:0 DL31
C3:7 TT3 C1:7
C3:6 TT2 C1:6
C3:5
C3:4 BG* C1:4
TEA*]
C1:5
TRST* (603 and 604) [
TMS (603 and 604) [
TDO (603 and 604) [
TDI (603 and 604) [
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
1–17
Page 31
Getting Started
T able 1–5: 192-channel: PowerPC 60X connections for the LO module (cont.)
Section:
channel
C3:3 TSIZ2 C1:3
C3:2 TBST* C1:2
C3:1 TT0 C1:1
C3:0
C2:7 TSIZ1 C0:7
C2:6 TSIZ0 C0:6
C2:5
C2:4 ABB* C0:4
C2:3
C2:2 TS*# C0:2
C2:1 AACK*% C0:1
C2:0 ARTR Y*@ C0:0 Not connected
[ Not required for disassembly.
] TEA* is also probed by HI_CLK:0 and LO_CLK:0.
w XATS* is also probed by HI_C2:3.
W DBB* is also probed by HI_CLK:2 and LO_CLK:2.
Connect to PPC60X signal
XA TS*w
DBB*W
XA TS*w
Section:
channel
C1:0
C0:5
C0:3
Connect to PPC60X signal
CKSTP_OUT*= (603 and 604) [
CKSTP_IN*= (603 and 604) [
MPC* (603 and 604) [
SMI* (603 and 604) [
TC2 (604) [
HAL TED (604) [
ARRA Y_WR* (604) [
RUN (604) [
LSSD_MODE* (603 and 604) [
L1_TSTCLK (603 and 604) [
L2_TSTCLK (603 and 604) [
# TS* is also probed by HI_C2:2.
% AACK* is also probed by HI_C2:1.
@ ARTY* is also probed by HI_C2:0, and HI_C3:6.
Table 1–6 shows the PowerPC 60X signals to which the clock channels must
connect for disassembly to be correct.
T able 1–6: PowerPC 60X connections for the clock channels
136-channel
section & probe
CK:3 HI_CK:3, LO_CK:3 Clock (rising edge)
CK:2 HI_CK:2, LO_CK:2 Qual DBB*= (DBB*)
CK:1 HI_CK:1, LO_CK:1 Qual TA*= (T A*)
CK:0 HI_CK:0, LO_CK:0 Qual TEA*= (TEA*)
[ In a 601 SUT, connect the SYSCLK= signal to a 1X clock (such as the BCLK_EN*
signal). Refer to Requirements and Restrictions in the Getting Started chapter for
more detailed information on this clock.
192-channel
section & probe
Clock or Qual PowerPC 60X signal name
SYSCLK= (SYSCLK)[
1–18
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 32
6. Align pin 1 of your test clip with the corresponding pin 1 of the microproces-
sor in your SUT and attach it to the microprocessor.
Refer to the channel assignment tables in the Specifications chapter to see the
signal-to-channel assignments.
Applying and Removing Power
A power supply for the PowerPC 60X probe adapter is included with the support.
The power supply provides +5 volts power to the probe adapter. The center
connector of the power jack connects to Vcc.
NOTE. Whenever the SUT is powered off, be sure to remove power from the probe
adapter.
To apply power to the PowerPC 60X probe adapter and SUT, follow these steps:
Getting Started
1. Measure the resistance between Vcc and ground to verify that they are not
shorted together.
If you detect a short, determine the source and repair the problem before
applying power.
CAUTION. Failure to use the +5 V power supply provided by Tektronix might
permanently damage the probe adapter and PowerPC 60X microprocessor. Do
not mistake another power supply that looks similar for the +5 V power supply.
2. Connect the +5 V power supply to the jack on the probe adapter. Figure 1–9
shows the location of the jack on the adapter board.
CAUTION. Failure to apply power to the probe adapter before applying power to
your SUT might permanently damage the PowerPC 60X microprocessor and
SUT.
3. Plug the power supply for the probe adapter into an electrical outlet. When
power is present on the probe adapter, an LED lights near the power jack.
4. Power on the SUT.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Page 33
Getting Started
Power Jack
Figure 1–9: Location of the power jack
To remove power from the SUT and PowerPC 60X probe adapter, follow these
steps:
CAUTION. Failure to power down your SUT before removing the power from the
probe adapter might permanently damage the PowerPC 60X microprocessor and
SUT.
1. Power off the SUT.
2. Unplug the power supply for the probe adapter from the electrical outlet.
1–20
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 34
Setting Up the Support
This section provides information on how to set up the support. Information
covers the following topics:
H Channel group definitions
H Clocking options
H Symbol table files
Remember that the information in this section is specific to the operations and
functions of the TMS 540 PowerPC 60X support on any Tektronix logic analyzer
for which it can be purchased. Information on basic operations describes general
tasks and functions.
Before you acquire and disassemble data, you need to load the support and
specify setups for clocking and triggering as described in the information on
basic operations. The support provides default values for each of these setups,
but you can change them as needed.
Channel Group Definitions
Clocking Options
The software automatically defines channel groups for the support. The channel
groups for the PowerPC 60X microprocessor are Address, Hi_Data, Lo_Data,
Control, Transfer, Tsiz, Com_60X, PPC601_4, PPC603_4 , PPC604, Misc, and
Clock. If you want to know which signal is in which group, refer to the channel
assignment tables beginning on page 3–4.
The TMS 540 support offers a microprocessor-specific clocking mode for the
PowerPC 60X microprocessor. This clocking mode is the default selection
whenever you load the PPC60X support.
NOTE. For the PPC601 microprocessor, you might not acquire correct data when
you connect the HI:CK3 and LO:CK3 channels to the BCLK_EN* signal. Refer
to the description of the PPC601 SYSCLK signal under Requirements and
Restrictions in the Getting Started chapter.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Setting Up the Support
A description of how cycles are sampled by the module using the TMS 540
support and probe adapter is found in the Specifications chapter.
Disassembly will not be correct with the Internal or External clocking modes.
Information on basic operations describes how to use these clock selections for
general purpose analysis.
NOTE. An earlier version of this software had a clocking option in which you
could acquire data with Joined Address and Data, or Separated Address and
Data. Although this clocking option is no longer available, you can still use this
software to view data acquired with Joined or Separated address and data.
The clocking option for the TMS 540 application is DRTRY Cycles.
Symbols
DRTRY Cycles
You can include or exclude DRTRY Cycles. These types of cycles are acquired
when you select Included.
You must select to always acquire data after the TA signal goes true to test for the
DRTRY signal, or to skip the sample unless some other important signals are
valid at that time. If you include DRTRY cycles, and there is no DRTRY cycle or
no other valid informationat this time, then the cycle is labeled .
The TMS 540 application supplies three symbol table files. The symbol table
file replaces specific channel group values with symbolic values when the group
is displayed symbolically.
Table 2–1 shows the name, bit pattern, and meaning for the symbols in the
Control channel group symbol table. The Control group symbol table file name
is PPC60X_Ctrl.
2–2
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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T able 2–1: Control group symbol table definitions
Control group value
XATS_B2* DBG* ARTRY_ERLY* ARTRY_DA TA*
TS* ARTRY* DRTRY_ERLY* ABB*
Symbol
ART_M0E
ART_M1E
ART_DRT
ART_M0D
ART_M1D
M0A_M0E
M0P0_M0E
M0P1_M0E
M0A_M1E
M0P0_M1E
M0P1_M1E
M1A_M0E
M1P0_M0E
M1P1_M0E
M1A_M1E
M1P0_M1E
M1P1_M1E
M0A_DRT
M0P0_DRT
M0P1_DRT
M1A_DRT
M1P0_DRT
M1P1_DRT
M0A_M0D
M0P0_M0D
M0P1_M0D
M0A_M1D
M0P0_M1D
M0P1_M1D
M1A_M0D
M1P0_M0D
M1P1_M0D
XATS* DRTRY* TA* DBWO*
BG* AACK* TEA* DBB*
Setting Up the Support
Meaning
ARTRY cycle and MPC0’s Data Error
ARTRY cycle and MPC1’s Data Error
ARTRY cycle and Data Retry
ARTRY cycle and MPC0’s Data
ARTRY cycle and MPC1’s Data
MPC0’s Address and MPC0’s Data Error
MPC0’s DSA packet 0 and MPC0’s Data Error
MPC0’s DSA packet 1 and MPC0’s Data Error
MPC0’s Address and MPC1’s Data Error
MPC0’s DSA packet 0 and MPC1’s Data Error
MPC0’s DSA packet 1 and MPC1’s Data Error
MPC1’s Address and MPC0’s Data Error
MPC1’s DSA packet 0 and MPC0’s Data Error
MPC1’s DSA packet 1 and MPC0’s Data Error
MPC1’s Address and MPC1’s Data Error
MPC1’s DSA packet 0 and MPC1’s Data Error
MPC1’s DSA packet 1 and MPC1’s Data Error
MPC0’s Address and Data retry
MPC0’s DSA packet 0 and Data retry
MPC0’s DSA packet 1 and Data retry
MPC1’s Address and Data retry
MPC1’s DSA packet 0 and Data retry
MPC1’s DSA packet 1 and Data retry
MPC0’s Address and Data
MPC0’s DSA packet 0 and Data
MPC0’s DSA packet 1 and Data
MPC0’s Address and MPC1’s Data
MPC0’s DSA packet 0 and MPC1’s Data
MPC0’s DSA packet 1 and MPC1’s Data
MPC1’s Address and MPC0’s Data
MPC1’s DSA packet 0 and MPC0’s Data
MPC1’s DSA packet 1 and MPC0’s Data
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Setting Up the Support
T able 2–1: Control group symbol table definitions (cont.)
Control group value
XATS_B2* DBG* ARTRY_ERLY* ARTRY_DA TA*
TS* ARTRY* DRTRY_ERLY* ABB*
Symbol Meaning
M1A_M1D
M1P0_M1D
M1P1_M1D
M0_A
M0_P0
M0_P1
M1_A
M1_P0
M1_P1
M0_E
M1_E
DRT
M0_D
M1_D
ART
UNKNOWN
XATS* DRTRY* TA* DBWO*
BG* AACK* TEA* DBB*
MPC1’s Address and Data
MPC1’s DSA packet 0 and Data
MPC1’s DSA packet 1 and Data
MPC0’s Address cycle
MPC0’s DSA packet 0 cycle
MPC0’s DSA packet 1 cycle
MPC1’s Address cycle
MPC1’s DSA packet 0 cycle
MPC1’s DSA packet 1 cycle
MPC0’s Data Error
MPC1’s Data Error
DRTRY cycle
MPC0’s Data cycle
MPC1’s Data cycle
ARTRY cycle
Unknown cycle
2–4
Table 2–2 shows the name, bit pattern, and meaning for the symbols in the
Transfer channel group symbol table. The Transfer group symbol table file name
is PPC60X_Trans.
T able 2–2: Transfer group symbol table definitions
Transfer group value
TT0
TT1
Symbol
FETCH
READ
WRITE
ADDR_ONLY
UNKNOWN
TT2 TC0
TT3 GBL*
Meaning
Instruction Fetch cycle
Data Read cycle
Data Write cycle
Address only cycle
Unknown cycle
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Setting Up the Support
Table 2–3 shows the name, bit pattern, and meaning for the symbols in the the
Transfer Size channel group symbol table. The Transfer Size group symbol table
file name is PPC60X_Tsiz.
T able 2–3: Transfer Size group symbol table definitions
Transfer Size group value
TSIZ0
TSIZ1
Symbol
BURST
8BYTE
4BYTE
2BYTE
1BYTE
UNKNOWN
TSIZ2
TBST*
Meaning
Burst transfer
Eight byte transfer
Four byte transfer
Two byte transfer
One byte transfer
Unknown transfer size
Information on basic operations describes how to use symbolic values for
triggering and for displaying other channel groups symbolically, such as the
Address channel group.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Acquiring and Viewing Disassembled Data
This section describes how to acquire data and view it disassembled. Information
covers the following topics and tasks:
H Acquiring data
H Viewing disassembled data in various display formats
H Cycle type labels
H Changing the way data is displayed
H Changing disassembled cycles with the mark cycles function
Acquiring Data
Once you load the PPC60X support, choose a clocking mode, and specify the
trigger, you are ready to acquire and disassemble
If you have any problems acquiring data, refer to information on basic operations
in your online help or Appendix A: Error Messages and Disassembly Problems in
the basic operations user manual.
data.
Viewing Disassembled Data
You can view disassembled data in four display formats: Hardware, Software,
Control Flow, and Subroutine. The information on basic operations describes
how to select the disassembly display formats.
NOTE. Selections in the Disassembly property page (the Disassembly Format
Definition overlay) must be set correctly for your acquired data to be disassembled correctly. Refer to Changing How Data is Displayed on page 2–13.
The default display format shows the Address, Data, Control, Transfer, and Tsiz
channel group values for each sample of acquired data.
The disassembler displays special characters and strings in the instruction
mnemonics to indicate significant events. Table 2–4 shows these special
characters and strings, and gives a definition of what they represent.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Acquiring and Viewing Disassembled Data
T able 2–4: Meaning of special characters in the display
Character or string displayed Meaning
or m
The instruction was manually marked as a program fetch
Hardware Display Format
****
-ā-ā-ā-ā-ā-ā-ā-
-ā-ā-ā-ā-ā-ā-ā-
-ā-ā-ā-ā-ā-ā-ā-
-ā-
-ā-ā-ā-ā-ā-ā-ā-
<Hex value>
Indicates there is insufficient data available for complete
disassembly of the instruction; the number of asterisks
indicates the width of the data that is unavailable. Each two
asterisks represent one byte.
In the Address channel group, this indicates that the Data
group did not have information that could be disassembled
In the HI_Data and LO_Data groups, this indicates that the
sequence does not contain valid data
In the LO_Data group, indicates that the bus configuration is
32-Bits
In the invalidate byte lanes, this indicates a Data Read or
Data Write transaction
Indicates a flushed instruction when the microprocessor is
operating in 64-bit mode and only one of the instructions
fetched is executed
In whole bytes that are not valid, indicates invalidated data;
the value for invalidated data is hexcadecimal
In Hardware display format, the disassembler displays certain cycle type labels in
parentheses.
2–8
If a single sequence has both an Address/Direct Store Access cycle and a Data
cycle, then a combination of cycle type labels described in Tables 2–5, 2–6, and
2–7 are displayed. For example, if Alternate Master Address and Alternate
Master Data are acquired in one sample, the disassembler would display the
cycle type label ( ALT ADDRS AND ALT DATA ).
Table 2–5 shows cycle type labels for Address sequences, and gives a definition
of the cycle they represent.
T able 2–5: Cycle type labels for Address sequences and definitions
Cycle type label Definition
( 60X_ADDRS ) Address cycle with selected PPC60X master
( 60X_ART_ADDRS ) Selected PPC60X Address retried
( ALT_ADDRS ) Alternate masters address
( INCOM_ADDRS ) Invalid selected PPC60X Address which is not associated with its
data
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Acquiring and Viewing Disassembled Data
Table 2–6 shows cycle type labels for Direct Store Access sequences, and gives a
definition of the cycle they represent.
T able 2–6: Cycle type labels for Direct Store Access sequences and definitions
Cycle type label Definition
( LOAD START ) Request for I/O load operations
( LOAD IMMEDIATE ) Transfer of up to 32 bits of data from the Bus Unit Controller to the
selected PPC60X
( LOAD LAST ) Transfer of last 32 bits of data from the Bus Unit Controller to the
selected PPC60X
( STORE IMMEDIATE ) Transfer of up to 32 bits of data from the selected PPC60X to the
Bus Unit Controller
( STORE LAST ) Transfer of last 32 bits of data from the selected PPC60X to the Bus
Unit Controller
( LOAD REPLY ) Reply from the Bus Unit Controller to indicate the success or failure
of an I/O load operation
( STORE REPLY ) Reply from the Bus Unit Controller to indicate the success or failure
of an I/O store operation
( UNKNOWN DSA ) Unrecognized I/O operation
( 60X_PKT1 XATC=0x$$ )
( 60X_ART_DSA )
( ALT_PKT0 )
( ALT_PKT1 )
Selected PPC60X Direct Store Access Packet 1 with XATC in Hex
Direct Store Access retried
Alternate Masters Direct Store Access packet 0
Alternate Masters Direct Store Access packet 1
Table 2–7 shows cycle type labels for Data sequences, and gives a definition of
the cycle they represent.
T able 2–7: Cycle type labels for Data sequences and definitions
Cycle type label Definition
( 60X_DATA ) Data cycle with selected PPC60X master
( ALT_DATA ) Alternate masters data
( 60X_DRT_DA TA ) Selected PPC60X Data retried
( INCOM_DATA ) Invalid selected PPC60X Data which is not associated with its
address
( 60X_DSA_DATA ) Selected PPC60X Direct Storage Access Data
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Acquiring and Viewing Disassembled Data
Table 2–8 shows cycle type labels for ARTRY, DRTRY, and Data Error cycles,
and gives a definition of the cycle they represent.
T able 2–8: Cycle type labels for ARTRY, DRTRY, and Data Error cycles
Cycle type label Definition
( DATA_RETRY ) Sequence with the DRTRY* signal asserted
( 60X_DATA_ERR ) Data error in the selected PPC60X data; the TEA* signal is
( ALT_DATA_ERR ) Data error in Alternate masters data
( ARTRY_CYCLE ) Sequence with the ARTRY* signal asserted
( UNKNOWN )* Cycle with out valid information
* If acquired with the DRTRY Included clocking option, the cycle following a valid data
cycle is always acquired in anticipation of a Data retry. If that cycle does not have any
valid information, the cycle is not displayed.
asserted
Table 2–9 shows cycle type labels for general cycle types (not sequence types),
and gives a definition of the cycle they represent.
T able 2–9: General cycle type labels definitions
Cycle type label Definition
( FLUSH ) An instruction that was fetched but not executed
( FLUSH: PREDICTION FAIL ) An instruction that was fetched based on the prediction bit, but
the prediction bit was incorrect
( CACHE FILL ) Burst read transfer that occurrs after the wrap around of the end
of the cache line
( CLEAN BLOCK ) Clean Block transaction
( WRT WITH FLUSH ) Write-with-Flush operation issued by the microprocessor
( FLUSH BLOCK ) Flush Block transaction
( WRT WITH KILL ) Write-with-Kill transaction
( SYNC ) Address Only transaction due to the execution of Sync instruction
( DATA READ ) Single Beat Read or Burst Read operation
( KILL BLOCK ) Kill Block transaction
( RWITM ) Read-with-Intent-to-Modify transaction
2–10
( ORD I/O OPRN ) Ordered I/O operation
( WWF-AT OMIC ) Write-with-Flush-Atomic operation issued by the microprocessor
( EXT CTR WD WRT ) External Control Word Write transaction
( TLB INVAL ) TLB invalidate transaction issued by the microprocessor
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Acquiring and Viewing Disassembled Data
T able 2–9: General cycle type labels definitions (cont.)
Cycle type label Definition
( READ-AT OMIC ) Read-Atomic operation
( EXT CTR WD RD ) External Control Word Read transaction
( RWITM-ATOMIC ) Read-with-Intent-to-Modify-Atomic transaction
( RESVD ) Reserved-with-Intent-to-Modify transaction type
( **BAD CYCLE TYPE** ) Cycle type where the value in the Trans group does not match
any of the defined patterns
Figure 2–1 shows an example of disassembled PPC60X data in the Hardware
display format.
1 2 3 4 5
Sample Address Hi_Data Lo_Data Mnemonics
---------------------------------------------------------------------394 -------- 60420001 7C5B03A6 ( ALT DATA )
396 0078404F -------- -------- ( 60X ADDRS )
397 007024C0 307F0344 419AFFF8 addic r3,r31,#344
007024C4 307F0344 419AFFF8 bc 12,26,007024BC
399 FFF00420 -------- -------- ( ALT ADDRS )
400 0078404F -------- ------00 ( DATA READ )
402 007024B8 -------- -------- ( 60X ADDRS )
403 -------- 746000A6 60633000 ( ALT DATA )
405 FFF00428 -------- -------- ( ALT ADDRS )
406 007024BC -------- 887F0000 lbz r3,#0(r31)
408 80000087 -------- -------- ( ALT ADDRS )
409 -------- 64630001 54630732 ( ALT DATA )
411 007024C0 F2FAFAFA FAFAFAFA ( 60X ADDRS AND ALT DATA )
412 007024C0 -------- -------- ( 60X ADDRS )
413 FFF00430 -------- -------- ( ALT ADDRS )
414 007024C0 307F0344 419AFFF8 addic r3,r31,#344
007024C4 307F0344 419AFFF8 bc 12,26,007024BC
416 0078404F -------- -------- ( 60X ADDRS )
417 -------- 74600124 4C00012C ( ALT DATA )
419 007024B8 -------- -------- ( 60X ADDRS )
420 0078404F -------- ------00 ( DATA READ )
422 FFF00430 -------- -------- ( ALT ADDRS )
423 007024B8 27030000 887F0000 dozi r24,r3,#0
007024BC 27030000 887F0000 lbz r3,#0(r31)
Figure 2–1: Disassembled data in the Hardware display format
1
Sample Column. Lists the memory locations for the acquired data.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Acquiring and Viewing Disassembled Data
2
Address Group. Lists data from channels connected to the PowerPC 60X
address bus.
3
Hi_Data Group. Lists data from channels connected to the PowerPC 60X
DH31-DH0 signals.
4
Lo_Data Group. Lists data from channels connected to the PowerPC 60X
DL31-DL0 signals.
5
Mnemonics Column. Lists the disassembled instructions and cycle types.
Software Display Format
Control Flow Display
Format
The Software display format shows only the first fetch of executed instructions.
Flushed cycles and extensions are not shown, even though they are part of the
executed instruction. Data reads and writes are not displayed.
The Control Flow display format shows only the first fetch of instructions that
change the flow of control.
Instructions that generate a change in the flow of control in the PowerPC 60X
microprocessor are as follows:
bblsc
ba bla rfi
Instructions that might generate a change in the flow of control in the PowerPC
60X microprocessor are as follows:
bc bcla bcctr tdi
bca bclr bcctrl tw
bcl bclrl td twi
The disassembler displays some instructions that cause traps or interrupts, as well
as exception vector reads that are taken and ( **BAD CYCLE TYPE** ).
Mnemonics misinterpreted by the disassembler are also displayed.
2–12
Subroutine Display
Format
The Subroutine display format shows only the first fetch of subroutine call and
return instructions. It will display conditional subroutine calls if they are
considered to be taken.
Instructions that generate a subroutine call or a return in the PowerPC 60X
microprocessor are as follows:
sc rfi
Instructions that might generate a subroutine call or a return in the PowerPC 60X
microprocessor are as follows:
td tdi tw twi
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 45
The disassembler displays some instructions that cause traps or interrupts, as well
as exception vector reads that are taken and ( **BAD CYCLE TYPE** ).
Mnemonics misinterpreted by the disassembler are also displayed.
Changing How Data is Displayed
There are common fields and features that allow you to further modify displayed
data to suit your needs. You can make common and optional display selections in
the Disassembly property page (the Disassembly Format Definition overlay).
You can make selections unique to the PowerPC 60X support to do the following
tasks:
H Change how data is displayed across all display formats
H Change the interpretation of disassembled cycles
H Display exception vectors
Acquiring and Viewing Disassembled Data
Optional Display
Selections
You can make optional selections for disassembled
common selections (described in the information on basic operations), you can
change the displayed data in the following ways:
H Select a bus configuration and the trace PPC60X microprocessor
H Select the prefetch byte order
H Select the alternate byte order low and high bounds
H Select the exception byte order
H Specify the exception prefix
You can include or exclude DRTRY cycles in the acquisition through the
DRTRY Cycles clocking option.
The PowerPC 60X microprocessor support product has six additional fields: Bus
Config/Proc Select, Prefetch Byte Ord, Alt-Byte Ord - Lo Bound, Alt-Byte Ord Hi Bound, Exception Byte Ord, and Exception Prefix. These fields appear in the
area indicated in the basic operations user manual.
Bus Config/Proc Select. The PPC60X microprocessor can support optional
configurations that are selected by the DRTRY*, TLBISYNC*, and QACK*
signals when the HRESET* is deasserted after you start the system.
data. In addition to the
You should select the bus configuration that matches the one in your PPC60Xbased system: 64-bit Data bus, or 32-Bit Data bus.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Acquiring and Viewing Disassembled Data
You can use either 64-bit configuration when your SUT is operating in 64–bit
mode. This is the default bus configuration.
You can also use either 32-Bit Data Bus configuration when your SUT is
operating in 32-bit mode. With this configuration, only the Hi_Data channels
corresponding to the DH31-DH0 signals are valid.
You can also select which PPC60X microprocessor to trace: MPC0 or MPC1.
The MPC0 is considered to be the microprocessor from which the BG* and
DBG* signals are acquired. All other microprocessors, including controllers, are
considered to be MPC1s.
Prefetch Byte Ord. You can select the byte ordering for the predominant instruction fetches as Big- or Little-Endian.
Alt Byte Ord - Lo Bound and Alt Byte Ord - Hi Bound. You can enter the low and
high bounds for the alternate byte ordering range. The default is 00000000.
You should enter alternate values on double-word boundaries. If the value is not
on a double-word boundary, the disassembler assumes the value to be the nearest
double-word.
If you do not enter a value in the field, the data is acquired and disassembled
according to the selection in the Prefetch Byte Ord field.
NOTE. The alternate high bound value must be greater than the alternate low
bound value or disassembly will be incorrect.
Exception Byte Ord. You can select the byte ordering for exception processing as
Big- or Little-Endian.
Exception Prefix. You can enter the prefix value of the exception table as 000 to
FFF. The default prefix value is FFF. The exception table must reside in external
memory for interrupt and exception cycles to be visible to the disassembler.
NOTE. If an address is in the Exception processing region and in the range
selected for the alternate byte ordering, the disassembler uses the byte ordering
selected for the Exception processing.
2–14
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Acquiring and Viewing Disassembled Data
Marking Cycles
The disassembler has a Mark Opcode function that allows you to change the
interpretation of a cycle type. Using this function, you can select a cycle and
change it.
The list of selections varies depending on the selection in the Bus Config/Proc
Select field in the Disassembly property page (Disassembly Format Definition
overlay).
Mark selections available on data sequences without an address and data cycle
associated with a fetch cycle when the PPC60X microprocessor is operating in
64-bit mode are as follows:
Opcode Opcode
Opcode Flush
Flush Opcode
Flush Flush
Incom_Data
Undo Mark
Mark selections available on data sequences without an address and data cycle
associated with a fetch cycle when the PPC60X microprocessor is operating in
32-bit mode are as follows:
Opcode
Flush
Incom_Data
Undo Mark
Mark selections available on sequences with only an Address cycle are as
follows:
Incom_Address
Undo Mark
Mark selections available on sequences with both data and address cycles (if the
data cyle is associated with a fetch cycle) and the PPC60X microprocessor is
operating in 64-bit mode are as follows:
Opcode Opcode
Opcode Flush
Flush Opcode
Flush Flush
Incom_Data
Incom_Address
Opcode Opcode Incom_Addrs
Opcode Flush Incom_Addrs
Flush Opcode Incom_Addrs
Flush Flush Incom_Addrs
Incom_Data Incom_Addrs
Undo Mark
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Acquiring and Viewing Disassembled Data
Mark selections available on sequences with both data and address cycles (if the
data cyle is associated with a fetch cycle) and the PPC60X microprocessor is
operating in 32-bit mode are as follows:
Opcode
Flush
Incom_Data
Incom_Address
Opcode Incom_Addrs
Flush Incom_Addrs
Incom_Data Incom_Addrs
Undo Mark
Mark selections available on sequences with data that is not associated with a
Fetch cycle are as follows:
Incom_Data
Undo Mark
Table 2–10 describes the various combinations of mark selections.
T able 2–10: Mark selections and definitions
Mark selection or combination[
Opcode Opcode
Opcode Flush
Flush Opcode
Flush Flush Instructions not disassembled and labeled as ( FLUSH )
Incom_Addrs Valid PPC60X address is invalidated and labeled as ( Incom_Addrs )
Opcode Opcode Incom_Addrs
Opcode Flush Incom_Addrs
Flush Opcode Incom_Addrs
Flush Flush Incom_Addrs Instructions not disassembled and labeled as ( FLUSH ); the address is invalidated
Opcode
Flush HI_Data and LO_Data are not disassembled and labeled as ( FLUSH )
Incom_Addrs
Definition
HI_Data and LO_Data are disassembled
Only HI_Data is disassembled in Big-Endian mode or only LO_Data is disassembled in
Little-Endian mode
Only LO_Data is disassembled in Big-Endian mode or only HI_Data is disassembled in
Little-Endian mode
Use to mark a sequence with PPC60X address and data from different transactions;
HI_Data and LO_Data are disassembled; the address is invalidated
HI_Data is disassembled only in Big-Endian mode or LO_Data is disassembled only in
Little-Endian mode; the address is invalidated
LO_Data is disassembled only in Big-Endian mode or HI_Data is disassembled only in
Little-Endian mode; the address is invalidated
HI_Data and LO_Data are disassembled
Address is invalidated
Opcode Incom_Addrs
Flush Incom_Addrs HI_Data and LO_Data are not disassembled and labeled as ( FLUSH ); the address
2–16
HI_Data and LO_Data are disassembled; the address is invalidated
is invalidated
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 49
T able 2–10: Mark selections and definitions (cont.)
Acquiring and Viewing Disassembled Data
Mark selection or combination[
[ Mark selections intended to be used on sequences with data are not available for non-instructions.
Definition
HI_Data and LO_Data are invalidated
Address, HI_Data, and LO_Data are invalidated
Removes all marks
The Incom_Addrs mark invalidates the address from being associated with the
wrong data. You can use this mark if you determine that the data for the address
was not acquired.
The Incom_Data mark invalidates the data from being associated with the wrong
address. You can use this mark if you determine that the address for the data was
not acquired.
Information on basic operations contains more details on marking cycles.
Displaying Exception
Labels
The disassembler can display PowerPC 60X exception labels. The exception
table must reside in external memory for interrupt and exception cycles to be
visible to the disassembler.
You can enter the table prefix in the Exception Prefix field. The Exception Prefix
field provides the disassembler with the offset address; enter a three-digit
hexadecimal value corresponding to the prefix of the exception table.
These fields are located in the Disassembly property page (Disassembly Format
Definition overlay).
Table 2–11 lists the PowerPC 60X interrupt and exception labels.
T able 2–11: Interrupt and exception labels
Exception
number
0 0x00000 ( RESERVED )
1 0x00100 ( SYSTEM RESET )
2 0x00200 ( MACHINE CHECK )
3 0x00300 ( DSI )
4 0x00400 ( ISI )
5 0x00500 ( EXTERNAL INTERRUPT )
6 0x00600 ( ALIGNMENT )
7 0x00700 ( PROGRAM )
Offset Displayed interrupt or exception name
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
2–17
Page 50
Acquiring and Viewing Disassembled Data
T able 2–11: Interrupt and exception labels (cont.)
Exception
number
8 0x00800 ( FLOATING-POINT UNAVAILABLE )
9 0x00900 ( DECREMENTER )
10 0x00A00 ( RESERVED )
11 0x00B00 ( RESERVED )
12 0x00C00 ( SYSTEM CALL )
13 0x00D00 ( TRACE )
14 0x00E00 ( FLOATING-POINT ASSIST )
15 0x00F00 ( PERF MONITORING INTRPT )
16 0x01000 ( INST TRANS MISS )
17 0x01100 ( DATA LOAD TRANS MISS )
18 0x01200 ( DATA TRANS MISS )
19 0x01300 ( INST ADDRESS BREAKPOINT )
20 0x01400 ( SYS MANAGEMENT INTERRUPT )
21-32 0x014FF to 0x02FFF ( RESERVED )
Displayed interrupt or exception nameOffset
Viewing an Example of Disassembled Data
A demonstration system file (or demonstration reference memory) is provided so
you can see an example of how your PowerPC 60X microprocessor bus cycles
and instruction mnemonics look when they are disassembled. Viewing the system
file is not a requirement for preparing the module for use and you can view it
without connecting the logic analyzer to your SUT.
Information on basic operations describes how to view the file.
2–18
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 51
Specifications
This chapter contains the following information:
H Probe adapter description
H Specification tables
H Dimensions of the probe adapter
H Channel assignment tables
H Description of how the module acquires PowerPC 60X signals
H List of other accessible microprocessor signals and extra probe channels
H Alphabetical list of signal names mapped to the PGA socket pin numbers for
Probe Adapter Description
The probe adapter is nonintrusive hardware that allows the logic analyzer to
acquire data from a microprocessor in its own operating environment with little
effect, if any, on that system. Information on basic operations contains a figure
showing the logic analyzer connected to a typical probe adapter. Refer to that
figure while reading the following description.
each type of PowerPC 60X microprocessor supported
The probe adapter consists of a circuit board and a socket for a PowerPC 60X
microprocessor. The probe adapter connects to the microprocessor in the SUT.
Signals from the microprocessor-based system flow from the probe adapter to the
channel groups and through the probe signal leads to the module.
All circuitry on the probe adapter is powered from the SUT.
Table 1–1 in the Getting Started chapter shows which microprocessors and their
packages the TMS 540 supports.
Specifications
These specifications are for a probe adapter connected between a compatible
Tektronix logic analyzer and a SUT. Table 3–1 shows the electrical requirements
the SUT must produce for the support to acquire correct data. Table 3–2 shows
the environmental specifications. Table 3–3 shows the certifications and
compliances that apply to the probe adapter.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
3–1
Page 52
Specifications
T able 3–1: Electrical specifications
Characteristics Requirements
Probe adapter power supply requirements
Voltage 90-265 VAC
Current 1.1 A maximum at 100 VAC
Frequency 47-63 Hz
Power 25 W maximum
SUT clock
Clock rate Max. 66 MHz
Specification
Measured typical SUT signal loading AC load DC load
SYSCLK, DBB*, TA*, TEA*, XATS*, ARTRY*, DRTRY* 21 pF 2 @ 74FCT162244ET
Remaining signals 14 pF 74FCT162244ET
T able 3–2: Environmental specifications*
Characteristic Description
Temperature
Maximum operating
Minimum operating 0° C (+32° F)
Non-operating –55° C to +75° C (–67° to +167° F)
Humidity 10 to 95% relative humidity
Altitude
Operating 4.5 km (15,000 ft) maximum
Non-operating 15 km (50,000 ft) maximum
Electrostatic immunity The probe adapter is static sensitive
* Designed to meet Tektronix standard 062-2847-00 class 5.
[
Not to exceed PowerPC 60X microprocessor thermal considerations. Forced air
cooling might be required across the CPU.
+50° C (+122° F)[
T able 3–3: Certifications and compliances
3–2
EC Compliance There are no current European Directives that apply to this product.
Figure 3–1 shows the dimensions of the probe adapter. The figure also shows the
minimum vertical clearance of the high-density probe cable.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 53
89 mm
(3.500 in)
Specifications
5 mm (.187 in)
79 mm
(3.125 in)
35.2 mm
(1.385 in)
25.4 mm
(1.000 in)
72.5 mm
(2.855 in)
112 mm
(4.420 in)
40 mm
(1.600 in)
40 mm
(1.600 in)
35 mm
(1.400 in)
35 mm
(1.400 in)
52.1 mm
(2.050 in)
43 mm
(1.700 in)
36.3 mm
(1.430 in)
6 mm (.240 in)
13 mm
(.520 in)
13 mm
(.520 in)
25.4 mm
(1.00 in)
7 mm (.26 in)
21 mm
(.850 in)
25.4 mm
(1.00 in)
7 mm (.26 in)
21 mm
(.850 in)
MPC601, PPC601
PGA–to-QFP Clip
MPC603, PPC603
PGA–to-QFP Clip
Figure 3–1: Dimensions of the probe adapter and converter clips
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
3–3
Page 54
Specifications
Channel Assignments
Channel assignments shown in Table 3–4 through Table 3–15 use the following
conventions:
H All signals are required by the support unless indicated otherwise.
H Channels are shown starting with the most significant bit (MSB) descending
to the least significant bit (LSB).
H Channel group assignments are for all modules unless otherwise noted.
H An asterisk following a signal name indicates an active low signal.
H An equals sign (=) following a signal name indicates that it is double probed.
H For the 192-channel module, the module in the higher-numbered slot is
referred to as the HI module and the module in the lower-numbered slot is
referred to as the LO module.
Table 3–4 shows the probe section and channel assignments for the Address
group, and the microprocessor signal to which each channel connects. The
default display radix is HEX.
3–4
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 55
T able 3–4: Address group channel assignments
Specifications
Bit
order
31 A3:7 LO_A3:7 A0
30 A3:6 LO_A3:6 A1
29 A3:5 LO_A3:5 A2
28 A3:4 LO_A3:4 A3
27 A3:3 LO_A3:3 A4
26 A3:2 LO_A3:2 A5
25 A3:1 LO_A3:1 A6
24 A3:0 LO_A3:0 A7
23 A2:7 LO_A2:7 A8
22 A2:6 LO_A2:6 A9
21 A2:5 LO_A2:5 A10
20 A2:4 LO_A2:4 A1 1
19 A2:3 LO_A2:3 A12
18 A2:2 LO_A2:2 A13
17 A2:1 LO_A2:1 A14
16 A2:0 LO_A2:0 A15
15 A2:7 LO_A1:7 A16
14 A1:6 LO_A1:6 A17
13 A1:5 LO_A1:5 A18
12 A1:4 LO_A1:4 A19
11 A1:3 LO_A1:3 A20
10 A1:2 LO_A1:2 A21
9 A1:1 LO_A1:1 A22
8 A1:0 LO_A1:0 A23
7 A0:7 LO_A0:7 A24
6 A0:6 LO_A0:6 A25
5 A0:5 LO_A0:5 A26
4 A0:4 LO_A0:4 A27
3 A0:3 LO_A0:3 A28
2 A0:2 LO_A0:2 A29
1 A0:1 LO_A0:1 A30
0 A0:0 LO_A0:0 A31
136-channel
section & probe
192-channel
section & probe
PowerPC 60X signal name
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
3–5
Page 56
Specifications
Table 3–5 shows the probe section and channel assignments for the Hi_Data
group, and the microprocessor signal to which each channel connects. By default,
this channel group is displayed in hexadecimal.
T able 3–5: Hi_Data group channel assignments
Bit
order
31 E3:7 HI_A3:7 DH0
30 E3:6 HI_A3:6 DH1
29 E3:5 HI_A3:5 DH2
28 E3:4 HI_A3:4 DH3
27 E3:3 HI_A3:3 DH4
26 E3:2 HI_A3:2 DH5
25 E3:1 HI_A3:1 DH6
24 E3:0 HI_A3:0 DH7
23 E2:7 HI_A2:7 DH8
22 E2:6 HI_A2:6 DH9
21 E2:5 HI_A2:5 DH10
20 E2:4 HI_A2:4 DH1 1
19 E2:3 HI_A2:3 DH12
18 E2:2 HI_A2:2 DH13
17 E2:1 HI_A2:1 DH14
16 E2:0 HI_A2:0 DH15
15 E1:7 HI_A1:7 DH16
14 E1:6 HI_A1:6 DH17
13 E1:5 HI_A1:5 DH18
12 E1:4 HI_A1:4 DH19
11 E1:3 HI_A1:3 DH20
10 E1:2 HI_A1:2 DH21
9 E1:1 HI_A1:1 DH22
8 E1:0 HI_A1:0 DH23
7 E0:7 HI_A0:7 DH24
6 E0:6 HI_A0:6 DH25
5 E0:5 HI_A0:5 DH26
4 E0:4 HI_A0:4 DH27
3 E0:3 HI_A0:3 DH28
2 E0:2 HI_A0:2 DH29
1 E0:1 HI_A0:1 DH30
0 E0:0 HI_A0:0 DH31
136-channel
section & probe
192-channel
section & probe
PowerPC 60X signal name
3–6
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 57
Specifications
Table 3–6 shows the probe section and channel assignments for the Lo_Data
group, and the microprocessor signal to which each channel connects. By default,
this channel group is displayed in hexadecimal.
T able 3–6: Lo_Data group channel assignments
Bit
order
31 D3:7 LO_D3:7 DL0
30 D3:6 LO_D3:6 DL1
29 D3:5 LO_D3:5 DL2
28 D3:4 LO_D3:4 DL3
27 D3:3 LO_D3:3 DL4
26 D3:2 LO_D3:2 DL5
25 D3:1 LO_D3:1 DL6
24 D3:0 LO_D3:0 DL7
23 D2:7 LO_D2:7 DL8
22 D2:6 LO_D2:6 DL9
21 D2:5 LO_D2:5 DL10
20 D2:4 LO_D2:4 DL11
19 D2:3 LO_D2:3 DL12
18 D2:2 LO_D2:2 DL13
17 D2:1 LO_D2:1 DL14
16 D2:0 LO_D2:0 DL15
15 D1:7 LO_D1:7 DL16
14 D1:6 LO_D1:6 DL17
13 D1:5 LO_D1:5 DL18
12 D1:4 LO_D1:4 DL19
11 D1:3 LO_D1:3 DL20
10 D1:2 LO_D1:2 DL21
9 D1:1 LO_D1:1 DL22
8 D1:0 LO_D1:0 DL23
7 D0:7 LO_D0:7 DL24
6 D0:6 LO_D0:6 DL25
5 D0:5 LO_D0:5 DL26
4 D0:4 LO_D0:4 DL27
3 D0:3 LO_D0:3 DL28
2 D0:2 LO_D0:2 DL29
1 D0:1 LO_D0:1 DL30
0 D0:0 LO_D0:0 DL31
136-channel
section & probe
192-channel
section & probe
PowerPC 60X signal name
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
3–7
Page 58
Specifications
Table 3–7 shows the probe section and channel assignments for the Control
group, and the microprocessor signal to which each channel connects. By default,
this channel group is displayed symbolically.
T able 3–7: Control group channel assignments
Bit
order
15 C3:0 LO_C3:0 XATS_B2* (Delayed XA TS*)
14 C2:2 LO_C2:2 TS*
13 C2:3 LO_C2:3 XATS*
12 C3:4 LO_C3:4 BG*
11 C1:4 HI_C3:4 DBG*
10 C1:6 HI_C3:6 ARTRY*
9 C1:2 HI_C3:2 DRTRY*
8 C2:1 LO_C2:1 AACK*
7 C2:0 LO_C2:0 ARTRY_ERLY* (ARTRY* sampled early to
6 C1:0 HI_C3:0 DRTRY_ERLY* (DRTRY* sampled early to
5 C0:6 HI_C2:6 TA*
4 C3:5 LO_C3:5 TEA*
3 C0:0 HI_C2:0 ARTRY_DATA* (ARTRY* sampled before TA*
2 C2:4 LO_C2:4 ABB*
1 C0:4 HI_C2:4 DBWO*
0 C2:5 LO_C2:5 DBB*
136-channel
section & probe
192-channel
section & probe
PowerPC 60X signal name
determine bus master)
determine bus master)
to determine bus master)
3–8
Table 3–8 shows the probe section and channel assignments for the Transfer
group, and the microprocessor signal to which each channel connects. By default,
this channel group is displayed symbolically.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 59
T able 3–8: Transfer group channel assignments
Specifications
Bit
order
5 C3:1 LO_C3:1 TT0
4 C0:7 HI_C2:7 TT1
3 C3:6 LO_C3:6 TT2
2 C3:7 LO_C3:7 TT3
1 C1:7 HI_C3:7 TC0
0 C0:5 HI_C2:5 GBL*
136-channel
section & probe
192-channel
section & probe
PowerPC 60X signal name
Table 3–9 shows the probe section and channel assignments for the Tsiz group,
and the microprocessor signal to which each channel connects. By default, this
channel group is not visible.
T able 3–9: Tsiz group channel assignments
Bit
order
3 C2:6 LO_C2:6 TSIZ0
2 C2:7 LO_C2:7 TSIZ1
1 C3:3 LO_C3:3 TSIZ2
0 C3:2 LO_C3:2 TBST*
136-channel
section & probe
192-channel
section & probe
PowerPC 60X signal name
Table 3–10 shows the probe section and channel assignments for the Misc group,
and the microprocessor signal to which each channel connects. By default, this
channel group is not visible.
T able 3–10: Misc group channel assignments
Bit
order
2 C1:1 HI_C3:1
1 C1:3 HI_C3:3
0 C1:5 HI_C3:5
[ Signal not required for disassembly.
] BR* signal on the PPC603 microprocessor; SHD* signal on the PPC601 microproces-
136-channel
section & probe
sor.
192-channel
section & probe
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
PowerPC 60X signal name
HRESET*[
SYSCLK[
BR_SHD*[]
3–9
Page 60
Specifications
Table 3–11 shows the probe section and channel assignments for the Com_60X
group, and the microprocessor signal to which each channel connects. By default,
this channel group is not visible.
T able 3–11: 192-channel: Com_60X group channel assignments
Bit
order
20 HI_D3:7
19 HI_D3:6
18 HI_D3:5
17 HI_D3:4
16 HI_D3:3
15 HI_D3:2
14 HI_D3:1
13 HI_D3:0
12 HI_D2:7
11 HI_D2:6
10 HI_D2:5
9 HI_D2:4
8 HI_D2:3
7 HI_D2:2
6 HI_D2:1
5 HI_D2:0
4 HI_D1:7
3 HI_D1:6
2 HI_D1:5
1 HI_D1:4
0 HI_D1:3
[ Signal not required for disassembly.
Section & probe PowerPC 60X signal name
DPE*[
DP7[
DP6[
DP5[
DP4[
DP3[
DP2[
DP1[
DP0[
RSRV*[
TC1[
WT*[
TT4[
SRESET*[
INT*[
APE*[
AP3[
AP2[
AP1[
AP0[
CI*[
3–10
Table 3–12 shows the probe section and channel assignments for the PPC601_4
group, and the microprocessor signal to which each channel connects. By default,
this channel group is not visible.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 61
T able 3–12: 192-channel: PPC601_4 group channel assignments
Bit
order
18 HI_D1:2
17 HI_D1:1
16 HI_D1:0
15 HI_D0:7
14 HI_D0:6
13 HI_D0:5
12 HI_D0:4
11 HI_D0:3
10 HI_D0:2
9 HI_D0:1
8 HI_D0:0
7 HI_C1:7
6 HI_C1:6
5 HI_C1:5
4 HI_C1:4
3 HI_C1:3
2 HI_C1:2
1 HI_C1:1
0 HI_C1:0
[ Signal not required for disassembly.
Section & probe PowerPC 60X signal name
SCAN_CTL[
SCAN_SIN[
SCAN_CLK[
SC_DRIVE[
CSE1[
CSE2[
CSE0[
BSCAN_EN*[
PCLK_EN*[
RESUME[
ESP_EN*[
RTC[
SYS_QUIESC*[
CKSTP_IN*[
QUIESC_REQ[
HP_SNP_REQ*[
SCAN_OUT[
RUN_NSTOP[
CKSTP_OUT*[
Specifications
Table 3–13 shows the probe section and channel assignments for the PPC603_4
group, and the microprocessor signal to which each channel connects. By default,
this channel group is not visible.
T able 3–13: 192-channel: PPC603_4 group channel
assignments
Bit
order
15 HI_C0:7
14 HI_C0:6
13 HI_C0:5
12 HI_C0:4
11 HI_C0:3
10 HI_C0:2
Section & probe PowerPC 60X signal name
DBDIS*[
TLBISYNC*[
TBEN[
QACK*[
QREQ*[
CSE[
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
3–11
Page 62
Specifications
T able 3–13: 192-channel: PPC603_4 group channel
assignments (cont.)
Bit
order
9 HI_C0:1
8 HI_C0:0
7 LO_C1:7
6 LO_C1:6
5 LO_C1:5
4 LO_C1:4
3 LO_C1:3
2 LO_C1:2
1 LO_C1:1
0 LO_C1:0
[ Signal not required for disassembly.
PowerPC 60X signal nameSection & probe
CLK_OUT[
TCK[
TRST*[
TMS[
TDO[
TDI[
CKSTP_OUT*=[
CKSTP_IN*=[
MCP*[
SMI*[
Table 3–14 shows the probe section and channel assignments for the PPC604
group, and the microprocessor signal to which each channel connects. By default,
this channel group is not visible.
T able 3–14: 192-channel: PPC604 group channel assignments
Bit
order
7 LO_C0:7
6 LO_C0:6
5 LO_C0:5
4 LO_C0:4
3 LO_C0:3
2 LO_C0:2
1 LO_C0:1
0 LO_C0:0 not connected
[ Signal not required for disassembly.
Section & probe PowerPC 60X signal name
TC2[
HAL TED[
ARRA Y_WR* [
RUN[
LSSD_MODE*[
L1_TSTCLK[
L2_TSTCLK[
Table 3–15 shows the probe section and channel assignments for the clock probes
(not part of any group), and the PowerPC 60X signal to which each channel
connects.
3–12
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 63
T able 3–15: Clock channel assignments (not a group)
Specifications
How Data is Acquired
Custom Clocking
136-channel
section & probe
CK:3 HI_CK:3, LO_CK:3 Clock (rising edge)
CK:2 HI_CK:2, LO_CK:2 Qual DBB*= (DBB*)
CK:1 HI_CK:1, LO_CK:1 Qual TA*= (TA*)
CK:0 HI_CK:0, LO_CK:0 Qual TEA*= (TEA*)
[ In an MPC601 or PPC601 SUT, connect the SYSCLK= signal to a 1X clock (such as the
BCLK_EN* signal). Refer to Requirements and Restrictions in the Getting Started
chapter for more detailed information on this clock.
192-channel
section & probe
Clock or Qual PowerPC 60X signal name
SYSCLK= (SYSCLK)[
This section explains how the module acquires PowerPC 60X signals using the
TMS 540 probe adapter and application. This part also provides additional
information on microprocessor signals accessible on or not accessible on the
probe adapter, and on extra acquisition channels available for you to use for
additional connections.
A special clocking program is loaded to the module every time you load the
PPC60X support. This special clocking is called Custom.
With Custom clocking, the module logs in signals from multiple groups of
channels at different times when they are valid on the PowerPC 60X bus. The
module then sends all the logged-in signals to the trigger machine and to the
acquisition memory of the module for storage.
In Custom clocking, the module clocking state machine (CSM) generates one
master sample for each microprocessor bus cycle, no matter how many clock
cycles are contained in the bus cycle.
Figure 3–2 shows one sample point and five master sample points.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
3–13
Page 64
Specifications
T1 T2 T3 T4 T5 T6
SYSCLK
TS*
TA*/TEA*
XATS*
Sample point
Master sample points
Figure 3–2: PowerPC 60X bus timing
T1 Clock Edge. The BG*, ABB*, and ARTRY* signals are logged in on this clock
edge.
T2 Clock Edge. The A31-A0, TT3-TT1, TSIZ2-TSIZ0, XATS*, TBST*, TS*,
TC0, SYSCLK, DBG*, DRTRY_ERLY*, DBWO*, and ARTRY_DATA* signals
are logged in on this clock edge.
T3 Clock Edge. The DH31-DH0, DL31-DL0, TEA*, TA*, TT0, DBB*, AACK*,
ARTRY*, DRTRY*, BR*, APE*, GBL*, BG*, ABB*, ARTRY_ERLY*, and
XATS_B2* signals are logged in on this clock edge. Signals logged in on the T2
clock edge are also logged in except the A31-A0 signals.
T4 Clock Edge. The A31-A0, TT3-TT1, TSIZ2-TSIZ0, XATS*, TBST*, TS*,
TC0, SYSCLK, DBG*, DRTRY_ERLY*, DBWO*, ARTRY_DATA*, BG*,
ABB*, ARTRY_ERLY*, and XATS_B2 signals are logged in on this clock edge.
3–14
Clocking Options
T5 Clock Edge. The A31-A0, TT3-TT1, TSIZ2-TSIZ0, XATS*, TBST*, TS*,
TC0, SYSCLK, DBG*, DRTRY_ERLY*, DBWO*, and ARTRY_DATA* signals
are logged in on this clock edge.
T6 Clock Edge. The DH31-DH0, DL31-DL0, TEA*, TA*, TT0, DBB*, AACK*,
ARTRY*, DRTRY*, BR*, APE*, GBL*, BG*, ABB*, ARTRY_ERLY*, and
XATS_B2* signals are logged in on this clock edge. Signals logged in on the T5
clock edge are also logged in except the A31-A0 signals.
The clocking algorithm for the PowerPC 60X microprocessor support has two
variations: DRTRY Cycles Included or DRTRY Cycles Excluded.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 65
DRTRY Cycles. When DRTRY Cycles are included, the clocking stores the cycle
right after the assertion of the TA* signal to check for the assertion of the
DRTRY* signal. When DRTRY Cycles are excluded, the clocking will not store
the cycle right after the assertion of the TA* signal to check for the assertion of
the DRTRY* signal.
Alternate Microprocessor Connections
You can connect to microprocessor signals that are not required by the support so
that you can do more advanced timing analysis. These signals might or might not
be accessible on the probe adapter board. The following paragraphs and tables
list signals that are or are not accessible on the probe adapter board.
For a list of signals required or not required for disassembly, refer to the channel
assignment tables beginning on page 3–4. Remember that these channels are
already included in a channel group. If you do connect these channels to other
signals, you should set up another channel group for them.
Specifications
Signals Not On the Probe
Adapter
The probe adapter does not provide access for the following MPC601 or PPC601
microprocessor signals:
H BLK_EN*
H 2X_PCLK
H BR*
The probe adapter also does not provide access to the Reserved pins (three) or to
the Test pins (twenty).
The probe adapter does not provide access for the following MPC603 or PPC603
microprocessor signals:
H AVDD
H PLL_CFG0
H PLL_CFG1
H PLL_CFG2
H PLL_CFG3
Extra Channels
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Table 3–16 lists extra sections and channels that are left after you have connected
all the probes used by the support. You can use these extra channels to make
alternate SUT connections.
3–15
Page 66
Specifications
Channels not defined in a channel group by the TMS 540 software are logged in
with the Master sample point.
T able 3–16: Extra module sections and channels
Module Section: channels
136-channels Qual:3-0
192-channels None
These channels are not defined in any channel group and data acquired from
them is not displayed. To display data, you will need to define a channel group.
PPC60X Microprocessor Signal Names to PGA Socket Pin Numbers
You might want to connect to signals with other equipment, such as an oscilloscope, while analyzing activity in your SUT. You can connect to PPC60X
microprocessor signals through the PGA socket on the probe adapter board since
it does not have a microprocessor installed in it.
Table 3–17 shows PPC60X signal names and pin number connections between
the PGA socket on the probe adapter and the various PPC60X microprocessors.
T able 3–17: PGA socket pin numbers to PPC60X signal names
PGA socket Microprocessor pin number
PPC60X signal PGA pin no. MPC601/PPC601 MPC603/PPC603
A0 G5 18 179 225
A1 G4 19 2 4
A2 H3 21 178 223
A3 H2 22 3 6
A4 H5 23 176 221
A5 J1 26 5 8
A6 J4 27 175 219
A7 J5 28 6 10
A8 J3 30 174 217
A9 K1 31 7 12
A10 K3 32 170 215
MPC604
[
3–16
A1 1 K4 34 11 14
A12 L4 35 169 213
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 67
Specifications
T able 3–17: PGA socket pin numbers to PPC60X signal names (cont.)
PGA socket Microprocessor pin number
PPC60X signal
A13 L3 36 12 16
A14 M3 41 168 211
A15 M2 42 13 18
A16 M4 43 166 209
A17 M1 45 15 20
A18 N3 46 165 207
A19 N2 47 16 22
A20 N4 49 164 205
A21 N1 50 17 24
A22 P3 51 160 203
A23 P1 54 21 26
MPC603/PPC603MPC601/PPC601PGA pin no.
MPC604
[
A24 P4 55 159 201
A25 P5 56 22 28
A26 Q5 58 158 199
A27 Q2 59 23 30
A28 Q4 60 151 191
A29 Q1 62 30 38
A30 R3 63 144 182
A31 R5 64 37 47
AACK* E6 295 28 36
ABB* E21 224 36 45
AP0 R1 67 231 295
AP1 S4 68 230 294
AP2 R2 69 227 292
AP3 S1 71 226 290
APE* C17 231 218 276
ARRA Y_WR* C10 --- --- 271
ARTRY* F21 221 32 42
BG* A5 298 27 35
BR* A17 --- 219 278
BSCAN_EN* D5 299 --- ---
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
3–17
Page 68
Specifications
T able 3–17: PGA socket pin numbers to PPC60X signal names (cont.)
PGA socket Microprocessor pin number
PPC60X signal
CI* F18 216 237 304
CKSTP_IN* A13 258 --- --CKSTP_IN* D11 --- 215 266
CKSTP_OUT* D10 --- 216 267
CKSTP_OUT* S3 72 --- --CLK_OUT B10 --- 221 280
CSE B8 --- 225 --CSE0 G17 215 --- 288
CSE1 G18 211 --- 287
CSE2 G21 212 --- --DBB* F17 220 145 184
MPC603/PPC603MPC601/PPC601PGA pin no.
MPC604
[
DBDIS* L21 --- 153 193
DBG* E5 300 26 34
DBWO* C5 297 25 32
DH0 U14 127 115 147
DH1 W13 126 114 145
DH2 T13 125 113 143
DH3 S13 123 110 142
DH4 U13 122 109 140
DH5 W12 121 108 138
DH6 S12 119 99 126
DH7 V12 118 98 124
DH8 U11 112 97 122
DH9 W10 111 94 121
DH10 T10 110 93 119
DH1 1 V10 108 92 117
DH12 U10 107 91 115
DH13 W9 106 90 114
3–18
DH14 T9 104 89 112
DH15 V9 103 87 110
DH16 T8 99 85 108
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 69
Specifications
T able 3–17: PGA socket pin numbers to PPC60X signal names (cont.)
PGA socket Microprocessor pin number
PPC60X signal
DH17 V8 98 84 107
DH18 U8 97 83 105
DH19 S8 95 82 103
DH20 W7 94 81 101
DH21 T7 93 80 100
DH22 V7 91 78 98
DH23 S7 90 76 96
DH24 U6 86 75 94
DH25 V6 85 74 93
DH26 T6 84 73 91
DH27 S6 83 72 89
MPC603/PPC603MPC601/PPC601PGA pin no.
MPC604
[
DH28 W5 82 71 87
DH29 U5 81 68 86
DH30 V5 80 67 84
DH31 S5 75 66 82
DL0 L19 188 143 180
DL1 M17 185 141 178
DL2 N21 182 140 176
DL3 N18 181 139 174
DL4 N17 180 135 172
DL5 N19 178 134 170
DL6 P19 173 133 168
DL7 Q21 172 131 166
DL8 Q20 169 130 164
DL9 Q19 168 129 162
DL10 R21 167 126 160
DL1 1 R17 165 125 158
DL12 R20 161 124 156
DL13 R19 159 123 154
DL14 S21 157 119 152
DL15 S19 155 118 150
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
3–19
Page 70
Specifications
T able 3–17: PGA socket pin numbers to PPC60X signal names (cont.)
PGA socket Microprocessor pin number
PPC60X signal
DL16 S17 151 117 148
DL17 T17 149 107 136
DL18 V17 148 106 135
DL19 U17 147 105 133
DL20 W17 145 102 131
DL21 T16 144 101 129
DL22 V16 143 100 128
DL23 S16 140 51 65
DL24 U16 139 52 67
DL25 V15 138 55 69
DL26 W15 136 56 71
MPC603/PPC603MPC601/PPC601PGA pin no.
MPC604
[
DL27 T15 135 57 73
DL28 S15 134 58 75
DL29 U15 132 62 77
DL30 W14 131 63 79
DL31 T14 130 64 81
DP0 H19 203 38 49
DP1 J21 202 40 51
DP2 J18 201 41 53
DP3 J20 199 42 55
DP4 J19 198 46 57
DP5 K21 197 47 59
DP6 K17 195 48 61
DP7 K20 194 50 63
DPE* E19 222 217 274
DRTRY* B6 292 156 197
ESP_EN* B9 275 --- --GBL* C16 233 1 2
3–20
HAL TED C12 --- --- 269
HP_SNP_REQ* B14 250 --- --HRESET* C8 279 214 265
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 71
Specifications
T able 3–17: PGA socket pin numbers to PPC60X signal names (cont.)
PGA socket Microprocessor pin number
PPC60X signal
INT* D12 262 188 234
L1_TSTCLK C7 --- 204 255
L2_TSTCLK E3 --- 203 254
LSSD_MODE* A7 --- 205 256
MCP* A15 --- 186 232
PCLK_EN* B7 285 --- --QACK* D7 --- 235 --QREQ* L2 --- 31 --QUIESC_REQ E12 256 --- --RESUME D9 277 --- --RSRV* C13 254 232 297
MPC603/PPC603MPC601/PPC601PGA pin no.
MPC604
[
RTC A10 273 --- --RUN D8 --- --- 270
RUN_NSTOP S2 74 --- --SC_DRIVE H17 210 --- --SCAN_CLK M21 187 --- --SCAN_CTL M20 184 --- --SCAN_OUT T5 78 --- --SCAN_SIN M18 186 --- --SHD* A17 235 --- --SMI* E18 --- 187 233
SRESET* C11 264 189 236
SYS_QUIESC* B12 260 --- --SYSCLK E10 271 212 263
TA* E13 290 155 195
TBEN A6 --- 234 299
TBST* E16 236 192 241
TC0 E15 243 224 285
TC1 E14 251 223 283
TC2 C14 --- --- 281
TCK A11 --- 201 252
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
3–21
Page 72
Specifications
T able 3–17: PGA socket pin numbers to PPC60X signal names (cont.)
PGA socket Microprocessor pin number
PPC60X signal
TDI B13 --- 199 250
TDO D13 --- 198 248
TEA* E7 291 154 194
TLBISYNC* C6 --- 233 --TMS A12 --- 200 251
TRST* A9 --- 202 253
TS* H20 226 149 187
TSIZ0 B15 241 197 246
TSIZ1 B17 232 196 245
TSIZ2 B16 237 195 243
TT0 E17 228 191 239
MPC603/PPC603MPC601/PPC601PGA pin no.
MPC604
[
TT1 E20 227 190 238
TT2 D14 248 185 231
TT3 D15 244 184 229
TT4 D16 238 180 227
WT* F20 214 236 302
XA TS* D17 229 150 189
[
Pin information included for general purpose probing.
Figure 3–3 shows the PGA socket on the probe adapter with the grid row and
column labels for the pin numbers.
3–22
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 73
123456789101112131415161718192021
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
T
U
V
W
Specifications
Figure 3–3: Grid row and column labels for the pin numbers on the PGA socket
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
3–23
Page 74
Maintenance
This chapter contains information on the following topics:
H Probe adapter circuit description
H How to replace a fuse
Probe Adapter Circuit Description
The probe adapter contains many 74FCT162244 devices that buffer all acquired
signals. These devices have a chip-to-chip skew of 2 ns.
Replacing Signal Leads
Information on basic operations describes how to replace signal leads (individual
channel and clock probes).
Replacing Protective Sockets
Information on basic operations describes how to replace protective sockets.
Replacing the Fuse
If the fuse on the PowerPC 60X probe adapter opens (burns out), you can replace
it with a 5 A, 125 V fuse. Figure 4–1 shows the location of the fuse on the probe
adapter.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
4–1
Page 75
Maintenance
Fuse
Figure 4–1: Location of the fuse
4–2
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 76
Replaceable Electrical Parts
This chapter contains a list of the replaceable electrical components for the
TMS 540 PowerPC 60X microprocessor support. Use this list to identify and
order replacement parts.
Parts Ordering Information
Replacement parts are available through your local Tektronix field office or
representative.
Changes to Tektronix products are sometimes made to accommodate improved
components as they become available and to give you the benefit of the latest
improvements. Therefore, when ordering parts, it is important to include the
following information in your order:
H Part number
H Instrument type or model number
H Instrument serial number
H Instrument modification number, if applicable
If you order a part that has been replaced with a different or improved part, your
local Tektronix field office or representative will contact you concerning any
change in part number.
Change information, if any, is located at the rear of this manual.
Using the Replaceable Electrical Parts List
The tabular information in the Replaceable Electrical Parts List is arranged for
quick retrieval. Understanding the structure and features of the list will help you
find all of the information you need for ordering replacement parts. The
following table describes each column of the electrical parts list.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
5–1
Page 77
Replaceable Electrical Parts
Parts list column descriptions
Column Column name Description
1 Component number The component number appears on diagrams and circuit board illustrations, located in the diagrams
section. Assembly numbers are clearly marked on each diagram and circuit board illustration in the
Diagrams section, and on the mechanical exploded views in the Replaceable Mechanical Parts list
section. The component number is obtained by adding the assembly number prefix to the circuit
number (see Component Number illustration following this table).
The electrical parts list is arranged by assemblies in numerical sequence (A1, with its subassemblies
and parts, precedes A2, with its subassemblies and parts).
Chassis-mounted parts have no assembly number prefix, and they are located at the end of the
electrical parts list.
2 Tektronix part number Use this part number when ordering replacement parts from Tektronix.
3 and 4 Serial number Column three indicates the serial number at which the part was first effective. Column four indicates
the serial number at which the part was discontinued. No entry indicates the part is good for all serial
numbers.
5 Name & description An item name is separated from the description by a colon (:). Because of space limitations, an item
name may sometimes appear as incomplete. Use the U.S. Federal Catalog handbook H6-1 for
further item name identification.
6 Mfr. code This indicates the code number of the actual manufacturer of the part.
7 Mfr. part number This indicates the actual manufacturer’s or vendor’s part number.
Abbreviations
Component Number
List of Assemblies
Chassis Parts
Mfr. Code to Manufacturer
Cross Index
Abbreviations conform to American National Standard ANSI Y1.1–1972.
Component number
A23A2R1234 A23 R1234
Assembly number Circuit number
Read: Resistor 1234 (of Subassembly 2) of Assembly 23
A2
Subassembly number
(optional)
A list of assemblies is located at the beginning of the electrical parts list. The
assemblies are listed in numerical order. When a part’s complete component
number is known, this list will identify the assembly in which the part is located.
Chassis-mounted parts and cable assemblies are located at the end of the
Replaceable Electrical Parts List.
The table titled Manufacturers Cross Index shows codes, names, and addresses of
manufacturers or vendors of components listed in the parts list.
5–2
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 78
Replaceable Electrical Parts
Manufacturers cross index
Mfr.
code
TK0875 MATSUO ELECTRONICS INC 831 S DOUBLAS ST EL SEGUNDO CA 92641
04222 A VX/KYOCERA
50434 HEWLETT–P ACKARD CO
61772 INTEGRA TED DEVICE TECHNOLOGY 3236 SCOTT BLVD SANTA CLARA CA 95051
80009 TEKTRONIX INC 14150 SW KARL BRAUN DR
Manufacturer Address City, state, zip code
DIV OF AVX CORP
OPTOELECTRONICS DIV
19TH AVE SOUTH
P O BOX 867
370 W TRIMBLE RD SAN JOSE CA 95131–1008
PO BOX 500
MYRTLE BEACH SC 29577
BEAVERT ON OR 97077–0001
Replaceable electrical parts list
Component
number
A1 671–3566–00 CKT BD ASSY:PGA–321 SOCKETED 80009 671356600
A1C120 283–5114–00 CAP,FXD,CERAMIC:MLC;0.1UF,10%,50V,X7R,1206 04222 12065C104KAT(1A
A1C130 283–5114–00 CAP,FXD,CERAMIC:MLC;0.1UF,10%,50V,X7R,1206 04222 12065C104KAT(1A
A1C140 283–5114–00 CAP,FXD,CERAMIC:MLC;0.1UF,10%,50V,X7R,1206 04222 12065C104KAT(1A
A1C150 283–5114–00 CAP,FXD,CERAMIC:MLC;0.1UF,10%,50V,X7R,1206 04222 12065C104KAT(1A
A1C200 283–5114–00 CAP,FXD,CERAMIC:MLC;0.1UF,10%,50V,X7R,1206 04222 12065C104KAT(1A
A1C210 283–5114–00 CAP,FXD,CERAMIC:MLC;0.1UF,10%,50V,X7R,1206 04222 12065C104KAT(1A
A1C250 283–5114–00 CAP,FXD,CERAMIC:MLC;0.1UF,10%,50V,X7R,1206 04222 12065C104KAT(1A
A1C350 283–5114–00 CAP,FXD,CERAMIC:MLC;0.1UF,10%,50V,X7R,1206 04222 12065C104KAT(1A
A1C400 283–5114–00 CAP,FXD,CERAMIC:MLC;0.1UF,10%,50V,X7R,1206 04222 12065C104KAT(1A
A1C450 283–5114–00 CAP,FXD,CERAMIC:MLC;0.1UF,10%,50V,X7R,1206 04222 12065C104KAT(1A
A1C530 283–5114–00 CAP,FXD,CERAMIC:MLC;0.1UF,10%,50V,X7R,1206 04222 12065C104KAT(1A
A1C540 283–5114–00 CAP,FXD,CERAMIC:MLC;0.1UF,10%,50V,X7R,1206 04222 12065C104KAT(1A
A1C550 283–5114–00 CAP,FXD,CERAMIC:MLC;0.1UF,10%,50V,X7R,1206 04222 12065C104KAT(1A
A1C630 290–5005–00 CAP,FXD,TANT:;47UF,10%,10V,5.8MM X 4.6MM TK0875 267M–1002–476–K
A1C655 290–5005–00 CAP,FXD,TANT:;47UF,10%,10V,5.8MM X 4.6MM TK0875 267M–1002–476–K
A1CR630 152–5045–00 DIODE,SIG:SCHTKY,;20V,1.2PF,24 OHM 50434 HSMS–2810–T31
A1J335 ––––––––––– SOCKET PGA:PCB,321 POS 21 X 21 SHORT PINS
A1F610 159–0059–00 FUSE,WIRE LEAD:5A,125V ,
A1U120 156–6982–00 IC,DIGITAL:FCTCMOS,BUFFER;16–BIT,RESISTOR TERMINATED
A1U130 156–6982–00 IC,DIGITAL:FCTCMOS,BUFFER;16–BIT,RESISTOR TERMINATED
Tektronix
part number
Serial no.
effective
Serial no.
discont’d
Name & description
(SEE RMPL)
(F610)
OUTPUTS,3–STATE,SPECIALLY TESTED
OUTPUTS,3–STATE,SPECIALLY TESTED
Mfr.
code
61857 SPI–5A
61772 SCD5439
61772 SCD5439
Mfr. part number
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
5–3
Page 79
Replaceable Electrical Parts
Replaceable electrical parts list (cont.)
Component
number
A1U140 156–6982–00 IC,DIGITAL:FCTCMOS,BUFFER;16–BIT,RESISTOR TERMINATED
A1U150 156–6982–00 IC,DIGITAL:FCTCMOS,BUFFER;16–BIT,RESISTOR TERMINATED
A1U200 156–6982–00 IC,DIGITAL:FCTCMOS,BUFFER;16–BIT,RESISTOR TERMINATED
A1U250 156–6982–00 IC,DIGITAL:FCTCMOS,BUFFER;16–BIT,RESISTOR TERMINATED
A1U300 156–6982–00 IC,DIGITAL:FCTCMOS,BUFFER;16–BIT,RESISTOR TERMINATED
A1U350 156–6982–00 IC,DIGITAL:FCTCMOS,BUFFER;16–BIT,RESISTOR TERMINATED
A1U400 156–6982–00 IC,DIGITAL:FCTCMOS,BUFFER;16–BIT,RESISTOR TERMINATED
A1U450 156–6982–00 IC,DIGITAL:FCTCMOS,BUFFER;16–BIT,RESISTOR TERMINATED
A1U530 156–6982–00 IC,DIGITAL:FCTCMOS,BUFFER;16–BIT,RESISTOR TERMINATED
A1U540 156–6982–00 IC,DIGITAL:FCTCMOS,BUFFER;16–BIT,RESISTOR TERMINATED
Tektronix
part number
Serial no.
effective
Serial no.
discont’d
Name & description
OUTPUTS,3–STATE,SPECIALLY TESTED
OUTPUTS,3–STATE,SPECIALLY TESTED
OUTPUTS,3–STATE,SPECIALLY TESTED
OUTPUTS,3–STATE,SPECIALLY TESTED
OUTPUTS,3–STATE,SPECIALLY TESTED
OUTPUTS,3–STATE,SPECIALLY TESTED
OUTPUTS,3–STATE,SPECIALLY TESTED
OUTPUTS,3–STATE,SPECIALLY TESTED
OUTPUTS,3–STATE,SPECIALLY TESTED
OUTPUTS,3–STATE,SPECIALLY TESTED
Mfr.
code
61772 SCD5439
61772 SCD5439
61772 SCD5439
61772 SCD5439
61772 SCD5439
61772 SCD5439
61772 SCD5439
61772 SCD5439
61772 SCD5439
61772 SCD5439
Mfr. part number
A1U550 156–6982–00 IC,DIGITAL:FCTCMOS,BUFFER;16–BIT,RESISTOR TERMINATED
OUTPUTS,3–STATE,SPECIALLY TESTED
61772 SCD5439
5–4
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 80
Replaceable Mechanical Parts
This chapter contains a list of the replaceable mechanical components for the
TMS 540 PowerPC 60X microprocessor support. Use this list to identify and
order replacement parts.
Parts Ordering Information
Replacement parts are available through your local Tektronix field office or
representative.
Changes to Tektronix products are sometimes made to accommodate improved
components as they become available and to give you the benefit of the latest
improvements. Therefore, when ordering parts, it is important to include the
following information in your order:
H Part number
H Instrument type or model number
H Instrument serial number
H Instrument modification number, if applicable
If you order a part that has been replaced with a different or improved part, your
local Tektronix field office or representative will contact you concerning any
change in part number.
Change information, if any, is located at the rear of this manual.
Using the Replaceable Mechanical Parts List
The tabular information in the Replaceable Mechanical Parts List is arranged for
quick retrieval. Understanding the structure and features of the list will help you
find all of the information you need for ordering replacement parts. The
following table describes the content of each column in the parts list.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
6–1
Page 81
Replaceable Mechanical Parts
Parts list column descriptions
Column Column name Description
1 Figure & index number Items in this section are referenced by figure and index numbers to the exploded view illustrations
that follow.
2 Tektronix part number Use this part number when ordering replacement parts from Tektronix.
3 and 4 Serial number Column three indicates the serial number at which the part was first effective. Column four
indicates the serial number at which the part was discontinued. No entries indicates the part is
good for all serial numbers.
5 Qty This indicates the quantity of parts used.
6 Name & description An item name is separated from the description by a colon (:). Because of space limitations, an
item name may sometimes appear as incomplete. Use the U.S. Federal Catalog handbook H6-1
for further item name identification.
7 Mfr. code This indicates the code of the actual manufacturer of the part.
8 Mfr. part number This indicates the actual manufacturer’s or vendor’s part number.
Abbreviations
Chassis Parts
Abbreviations conform to American National Standard ANSI Y1.1–1972.
Chassis-mounted parts and cable assemblies are located at the end of the
Replaceable Electrical Parts List.
Mfr. Code to Manufacturer
Cross Index
The table titled Manufacturers Cross Index shows codes, names, and addresses of
manufacturers or vendors of components listed in the parts list.
Manufacturers cross index
Mfr.
code
0B445 ELECTRI–CORD MFG CO INC 312 EAST MAIN ST WESTFIELD PA 16950
0LXM2 LZR ELECTRONICS INC 8051 CESSNA A VENUE GAITHERSBURG MD 20879
00779 AMP INC 2800 FULLING MILL
14310 AUL T INC 7300 BOONE AVENUE NORTH MINNEAPOLIS MN 55428
26742 METHODE ELECTRONICS INC 7447 W WILSON AVE CHICAGO IL 60656–4548
58050 TEKA PRODUCTS INC 45 SALEM ST PROVIDENCE RI 02907
61857 SAN–0 INDUSTRIAL CORP 91–3 COLIN DRIVE HOLBROOK NY 11741
80009 TEKTRONIX INC 14150 SW KARL BRAUN DR
Manufacturer Address City, state, zip code
HARRISBURG PA 17105
PO BOX 3608
BEAVERT ON OR 97077–0001
PO BOX 500
6–2
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 82
Replaceable Mechanical Parts
Replaceable mechanical parts list
Fig. &
index
number
1–0 010–0588–00 1 PROBE ADAPTER:PPC60X,PGA–321,SOCKETED;TMS 540 80009 010058800
Tektronix part
number
Serial no.
effective
Serial no.
discont’d
Qty Name & description
Mfr.
code
Mfr. part number
–1 174–3419–00 1 CA ASSY,SP:TLC,MICRO–STRIP;TLC,50 OHM,FEP,1.4NS, 13.0
L,100 POS,PLUG,LATCHING
(W730)
–2 174–3418–00 1 CA ASSY,RF:TLC,MICRO–STRIP;TLC,50 OHM,FEP,PROP
DELAY 1.4NS,12.0 L,100 POS,PLUG,LATCHING BOTH ENDS
(W830)
–3 131–4356–00 1 CONN,SHUNT:SHUNT/SHORTING,;FEMALE,1 X 2,0.1
CTR,0.63 H,BLK,W/HANDLE,JUMPER
(P300)
–4 131–1857–00 1 CONN,HDR:PCB,;MALE,STR,1 X 36,0.1 CTR,0.230
MLG X 0.100 TAIL,GOLD
(J300)
–5 671–3566–00 1 CKT BD ASSY:PGA–321 SOCKETED,389–2071–00 WI
RED
–6 136–1283–00 2 SOCKET ,PGA:PCB,321 POS,21 X 21,SHOR T PINS
(J335)
–7 103–0369–01 1 MPC603 SUPPORT:MOT MPC603 ADAPTER,QFP–240 REQ.
GENERIC PPC60X PROBE
103–0399–01 1 PPC603 SUPPORT:IBM PPC603 ADAPTER,QFP–240
REQ.GENERIC PPC60X PROBE
–8 103–0398–00 1 MPC601 SUPPORT:MOT MPC601 ADAPER,
QGP–304,REQ.GENERIC PPC60X PROBE
–9 131–5947–00 2 CONN,BOX:PCB,MICRO–STRIP;FEMALE,STR,100 POS,
0.05 CTR,W/GRD PLANE,0.320 H X 0.125 TAIL,
LATCHING,4 ROW,0.05 PCB,STAGGER
(J730,J830)
–10 159–0059–00 1 FUSE,WIRE LEAD:5A,125V,
(F610)
–11 131–5527–00 1 JACK,POWER DC:PCB,;MALE,RTANG,2MM PIN,11MM
H(0.433) X 3.5MM(0.137) TAIL,9MM(0.354) W,T
IN,W/SWITCH,DC PWR JACK,2.0 MM
(J510)
STANDARD ACCESSORIES
070–9829–00 1 MANUAL,TECH:INSTRUCTION,PPC60X,DISSASEMBLER,
TMS 540
070–9803–00 1 MANUAL, TECH:TLA 700 SERIES MICRO SUPPORT
INSTALLATION
119–5061–01 1 POWER SUPPLY:25W,5V 5A,CONCENTRIC
2MM,90–265V,47–63HZ (NOT SHOWN)
161–0104–00 1 CA ASSY,PWR:3,18 AWG,98 L,250V/10AMP,98 INCH,
RTANG,IEC320,RCPT X STR,NEMA 15–5P,W/CORD GRIP
00779 2–340014–5
00779 1–340014–0
26742 9618–302–50
58050 082–3644–SS10
80009 671356600
80009 136128300
80009 ORDER BY DESC
80009 ORDER BY DESC
80009 ORDER BY DESC
00779 121289–7
61857 SPI–5A
0LXM2 DJ005A
80009 070–9829–00
80009 070–9803–00
14310 SW106KA002F01
S3109 ORDER BY DE-
SCRIPTION
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
6–3
Page 83
Replaceable Mechanical Parts
Replaceable mechanical parts list (cont.)
Fig. &
index
number
Tektronix part
number
070–9802–00 1 MANUAL, TECH:BASIC OPS MICRO SUP ON DAS/TLA 500
161–0104–06 1 CA ASSY,PWR:3,1.0MM SQ,250V/10AMP,2.5 METER,
161–0104–07 1 CA ASSY,PWR:3,1.0MM SQ,240V/10AMP,2.5 METER,
161–0104–05 1 CA ASSY,PWR:3,1.0MM SQ,250V/10AMP,2.5 METER,
161–0167–00 1 CA ASSY,PWR:3,0.75MM SQ,250V/10AMP,2.5 METER,
Serial no.
effective
Serial no.
discont’d
Name & descriptionQty
OPTIONAL ACCESSORIES
SERIES LOGIC ANALYZERS
RTANG,IEC320,RCPT, EUROPEAN,SAFETY CONTROLLED
(OPT A1)
RTANG,IEC320,RCPT X 13A, FUSED, UK PLUG, (13A FUSE),
UNITED KINGDOM,SAFETY CONTROL (OPT A2)
RTANG,IEC320,RCPT, AUSTRALIA,SAFETY CONTROLLED
(OPT A3)
RTANG,IEC320,RCPT, SWISS,NO CORD GRIP, SAFETY
CONTROLLED (OPT A5)
Mfr.
Mfr. part number
code
80009 070–9802–00
S3109 ORDER BY DE-
SCRIPTION
S3109 ORDER BY DE-
SCRIPTION
S3109 ORDER BY DE-
SCRIPTION
S3109 ORDER BY DE-
SCRIPTION
6–4
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 84
Replaceable Mechanical Parts
1
2
11
3
10
9
8
4
5
6
7
Figure 1: PowerPC 60X probe adapter exploded view
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
6–5
Page 85
Replaceable Mechanical Parts
Replaceable mechanical parts list
Fig. &
index
number
2–0 010– 0582–00 1 ADAPTER,PROBE:192–CHANNEL,HIGH DENSITY PROBE 80009 010058200
–1 380–1095–00 1 HOUSING,HALF:UPPER,192 CHANNEL HIGH DENSITY
–2 211–0152–00 4 SCR,ASSEM WSHR:4–40 X 0.625,PNH,BRS,NP,POZ TK0435 ORDER BY DESC
–3 131–5947–00 2 CONN BOX:CPCB, MICRO–STRIP;FEMALE,STR,100 POS,0.05
–4 671–3395–00 1 CKT BD ASSY:192–CHANNELS,HIGH DENSITY PROBE 80009 671339500
Tektronix part
number
Serial no.
effective
Serial no.
discont’d
Qty Name & description
PROBE
CTR,W/GRD PLANE,0.320 H X 0.124 TAIL, LATCHING, 4 ROW,
0.05 PCB, STAGGER
(J150, J250)
Mfr.
code
80009 380109500
80009 131594700
Mfr. part number
–5 380–1096–00 1 HOUSING,HALF:LOWER,192 CHANNEL HIGH DENSITY
PROBE
–6 348–0070–01 2 PAD,CUSHIONING:2.03 X 0.69 X 0.18 SI RBR 85471 ORDER BY DESC
–7 131–4917–00 8 CONN,HDR CPCB,;MALE,STR,1 X 2,0.1 CTR,0.235 MLF X
0.110 TAIL,20 BOLD, TUBE, HIGH TEMP
(J300,J340J400,J440,J500,J640,J600)
–8 131–5267–00 5 CONN,HDR CPCB,;MALE,STR,2 X 40.O.1 CTR,0.234 MLG X
0.110 TAIL, 30 GOLD
(J310,J320,J330,J340,J350,J360,J370,J410,J420,J430,J450,J46
0,J470,J510,J520,J530,J550,J560,J570,J610,J620,J630,J650,J6
60,J670)
80009 380109600
53387 131491700
53387 131526700
6–6
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 86
Replaceable Mechanical Parts
1
2
8
7
6
3
4
5
Figure 2: 192-Channel High-Density Probe exploded view
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
6–7
Page 87
Index
Numbers
32-Bit bus configuration, 2–14
64-Bit bus configuration, 2–14
A
about this manual set, xi
acquiring data, 2–7
Address group
channel assignments, 3–4
display column, 2–12
address pipelining, 1–3
Alt Byte Ord - Hi Bound field, 2–14
Alt Byte Ord - Lo Bound field, 2–14
alternate connections
extra channel probes, 3–15
to other signals, 3–15
B
basic operations, where to find information, xi
Big-Endian byte order, 2–14
Bus Config/Proc Select field, 2–13
bus cycles
Address cycle types, 2–8
AR TRY, DRTRY, and Data Error, 2–10
Data cycle types, 2–9
Direct Store Access cycle types, 2–9
displayed general cycle types, 2–10
bus timing, 3–14
C
certifications, 3–1
channel assignments
192-channel module
Com_60X group, 3–10
PPC601_4 group, 3–10
PPC603_4 group, 3–11
PPC604 group, 3–12
Address group, 3–4
clocks, 3–12
Control group, 3–8
Hi_Data group, 3–6
Lo_Data group, 3–7
Misc group, 3–9
Transfer group, 3–8
T siz group, 3–9
channel groups, 2–1
clock channel assignments, 3–12
clock rate, 1–3
clocking, Custom, 2–1
how data is acquired, 3–13
clocking options
DR TRY Cycles, 2–2
field names, 2–2
how data is acquired, 3–14
Com_60X group, 192-channel module, channel
assignments, 3–10
compliances, 3–1
connections
no probe adapter, 1–11
136-channel module, 1–12
192-channel module, 1–14
other microprocessor signals, 3–15
probe adapter to SUT
MPC601 and PPC601 converter clip, 1–4
MPC603 and PPC603 converter clip, 1–4
Control Flow display format, 2–12
Control group
channel assignments, 3–8
symbol table, 2–3
Custom clocking, 2–1
DR TRY Cycles, 2–2
how data is acquired, 3–13
cycle types
Address, 2–8
AR TRY, 2–10
combined labels, 2–8
Data, 2–9
Data Error, 2–10
Direst Store Access, 2–9
DR TRY, 2–10
general, 2–10
D
data
acquiring, 2–7
disassembly formats
Control Flow, 2–12
Hardware, 2–8
Software, 2–12
Subroutine, 2–12
how it is acquired, 3–13
data display , changing, 2–13
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Index–1
Page 88
Index
demonstration file, 2–18
dimensions, probe adapter, 3–2
disassembled data
Address cycle types, 2–8
AR TRY, DRTRY, and Data Error cycle types, 2–10
Data cycle types, 2–9
Direct Store Access cycle types, 2–9
general cycle type definitions, 2–10
viewing, 2–7
viewing an example, 2–18
disassembler
definition, xi
logic analyzer configuration, 1–2
setup, 2–1
Disassembly Format Definition overlay, 2–13
Disassembly property page, 2–13
display formats
Control Flow, 2–12
Hardware, 2–8
Software, 2–12
special characters, 2–7
Subroutine, 2–12
DR TRY Cycles
clocking option, 2–2
how data is acquired, 3–15
E
electrical specifications, 3–1
environmental specifications, 3–1
Exception Byte Ord field, 2–14
exception labels, 2–17
Exception Prefix field, 2–14
F
fuse, replacing, 4–1
H
Hardware display format, 2–8
Address cycle types, 2–8
AR TRY, DRTRY, and Data Error cycle types, 2–10
Data cycle types, 2–9
Direct Store Access cycle types, 2–9
general cycle type definitions, 2–10
Hi_Data group
channel assignments, 3–6
display column, 2–12
high-density probe, connecting channels to, 1–9
I
installing hardware. See connections
J
Joined Address and Data, 2–2
L
leads (podlets), high-density probe. See connections
Little-Endian byte order, 2–14
Lo_Data group
channel assignments, 3–7
display column, 2–12
logic analyzer
configuration for disassembler, 1–2
software compatibility, 1–2
M
manual
conventions, xi
how to use the set, xi
Mark Cycle function, 2–15
Mark Opcode function, 2–15
marking cycles, definition of, 2–15
microprocessor
package types supported, 1–1
signals not accessible on probe adpter, 3–15
specific clocking and how data is acquired, 3–13
microprocessor signal names, pin number on socket on
probe adapter, 3–16
grid row and column labels, 3–23
Misc group, channel assignments, 3–9
Mnemonics display column, 2–12
MPC601 microprocessor, connection procedure, 1–4
MPC603 microprocessor, connection procedure, 1–4
MPC604 microprocessor support, application setup and
disassembler only, 1–3
P
PGA socket on probe adapter
grid row and column labels, 3–23
microprocessor signal names, 3–16
pipelining address, 1–3
Index–2
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 89
Index
power
for the probe adapter
applying, 1–19
removing, 1–20
SUT, 1–3
power adapter, 1–19
power jack, 1–20
PPC601 microprocessor, connection procedure, 1–4
PPC601_4 group, 192-channel module, channel
assignments, 3–10
PPC603 microprocessor, connection procedure, 1–4
PPC603_4 group, 192-channel module, channel
assignments, 3–11
PPC604 group, 192-channel module, channel assign-
ments, 3–12
PPC604 microprocessor support, application setup and
disassembler only, 1–3
Prefetch Byte Ord field, 2–14
probe adapter
circuit description, 4–1
clearance, 1–4
dimensions, 3–2
configuring, 1–3
hardware description, 3–1
not using one, 1–11
PGA socket
grid row and column labels, 3–23
microprocessor signal names, 3–16
replacing the fuse, 4–1
R
reference memory, 2–18
restrictions, 1–2
without a probe adapter, 1–11
service information, 4–1
setups, disassembler, 2–1
signals
active low sign, xii
extra channel probes, 3–15
Software display format, 2–12
special characters displayed, 2–7
specifications, 3–1
certifications, 3–1
channel assignments, 3–4
compliances, 3–1
electrical, 3–1
environmental, 3–1
mechanical (dimensions), 3–2
Subroutine display format, 2–12
support setup, 2–1
SUT, definition, xi
SUT power, 1–3
symbol table
Control channel group, 2–3
Transfer channel group, 2–4
Transfer Size channel group, 2–5
SYSCLK system requirements, 1–3
system file, demonstration, 2–18
T
terminology, xi
Transfer group
channel assignments, 3–8
symbol table, 2–4
Transfer Size group, symbol table, 2–5
T siz group, channel assignments, 3–9
V
S
Separated Address and Data, 2–2
viewing disassembled data, 2–7
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Index–3
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