There are no current European directives that
apply to this product. This product provides
cable and test lead connections to a test object of
electronic measuring and test equipment.
Warning
The servicing instructions are for use by
qualified personnel only. To avoid personal
injury, do not perform any servicing unless you
are qualified to do so. Refer to all safety
summaries prior to performing service.
Page 2
Copyright T ektronix, Inc. All rights reserved. Licensed software products are owned by Tektronix or its suppliers and are
protected by United States copyright laws and international treaty provisions.
Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the
Rights in T echnical Data and Computer Software clause at DFARS 252.227-7013, or subparagraphs (c)(1) and (2) of the
Commercial Computer Software – Restricted Rights clause at F AR 52.227-19, as applicable.
T ektronix products are covered by U.S. and foreign patents, issued and pending. Information in this publication supercedes
that in all previously published material. Specifications and price change privileges reserved.
Printed in the U.S.A.
T ektronix, Inc., P.O. Box 1000, Wilsonville, OR 97070–1000
TEKTRONIX and TEK are registered trademarks of T ektronix, Inc.
Page 3
SOFTWARE WARRANTY
T ektronix warrants that the media on which this software product is furnished and the encoding of the programs on
the media will be free from defects in materials and workmanship for a period of three (3) months from the date of
shipment. If a medium or encoding proves defective during the warranty period, T ektronix will provide a
replacement in exchange for the defective medium. Except as to the media on which this software product is
furnished, this software product is provided “as is” without warranty of any kind, either express or implied.
T ektronix does not warrant that the functions contained in this software product will meet Customer’s
requirements or that the operation of the programs will be uninterrupted or error-free.
In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration
of the warranty period. If T ektronix is unable to provide a replacement that is free from defects in materials and
workmanship within a reasonable time thereafter, Customer may terminate the license for this software product
and return this software product and any associated materials for credit or refund.
THIS WARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER WARRANTIES, EXPRESS
OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’
RESPONSIBILITY TO REPLACE DEFECTIVE MEDIA OR REFUND CUSTOMER’S PAYMENT IS
THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS
WARRANTY. TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT,
SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER
TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH
DAMAGES.
Page 4
HARDWARE WARRANTY
T ektronix warrants that the products that it manufactures and sells will be free from defects in materials and
workmanship for a period of one (1) year from the date of shipment. If a product proves defective during this
warranty period, T ektronix, at its option, either will repair the defective product without charge for parts and labor,
or will provide a replacement in exchange for the defective product.
In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration
of the warranty period and make suitable arrangements for the performance of service. Customer shall be
responsible for packaging and shipping the defective product to the service center designated by T ektronix, with
shipping charges prepaid. Tektronix shall pay for the return of the product to Customer if the shipment is to a
location within the country in which the T ektronix service center is located. Customer shall be responsible for
paying all shipping charges, duties, taxes, and any other charges for products returned to any other locations.
This warranty shall not apply to any defect, failure or damage caused by improper use or improper or inadequate
maintenance and care. T ektronix shall not be obligated to furnish service under this warranty a) to repair damage
resulting from attempts by personnel other than T ektronix representatives to install, repair or service the product;
b) to repair damage resulting from improper use or connection to incompatible equipment; c) to repair any
damage or malfunction caused by the use of non-T ektronix supplies; or d) to service a product that has been
modified or integrated with other products when the effect of such modification or integration increases the time
or difficulty of servicing the product.
THIS WARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER WARRANTIES, EXPRESS
OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’
RESPONSIBILITY TO REPAIR OR REPLACE DEFECTIVE PRODUCTS IS THE SOLE AND
EXCLUSIVE REMEDY PROVIDED TO THE CUST OMER FOR BREACH OF THIS WARRANTY.
TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT , SPECIAL,
INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER TEKTRONIX OR
THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.
Table 3–17: PGA socket pin numbers to PPC60X signal names 3–16. . . .
iv
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 9
General Safety Summary
Review the following safety precautions to avoid injury and prevent damage to
this product or any products connected to it. To avoid potential hazards, use this
product only as specified.
Only qualified personnel should perform service procedures.
While using this product, you may need to access other parts of the system. Read
the General Safety Summary in other system manuals for warnings and cautions
related to operating the system.
To Avoid Fire or
Personal Injury
Use Proper Power Cord. Use only the power cord specified for this product and
certified for the country of use.
Connect and Disconnect Properly . Do not connect or disconnect probes or test
leads while they are connected to a voltage source.
Ground the Product. This product is grounded through the grounding conductor
of the power cord. To avoid electric shock, the grounding conductor must be
connected to earth ground. Before making connections to the input or output
terminals of the product, ensure that the product is properly grounded.
Observe All Terminal Ratings. To avoid fire or shock hazard, observe all ratings
and marking on the product. Consult the product manual for further ratings
information before making connections to the product.
Do not apply a potential to any terminal, including the common terminal, that
exceeds the maximum rating of that terminal.
Use Proper AC Adapter. Use only the AC adapter specified for this product.
Do Not Operate Without Covers. Do not operate this product with covers or panels
removed.
Use Proper Fuse. Use only the fuse type and rating specified for this product.
Avoid Exposed Circuitry. Do not touch exposed connections and components
when power is present.
Do Not Operate With Suspected Failures. If you suspect there is damage to this
product, have it inspected by qualified service personnel.
Do Not Operate in Wet/Damp Conditions.
Do Not Operate in an Explosive Atmosphere.
Keep Product Surfaces Clean and Dry .
Provide Proper Ventilation. Refer to the manual’s installation instructions for
details on installing the product so it has proper ventilation.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
v
Page 10
General Safety Summary
Symbols and Terms
T erms in this Manual. These terms may appear in this manual:
WARNING. Warning statements identify conditions or practices that could result
in injury or loss of life.
CAUTION. Caution statements identify conditions or practices that could result in
damage to this product or other property.
T erms on the Product. These terms may appear on the product:
DANGER indicates an injury hazard immediately accessible as you read the
marking.
WARNING indicates an injury hazard not immediately accessible as you read the
marking.
CAUTION indicates a hazard to property including the product.
Symbols on the Product. The following symbols may appear on the product:
WARNING
High Voltage
Protective Ground
(Earth) T erminal
CAUTION
Refer to Manual
Double
Insulated
vi
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 11
Service Safety Summary
Only qualified personnel should perform service procedures. Read this Service
Safety Summary and the General Safety Summary before performing any service
procedures.
Do Not Service Alone. Do not perform internal service or adjustments of this
product unless another person capable of rendering first aid and resuscitation is
present.
Disconnect Power. To avoid electric shock, disconnect the main power by means
of the power cord or, if provided, the power switch.
Use Care When Servicing With Power On. Dangerous voltages or currents may
exist in this product. Disconnect power, remove battery (if applicable), and
disconnect test leads before removing protective panels, soldering, or replacing
components.
To avoid electric shock, do not touch exposed connections.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
vii
Page 12
Preface: Microprocessor Support Documentation
This instruction manual contains specific information about the TMS 540
PowerPC 60X microprocessor support package and is part of a set of information
on how to operate this product on compatible Tektronix logic analyzers.
If you are familiar with operating microprocessor support packages on the logic
analyzer for which the TMS 540 PowerPC 60X support was purchased, you will
probably only need this instruction manual to set up and run the support.
If you are not familiar with operating microprocessor support packages, you will
need to supplement this instruction manual with information on basic operations
to set up and run the support.
Information on basic operations of microprocessor support packages is included
with each product. Each logic analyzer has basic information that describes how
to perform tasks common to support packages on that platform. This information
can be in the form of online help, an installation manual, or a user manual.
This manual provides detailed information on the following topics:
HConnecting the logic analyzer to the system under test
Manual Conventions
HSetting up the logic analyzer to acquire data from the system under test
HAcquiring and viewing disassembled data
HUsing the probe adapter
This manual uses the following conventions:
HThe term disassembler refers to the software that disassembles bus cycles
into instruction mnemonics and cycle types.
HThe phrase “information on basic operations” refers to online help, an
installation manual, or a basic operations of microprocessor supports user
manual.
HIn the information on basic operations, the term XXX or P54C used in field
selections and file names must be replaced with PPC60X. This is the name of
the microprocessor in field selections and file names you must use to operate
the PowerPC 60X support.
HThe term system under test (SUT) refers to the microprocessor-based system
from which data will be acquired.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
ix
Page 13
Preface: Microprocessor Support Documentation
HThe term logic analyzer refers to the Tektronix logic analyzer for which this
product was purchased.
HThe term module refers to a 136-channel or a 192-channel module.
HPPC60X refers to all supported variations of the PowerPC 60X microproces-
sor unless otherwise noted.
HAn asterisk (*) following a signal name indicates an active low signal.
Logic Analyzer Documentation
A description of other documentation available for each type of Tektronix logic
analyzer is located in the corresponding module user manual. The manual set
provides the information necessary to install, operate, maintain, and service the
logic analyzer and associated products.
Contacting Tektronix
Product
Support
Service
Support
For other
information
To write usTektronix, Inc.
For application-oriented questions about a Tektronix measurement product, call toll free in North America:
1-800-TEK-WIDE (1-800-835-9433 ext. 2400)
6:00 a.m. – 5:00 p.m. Pacific time
Or, contact us by e-mail:
tm_app_supp@tek.com
For product support outside of North America, contact your
local Tektronix distributor or sales office.
Contact your local Tektronix distributor or sales office. Or, visit
our web site for a listing of worldwide service locations.
http://www.tek.com
In North America:
1-800-TEK-WIDE (1-800-835-9433)
An operator will direct your call.
P.O. Box 1000
Wilsonville, OR 97070-1000
x
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 14
Getting Started
Support Description
This chapter provides information on the following topics and tasks:
HA description of the TMS 540 microprocessor support package
HLogic analyzer software compatibility
HYour system under test requirements
HSupport restrictions
HHow to connect to the system under test (SUT)
HHow to apply power to and remove power from the probe adapter
The TMS 540 microprocessor support package disassembles data from systems
that are based on Motorola MPC601, MPC603, and MPC604 microprocessors,
and IBM PPC601, PPC603 and PPC604 microprocessors. The Motorola
MPC604 and IBM PPC604 microprocessors are only supported through the
software setup and disassembler.
The support runs on a compatible Tektronix logic analyzer equipped with a
136-channel module or a 192-channel module.
Refer to information on basic operations to determine how many modules and
probes your logic analyzer needs to meet the minimum channel requirements for
the TMS 540 microprocessor support.
Table 1–1 shows the microprocessors and packages from which the TMS 540
support can acquire and disassemble data.
T able 1–1: Supported microprocessors
NamePackage
Motorola MPC601304-pin QFP
Motorola MPC603240-pin QFP
Motorola MPC604*304-pin QFP
IBM PPC601304-pin QFP
IBM PPC603240-pin QFP
IBM PPC604*304-pin QFP
*Contact Tektronix for availability of the MPC604 or PPC604 microprocessor support.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
1–1
Page 15
Getting Started
A complete list of standard and optional accessories is provided at the end of the
parts list in the Replaceable Mechanical Parts chapter.
To use this support efficiently, you need to have the items listed in the information on basic operations as well as the following documents:
HThe PowerPC System Architecture Manual, Mindshare, Inc.,1995
HThe PowerPC Microprocessor Family: The Programming Environments
tronics, and Motorola, Inc., 1993
HThe PowerPC 603 RISC Microprocessor Hardware Specification, IBM
Microelectronics, and Motorola, Inc., 1993
HThe PowerPC 604 RISC Microprocessor User’s Manual, IBM Microelec-
tronics, and Motorola, Inc., 1993
Information on basic operations also contains a general description of supports.
Logic Analyzer Software Compatibility
The label on the microprocessor support floppy disk states which version of logic
analyzer software the support is compatible with.
Logic Analyzer Configuration
To use the PowerPC 60X support, the Tektronix logic analyzer must be equipped
with either a 136-channel module, or a 192-channel module at a minimum. The
module must be equipped with enough probes to acquire channel and clock data
from signals in your PowerPC 60X-based system.
Refer to information on basic operations to determine how many modules and
probes the logic analyzer needs to meet the channel requirements.
Requirements and Restrictions
You should review the general requirements and restrictions of microprocessor
supports in the information on basic operations as they pertain to your SUT.
1–2
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 16
Getting Started
You should also review electrical, environmental, and mechanical specifications
in the Specifications chapter in this manual as they pertain to your system under
test, as well as the following descriptions of other PowerPC 60X support
requirements and restrictions.
System Clock Rate. The TMS 540 support can acquire data from the PowerPC
60X microprocessor at speeds of up to 66 MHz
1
.
SUT Power. Whenever the SUT is powered off, be sure to remove power from
the probe adapter. Refer to Applying and Removing Power at the end of this
chapter for information on how to remove power from the probe adapter.
PPC601 SYSCLK Signal. When connecting to a PPC601 microprocessor system
under test, the HI_C3:3, HI_CK3, and LO_CK3 podlets must connect to a 1X
clock. When using the TMS 540 product, the application assumes that the
BCLK_EN* signal is a 1X clock. If it is not, you must remove the jumper on
J300 on the probe adapter and connect a 1X clock to pin 2 of J300.
For the relationship between the clock and signals to be correct, you need to
compare the 1X clock to the TS* and TA* signals with a 200 MHz oscilloscope.
There should be 6 ns setup time between the assertion of TS* and TA* (going
low) and the rising clock edge of the 1X clock. To improve the clock trace, you
can add a small ferrite bead to the wire connecting the 1X clock to pin 2 of J300.
MPC604 and PPC604 Microprocessor Support. The Motorola MPC604 and IBM
PPC604 microprocessors are only supported through the application setup and
disassembler. You can, however, use a commercial test clip and the PPC60X
probe adapter to connect to the signals in you SUT. Refer to the connection
procedure beginning on page 1–11.
Address Pipelining. If address pipelining sustains for many sequences (approximately 1 K), there might be performance degradation when scrolling data by
entering a sequence number in the Cursor field.
If address pipelining sustains for additional sequences (1 K or greater), there
might be erroneous address and data association. You can use the Mark Cycles
function to correct the interpretation of erroneous address and data association.
Configuring the Probe Adapter
The probe adapter does not require any configuration.
1
Specification at time of printing. Contact your Tektronix sales representative for
current information on the fastest devices supported.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
1–3
Page 17
Getting Started
Connecting to a System Under Test
Before you connect to the SUT, you must connect the probes to the module.
Your SUT must also have a minimum amount of clear space surrounding the
microprocessor to accommodate the probe adapter. Refer to the Specifications
chapter in this manual for the required clearances.
The channel and clock probes shown in this chapter are for a 136-channel
module. The probes will look different if you are using a 192-channel module.
The general requirements and restrictions of microprocessor supports in the
information on basic operations shows the vertical dimensions of a channel or
clock probe connected to square pins on a circuit board.
MPC601, PPC601,
MPC603, and PPC603
Converter Clips
This procedure requires contact lubricant and thermal joint compound. To
connect the logic analyzer to a SUT using a QFP probe adapter and PGA-to-QFP
converter clip, follow these steps:
1. Turn off power to your SUT. It is not necessary to turn off the logic analyzer.
CAUTION. Static discharge can damage the microprocessor, the probe adapter,
the acquisition probes, or the module. To prevent static damage, handle all the
above only in a static-free environment.
Always wear a grounding wrist strap or similar device while handling the
microprocessor and probe adapter.
2. To discharge your stored static electricity, touch the ground connector located
on the back of the logic analyzer. Then, touch the black foam on the
underside of the probe adapter to discharge stored static electricity from the
probe adapter.
CAUTION. Failure to place the SUT on a horizontal surface before connecting the
probe adapter might permanently damage the pins on the microprocessor.
1–4
3. Place the SUT on a horizontal surface.
4. Use a magnifying glass to examine the pins of the microprocessor soldered
into the SUT. Check for the following characteristics:
a. The pins are cleanly soldered to the board without excess solder or
deformity.
b. The bends of the pins are uniform (consistent and even).
5. Apply contact lubricant to the pins of the converter clip to improve the
connection to the microprocessor.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 18
Getting Started
6. Check that the heat sink moves easily, and yet stays in position when not
being moved.
If the heat sink is very difficult to move or does not stay in position, you
need to adjust the friction of the O-ring in the PGA-to-QFP converter clip. To
adjust the friction, refer to Figure 1–1 and follow these steps:
a. If you have difficulty moving the heat sink, loosen each of the four
O-ring screws a little until the heat sink is moveable, and yet will stay in
position.
b. If the heat sink does not stay in position, tighten each of the four O-ring
screws a little until the heat sink is moveable, and yet will stay in
position.
CAUTION. Do not loosen or tighten the four screws closest to the corners of the
PGA-to-QFP converter clip. These are set by the manufacturer.
Do not adjust
outside screws
O-ring
adjustment
screws
Figure 1–1: Adjusting the friction of the O-ring in the converter clip
7. Pull up the heat sink on the converter clip to allow vertical clearance for the
microprocessor.
8. Apply a small amount of thermal joint compound to the end of the heat sink
that faces the microprocessor (the end that will contact the microprocessor).
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
1–5
Page 19
Getting Started
CAUTION. Failure to correctly place the PGA-to-QFP converter clip onto the
microprocessor might permanently damage the microprocessor and converter
clip once power is applied.
9. Line up the pin E1 indicator on the converter clip with the pin 1 indicator on
the microprocessor.
10. Place the converter clip onto the microprocessor as shown in Figure 1–2.
Center the clip on the microprocessor and press the clip down while slightly
rocking the clip.
PGA-to–QFP converter clip*
Pin E1
Microprocessor
Pin 1
SUT
Figure 1–2: Placing the PGA-to-QFP converter clip onto the microprocessor
11. Measure the resistance between Vcc and ground to verify that they are not
shorted together. If you detect a short, determine the source and repair the
problem before applying power (described at the end of this chapter).
12. If there are tie-down holes in your SUT that match the tie-down holes on the
converter clip, you can use screws to secure the clip (and probe adapter) to
the SUT.
Figure 1–3 shows the placement of the tie-down holes on the MPC601 or
PPC601 clips. Figure 1–4 shows the placement of the tie-down holes on the
MPC603 or PPC603 clips.
1–6
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 20
60 mm
(2.350 in)
Getting Started
53 mm
(2.080 in)
3 mm
(.135 in)
53 mm
(2.080 in)
Figure 1–3: Tie-down hole placement on the MPC601 or PPC601 converter clips
60 mm
(2.350 in)
46 mm
(1.800 in)
7 mm
(.275 in)
46 mm
(1.800 in)
Figure 1–4: Tie-down hole placement on the MPC603 or PPC603 converter clips
13. Gently press down and turn the heat sink in the converter clip until it just
makes contact with the microprocessor.
14. If you cannot secure the clip through tie-down holes and screws, you can use
a nonconductive retention device around the clip and SUT circuit board to
make sure the clip is secure. Figure 1–5 shows an example of this method.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
1–7
Page 21
Getting Started
Nonconductive
retention device
Figure 1–5: Using an alternate method to secure the PGA-to-QFP converter clip
CAUTION. Failure to correctly place the probe adapter onto the PGA-to-QFP
converter clip might permanently damage the microprocessor, probe adapter, and
clip once power is applied.
15. Remove the black foam from the underside of the probe adapter.
16. Line up the pin E1 indicator on the probe adapter with the pin E1 indicator
on the PGA-to-QFP clip.
17. Place the probe adapter onto the PGA-to-QFP clip as shown in Figure 1–6.
1–8
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 22
Getting Started
Pin E1
Pin 1
SUT
Pin E1
Probe adapter
PGA–to–QFP clip*
* Earlier versions of some clips might not have a heat sink.
Figure 1–6: Placing the probe adapter onto the PGA-to-QFP converter clip
18. Connect the clock and channel probes to the high-density probe as shown in
Figure 1–7. For the 192-channel module, match the channel groups and
numbers on the probe labels to the corresponding HI_ and LO_pins on the
high-density probe. Match the ground pins on the probes to the corresponding pins on the probe adapter.
For the 136-channel module, match the channel groups and numbers on the
probe labels to the corresponding LO_ pins on the high-density probe. There
are some exceptions; they are shown in Table 1–2.
T able 1–2: High-density probe exceptions for the 136-channel module
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
1–9
Page 23
Getting Started
Clock probe
Hold the channel probes by the podlet
holder when connecting them to the
high-density probe. Do not hold them
by the cables or necks of the podlets.
Channel probe
and podlet holder
Channels connect to
the logic analyzer
High-density probe
Figure 1–7: Connecting probes to a high-density probe
19. Align pin 1 on the LO cable connector, the end on the narrowest cable strip
of the cable, with pin 1 on the LO connector on the high-density probe.
Connect the cable to the connector as shown in Figure 1–8.
NOTE. The LO cable is 12 inches long; the HI cable is 13 inches long.
20. Align pin 1 on the HI cable connector, the end on the narrowest cable strip of
the cable, with pin 1 on the HI connector on the high-density probe. Connect
the cable to the connector as shown in Figure 1–8.
1–10
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 24
HI cable
Pin 1 side
Getting Started
Probe adapter
LO cable
SUT
High-density probe
Figure 1–8: Connecting cables to a high-density probe
Without a Probe Adapter
You can use channel probes, clock probes, and leadsets with a commercial test
clip (or adapter) to make connections between the logic analyzer and your SUT.
To connect the probes to PowerPC 60X signals in the SUT using a test clip,
follow these steps:
1. Turn off power to your SUT. It is not necessary to turn off power to the logic
analyzer.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
1–11
Page 25
Getting Started
CAUTION. Static discharge can damage the microprocessor, the probes, or the
module. To prevent static damage, handle all of the above only in a static-free
environment.
Always wear a grounding wrist strap or similar device while handling the
microprocessor.
2. To discharge your stored static electricity, touch the ground connector located
on the back of the logic analyzer. If you are using a test clip, touch any of the
ground pins on the clip to discharge stored static electricity from it.
CAUTION. Failure to place the SUT on a horizontal surface before connecting the
test clip might permanently damage the pins on the microprocessor.
3. Place the SUT on a horizontal static-free surface.
4. For the 136-channel module, use Tables 1–3 and 1–6 to connect the channel
and clock probes to PowerPC 60X signal pins on a test clip or in the SUT.
Use leadsets to connect at least one ground lead from each channel probe and
the ground lead from each clock probe to ground pins in your SUT or on
your test clip.
T able 1–3: 136-channel: PowerPC 60X connections for channel probes
Section:channel PowerPC 60X signal Section:channel PowerPC 60X signal
[TEA* is also probed by CK:0.
]Signal not required for disassembly.
wBR* signal on the 603 microprocessor; SHD* signal on the 601 microprocessor.
WSYSCLK* is also probed by CK:3.
#TA* is also probed by CK:1.
BR_SHD*]w
SYSCLK]W
HRESET*]
1–14
5. For the 192-channel module, use Tables 1–4, 1–5, and 1–6 to connect the HI
and LO module probes to PowerPC 60X signal pins on a test clip or in the
SUT.
For both modules, use leadsets to connect at least one ground lead from each
channel probe and the ground lead from each clock probe to ground pins in
your SUT or on your test clip.
Table 1–4 shows the 192-channel HI module probes and the PPC60X signals
to which they must connect for disassembly to be correct.
T able 1–4: 192-channel: PowerPC 60X connections for the HI module
Section:
channel
A3:7DH0D3:7
A3:6DH1D3:6
Connect to PPC60X signal
Section:
channel
Connect to PPC60X signal
DPE*[
DP7[
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 28
Getting Started
T able 1–4: 192-channel: PowerPC 60X connections for the HI module (cont.)
[Not required for disassembly.
]TEA* is also probed by HI_CLK:0 and LO_CLK:0.
wXATS* is also probed by HI_C2:3.
WDBB* is also probed by HI_CLK:2 and LO_CLK:2.
Connect to PPC60X signal
XA TS*w
DBB*W
XA TS*w
Section:
channel
C1:0
C0:5
C0:3
Connect to PPC60X signal
CKSTP_OUT*= (603 and 604) [
CKSTP_IN*= (603 and 604) [
MPC* (603 and 604) [
SMI* (603 and 604) [
TC2 (604) [
HAL TED (604) [
ARRA Y_WR* (604) [
RUN (604) [
LSSD_MODE* (603 and 604) [
L1_TSTCLK (603 and 604) [
L2_TSTCLK (603 and 604) [
#TS* is also probed by HI_C2:2.
%AACK* is also probed by HI_C2:1.
@ ARTY* is also probed by HI_C2:0, and HI_C3:6.
Table 1–6 shows the PowerPC 60X signals to which the clock channels must
connect for disassembly to be correct.
T able 1–6: PowerPC 60X connections for the clock channels
[In a 601 SUT, connect the SYSCLK= signal to a 1X clock (such as the BCLK_EN*
signal). Refer to Requirements and Restrictions in the Getting Started chapter for
more detailed information on this clock.
192-channel
section & probe
Clock or Qual PowerPC 60X signal name
SYSCLK=(SYSCLK)[
1–18
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 32
6. Align pin 1 of your test clip with the corresponding pin 1 of the microproces-
sor in your SUT and attach it to the microprocessor.
Refer to the channel assignment tables in the Specifications chapter to see the
signal-to-channel assignments.
Applying and Removing Power
A power supply for the PowerPC 60X probe adapter is included with the support.
The power supply provides +5 volts power to the probe adapter. The center
connector of the power jack connects to Vcc.
NOTE. Whenever the SUT is powered off, be sure to remove power from the probe
adapter.
To apply power to the PowerPC 60X probe adapter and SUT, follow these steps:
Getting Started
1. Measure the resistance between Vcc and ground to verify that they are not
shorted together.
If you detect a short, determine the source and repair the problem before
applying power.
CAUTION. Failure to use the +5 V power supply provided by Tektronix might
permanently damage the probe adapter and PowerPC 60X microprocessor. Do
not mistake another power supply that looks similar for the +5 V power supply.
2. Connect the +5 V power supply to the jack on the probe adapter. Figure 1–9
shows the location of the jack on the adapter board.
CAUTION. Failure to apply power to the probe adapter before applying power to
your SUT might permanently damage the PowerPC 60X microprocessor and
SUT.
3. Plug the power supply for the probe adapter into an electrical outlet. When
power is present on the probe adapter, an LED lights near the power jack.
4. Power on the SUT.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Getting Started
Power Jack
Figure 1–9: Location of the power jack
To remove power from the SUT and PowerPC 60X probe adapter, follow these
steps:
CAUTION. Failure to power down your SUT before removing the power from the
probe adapter might permanently damage the PowerPC 60X microprocessor and
SUT.
1. Power off the SUT.
2. Unplug the power supply for the probe adapter from the electrical outlet.
1–20
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Setting Up the Support
This section provides information on how to set up the support. Information
covers the following topics:
HChannel group definitions
HClocking options
HSymbol table files
Remember that the information in this section is specific to the operations and
functions of the TMS 540 PowerPC 60X support on any Tektronix logic analyzer
for which it can be purchased. Information on basic operations describes general
tasks and functions.
Before you acquire and disassemble data, you need to load the support and
specify setups for clocking and triggering as described in the information on
basic operations. The support provides default values for each of these setups,
but you can change them as needed.
Channel Group Definitions
Clocking Options
The software automatically defines channel groups for the support. The channel
groups for the PowerPC 60X microprocessor are Address, Hi_Data, Lo_Data,
Control, Transfer, Tsiz, Com_60X, PPC601_4, PPC603_4 , PPC604, Misc, and
Clock. If you want to know which signal is in which group, refer to the channel
assignment tables beginning on page 3–4.
The TMS 540 support offers a microprocessor-specific clocking mode for the
PowerPC 60X microprocessor. This clocking mode is the default selection
whenever you load the PPC60X support.
NOTE. For the PPC601 microprocessor, you might not acquire correct data when
you connect the HI:CK3 and LO:CK3 channels to the BCLK_EN* signal. Refer
to the description of the PPC601 SYSCLK signal under Requirements and
Restrictions in the Getting Started chapter.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Setting Up the Support
A description of how cycles are sampled by the module using the TMS 540
support and probe adapter is found in the Specifications chapter.
Disassembly will not be correct with the Internal or External clocking modes.
Information on basic operations describes how to use these clock selections for
general purpose analysis.
NOTE. An earlier version of this software had a clocking option in which you
could acquire data with Joined Address and Data, or Separated Address and
Data. Although this clocking option is no longer available, you can still use this
software to view data acquired with Joined or Separated address and data.
The clocking option for the TMS 540 application is DRTRY Cycles.
Symbols
DRTRY Cycles
You can include or exclude DRTRY Cycles. These types of cycles are acquired
when you select Included.
You must select to always acquire data after the TA signal goes true to test for the
DRTRY signal, or to skip the sample unless some other important signals are
valid at that time. If you include DRTRY cycles, and there is no DRTRY cycle or
no other valid informationat this time, then the cycle is labeled .
The TMS 540 application supplies three symbol table files. The symbol table
file replaces specific channel group values with symbolic values when the group
is displayed symbolically.
Table 2–1 shows the name, bit pattern, and meaning for the symbols in the
Control channel group symbol table. The Control group symbol table file name
is PPC60X_Ctrl.
2–2
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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T able 2–1: Control group symbol table definitions
ARTRY cycle and MPC0’s Data Error
ARTRY cycle and MPC1’s Data Error
ARTRY cycle and Data Retry
ARTRY cycle and MPC0’s Data
ARTRY cycle and MPC1’s Data
MPC0’s Address and MPC0’s Data Error
MPC0’s DSA packet 0 and MPC0’s Data Error
MPC0’s DSA packet 1 and MPC0’s Data Error
MPC0’s Address and MPC1’s Data Error
MPC0’s DSA packet 0 and MPC1’s Data Error
MPC0’s DSA packet 1 and MPC1’s Data Error
MPC1’s Address and MPC0’s Data Error
MPC1’s DSA packet 0 and MPC0’s Data Error
MPC1’s DSA packet 1 and MPC0’s Data Error
MPC1’s Address and MPC1’s Data Error
MPC1’s DSA packet 0 and MPC1’s Data Error
MPC1’s DSA packet 1 and MPC1’s Data Error
MPC0’s Address and Data retry
MPC0’s DSA packet 0 and Data retry
MPC0’s DSA packet 1 and Data retry
MPC1’s Address and Data retry
MPC1’s DSA packet 0 and Data retry
MPC1’s DSA packet 1 and Data retry
MPC0’s Address and Data
MPC0’s DSA packet 0 and Data
MPC0’s DSA packet 1 and Data
MPC0’s Address and MPC1’s Data
MPC0’s DSA packet 0 and MPC1’s Data
MPC0’s DSA packet 1 and MPC1’s Data
MPC1’s Address and MPC0’s Data
MPC1’s DSA packet 0 and MPC0’s Data
MPC1’s DSA packet 1 and MPC0’s Data
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Setting Up the Support
T able 2–1: Control group symbol table definitions (cont.)
MPC1’s Address and Data
MPC1’s DSA packet 0 and Data
MPC1’s DSA packet 1 and Data
MPC0’s Address cycle
MPC0’s DSA packet 0 cycle
MPC0’s DSA packet 1 cycle
MPC1’s Address cycle
MPC1’s DSA packet 0 cycle
MPC1’s DSA packet 1 cycle
MPC0’s Data Error
MPC1’s Data Error
DRTRY cycle
MPC0’s Data cycle
MPC1’s Data cycle
ARTRY cycle
Unknown cycle
2–4
Table 2–2 shows the name, bit pattern, and meaning for the symbols in the
Transfer channel group symbol table. The Transfer group symbol table file name
is PPC60X_Trans.
T able 2–2: Transfer group symbol table definitions
Transfer group value
TT0
TT1
Symbol
FETCH
READ
WRITE
ADDR_ONLY
UNKNOWN
TT2TC0
TT3GBL*
Meaning
Instruction Fetch cycle
Data Read cycle
Data Write cycle
Address only cycle
Unknown cycle
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Setting Up the Support
Table 2–3 shows the name, bit pattern, and meaning for the symbols in the the
Transfer Size channel group symbol table. The Transfer Size group symbol table
file name is PPC60X_Tsiz.
T able 2–3: Transfer Size group symbol table definitions
Transfer Size group value
TSIZ0
TSIZ1
Symbol
BURST
8BYTE
4BYTE
2BYTE
1BYTE
UNKNOWN
TSIZ2
TBST*
Meaning
Burst transfer
Eight byte transfer
Four byte transfer
Two byte transfer
One byte transfer
Unknown transfer size
Information on basic operations describes how to use symbolic values for
triggering and for displaying other channel groups symbolically, such as the
Address channel group.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Acquiring and Viewing Disassembled Data
This section describes how to acquire data and view it disassembled. Information
covers the following topics and tasks:
HAcquiring data
HViewing disassembled data in various display formats
HCycle type labels
HChanging the way data is displayed
HChanging disassembled cycles with the mark cycles function
Acquiring Data
Once you load the PPC60X support, choose a clocking mode, and specify the
trigger, you are ready to acquire and disassemble
If you have any problems acquiring data, refer to information on basic operations
in your online help or Appendix A: Error Messages and Disassembly Problems in
the basic operations user manual.
data.
Viewing Disassembled Data
You can view disassembled data in four display formats: Hardware, Software,
Control Flow, and Subroutine. The information on basic operations describes
how to select the disassembly display formats.
NOTE. Selections in the Disassembly property page (the Disassembly Format
Definition overlay) must be set correctly for your acquired data to be disassembled correctly. Refer to Changing How Data is Displayed on page 2–13.
The default display format shows the Address, Data, Control, Transfer, and Tsiz
channel group values for each sample of acquired data.
The disassembler displays special characters and strings in the instruction
mnemonics to indicate significant events. Table 2–4 shows these special
characters and strings, and gives a definition of what they represent.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Acquiring and Viewing Disassembled Data
T able 2–4: Meaning of special characters in the display
Character or string displayedMeaning
or m
The instruction was manually marked as a program fetch
Hardware Display Format
****
-ā-ā-ā-ā-ā-ā-ā-
-ā-ā-ā-ā-ā-ā-ā-
-ā-ā-ā-ā-ā-ā-ā-
-ā-
-ā-ā-ā-ā-ā-ā-ā-
<Hex value>
Indicates there is insufficient data available for complete
disassembly of the instruction; the number of asterisks
indicates the width of the data that is unavailable. Each two
asterisks represent one byte.
In the Address channel group, this indicates that the Data
group did not have information that could be disassembled
In the HI_Data and LO_Data groups, this indicates that the
sequence does not contain valid data
In the LO_Data group, indicates that the bus configuration is
32-Bits
In the invalidate byte lanes, this indicates a Data Read or
Data Write transaction
Indicates a flushed instruction when the microprocessor is
operating in 64-bit mode and only one of the instructions
fetched is executed
In whole bytes that are not valid, indicates invalidated data;
the value for invalidated data is hexcadecimal
In Hardware display format, the disassembler displays certain cycle type labels in
parentheses.
2–8
If a single sequence has both an Address/Direct Store Access cycle and a Data
cycle, then a combination of cycle type labels described in Tables 2–5, 2–6, and
2–7 are displayed. For example, if Alternate Master Address and Alternate
Master Data are acquired in one sample, the disassembler would display the
cycle type label ( ALT ADDRS AND ALT DATA ).
Table 2–5 shows cycle type labels for Address sequences, and gives a definition
of the cycle they represent.
T able 2–5: Cycle type labels for Address sequences and definitions
Cycle type labelDefinition
( 60X_ADDRS )Address cycle with selected PPC60X master
( 60X_ART_ADDRS )Selected PPC60X Address retried
( ALT_ADDRS )Alternate masters address
( INCOM_ADDRS )Invalid selected PPC60X Address which is not associated with its
data
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Acquiring and Viewing Disassembled Data
Table 2–6 shows cycle type labels for Direct Store Access sequences, and gives a
definition of the cycle they represent.
T able 2–6: Cycle type labels for Direct Store Access sequences and definitions
Cycle type labelDefinition
( LOAD START )Request for I/O load operations
( LOAD IMMEDIATE )Transfer of up to 32 bits of data from the Bus Unit Controller to the
selected PPC60X
( LOAD LAST )Transfer of last 32 bits of data from the Bus Unit Controller to the
selected PPC60X
( STORE IMMEDIATE )Transfer of up to 32 bits of data from the selected PPC60X to the
Bus Unit Controller
( STORE LAST )Transfer of last 32 bits of data from the selected PPC60X to the Bus
Unit Controller
( LOAD REPLY )Reply from the Bus Unit Controller to indicate the success or failure
of an I/O load operation
( STORE REPLY )Reply from the Bus Unit Controller to indicate the success or failure
of an I/O store operation
( UNKNOWN DSA )Unrecognized I/O operation
( 60X_PKT1 XATC=0x$$ )
( 60X_ART_DSA )
( ALT_PKT0 )
( ALT_PKT1 )
Selected PPC60X Direct Store Access Packet 1 with XATC in Hex
Direct Store Access retried
Alternate Masters Direct Store Access packet 0
Alternate Masters Direct Store Access packet 1
Table 2–7 shows cycle type labels for Data sequences, and gives a definition of
the cycle they represent.
T able 2–7: Cycle type labels for Data sequences and definitions
Cycle type labelDefinition
( 60X_DATA )Data cycle with selected PPC60X master
( ALT_DATA )Alternate masters data
( 60X_DRT_DA TA )Selected PPC60X Data retried
( INCOM_DATA )Invalid selected PPC60X Data which is not associated with its
address
( 60X_DSA_DATA )Selected PPC60X Direct Storage Access Data
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Acquiring and Viewing Disassembled Data
Table 2–8 shows cycle type labels for ARTRY, DRTRY, and Data Error cycles,
and gives a definition of the cycle they represent.
T able 2–8: Cycle type labels for ARTRY, DRTRY, and Data Error cycles
Cycle type labelDefinition
( DATA_RETRY )Sequence with the DRTRY* signal asserted
( 60X_DATA_ERR )Data error in the selected PPC60X data; the TEA* signal is
( ALT_DATA_ERR )Data error in Alternate masters data
( ARTRY_CYCLE )Sequence with the ARTRY* signal asserted
( UNKNOWN )*Cycle with out valid information
*If acquired with the DRTRY Included clocking option, the cycle following a valid data
cycle is always acquired in anticipation of a Data retry. If that cycle does not have any
valid information, the cycle is not displayed.
asserted
Table 2–9 shows cycle type labels for general cycle types (not sequence types),
and gives a definition of the cycle they represent.
T able 2–9: General cycle type labels definitions
Cycle type labelDefinition
( FLUSH )An instruction that was fetched but not executed
( FLUSH: PREDICTION FAIL ) An instruction that was fetched based on the prediction bit, but
the prediction bit was incorrect
( CACHE FILL )Burst read transfer that occurrs after the wrap around of the end
of the cache line
( CLEAN BLOCK )Clean Block transaction
( WRT WITH FLUSH )Write-with-Flush operation issued by the microprocessor
( FLUSH BLOCK )Flush Block transaction
( WRT WITH KILL )Write-with-Kill transaction
( SYNC )Address Only transaction due to the execution of Sync instruction
( DATA READ )Single Beat Read or Burst Read operation
( KILL BLOCK )Kill Block transaction
( RWITM )Read-with-Intent-to-Modify transaction
2–10
( ORD I/O OPRN )Ordered I/O operation
( WWF-AT OMIC )Write-with-Flush-Atomic operation issued by the microprocessor
( EXT CTR WD WRT )External Control Word Write transaction
( TLB INVAL )TLB invalidate transaction issued by the microprocessor
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Acquiring and Viewing Disassembled Data
T able 2–9: General cycle type labels definitions (cont.)
Cycle type labelDefinition
( READ-AT OMIC )Read-Atomic operation
( EXT CTR WD RD )External Control Word Read transaction
( RWITM-ATOMIC )Read-with-Intent-to-Modify-Atomic transaction
( RESVD )Reserved-with-Intent-to-Modify transaction type
( **BAD CYCLE TYPE** )Cycle type where the value in the Trans group does not match
any of the defined patterns
Figure 2–1 shows an example of disassembled PPC60X data in the Hardware
display format.
Figure 2–1: Disassembled data in the Hardware display format
1
Sample Column. Lists the memory locations for the acquired data.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Acquiring and Viewing Disassembled Data
2
Address Group. Lists data from channels connected to the PowerPC 60X
address bus.
3
Hi_Data Group. Lists data from channels connected to the PowerPC 60X
DH31-DH0 signals.
4
Lo_Data Group. Lists data from channels connected to the PowerPC 60X
DL31-DL0 signals.
5
Mnemonics Column. Lists the disassembled instructions and cycle types.
Software Display Format
Control Flow Display
Format
The Software display format shows only the first fetch of executed instructions.
Flushed cycles and extensions are not shown, even though they are part of the
executed instruction. Data reads and writes are not displayed.
The Control Flow display format shows only the first fetch of instructions that
change the flow of control.
Instructions that generate a change in the flow of control in the PowerPC 60X
microprocessor are as follows:
bblsc
bablarfi
Instructions that might generate a change in the flow of control in the PowerPC
60X microprocessor are as follows:
bcbclabcctrtdi
bcabclrbcctrltw
bclbclrltdtwi
The disassembler displays some instructions that cause traps or interrupts, as well
as exception vector reads that are taken and ( **BAD CYCLE TYPE** ).
Mnemonics misinterpreted by the disassembler are also displayed.
2–12
Subroutine Display
Format
The Subroutine display format shows only the first fetch of subroutine call and
return instructions. It will display conditional subroutine calls if they are
considered to be taken.
Instructions that generate a subroutine call or a return in the PowerPC 60X
microprocessor are as follows:
scrfi
Instructions that might generate a subroutine call or a return in the PowerPC 60X
microprocessor are as follows:
tdtditwtwi
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 45
The disassembler displays some instructions that cause traps or interrupts, as well
as exception vector reads that are taken and ( **BAD CYCLE TYPE** ).
Mnemonics misinterpreted by the disassembler are also displayed.
Changing How Data is Displayed
There are common fields and features that allow you to further modify displayed
data to suit your needs. You can make common and optional display selections in
the Disassembly property page (the Disassembly Format Definition overlay).
You can make selections unique to the PowerPC 60X support to do the following
tasks:
HChange how data is displayed across all display formats
HChange the interpretation of disassembled cycles
HDisplay exception vectors
Acquiring and Viewing Disassembled Data
Optional Display
Selections
You can make optional selections for disassembled
common selections (described in the information on basic operations), you can
change the displayed data in the following ways:
HSelect a bus configuration and the trace PPC60X microprocessor
HSelect the prefetch byte order
HSelect the alternate byte order low and high bounds
HSelect the exception byte order
HSpecify the exception prefix
You can include or exclude DRTRY cycles in the acquisition through the
DRTRY Cycles clocking option.
The PowerPC 60X microprocessor support product has six additional fields: Bus
Config/Proc Select, Prefetch Byte Ord, Alt-Byte Ord - Lo Bound, Alt-Byte Ord Hi Bound, Exception Byte Ord, and Exception Prefix. These fields appear in the
area indicated in the basic operations user manual.
Bus Config/Proc Select. The PPC60X microprocessor can support optional
configurations that are selected by the DRTRY*, TLBISYNC*, and QACK*
signals when the HRESET* is deasserted after you start the system.
data. In addition to the
You should select the bus configuration that matches the one in your PPC60Xbased system: 64-bit Data bus, or 32-Bit Data bus.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Acquiring and Viewing Disassembled Data
You can use either 64-bit configuration when your SUT is operating in 64–bit
mode. This is the default bus configuration.
You can also use either 32-Bit Data Bus configuration when your SUT is
operating in 32-bit mode. With this configuration, only the Hi_Data channels
corresponding to the DH31-DH0 signals are valid.
You can also select which PPC60X microprocessor to trace: MPC0 or MPC1.
The MPC0 is considered to be the microprocessor from which the BG* and
DBG* signals are acquired. All other microprocessors, including controllers, are
considered to be MPC1s.
Prefetch Byte Ord. You can select the byte ordering for the predominant instruction fetches as Big- or Little-Endian.
Alt Byte Ord - Lo Bound and Alt Byte Ord - Hi Bound. You can enter the low and
high bounds for the alternate byte ordering range. The default is 00000000.
You should enter alternate values on double-word boundaries. If the value is not
on a double-word boundary, the disassembler assumes the value to be the nearest
double-word.
If you do not enter a value in the field, the data is acquired and disassembled
according to the selection in the Prefetch Byte Ord field.
NOTE. The alternate high bound value must be greater than the alternate low
bound value or disassembly will be incorrect.
Exception Byte Ord. You can select the byte ordering for exception processing as
Big- or Little-Endian.
Exception Prefix. You can enter the prefix value of the exception table as 000 to
FFF. The default prefix value is FFF. The exception table must reside in external
memory for interrupt and exception cycles to be visible to the disassembler.
NOTE. If an address is in the Exception processing region and in the range
selected for the alternate byte ordering, the disassembler uses the byte ordering
selected for the Exception processing.
2–14
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Acquiring and Viewing Disassembled Data
Marking Cycles
The disassembler has a Mark Opcode function that allows you to change the
interpretation of a cycle type. Using this function, you can select a cycle and
change it.
The list of selections varies depending on the selection in the Bus Config/Proc
Select field in the Disassembly property page (Disassembly Format Definition
overlay).
Mark selections available on data sequences without an address and data cycle
associated with a fetch cycle when the PPC60X microprocessor is operating in
64-bit mode are as follows:
OpcodeOpcode
OpcodeFlush
FlushOpcode
FlushFlush
Incom_Data
Undo Mark
Mark selections available on data sequences without an address and data cycle
associated with a fetch cycle when the PPC60X microprocessor is operating in
32-bit mode are as follows:
Opcode
Flush
Incom_Data
Undo Mark
Mark selections available on sequences with only an Address cycle are as
follows:
Incom_Address
Undo Mark
Mark selections available on sequences with both data and address cycles (if the
data cyle is associated with a fetch cycle) and the PPC60X microprocessor is
operating in 64-bit mode are as follows:
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Acquiring and Viewing Disassembled Data
Mark selections available on sequences with both data and address cycles (if the
data cyle is associated with a fetch cycle) and the PPC60X microprocessor is
operating in 32-bit mode are as follows:
Mark selections available on sequences with data that is not associated with a
Fetch cycle are as follows:
Incom_Data
Undo Mark
Table 2–10 describes the various combinations of mark selections.
T able 2–10: Mark selections and definitions
Mark selection or combination[
OpcodeOpcode
OpcodeFlush
FlushOpcode
FlushFlushInstructions not disassembled and labeled as ( FLUSH )
Incom_AddrsValid PPC60X address is invalidated and labeled as ( Incom_Addrs )
OpcodeOpcode Incom_Addrs
OpcodeFlush Incom_Addrs
FlushOpcode Incom_Addrs
FlushFlush Incom_AddrsInstructions not disassembled and labeled as ( FLUSH ); the address is invalidated
Opcode
FlushHI_Data and LO_Data are not disassembled and labeled as ( FLUSH )
Incom_Addrs
Definition
HI_Data and LO_Data are disassembled
Only HI_Data is disassembled in Big-Endian mode or only LO_Data is disassembled in
Little-Endian mode
Only LO_Data is disassembled in Big-Endian mode or only HI_Data is disassembled in
Little-Endian mode
Use to mark a sequence with PPC60X address and data from different transactions;
HI_Data and LO_Data are disassembled; the address is invalidated
HI_Data is disassembled only in Big-Endian mode or LO_Data is disassembled only in
Little-Endian mode; the address is invalidated
LO_Data is disassembled only in Big-Endian mode or HI_Data is disassembled only in
Little-Endian mode; the address is invalidated
HI_Data and LO_Data are disassembled
Address is invalidated
Opcode Incom_Addrs
Flush Incom_AddrsHI_Data and LO_Data are not disassembled and labeled as ( FLUSH ); the address
2–16
HI_Data and LO_Data are disassembled; the address is invalidated
is invalidated
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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T able 2–10: Mark selections and definitions (cont.)
Acquiring and Viewing Disassembled Data
Mark selection or combination[
[Mark selections intended to be used on sequences with data are not available for non-instructions.
Definition
HI_Data and LO_Data are invalidated
Address, HI_Data, and LO_Data are invalidated
Removes all marks
The Incom_Addrs mark invalidates the address from being associated with the
wrong data. You can use this mark if you determine that the data for the address
was not acquired.
The Incom_Data mark invalidates the data from being associated with the wrong
address. You can use this mark if you determine that the address for the data was
not acquired.
Information on basic operations contains more details on marking cycles.
Displaying Exception
Labels
The disassembler can display PowerPC 60X exception labels. The exception
table must reside in external memory for interrupt and exception cycles to be
visible to the disassembler.
You can enter the table prefix in the Exception Prefix field. The Exception Prefix
field provides the disassembler with the offset address; enter a three-digit
hexadecimal value corresponding to the prefix of the exception table.
These fields are located in the Disassembly property page (Disassembly Format
Definition overlay).
Table 2–11 lists the PowerPC 60X interrupt and exception labels.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Acquiring and Viewing Disassembled Data
T able 2–11: Interrupt and exception labels (cont.)
Exception
number
80x00800( FLOATING-POINT UNAVAILABLE )
90x00900( DECREMENTER )
100x00A00( RESERVED )
110x00B00( RESERVED )
120x00C00( SYSTEM CALL )
130x00D00( TRACE )
140x00E00( FLOATING-POINT ASSIST )
150x00F00( PERF MONITORING INTRPT )
160x01000( INST TRANS MISS )
170x01100( DATA LOAD TRANS MISS )
180x01200( DATA TRANS MISS )
190x01300( INST ADDRESS BREAKPOINT )
200x01400( SYS MANAGEMENT INTERRUPT )
21-320x014FF to 0x02FFF( RESERVED )
Displayed interrupt or exception nameOffset
Viewing an Example of Disassembled Data
A demonstration system file (or demonstration reference memory) is provided so
you can see an example of how your PowerPC 60X microprocessor bus cycles
and instruction mnemonics look when they are disassembled. Viewing the system
file is not a requirement for preparing the module for use and you can view it
without connecting the logic analyzer to your SUT.
Information on basic operations describes how to view the file.
2–18
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
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Specifications
This chapter contains the following information:
HProbe adapter description
HSpecification tables
HDimensions of the probe adapter
HChannel assignment tables
HDescription of how the module acquires PowerPC 60X signals
HList of other accessible microprocessor signals and extra probe channels
HAlphabetical list of signal names mapped to the PGA socket pin numbers for
Probe Adapter Description
The probe adapter is nonintrusive hardware that allows the logic analyzer to
acquire data from a microprocessor in its own operating environment with little
effect, if any, on that system. Information on basic operations contains a figure
showing the logic analyzer connected to a typical probe adapter. Refer to that
figure while reading the following description.
each type of PowerPC 60X microprocessor supported
The probe adapter consists of a circuit board and a socket for a PowerPC 60X
microprocessor. The probe adapter connects to the microprocessor in the SUT.
Signals from the microprocessor-based system flow from the probe adapter to the
channel groups and through the probe signal leads to the module.
All circuitry on the probe adapter is powered from the SUT.
Table 1–1 in the Getting Started chapter shows which microprocessors and their
packages the TMS 540 supports.
Specifications
These specifications are for a probe adapter connected between a compatible
Tektronix logic analyzer and a SUT. Table 3–1 shows the electrical requirements
the SUT must produce for the support to acquire correct data. Table 3–2 shows
the environmental specifications. Table 3–3 shows the certifications and
compliances that apply to the probe adapter.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
3–1
Page 52
Specifications
T able 3–1: Electrical specifications
CharacteristicsRequirements
Probe adapter power supply requirements
Voltage90-265 VAC
Current1.1 A maximum at 100 VAC
Frequency47-63 Hz
Power25 W maximum
Non-operating–55° C to +75° C (–67° to +167° F)
Humidity10 to 95% relative humidity
Altitude
Operating4.5 km (15,000 ft) maximum
Non-operating15 km (50,000 ft) maximum
Electrostatic immunityThe probe adapter is static sensitive
*Designed to meet Tektronix standard 062-2847-00 class 5.
[
Not to exceed PowerPC 60X microprocessor thermal considerations. Forced air
cooling might be required across the CPU.
+50° C (+122° F)[
T able 3–3: Certifications and compliances
3–2
EC ComplianceThere are no current European Directives that apply to this product.
Figure 3–1 shows the dimensions of the probe adapter. The figure also shows the
minimum vertical clearance of the high-density probe cable.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 53
89 mm
(3.500 in)
Specifications
5 mm (.187 in)
79 mm
(3.125 in)
35.2 mm
(1.385 in)
25.4 mm
(1.000 in)
72.5 mm
(2.855 in)
112 mm
(4.420 in)
40 mm
(1.600 in)
40 mm
(1.600 in)
35 mm
(1.400 in)
35 mm
(1.400 in)
52.1 mm
(2.050 in)
43 mm
(1.700 in)
36.3 mm
(1.430 in)
6 mm (.240 in)
13 mm
(.520 in)
13 mm
(.520 in)
25.4 mm
(1.00 in)
7 mm (.26 in)
21 mm
(.850 in)
25.4 mm
(1.00 in)
7 mm (.26 in)
21 mm
(.850 in)
MPC601, PPC601
PGA–to-QFP Clip
MPC603, PPC603
PGA–to-QFP Clip
Figure 3–1: Dimensions of the probe adapter and converter clips
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
3–3
Page 54
Specifications
Channel Assignments
Channel assignments shown in Table 3–4 through Table 3–15 use the following
conventions:
HAll signals are required by the support unless indicated otherwise.
HChannels are shown starting with the most significant bit (MSB) descending
to the least significant bit (LSB).
HChannel group assignments are for all modules unless otherwise noted.
HAn asterisk following a signal name indicates an active low signal.
HAn equals sign (=) following a signal name indicates that it is double probed.
HFor the 192-channel module, the module in the higher-numbered slot is
referred to as the HI module and the module in the lower-numbered slot is
referred to as the LO module.
Table 3–4 shows the probe section and channel assignments for the Address
group, and the microprocessor signal to which each channel connects. The
default display radix is HEX.
3–4
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
3–5
Page 56
Specifications
Table 3–5 shows the probe section and channel assignments for the Hi_Data
group, and the microprocessor signal to which each channel connects. By default,
this channel group is displayed in hexadecimal.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 57
Specifications
Table 3–6 shows the probe section and channel assignments for the Lo_Data
group, and the microprocessor signal to which each channel connects. By default,
this channel group is displayed in hexadecimal.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
3–7
Page 58
Specifications
Table 3–7 shows the probe section and channel assignments for the Control
group, and the microprocessor signal to which each channel connects. By default,
this channel group is displayed symbolically.
T able 3–7: Control group channel assignments
Bit
order
15C3:0LO_C3:0XATS_B2* (Delayed XA TS*)
14C2:2LO_C2:2TS*
13C2:3LO_C2:3XATS*
12C3:4LO_C3:4BG*
11C1:4HI_C3:4DBG*
10C1:6HI_C3:6ARTRY*
9C1:2HI_C3:2DRTRY*
8C2:1LO_C2:1AACK*
7C2:0LO_C2:0ARTRY_ERLY* (ARTRY* sampled early to
6C1:0HI_C3:0DRTRY_ERLY* (DRTRY* sampled early to
5C0:6HI_C2:6TA*
4C3:5LO_C3:5TEA*
3C0:0HI_C2:0ARTRY_DATA* (ARTRY* sampled before TA*
Table 3–8 shows the probe section and channel assignments for the Transfer
group, and the microprocessor signal to which each channel connects. By default,
this channel group is displayed symbolically.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Table 3–9 shows the probe section and channel assignments for the Tsiz group,
and the microprocessor signal to which each channel connects. By default, this
channel group is not visible.
Table 3–10 shows the probe section and channel assignments for the Misc group,
and the microprocessor signal to which each channel connects. By default, this
channel group is not visible.
T able 3–10: Misc group channel assignments
Bit
order
2C1:1HI_C3:1
1C1:3HI_C3:3
0C1:5HI_C3:5
[Signal not required for disassembly.
]BR* signal on the PPC603 microprocessor; SHD* signal on the PPC601 microproces-
136-channel
section & probe
sor.
192-channel
section & probe
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
PowerPC 60X signal name
HRESET*[
SYSCLK[
BR_SHD*[]
3–9
Page 60
Specifications
Table 3–11 shows the probe section and channel assignments for the Com_60X
group, and the microprocessor signal to which each channel connects. By default,
this channel group is not visible.
T able 3–11: 192-channel: Com_60X group channel assignments
Table 3–12 shows the probe section and channel assignments for the PPC601_4
group, and the microprocessor signal to which each channel connects. By default,
this channel group is not visible.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 61
T able 3–12: 192-channel: PPC601_4 group channel assignments
Table 3–13 shows the probe section and channel assignments for the PPC603_4
group, and the microprocessor signal to which each channel connects. By default,
this channel group is not visible.
T able 3–13: 192-channel: PPC603_4 group channel
assignments
Table 3–14 shows the probe section and channel assignments for the PPC604
group, and the microprocessor signal to which each channel connects. By default,
this channel group is not visible.
T able 3–14: 192-channel: PPC604 group channel assignments
TC2[
HAL TED[
ARRA Y_WR* [
RUN[
LSSD_MODE*[
L1_TSTCLK[
L2_TSTCLK[
Table 3–15 shows the probe section and channel assignments for the clock probes
(not part of any group), and the PowerPC 60X signal to which each channel
connects.
3–12
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 63
T able 3–15: Clock channel assignments (not a group)
[In an MPC601 or PPC601 SUT, connect the SYSCLK= signal to a 1X clock (such as the
BCLK_EN* signal). Refer to Requirements and Restrictions in the Getting Started
chapter for more detailed information on this clock.
192-channel
section & probe
Clock or Qual PowerPC 60X signal name
SYSCLK=(SYSCLK)[
This section explains how the module acquires PowerPC 60X signals using the
TMS 540 probe adapter and application. This part also provides additional
information on microprocessor signals accessible on or not accessible on the
probe adapter, and on extra acquisition channels available for you to use for
additional connections.
A special clocking program is loaded to the module every time you load the
PPC60X support. This special clocking is called Custom.
With Custom clocking, the module logs in signals from multiple groups of
channels at different times when they are valid on the PowerPC 60X bus. The
module then sends all the logged-in signals to the trigger machine and to the
acquisition memory of the module for storage.
In Custom clocking, the module clocking state machine (CSM) generates one
master sample for each microprocessor bus cycle, no matter how many clock
cycles are contained in the bus cycle.
Figure 3–2 shows one sample point and five master sample points.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
3–13
Page 64
Specifications
T1T2T3T4T5T6
SYSCLK
TS*
TA*/TEA*
XATS*
Sample point
Master sample points
Figure 3–2: PowerPC 60X bus timing
T1 Clock Edge. The BG*, ABB*, and ARTRY* signals are logged in on this clock
edge.
T2 Clock Edge. The A31-A0, TT3-TT1, TSIZ2-TSIZ0, XATS*, TBST*, TS*,
TC0, SYSCLK, DBG*, DRTRY_ERLY*, DBWO*, and ARTRY_DATA* signals
are logged in on this clock edge.
T3 Clock Edge. The DH31-DH0, DL31-DL0, TEA*, TA*, TT0, DBB*, AACK*,
ARTRY*, DRTRY*, BR*, APE*, GBL*, BG*, ABB*, ARTRY_ERLY*, and
XATS_B2* signals are logged in on this clock edge. Signals logged in on the T2
clock edge are also logged in except the A31-A0 signals.
T4 Clock Edge. The A31-A0, TT3-TT1, TSIZ2-TSIZ0, XATS*, TBST*, TS*,
TC0, SYSCLK, DBG*, DRTRY_ERLY*, DBWO*, ARTRY_DATA*, BG*,
ABB*, ARTRY_ERLY*, and XATS_B2 signals are logged in on this clock edge.
3–14
Clocking Options
T5 Clock Edge. The A31-A0, TT3-TT1, TSIZ2-TSIZ0, XATS*, TBST*, TS*,
TC0, SYSCLK, DBG*, DRTRY_ERLY*, DBWO*, and ARTRY_DATA* signals
are logged in on this clock edge.
T6 Clock Edge. The DH31-DH0, DL31-DL0, TEA*, TA*, TT0, DBB*, AACK*,
ARTRY*, DRTRY*, BR*, APE*, GBL*, BG*, ABB*, ARTRY_ERLY*, and
XATS_B2* signals are logged in on this clock edge. Signals logged in on the T5
clock edge are also logged in except the A31-A0 signals.
The clocking algorithm for the PowerPC 60X microprocessor support has two
variations: DRTRY Cycles Included or DRTRY Cycles Excluded.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 65
DRTRY Cycles. When DRTRY Cycles are included, the clocking stores the cycle
right after the assertion of the TA* signal to check for the assertion of the
DRTRY* signal. When DRTRY Cycles are excluded, the clocking will not store
the cycle right after the assertion of the TA* signal to check for the assertion of
the DRTRY* signal.
Alternate Microprocessor Connections
You can connect to microprocessor signals that are not required by the support so
that you can do more advanced timing analysis. These signals might or might not
be accessible on the probe adapter board. The following paragraphs and tables
list signals that are or are not accessible on the probe adapter board.
For a list of signals required or not required for disassembly, refer to the channel
assignment tables beginning on page 3–4. Remember that these channels are
already included in a channel group. If you do connect these channels to other
signals, you should set up another channel group for them.
Specifications
Signals Not On the Probe
Adapter
The probe adapter does not provide access for the following MPC601 or PPC601
microprocessor signals:
HBLK_EN*
H2X_PCLK
HBR*
The probe adapter also does not provide access to the Reserved pins (three) or to
the Test pins (twenty).
The probe adapter does not provide access for the following MPC603 or PPC603
microprocessor signals:
HAVDD
HPLL_CFG0
HPLL_CFG1
HPLL_CFG2
HPLL_CFG3
Extra Channels
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Table 3–16 lists extra sections and channels that are left after you have connected
all the probes used by the support. You can use these extra channels to make
alternate SUT connections.
3–15
Page 66
Specifications
Channels not defined in a channel group by the TMS 540 software are logged in
with the Master sample point.
T able 3–16: Extra module sections and channels
ModuleSection: channels
136-channelsQual:3-0
192-channelsNone
These channels are not defined in any channel group and data acquired from
them is not displayed. To display data, you will need to define a channel group.
PPC60X Microprocessor Signal Names to PGA Socket Pin Numbers
You might want to connect to signals with other equipment, such as an oscilloscope, while analyzing activity in your SUT. You can connect to PPC60X
microprocessor signals through the PGA socket on the probe adapter board since
it does not have a microprocessor installed in it.
Table 3–17 shows PPC60X signal names and pin number connections between
the PGA socket on the probe adapter and the various PPC60X microprocessors.
T able 3–17: PGA socket pin numbers to PPC60X signal names
PGA socketMicroprocessor pin number
PPC60X signalPGA pin no.MPC601/PPC601MPC603/PPC603
TT1E20227190238
TT2D14248185231
TT3D15244184229
TT4D16238180227
WT*F20214236302
XA TS*D17229150189
[
Pin information included for general purpose probing.
Figure 3–3 shows the PGA socket on the probe adapter with the grid row and
column labels for the pin numbers.
3–22
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 73
123456789101112131415161718192021
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
T
U
V
W
Specifications
Figure 3–3: Grid row and column labels for the pin numbers on the PGA socket
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
3–23
Page 74
Maintenance
This chapter contains information on the following topics:
HProbe adapter circuit description
HHow to replace a fuse
Probe Adapter Circuit Description
The probe adapter contains many 74FCT162244 devices that buffer all acquired
signals. These devices have a chip-to-chip skew of 2 ns.
Replacing Signal Leads
Information on basic operations describes how to replace signal leads (individual
channel and clock probes).
Replacing Protective Sockets
Information on basic operations describes how to replace protective sockets.
Replacing the Fuse
If the fuse on the PowerPC 60X probe adapter opens (burns out), you can replace
it with a 5 A, 125 V fuse. Figure 4–1 shows the location of the fuse on the probe
adapter.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
4–1
Page 75
Maintenance
Fuse
Figure 4–1: Location of the fuse
4–2
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 76
Replaceable Electrical Parts
This chapter contains a list of the replaceable electrical components for the
TMS 540 PowerPC 60X microprocessor support. Use this list to identify and
order replacement parts.
Parts Ordering Information
Replacement parts are available through your local Tektronix field office or
representative.
Changes to Tektronix products are sometimes made to accommodate improved
components as they become available and to give you the benefit of the latest
improvements. Therefore, when ordering parts, it is important to include the
following information in your order:
HPart number
HInstrument type or model number
HInstrument serial number
HInstrument modification number, if applicable
If you order a part that has been replaced with a different or improved part, your
local Tektronix field office or representative will contact you concerning any
change in part number.
Change information, if any, is located at the rear of this manual.
Using the Replaceable Electrical Parts List
The tabular information in the Replaceable Electrical Parts List is arranged for
quick retrieval. Understanding the structure and features of the list will help you
find all of the information you need for ordering replacement parts. The
following table describes each column of the electrical parts list.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
5–1
Page 77
Replaceable Electrical Parts
Parts list column descriptions
ColumnColumn nameDescription
1Component numberThe component number appears on diagrams and circuit board illustrations, located in the diagrams
section. Assembly numbers are clearly marked on each diagram and circuit board illustration in the
Diagrams section, and on the mechanical exploded views in the Replaceable Mechanical Parts list
section. The component number is obtained by adding the assembly number prefix to the circuit
number (see Component Number illustration following this table).
The electrical parts list is arranged by assemblies in numerical sequence (A1, with its subassemblies
and parts, precedes A2, with its subassemblies and parts).
Chassis-mounted parts have no assembly number prefix, and they are located at the end of the
electrical parts list.
2Tektronix part numberUse this part number when ordering replacement parts from Tektronix.
3 and 4Serial numberColumn three indicates the serial number at which the part was first effective. Column four indicates
the serial number at which the part was discontinued. No entry indicates the part is good for all serial
numbers.
5Name & descriptionAn item name is separated from the description by a colon (:). Because of space limitations, an item
name may sometimes appear as incomplete. Use the U.S. Federal Catalog handbook H6-1 for
further item name identification.
6Mfr. codeThis indicates the code number of the actual manufacturer of the part.
7Mfr. part numberThis indicates the actual manufacturer’s or vendor’s part number.
Abbreviations
Component Number
List of Assemblies
Chassis Parts
Mfr. Code to Manufacturer
Cross Index
Abbreviations conform to American National Standard ANSI Y1.1–1972.
Component number
A23A2R1234 A23 R1234
Assembly numberCircuit number
Read: Resistor 1234 (of Subassembly 2) of Assembly 23
A2
Subassembly number
(optional)
A list of assemblies is located at the beginning of the electrical parts list. The
assemblies are listed in numerical order. When a part’s complete component
number is known, this list will identify the assembly in which the part is located.
Chassis-mounted parts and cable assemblies are located at the end of the
Replaceable Electrical Parts List.
The table titled Manufacturers Cross Index shows codes, names, and addresses of
manufacturers or vendors of components listed in the parts list.
5–2
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 78
Replaceable Electrical Parts
Manufacturers cross index
Mfr.
code
TK0875MATSUO ELECTRONICS INC831 S DOUBLAS STEL SEGUNDO CA 92641
04222A VX/KYOCERA
50434HEWLETT–P ACKARD CO
61772INTEGRA TED DEVICE TECHNOLOGY3236 SCOTT BLVDSANTA CLARA CA 95051
80009TEKTRONIX INC14150 SW KARL BRAUN DR
A1C655290–5005–00CAP,FXD,TANT:;47UF,10%,10V,5.8MM X 4.6MMTK0875 267M–1002–476–K
A1CR630152–5045–00 DIODE,SIG:SCHTKY,;20V,1.2PF,24 OHM50434HSMS–2810–T31
A1J335–––––––––––SOCKET PGA:PCB,321 POS 21 X 21 SHORT PINS
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Page 80
Replaceable Mechanical Parts
This chapter contains a list of the replaceable mechanical components for the
TMS 540 PowerPC 60X microprocessor support. Use this list to identify and
order replacement parts.
Parts Ordering Information
Replacement parts are available through your local Tektronix field office or
representative.
Changes to Tektronix products are sometimes made to accommodate improved
components as they become available and to give you the benefit of the latest
improvements. Therefore, when ordering parts, it is important to include the
following information in your order:
HPart number
HInstrument type or model number
HInstrument serial number
HInstrument modification number, if applicable
If you order a part that has been replaced with a different or improved part, your
local Tektronix field office or representative will contact you concerning any
change in part number.
Change information, if any, is located at the rear of this manual.
Using the Replaceable Mechanical Parts List
The tabular information in the Replaceable Mechanical Parts List is arranged for
quick retrieval. Understanding the structure and features of the list will help you
find all of the information you need for ordering replacement parts. The
following table describes the content of each column in the parts list.
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
6–1
Page 81
Replaceable Mechanical Parts
Parts list column descriptions
ColumnColumn nameDescription
1Figure & index numberItems in this section are referenced by figure and index numbers to the exploded view illustrations
that follow.
2Tektronix part numberUse this part number when ordering replacement parts from Tektronix.
3 and 4Serial numberColumn three indicates the serial number at which the part was first effective. Column four
indicates the serial number at which the part was discontinued. No entries indicates the part is
good for all serial numbers.
5QtyThis indicates the quantity of parts used.
6Name & descriptionAn item name is separated from the description by a colon (:). Because of space limitations, an
item name may sometimes appear as incomplete. Use the U.S. Federal Catalog handbook H6-1
for further item name identification.
7Mfr. codeThis indicates the code of the actual manufacturer of the part.
8Mfr. part numberThis indicates the actual manufacturer’s or vendor’s part number.
Abbreviations
Chassis Parts
Abbreviations conform to American National Standard ANSI Y1.1–1972.
Chassis-mounted parts and cable assemblies are located at the end of the
Replaceable Electrical Parts List.
Mfr. Code to Manufacturer
Cross Index
The table titled Manufacturers Cross Index shows codes, names, and addresses of
manufacturers or vendors of components listed in the parts list.
Manufacturers cross index
Mfr.
code
0B445ELECTRI–CORD MFG CO INC312 EAST MAIN STWESTFIELD PA 16950
0LXM2LZR ELECTRONICS INC8051 CESSNA A VENUEGAITHERSBURG MD 20879
00779AMP INC2800 FULLING MILL
14310AUL T INC7300 BOONE AVENUE NORTHMINNEAPOLIS MN 55428
26742METHODE ELECTRONICS INC7447 W WILSON AVECHICAGO IL 60656–4548
58050TEKA PRODUCTS INC45 SALEM STPROVIDENCE RI 02907
61857SAN–0 INDUSTRIAL CORP91–3 COLIN DRIVEHOLBROOK NY 11741
80009TEKTRONIX INC14150 SW KARL BRAUN DR
ManufacturerAddressCity, state, zip code
HARRISBURG PA 17105
PO BOX 3608
BEAVERT ON OR 97077–0001
PO BOX 500
6–2
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
T siz group, 3–9
channel groups, 2–1
clock channel assignments, 3–12
clock rate, 1–3
clocking, Custom, 2–1
how data is acquired, 3–13
clocking options
DR TRY Cycles, 2–2
field names, 2–2
how data is acquired, 3–14
Com_60X group, 192-channel module, channel
assignments, 3–10
compliances, 3–1
connections
no probe adapter, 1–11
136-channel module, 1–12
192-channel module, 1–14
other microprocessor signals, 3–15
probe adapter to SUT
MPC601 and PPC601 converter clip, 1–4
MPC603 and PPC603 converter clip, 1–4
Control Flow display format, 2–12
Control group
channel assignments, 3–8
symbol table, 2–3
Custom clocking, 2–1
DR TRY Cycles, 2–2
how data is acquired, 3–13
cycle types
Address, 2–8
AR TRY, 2–10
combined labels, 2–8
Data, 2–9
Data Error, 2–10
Direst Store Access, 2–9
DR TRY, 2–10
general, 2–10
D
data
acquiring, 2–7
disassembly formats
Control Flow, 2–12
Hardware, 2–8
Software, 2–12
Subroutine, 2–12
how it is acquired, 3–13
data display , changing, 2–13
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Index–1
Page 88
Index
demonstration file, 2–18
dimensions, probe adapter, 3–2
disassembled data
Address cycle types, 2–8
AR TRY, DRTRY, and Data Error cycle types, 2–10
Data cycle types, 2–9
Direct Store Access cycle types, 2–9
general cycle type definitions, 2–10
viewing, 2–7
viewing an example, 2–18