Tektronix TMS532 Instruction Manual
Instruction Manual
TMS 532
PPC405GP Microprocessor Support
071-0892-00
www.tektronix.com
Copyright © T ektronix, Inc. All rights reserved. Licensed software products are owned by Tektronix or its suppliers and
are protected by United States copyright laws and international treaty provisions.
Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the
Rights in T echnical Data and Computer Software clause at DFARS 252.227-7013, or subparagraphs (c)(1) and (2) of the
Commercial Computer Software – Restricted Rights clause at F AR 52.227-19, as applicable.
T ektronix products are covered by U.S. and foreign patents, issued and pending. Information in this publication supercedes
that in all previously published material. Specifications and price change privileges reserved.
T ektronix, Inc., P.O. Box 500, Beaverton, OR 97077
TEKTRONIX and TEK are registered trademarks of T ektronix, Inc.
SOFTWARE WARRANTY
T ektronix warrants that the media on which this software product is furnished and the encoding of the programs on
the media will be free from defects in materials and workmanship for a period of three (3) months from the date of
shipment. If a medium or encoding proves defective during the warranty period, T ektronix will provide a
replacement in exchange for the defective medium. Except as to the media on which this software product is
furnished, this software product is provided “as is” without warranty of any kind, either express or implied.
T ektronix does not warrant that the functions contained in this software product will meet Customer’s
requirements or that the operation of the programs will be uninterrupted or error-free.
In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration
of the warranty period. If T ektronix is unable to provide a replacement that is free from defects in materials and
workmanship within a reasonable time thereafter, Customer may terminate the license for this software product
and return this software product and any associated materials for credit or refund.
THIS WARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER WARRANTIES, EXPRESS
OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’
RESPONSIBILITY TO REPLACE DEFECTIVE MEDIA OR REFUND CUSTOMER’S PAYMENT IS
THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS
WARRANTY. TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT,
SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER
TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH
DAMAGES.
Table of Contents
Getting Started
Operating Basics
General Safety Summary v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preface vii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Manual Conventions vii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contacting T ektronix viii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Support Package Description 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Analyzer Software Compatibility 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Analyzer Configuration 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Requirements and Restrictions 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functionality Not T ested 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functionality Not Supported 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard Accessories 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Options 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connecting the Logic Analyzer to a System Under T est 1–4. . . . . . . . . . . . . . . . . . .
Setting Up the Support 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Installing the Support Software 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Group Definitions 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Support Package Setups 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocking 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acquiring and Viewing Disassembled Data 2–7. . . . . . . . . . . . . . . . . . . . .
Acquiring Data 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing Disassembled Data 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Display Format 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Display Format 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Display Format 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Flow Display Format 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subroutine Display Format 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Changing How Data is Displayed 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optional Display Selections 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Micro-Specific Fields for 405GPASYNC 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . .
Micro-Specific Fields for 405GPSDRAM 2–14. . . . . . . . . . . . . . . . . . . . . . . . . .
Marking Cycles 2–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing an Example of Disassembled Data 2–16. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifications
Replaceable Parts
Symbol Table 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Assignments 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU To Mictor Connections 5–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index
TMS532 PPC405GP Microprocessor Support
i
Table of Contents
List of Figures
Figure 2–1: SDRAM timing diagram with activate, four-word
read, percharge cycles 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2–2: Burst read transfer timing diagram 2–6. . . . . . . . . . . . . . . . .
Figure 2–3: 405GPSDRAM hardware display format 2–10. . . . . . . . . . . . .
Figure 2–4: 405GPASYNC hardware display format 2–10. . . . . . . . . . . . .
Figure 2–5: 405GPSDRAM software display format 2–11. . . . . . . . . . . . . .
Figure 2–6: 405GPASYNC software display format 2–11. . . . . . . . . . . . . .
Figure 2–7: 405GPSDRAM control flow display format 2–12. . . . . . . . . . .
Figure 2–8: 405GPASYNC control flow display format 2–12. . . . . . . . . . .
Figure 5–1: Pin assignments for a Mictor connector
(component side) 5–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ii
TMS532 PPC405GP Microprocessor Support
List of Tables
Table of Contents
Table 2–1: Description of special characters in the display 2–8. . . . . . . .
Table 2–2: Cycle type definitions 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2–3: Compatible SDRAM Memory Configuration 2–15. . . . . . . . . .
Table 3–1: PPC405GP Electrical specifications 3–1. . . . . . . . . . . . . . . . .
Table 5–1: 405GPASYNC_Cntr group symbol table definitions 5–1. . . .
Table 5–2: 405GPSDRAM_Cntr group symbol table definitions 5–2. . .
Table 5–3: Address channel group assignments for
405GPASYNC 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–4: Data channel group assignments for 405GPASYNC 5–6. . . .
Table 5–5: Control channel group assignments for
405GPASYNC 5–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–6: Chip Select channel group assignments for
405GPASYNC 5–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–7: Byte Enable channel group assignments for
405GPASYNC 5–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–8: Trace Status channel group assignments for
405GPASYNC 5–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–9: DMA Acknowledge channel group assignments for
405GPASYNC 5–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–10: Clock and Qualifier channel assignments for
405GPASYNC 5–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–11: 405GPASYNC signals required for clocking and
disassembly 5–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–12: 405GPASYNC signals not required for clocking and
disassembly 5–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–13: TLA Group A channel assignments for
405GPSDRAM 5–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–14: TLA group D channel assignments for
405GPSDRAM 5–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–15: Clock and Qualifier channel assignments for
405GPSDRAM 5–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–16: Bank Select channel assignments for 405GPSDRAM 5–14. .
Table 5–17: Bank Access channel assignments for
405GPSDRAM 5–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–18: Data Mask channel assignments for 405GPSDRAM 5–15. . .
Table 5–19: Signals required for clocking and disassembly for
405GPSDRAM 5–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS532 PPC405GP Microprocessor Support
iii
Table of Contents
List of Tables (Cont)
Table 5–20: CPU to Mictor connections for Mictor A pins for
405GPASYNC 5–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–21: CPU to Mictor connections for Mictor C pins for
405GPASYNC 5–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–22: CPU to Mictor connections for Mictor D pins for
405GPASYNC 5–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–23: CPU to Mictor connections for Mictor A pins for
405GPSDRAM 5–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–24: CPU to Mictor connections for Mictor C pins for
405GPSDRAM 5–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
TMS532 PPC405GP Microprocessor Support
General Safety Summary
Review the following safety precautions to avoid injury and prevent damage to
this product or any products connected to it. To avoid potential hazards, use this
product only as specified.
While using this product, you may need to access other parts of the system. Read
the General Safety Summary in other system manuals for warnings and cautions
related to operating the system.
Symbols and Terms
T erms in this Manual. These terms may appear in this manual:
CAUTION. Caution statements identify conditions or practices that could result in
damage to this product or other property.
T erms on the Product. These terms may appear on the product:
CAUTION indicates a hazard to property including the product.
Symbols on the Product. The following symbols may appear on the product:
CAUTION
Refer to Manual
TMS532 PPC405GP Microprocessor Support
v
General Safety Summary
vi
TMS532 PPC405GP Microprocessor Support
Preface
Manual Conventions
This instruction manual contains specific information about the
TMS 532 PPC405GP microprocessor support package and is part of a set of
information on how to operate this product on compatible Tektronix logic
analyzers.
If you are familiar with operating microprocessor support packages on the logic
analyzer for which the TMS 532 PPC405GP support was purchased, you only
need this instruction manual to set up and run the support.
If you are not familiar with operating microprocessor support packages, you need
to supplement this instruction manual with information on basic operations to set
up and run the support. See Manual Conventions below for more information.
This manual uses the following conventions:
H The term “disassembler” refers to the software that disassembles bus cycles
into instruction mnemonics and cycle types.
H The phrase “information on basic operations” refers to online help or a user
manual covering the basic operations of a microprocessor support.
TMS532 PPC405GP Microprocessor Support
vii
Preface
Contacting Tektronix
Phone 1-800-833-9200*
Address Tektronix, Inc.
Department or name (if known)
14200 SW Karl Braun Drive
P.O. Box 500
Beaverton, OR 97077
USA
Web site www.tektronix.com
Sales support 1-800-833-9200, select option 1*
Service support 1-800-833-9200, select option 2*
Technical support Email: techsupport@tektronix.com
1-800-833-9200, select option 3*
1-503-627-2400
6:00 a.m. – 5:00 p.m. Pacific time
* This phone number is toll free in North America. After office hours, please leave a
voice mail message.
Outside North America, contact a Tektronix sales office or distributor; see the
Tektronix web site for a list of offices.
viii
TMS532 PPC405GP Microprocessor Support
Getting Started
Getting Started
This section contains information on the TMS 532 PPC405GP microprocessor
support package and information on connecting your logic analyzer to your
system under test.
Support Package Description
The TMS 532 PPC405GP microprocessor support package displays disassembled
data from systems based on the IBM PPC405GP microprocessor.
The TMS 532 PPC405GP support includes the 405GPSDRAM software for the
SDRAM Interface and the 405GPASYNC software for the 405GPASYNC
Peripheral interface.
To use this support efficiently, you need to have the items listed in information
on basic operations in your logic analyzer online help and PPC405GP Controller
Users Manual: IBM, April 2000.
Information on basic operations in your online help also contains a general
description of the support.
Logic Analyzer Software Compatibility
The floppy disk label on the microprocessor support states which version of logic
analyzer software this support is compatible with.
Logic Analyzer Configuration
The TMS 532 PPC405GP support allows a choice of required minimum module
configurations:
H 405GPASYNC support requires a minimum of one 102 channel module
H 405GPSDRAM support requires a minimum of one 68 channel module
To use both supports at the same time requires the above two modules. If you
want to use only one support at a time, you must select the correct module and
specify the support.
TMS532 PPC405GP Microprocessor Support
1–1
Getting Started
Requirements and Restrictions
Review the general requirements and restrictions of microprocessor support
packages in the information on basic operations as they pertain to your system
under test.
Review electrical specifications in Specifications on page 3–1 as they pertain to
your system under test, as well as the following descriptions of other
TMS 532 PPC405GP support requirements and restrictions.
System Clock Rate
NonIntrusive Acquisition
Functionality Not Tested
The operating speeds that the TMS 532 PPC405GP support can acquire data from
the PPC405GP microprocessor are listed on Table 3–1 on page 3–1. These
specifications were valid at the time this manual was printed. Please contact your
Tektronix Sales Representative for current information on the fastest devices
supported.
Acquiring microprocessor bus cycles is nonintrusive to the system under test.
That is, the PPC405GP support will not intercept, modify, or present signals back
to the system under test.
H DMA cycles (both supports)
H External Master cycles (both supports)
H Device paced cycles for 405GPASYNC
H Bus widths 16 and 32 for 405GPASYNC
H CAS latency 3 and 4 for 405GPSDRAM
Functionality Not Supported
Cache
Data
1–2
The cache needs to be disabled for the disassembly to function correctly.
The data must be uncompressed or the supports will not disassembly correctly.
TMS532 PPC405GP Microprocessor Support
Standard Accessories
Options
Getting Started
The TMS 532 PPC405GP Support is shipped with the following standard
accessories:
H TMS 532 PPC405GP Support SW Disk includes:
405GPSDRAM interface
405GPASYNC
H TMS 532 PPC405GP Support Instruction Manual
The following options are available when ordering the TMS 532 PPC405GP
Support:
H Option 21–Add P6434 Mass-Termination Probes (3)
Peripheral interface
TMS532 PPC405GP Microprocessor Support
1–3
Getting Started
Connecting the Logic Analyzer to a System Under Test
You can use channel probes, clock probes, and leadsets with a commercial test
clip (or adapter) to make connections between the logic analyzer and your system
under test.
To connect the probes to PPC405GP signals in the system under test using a test
clip, follow these steps:
1. Power off your system under test. It is not necessary to power off the logic
analyzer.
CAUTION. To prevent static damage, handle the microprocessor, the probes, and
the logic analyzer module only in a static-free environment. Static discharge can
damage these components.
Always wear a grounding wrist strap, heel strap, or similar device while
handling the microprocessor.
2. To discharge your stored static electricity, touch the ground connector located
on the back of the logic analyzer. If you are using a test clip, touch any of the
ground pins on the clip to discharge stored static electricity from the test clip.
CAUTION. To prevent damage to the pins on the microprocessor,.place the system
under test on a horizontal surface before connecting the test clip.
3. Place the system under test on a horizontal, static-free surface.
4. Use Tables 5–3 through 5–19 beginning on page 5–5 to connect the channel
probes to PPC405GP signal pins on the test clip or in the system under test.
Use leadsets to connect at least one ground lead from each channel probe and
the ground lead from each clock probe to ground pins on your test clip.
1–4
TMS532 PPC405GP Microprocessor Support
Operating Basics
Setting Up the Support
The information in this section is specific to the operations and functions of the
TMS 532 PPC405GP microprocessor support on any Tektronix logic analyzer for
which it can be purchased.
Before you acquire and display disassembled data, you need to load the support
and specify setups for clocking and triggering as described in the information on
basic operations. The microprocessor support provides default values for each of
these setups as well as user-definable settings.
Installing the Support Software
NOTE. Before you install any software, it is recommended you verify that the
microprocessor support software is compatible with the logic analyzer software.
To install the TMS 532 PPC405GP software on your Tektronix logic analyzer,
follow these steps:
1. Insert the floppy disk in the disk drive.
2. Click the Windows Start button, point to Settings, and click Control Panel.
3. In the Control Panel window, double-click Add/Remove Programs.
4. Follow the instructions on the screen for installing the software from the
floppy disk.
To remove or uninstall software, follow the above instructions and select
Uninstall. You must close all windows before you uninstall any software.
TMS532 PPC405GP Microprocessor Support
2–1
Setting Up the Support
Á
Á
Á
Á
Channel Group Definitions
The software automatically defines channel groups for the support. The channel
groups for the TMS 532 PPC405GP support are listed in the following tables:
405GPASYNC support
Address
Data
ББББББББ
Control
ChipSel
ByteEnable
TraceStatus
DMAAck
Display radix
Hexadecimal
Hexadecimal
БББББББББ
Symbolic
OFF
OFF
OFF
OFF
405GPSDRAM support Display radix
BusAddr
Address
Data
Control
BankSelect
Misc
OFF
Hexadecimal
Hexadecimal
Symbolic
OFF
OFF
2–2
DataMask
ББББББББ
OFF
БББББББББ
The channel group tables begin on page 5–1.
TMS532 PPC405GP Microprocessor Support
Support Package Setups
The TMS 532 PPC405GP software installs two support package setup files. Each
setup file offers different clocking and display options.
Setting Up the Support
405GPSDRAM Setup
405GPASYNC Setup
This setup provides disassembly support for the SDRAM interface. Signals are
not inverted and are displayed as they appear electrically on the front side bus.
Disassembly channel groups:
Sample
Address
Data
Mnemonics
Control
Time Stamp
Timing channel groups:
Control
This setup provides disassembly support for the Peripheral interface. Signals are
not inverted and are displayed as they appear electrically on the front side bus.
Disassembly channel groups:
Sample
Address
Data
Mnemonics
Control
Time Stamp
Timing channel groups:
Control
TMS532 PPC405GP Microprocessor Support
2–3
Setting Up the Support
Clocking
Options
Custom Clocking
The TMS 532 PPC405GP software offers a microprocessor-specific clocking
mode for the PPC405GP microprocessor. This clocking mode is the default
selection whenever you load the PPC405GP
Disassembly is not correct if you use the Internal or External clocking modes.
See your logic analyzer online help for more details on how to use these clock
selections for general purpose analysis.
H Internal clocking is used for timing and is based on the clock generated by a
Tektronix logic analyzer. You can configure the clock rate from 50 ms down
to 4 ns resolution.
H External clocking is used when you configure the clocking of data based on
logical combinations of clocks and qualifiers.
When Custom is selected, the Custom Clocking Options menu has the subtitle
405GPSDRAM or 405GPASYNC Microprocessor Clocking Support added, and
the clocking options are also displayed.
The TMS 532 PPC405GP supports:
H SDRAM Support
H Peripheral Support
support.
2–4
Setup and Hold Time. You cannot change the Setup and Hold time for any signal
groups.
TMS532 PPC405GP Microprocessor Support
Loading...