Instruction Manual
TMS444
SH7750 Microprocessor Software Support
071-1048-00
www.tektronix.com
Copyright © Tektronix, Inc. All rights reserved.
Tektronix products are covered by U.S. and foreign patents, issued and pending. Information in this public ation supercedes
that in all previously published material. Specifications and price c hange privileges reserved.
Tektronix, Inc., P.O. Box 500, Beaverton, OR 97077
TEKTRONIX and TEK are registered trademarks of Tektronix, Inc.
SOFTWARE WARRANTY
Tektronix warrants that the media on which this software product is furnished and the encoding of the programs on
the media will be free from defects in materials and workmanship for a period of three (3) months from the date of
shipment. If a medium or encoding proves defective during the warranty period, Tektronix will provide a
replacement in exchange for the defective medium. Except as to the media on which this software product is
furnished, this software product is provided “as is” without warranty of any kind, either express or implied.
Tektronix does not warrant that the functions contained in this software product will meet Customer’s
requirements or that the operation of the programs will be uninterrupted or error-free.
In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration
of the warranty period. If Tektronix is unable to provide a replacement that is free from defects in materials and
workmanship within a reasonable time thereafter, Customer may terminate the license for this software product
and return this software product and any associated materials for credit or refund.
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DAMAGES.
Table of Contents
Getting Started
Operating Basics
Preface vii...................................................
Manual Conventions vii..............................................
Contacting Tektronix viii.............................................
Getting Started 1--1............................................
Support Package Description 1--1.......................................
Logic Analyzer Software Compatibility 1--1..............................
Logic Analyzer Configuration 1--1......................................
Requirements and Restrictions 1--1......................................
Timing Display Format 1--3...........................................
Functionality Not Supported 1--3.......................................
Functionality Not Tested 1--4..........................................
Connecting the Logic Analyzer to a Target System 1--4.....................
Setting Up the Support 2--1....................................
Installing the Support Software 2--1.....................................
Channel Group Definitions 2--2.........................................
Clocking 2--2.......................................................
Acquisition Setup 2--2............................................
Clocking Options 2--2.............................................
Custom Cl ocking 2--2.............................................
Acquiring and Viewing Disassembled Data 2--5....................
Acquiring Data 2--5..................................................
Viewing Disassembled Data 2--5........................................
Timing Display Format 2--5........................................
“All” Display Format 2--6.........................................
“No Idles/Waits” Display Format 2--10................................
Changing How Data is Displayed 2--11...................................
Optional Display Selections 2--11....................................
Displaying Exception Labels 2--12...................................
Disassembly Display Options 2 --12.......................................
Micro Specific Fields 2--12.............................................
Viewing an Example of Disassembled Data 2--21...........................
Reference
Reference:Tables 3--1..........................................
Symbol Tables 3--1..................................................
Channel Assignment Tables 3--2.......................................
CPU To Mictor Connections 3--12.......................................
Channel Assignments with AMP Mictor Connector diagrams for
SH7750 QFP208 Package 3--19......................................
Channel Assignment Diagram for AMP Mictor A 3--19......................
Channel Assignment Diagram for AMP Mictor C 3--20.......................
TMS444 SH7750 Microprocessor Software Support
i
Table of Contents
Specifications
Replaceable Parts List
Index
Channel Assignment Diagram for AMP Mictor D 3--21......................
Channel Assignment Diagram for AMP Mictor E 3--22.......................
Specifications 4--1.............................................
Specification Tables 4--1..............................................
Replaceable Parts List 5--1......................................
Parts Ordering Information 5 --1.........................................
Using the Replaceable Parts List 5--1....................................
ii
TMS444 SH7750 Microprocessor Software Support
List of Figures
Table of Contents
Figure 2--1: Basic timing for SDRAM Burst Read 2--3...............
Figure 2--2: Example of the “All” display format 2--10................
Figure 3 --1: Channel assignments for AMP Mictor A 3--19............
Figure 3 --2: Channel assignments for AMP Mictor C 3--20............
Figure 3 --3: Channel assignments for AMP Mictor D 3--21............
Figure 3 --4: Channel assignments for AMP Mictor E 3 --22............
TMS444 SH7750 Microprocessor Software Support
iii
Table of Contents
List of Tables
Table 2--1: BROM cycle type label definitions 2--6.................
Table 2--2: SDRAM cycle type label definitions 2--7.................
Table 2--3: SRAM cycle type label definitions 2--8..................
Table 2--4: PCMCIA cycle type label definitions 2--8................
Table 2--5: MPX cycle type label definitions 2--8...................
Table 2--6: DRAM cycle type label definitions 2--9..................
Table 2--7: BCSRAM cycle type lab el d efinitions 2--9...............
Table 2--8: General cycle type label definitions 2--9.................
Table 2--9: Cycle typ e label definitions in No Idles/Waits display
format 2--10...............................................
Table 2--10: Interrupt and exception labels 2--12....................
Table 2--11: Logic analyzer disassembly display options 2--12.........
Table 3--1: SH7750_Ctrl group symbol table definitions 3--1.........
Table 3--2: SH7750_ChipSelect group symbol table definitions 3--2...
Table 3--3: Channel assignment groups 3--2.......................
Table 3--4: Address group channel assignments 3--3................
Table 3--5: Data_Hi group channel assignments 3--4................
Table 3--6: Data_Lo group channel assignments 3--5................
Table 3--7: Control group channel assignments 3--6.................
Table 3-- 8: ChipSelect group channel assignments 3-- 7..............
Table 3--9: WE_CAS group channel assignments 3--7...............
Table 3--10: Misc group channel assignments 3--8..................
Table 3-- 11: Mode group channel assignments 3--8..................
Table 3--12: SDRAM group channel assignments 3--9...............
Table 3-- 13: SRAM group channel assignments 3--9................
Table 3--14: BROM group channel assignments 3--9................
Table 3--15: PCMCIA group channel assignments 3--10..............
Table 3-- 16: Clock channel assignments 3--10.......................
Table 3-- 17: Qualifier channel assignments 3--11....................
Table 3--18: Recommended pin assignments for a Mictor connector
(component side) 3--12......................................
T able 3--19: CPU to Mictor connections for AMP Mictor A pins 3--12..
T able 3--20: CPU to Mictor connections for AMP Mictor C pins 3--14..
T able 3--21: CPU to Mictor connections for AMP Mictor D pins 3--15..
T able 3--22: CPU to Mictor connections for AMP Mictor E pins 3--17..
iv
TMS444 SH7750 Microprocessor Software Support
Table of Contents
T able 4--1: Electrical specifications 4--1...........................
TMS444 SH7750 Microprocessor Software Support
v
Table of Contents
vi
TMS444 SH7750 Microprocessor Software Support
Preface
This instruction manual contains specific information about the
TMS444 SH7750 microprocessor support package and is part of a set of
information on how to operate this product on compatible Tektronix logic
analyzers.
If you are familiar with operating microprocessor support packages on the logic
analyzer for which the TMS444 SH7750 support was purchased, you will
probably only need this instruction manual to set up and run the support.
If you are not familiar with operating microprocessor support packages, you will
need to supplement this instruction manual with information on basic operations
to set up and run the support.
Information on basic operations of microprocessor support packages is included
with each product. Each logic analyzer includes basic information that describes
how to perform tasks common to s upport packages on that platform. This
information can be in the form of online help, an installation manual, or a user
manual.
This manual provides detailed information on the following topics:
Manual Conventions
H Connecting the logic analyzer to the target system
H Setting up the logic analyzer to acquire data from the target system
H Acquiring and viewing disassembled data
This manual uses the following conventions:
H The term “disassembler” refers to the software that identifies bus cycles and
displays cycle types.
H The phrase “information on basic operations” refers to logic analyzer online
help, or a user manual covering the basic operations of the microprocessor
support.
H The term “logic analyzer” refers to the Tektronix logic analyzer for which
this product was purchased.
TMS444 SH7750 Microprocessor Software Support
vii
Preface
Contacting Tektronix
Phone 1-800-833-9200*
Address Tektronix, Inc.
Department or name (if known)
14200 SW Karl Braun Dri ve
P.O. Box 500
Beaverton, OR 97077
USA
Web site www.tektronix.com
Sales support 1-800-833-9200, select option 1*
Service support 1-800-833-9200, select option 2*
Technical support Email: techsupport@tektronix.com
1-800-833-9200, select option 3*
1-503-627-2400
6:00 a.m. -- 5:00 p.m. Pacific time
* This phone number is toll free in North America. After office hours, please leave a
voice mail message.
Outside North America, contact a Tektronix sales office or distributor; see the
Tektronix web site for a list of offices.
viii
TMS444 SH7750 Microprocessor Software Support
Getting Started
Getting Started
This section contains information on the TMS444 S H7750 microprocessor
support and information on connecting your logic analyzer to your target system.
Support Package Description
The TMS444 microprocessor support package provides state only support and
software that decodes and displays the cycle types for systems based on the
Hitachi SH7750 microprocessors. This support does not decode the instructions.
Refer to information on basic operations to determine how many modules and
probes your logic analyzer needs to meet the minimum channel requirements for
the TMS444 SH7750 microprocessor support.
To use this support efficiently, you need the items listed in the information on
basic operations as well as the
H Hitachi SuperH RISC engine SH7750 Series (SH7750, SH7750S) Hardware
Manual ADE --602--124C Rev. 4.0 4/21/00 Hitachi, Ltd.
H SH7750 High Performance RISC Engine Programming M anual
ADE--602--156A Rev. 2.0 03/04/99 Hitachi, Ltd.
Logic Analyzer Software Compatibility
The label on the microprocessor support floppy disk states which version of
logic analyzer software this support is compatible with.
Logic Analyzer Configuration
The TMS444 SH7750 support requires a minimum of one 136-channel 100 MHz
acquisition module.
Requirements and Restrictions
Review electrical specifications in the Specifications section in this manual as
they pertain to your target system, as well as the following descriptions of other
TMS444 SH7750 support requirements and restrictions.
TMS444 SH7750 Microprocessor Software Support
1- 1
Getting Started
Hardware Reset. If a hardware reset occurs in your TMS444 SH7750 system
during an acquisition, the application disassembler might acquire invalid
samples.
System Clock Rate. The TMS 444 SH7750 microprocessor support can acquire
data from the SH7750 microprocessor operating at speeds of up to 100 MHz
1
.If
the bus speed is 100MHz, then for proper acquisition the support requires the use
of 200 MHz acquisition module. The TMS444 SH7750 microprocessor support
has been tested for bus speeds of 66 MHz.
Channel Groups. Channel groups required for clocking and disassembly are:
H Address
H Data_Hi
H Data_Lo
H Control
H ChipSelect
H WE_CAS
H Mode
H SDRAM
H SRAM
1- 2
H BROM (burstable ROM)
H PCMCIA
In the Misc group, no signals (except CKIO signal) are required for clocking and
disassembly.
Nonintrusive Acquisition. Acquiring microprocessor bus cycles is nonintrusive to
the target system. That is, the TMS444 SH7750 does not intercept, modify or
present back signals to the target system.
Disabling the Instruction Cache. To display disassembled acquired data, you must
disable the internal instruction cache. Disabling the cache makes all instruction
prefetches visible on the bus so that they can be acquired and their corresponding
cycle types are displayed.
1
Specification at time of printing. Contact your Tektronix sales representative for
current information on the fastest devices supported.
TMS444 SH7750 Microprocessor Software Support
Timing Display Format
Getting Started
Disabling the Data Cache. To display acquired data, you must disable the data
cache. Disabling the data cache makes visible on the bus all of the loads and
stores to memory, including data reads and writes, so that the software can
acquire and display them.
A Timing Display Format file is provided for the support. It sets up the display
to show the following waveforms:
H Address
H Data_Hi
H Data_Lo
H Control
H BS~
H RDY~
H RD/WR~
H ChipSelect
H WE_CAS
NOTE. Address, Data_Hi, Data_Lo, Control, ChipSelect and WE_CAS are
displayed in busform.
The method of selecting or restoring the Timing Display Format file is different
for each platform and is ignored in this document.
Functionality Not Supported
Alternate Bus Master. Alternate bus master transactions are not processed in the
disassembly.
Memory Types. The following memory types are simply identified. Their cycles
are not analyzed.
H MPX
H DRAM
TMS444 SH7750 Microprocessor Software Support
1- 3
Getting Started
H Byte Control SRAM (BCSRAM)
Functionality Not Tested
The following functionalities are supported but not tested.
H PCMCIA Cycles
H SRAM Write Cycles
H BROM Cycles
H Little Endian Mode
Connecting the Logic Analyzer to a Target System
You can use the channel probes, clock probes, and leadsets with a commercial
test clip (or adapter) to make the connections between the logic analyzer and
your target system.
To connect the probes to SH7750 signals in the target system using a test clip,
follow the steps:
1. Power off your target system. It is not necessary to power off the logic
analyzer.
CAUTION. To prevent static damage, handle the microprocessor, probes, and the
logic analyzer module in a static-free environment. Static discharge can damage
these components.
Always wear a grounding wrist strap, heel strap, or similar device while
handling the microprocessor.
2. To discharge your stored static electricity, touch the ground connector
located on the back of the logic analyzer. If you are using a test clip, touch
any of the ground pins on the clip to discharge stored electricity from the test
clip.
CAUTION. To prevent permanent damage to the pins on the microprocessor, place
the target system on a horizontal surface before connecting the test clip.
1- 4
3. Place the target system on a horizontal, static-free surface.
4. Use Tables 3--4 through 3--17 starting on page 3--3 to connect the channel
probes to SH7750 signal pins on the test clip or in the target system.
TMS444 SH7750 Microprocessor Software Support
Getting Started
5. Use leadsets to connect at least one ground lead from each channel and the
ground lead from each clock probe to the ground pins on your test clip.
TMS444 SH7750 Microprocessor Software Support
1- 5
Getting Started
1- 6
TMS444 SH7750 Microprocessor Software Support
Operating Basics
Setting Up the Support
This section provides information on how to set up the support and covers the
following topics:
H Clocking options
H Timing diagram
The information in this section is specific to the operations and functions of the
TMS444 SH7750 support on any Tektronix logic analyzer for which the support
can be purchased. Information on basic operations describes general tasks and
functions.
Before you acquire and display disassembled data, you need to load the support
and specify the setups for clocking and triggering as described in the information
on basic operations. The support provides default values for each of these setups,
but you can change them as needed.
Installing the Support Software
NOTE. Before you install any software, it is recommended you verify that the
microprocessor support software is compatible with the logic analyzer software.
To install the TMS444 SH7750 software on your Tektronix logic analyzer,
follow these steps:
1. Insert the floppy disk in the disk drive.
2. Click the Windows Start button, point to Settings, and click Control Panel.
3. In the Control Panel window, double-click Add/Remove Programs.
4. Follow the instructions on the screen for installing the software from the
floppy disk.
To remove or uninstall software, follow the above instructions and select
Uninstall. You need to close all windows before you uninstall any software.
TMS444 SH7750 Microprocessor Software Support
2- 1
Setting Up the Support
Channel Group Definitions
The software automatically defines channel groups for the support. The channel
groups for the TMS444 SH7750 support are Address, Data_Hi, Data_Lo,
Control, ChipSelect, WE_CAS, Misc, Mode, SDRAM, SRAM, BROM and
PCMCIA. If you want to know which signal is in which group, refer to the
channel assignment tables beginning on page 3--2.
Clocking
Acquisition Setup
Clocking Options
Custom Clocking
The SH7750 affects the logic analyzer setup menus (and submenus) by modifying existing fields and adding microprocessor-specific fields.
On the logic analyzer, the SH7750 adds the selection “SH7750” to the Load
Support Package dialog box, under the File pulldown menu. Once that
“SH7750” has been loaded, the “Custom” clocking mode selection in the logic
analyzer module Setup menu is also enabled.
The TMS444 SH7750 support offers a microprocessor-specific clocking mode
for the SH7750 microprocessor. This clocking mode is the default selection
whenever you load the TMS444 SH7750 support.
Disassembly is not correct when using the Internal or External clocking modes.
Information on basic operations describes how to use these clock selections for
general purpose analysis.
A special clocking program is loaded to the module every time you load the
TMS444 SH7750 support. This special clocking is called Custom.
In this support, with Custom Clocking, the module logs in signals from multiple
channel groups at every rising edge of the CKIO signal. The module then sends
all the logged in signals to the trigger machine and to the acquisition memory of
the module for storage.
2- 2
In Custom clocking, the module clocking state machine (CSM) generates one
master sample for each rising edge of the clock signal CKIO.
When Custom is selected, the Custom Clocking Options menu displays the
subtitle “SH7750 C locking”, and displays the Clocking Option Sample On —
Rising Edge of CKIO. This is the default and the only option available.
TMS444 SH7750 Microprocessor Software Support
Setting Up the Support
Bus Timing Diagram. CKIO is the clockout signal. At every rising edge of
CKIO, all the signals are sampled and mastered for all memory types. A basic
timing for SDRAM Burst Read is given in Figure 2--1.
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
D63-D0
(read)
BS
CKE
Tr Trw T c1 Tc2 Tc3 Tc4/Td1
Row
Row
Row
H/L
c0
Td2
d0 d1 d2 d3
Td3
Td4
DACKn
(SA: IO
memory)
Figure 2- 1: Basic timing for SDRAM Burst Read
TMS444 SH7750 Microprocessor Software Support
2- 3
Setting Up the Support
2- 4
TMS444 SH7750 Microprocessor Software Support
Acquiring and Viewing Disassembled Data
This section describes how to acquire data and view it disassembled. Information
covers the following topics and tasks:
H Acquiring data
H Viewing disassembled data in various display formats
H Viewing cycle type labels
H Changing the way data is displayed
Acquiring Data
Once you load the TMS444 SH7750 support, choose a clocking mode, and
specify the trigger, you are ready to acquire and disassemble data.
If you have any problems acquiring data, refer to information on basic operations
in your logic analyzer online help or Appendix A: Error Messages and
Disassembly Problems in the user manual.
Viewing Disassembled Data
You can view disassembled data in the following display formats:
All (This the default display format)
No Idles/Waits
NOTE. Selections in the Disassembly property page (the Disassembly Format
Definition overlay) must be set correctly for your acquired data to be disassembled correctly. Refer to Changing How Data is Displayed on page 2--11.
The default display format shows the Address, Data_Hi, Data_Lo, Control,
ChipSelect and WE_CAS channel group values for each sample of acquired data.
If a channel group is not visible, you must use the Add Column (Ctrl+L) to make
the group visible.
Timing Display Format
The timing-waveform display format file is provided for the logic analyzer 700
Series support. The timing-waveform display format file sets up and displays the
following waveforms:
TMS444 SH7750 Microprocessor Software Support
2- 5
Acquiring and Viewing Disassembled Data
This is the standard logic analyzer Waveform display. It sets up the display to
show the following waveforms:
Address (busform)
Data_Hi (busform)
Data_Lo (busform)
Control (busform)
BS~
RDY~
RD/WR~
ChipSelect (busform)
WE_CAS (busform)
With the logic analyzer, this file must be loaded before an acquisition is taken.
“All” Display Format
In the “All” display format, the disassembler displays cycle type labels in
parentheses. The following tables list the cycle type labels and give the
definitions of the cycle they represent for all the supported memory types.
Table 2--1 lists these cycle type labels for BROM (Burstable ROM) and
definitions of the cycles they represent.
Table 2- 1: BROM cycle type label definitions
Cycle type Definition
( BROM -- T1 Read Start ) Bus Read Start
( BROM -- T1 Write Start ) Bus Write Start
( BROM -- Read Data ) Data Read
( BROM -- Write Data ) Data Write
( BROM -- TB1 Cycle ) TB1 Cycle
( BROM -- TS1 Cycle ) TS1 (Setup) State
( BROM -- TH1 Cycle ) TH1 (Hold) State
( BROM -- TH2 Cycle ) TH2 (Hold) State
( BROM -- TH3 Cycle ) TH3 (Hold) State
( BROM -- WAIT Cycle ) Wait State
2- 6
( BROM Cycle ) BROM Cycle
TMS444 SH7750 Microprocessor Software Support
Acquiring and Viewing Disassembled Data
Table 2--2 lists the cycle type labels for SDRAM and definitions of the cycles
they represent.
Table 2- 2: SDRAM cycle type label definitions
Cycle type Definition
( SDRAM -- Tpr Cycle ) Pre--Charge
( SDRAM -- Tpc Cycle ) Pre--Charge
( SDRAM -- Trw Cycle ) Row Address Wait
( SDRAM -- Tr Cycle ) Row Address Start
( SDRAM -- Tc1 Cycle ) Tc1 Cycle
( SDRAM -- Tc2 Cycle ) Tc2 Cycle
( SDRAM -- Tc3 Cycle ) Tc3 Cycle
( SDRAM -- Tc4 Cycle ) Tc4 Cycle
( SDRAM(RAS DOWN) -- Tr Cycle ) Tr Cycle (RAS Down Mode)
( SDRAM -- TMw1 Cycle ) SDRAM TMw1 Cycle
( SDRAM(RAS DOWN) -- TRp1 Cycle ) TRp1 Cycle (RAS Down Mode)
( SDRAM Refresh ) Refresh Cycle
( SDRAM(RAS DOWN) -- D1 Write Data)Write Data (RAS Down Mode)
( SDRAM -- Tc1 Single Write Data ) Single Write Data
( SDRAM -- Tc1 D1 Write Data ) Write Data
( SDRAM -- Tc2 D2 Write Data ) Write Data
( SDRAM -- Tc3 D3 Write Data ) Write Data
( SDRAM -- Tc4 D4 Write Data ) Write Data
( SDRAM -- Td1 D1 Read Data ) Read Data
( SDRAM -- Td2 D2 Read Data ) Read Data
( SDRAM -- Td3 D3 Read Data ) Read Data
( SDRAM -- Td4 D4 Read Data ) Read Data
( SDRAM Cycle ) SDRAM Cycle
TMS444 SH7750 Microprocessor Software Support
2- 7
Acquiring and Viewing Disassembled Data
Table 2--3 lists these cycle type labels for SRAM and definitions of the cycles
they represent.
Table 2- 3: SRAM cycle type label definitions
Cycle type Definition
( SRAM -- T1 Read Start ) Bus Read Start
( SRAM -- T2 Read Data ) Data Read
( SRAM -- T1 Write Start ) Bus Write Start
( SRAM -- T2 Write Data ) Data Write
( SRAM -- WAIT Cycle ) Wait Cycl e
( SRAM Cycle ) SRAM Cycle
Table 2--4 lists the cycle type labels for PCMCIA and definitions of the cycles
they represent.
Table 2- 4: PCMCIA cycle type label definitions
Cycle type Definition
( PCMCIA -- Memory Read Start ) Bus Read Start
( PCMCIA -- Memory Read Data ) Data Read
( PCMCIA -- Memory Write Start ) Bus Write Start
( PCMCIA -- Memory Write Data ) Data Write
( PCMCIA -- I/O Read Start ) Bus Read Start
( PCMCIA -- I/O Read Data ) Data Read
( PCMCIA -- I/O Write Start ) Bus Write Start
( PCMCIA -- I/O Write Data ) Data Write
( PCMCIA -- WAIT Cycle ) Wait Cycle
( PCMCIA -- Hold Wait ) Hold Wait
( PCMCIA Cycle ) PCMCIA Cycle
Table 2--5 lists the cycle type labels for MPX and definitions of the cycles they
represent.
2- 8
Table 2- 5: MPX cycle type label definitions
Cycle type Definition
( MPX -- Cycle ) Any MPX Cycle
TMS444 SH7750 Microprocessor Software Support
Acquiring and Viewing Disassembled Data
Table 2--6 lists the cycle type labels for DRAM and definitions of the cycles they
represent.
Table 2- 6: DRAM cycle type label definitions
Cycle type Definition
( DRAM -- Cycle ) Any DRAM Cycle
Table 2--7 lists the cycle type labels for BCSRAM (Byte Control SRAM) and
definitions of the cycles they represent.
Table 2- 7: BCSRAM cycle type label definitions
Cycle type Definition
( BCSRAM -- Cycle ) Any BCSRAM Cycle
Table 2--8 lists the General cycle type labels and the definitions of the cycles
they represent.
Table 2- 8: General cycle type label definitions
Cycle types Definition
( RESET ) Reset
( MANUAL RESET ) Manual Reset
( Idle Cycle ) Idle Cycle
( No devices selected ) No devices selected
( UNKNOWN ) Unknown combination
TMS444 SH7750 Microprocessor Software Support
2- 9
Acquiring and Viewing Disassembled Data
Figure 2-- 2 displays an example of the “All” display format.
Figure 2- 2: Example of the “All “ display format
“No Idles/Waits” Display
Format
In “No Idles/Waits” display format only the data cycles are displayed. Other bus
cycles such as Bus starts, Waits and Idles are suppressed. The data cycles type
labels given in Tables 2--1 through 2--8 are displayed in this format.
Table 2--9 lists the cycle type label definitions and definitions of the cycles they
represent.
Table 2- 9: Cycle type label definitions in “No Idles/Waits” display format
Cycle type Definition
( BROM -- Read Data ) Data Read
( BROM -- Write Data ) Data Write
( SDRAM -- Tc1 Single Write Data ) Single Write Data
( SDRAM -- Tc1 D1 Write Data ) Write Data
2- 10
TMS444 SH7750 Microprocessor Software Support
Acquiring and Viewing Disassembled Data
Table 2- 9: Cycle type label definitions in “No Idles/Waits” display format (Cont.)
Cycle type Definition
( SDRAM(RAS DOWN) -- D1 Write Data)Write Data
( SDRAM -- Tc2 D2 Write Data ) Write Data
( SDRAM -- Tc3 D3 Write Data ) Write Data
( SDRAM -- Tc4 D4 Write Data ) Write Data
( SDRAM -- Td1 D1 Read Data ) Read Data
( SDRAM -- Td2 D2 Read Data ) Read Data
( SDRAM -- Td3 D3 Read Data ) Read Data
( SDRAM -- Td4 D4 Read Data ) Read Data
( SRAM -- T2 Read Data ) Read Data
( SRAM -- T2 Write Data ) Write Data
( PCMCIA -- Memory Read Data ) Read Data
( PCMCIA -- Memory Write Data ) Write Data
( PCMCIA -- I/O Read Data ) Read Data
( PCMCIA -- I/O Write Data ) Write Data
( MPX -- Cycle ) Any MPX Cycle
( DRAM -- Cycle ) Any DRAM Cycle
( BCSRAM -- Cycle ) Any BCSRAM Cycle
Changing How Data is Displayed
There are common fields and features that allow you to further modify displayed
data to suit your needs. You can make common and optional display selections in
the Disassembly property page (the Disassembly Format Definition overlay).
You can make selections unique to the TMS444 SH7750 support to do the
following tasks:
H Change how data is displayed across all display formats
H Display exception cycles
Optional Display
Selections
You can make optional selections for disassembled data. Refer to the information
on basic operations for more information.
TMS444 SH7750 Microprocessor Software Support
2- 11
Acquiring and Viewing Disassembled Data
Displaying Exception
Labels
The disassembler can display SH7750 exception labels. The exception table must
reside in external memory for interrupt and exception cycles to be visible to the
disassembler.
Enter the Vector Base Address in the Vector Base Register field. This field is
located in the Disassembly property page (Disassembly Format Definition
overlay).
Table 2--10 lists the SH7750 interrupt and exception labels.
Table 2- 10: Interrupt and exception labels
Offset Displayed interrupt or exception name
0x00100 ( GENERAL EXCEPTION )
0x00400 ( INTERRUPT--COMPLETION TYPE )
0x00600 ( TLB DATA/INST MISS EXCEPTION )
Disassembly Display Options
Table 2- 11: Logic analyzer disassembly display options
Micro Specific Fields
Description Option
Show: All (Default)
No Idles/Wait s
Highlight: No Idles/Waits (Default)
None
Disassemble Across Gaps: Yes
No (Default)
After you load the TMS444 SH7750 support, choose a clocking mode and
specify the trigger. Open the Disassembly window by right clicking on the
Listing window and selecting Properties. The following paragraph lists the
options:
2- 12
TMS444 SH7750 Microprocessor Software Support
Acquiring and Viewing Disassembled Data
Memory type connected to each of the seven areas. Choose the memory connected to each area using the drop-down bar. If no device is connected to a
particular area, select “No Device”. By default the selection is “No Device”.
AREA 0 (CS0~): Choose the memory type connected to AREA 0 by selecting
one of the options.
Area 0 (CS0~): No Device (default)
SRAM
BROM
MPX
AREA 1 (CS1~): Choose the memory type connected to AREA 1 by selecting
one of the options.
Area 1 (CS1~): No Device (default)
SRAM
BCSRAM
MPX
AREA 2 (CS2~): Choose the memory type connected to AREA 2 by selecting
one of the options.
Area 2 (CS2~): No Device (default)
SRAM
SDRAM
DRAM
MPX
AREA 3 (CS3~): Choose the memory type connected to AREA 3 by selecting
one of the options.
Area 3 (CS3~): No Device (default)
SRAM
SDRAM
DRAM
MPX
AREA 4 (CS4~): Choose the memory type connected to AREA 4 by selecting
one of the options.
Area 4 (CS4~): No Device (default)
SRAM
BCSRAM
MPX
TMS444 SH7750 Microprocessor Software Support
2- 13
Acquiring and Viewing Disassembled Data
AREA 5 (CS5~): Choose the memory type connected to AREA 5 by selecting
one of the options.
Area 5 (CS5~): No Device (default)
AREA 6 (CS6~): Choose the memory type connected to AREA 6 by selecting
one of the options.
Area 6 (CS6~): No Device (default)
NOTE. If nonburstable Flash Memory is used, select the SRAM option.
SRAM
BROM
PCMCIA
MPX
SRAM
BROM
PCMCIA
MPX
AREA0 SRAM Bus Width. Choose the Bus Width of the SRAM connected.
AREA0 SRAM Bus Width: 32 (default)
64
16
8
AREA1 SRAM Bus Width. Choose the Bus Width of the SRAM connected.
AREA1 SRAM Bus Width: 32 (default)
64
16
8
AREA2 SRAM Bus Width. Choose the Bus Width of the SRAM connected.
AREA2 SRAM Bus Width: 32 (default)
64
16
8
2- 14
TMS444 SH7750 Microprocessor Software Support
Acquiring and Viewing Disassembled Data
AREA3 SRAM Bus Width. Choose the Bus Width of the SRAM connected.
AREA3 SRAM Bus Width: 32 (default)
64
16
8
AREA4 SRAM Bus Width. Choose the Bus Width of the SRAM connected.
AREA4 SRAM Bus Width: 32 (default)
64
16
8
AREA5 SRAM Bus Width. Choose the Bus Width of the SRAM connected.
AREA5 SRAM Bus Width: 32 (default)
64
16
8
AREA6 SRAM Bus Width. Choose the Bus Width of the SRAM connected.
AREA6 SRAM Bus Width: 32 (default)
64
16
8
BROM Bus Width. Choose the width of the bus connected to the BROM by
selecting one of the options.
BROM Bus Width: 32 bits (default)
16 bits
8 bits
SDRAM Bus Width. Choose the width of the bus connected to the SDRAM by
selecting one of the options.
SDRAM Bus Width: 32 bits (default)
64 bits
PCMCIA- AREA 5 Bus. Choose the width of the bus connected to the PCMCIA in
AREA 5 by selecting one of the options.
PCMCIA--AREA 5: Fixed (default)
TMS444 SH7750 Microprocessor Software Support
Dynamic
2- 15
Acquiring and Viewing Disassembled Data
PCMCIA- AREA 6 Bus. Choose the width of the bus connected to the PCMCIA in
AREA 6 by selecting one of the options.
PCMCIA--AREA 6: Fixed (default)
PCMCIA- AREA 5 Hold. Choose the number of PCMCIA Hold Wait states.
PCMCIA--AREA 5 Hold: 15 (default)
PCMCIA- AREA 6 Hold. Choose the number of PCMCIA Hold Wait states.
Dynamic
12
9
6
3
2
1
0
PCMCIA--AREA 6 Hold: 15 (default)
12
9
6
3
2
1
0
AREA 0 WAIT STATES. Choose the number of wait states for the device connected
to this area.
AREA 0 WAIT STATES: 15 (default)
12
9
6
3
2
1
0
2- 16
TMS444 SH7750 Microprocessor Software Support
Acquiring and Viewing Disassembled Data
AREA 1 WAIT STATES. Choose the number of wait states for the device connected
to this area.
AREA 1 WAIT STATES: 15 (default)
12
9
6
3
2
1
0
AREA 2 WAIT STATES. Choose the number of wait states for the device connected
to this area.
AREA 2 WAIT STATES: 15 (default)
12
9
6
3
2
1
0
AREA 3 WAIT STATES. Choose the number of wait states for the device connected
to this area.
AREA 3 WAIT STATES: 15 (default)
12
9
6
3
2
1
0
TMS444 SH7750 Microprocessor Software Support
2- 17
Acquiring and Viewing Disassembled Data
AREA 4 WAIT STATES. Choose the number of wait states for the device connected
to this area.
AREA 4 WAIT STATES: 15 (default)
AREA 5 WAIT STATES. Choose the number of wait states for the device connected
to this area.
AREA 5 WAIT STATES: 15 (default)
12
9
6
3
2
1
0
12
9
6
3
2
1
0
AREA 6 WAIT STATES. Choose the number of wait states for the device connected
to this area.
AREA 6 WAIT STATES: 15 (default)
12
9
6
3
2
1
0
AREA 0 WAIT BY RDY~. Choose the wait state insertion by RDY~ pin by selecting
one of the options.
AREA 0 WAIT BY R DY~: ZERO (default)
NON-ZERO
2- 18
TMS444 SH7750 Microprocessor Software Support
Acquiring and Viewing Disassembled Data
AREA 1 WAIT BY RDY~. Choose the wait state insertion by RDY~ pin by selecting
one of the options.
AREA 1 WAIT BY R DY~: ZERO (default)
NON-ZERO
AREA 2 WAIT BY RDY~. Choose the wait state insertion by RDY~ pin by selecting
one of the options.
AREA 2 WAIT BY R DY~: ZERO (default)
NON-ZERO
AREA 3 WAIT BY RDY~. Choose the wait state insertion by RDY~ pin by selecting
one of the options.
AREA 3 WAIT BY R DY~: ZERO (default)
NON-ZERO
AREA 4 WAIT BY RDY~. Choose the wait state insertion by RDY~ pin by selecting
one of the options.
AREA 4 WAIT BY R DY~: ZERO (default)
NON-ZERO
AREA 5 WAIT BY RDY~. Choose the wait state insertion by RDY~ pin by selecting
one of the options.
AREA 5 WAIT BY R DY~: ZERO (default)
NON-ZERO
AREA 6 WAIT BY RDY~. Choose the wait state insertion by RDY~ pin by selecting
one of the options.
AREA 6 WAIT BY R DY~: ZERO (default)
NON-ZERO
TMS444 SH7750 Microprocessor Software Support
2- 19
Acquiring and Viewing Disassembled Data
AMX Setting. The AMX setting is required for the Address Multiplexing feature
of SDRAM. For example, for a bus width of 32 bits, when four banks of
(1Meg*8bit*2) are connected the AMX selection is 1.
AMX Setting: 0 (default)
AMXEXT Setting. The AMXEXT setting is required for the Address Multiplexing
feature of SDRAM. For example, for a bus width of 32 bits, when four banks of
(1Meg*8bit*2) are connected the AMXEXT selection is 0.
AMXEXT Setting: 0 (default)
1
2
3
4
5
6
7
1
BROM Setup. Choose the number of BROM setup cycles introduced.
BROM Setup: 0 (default)
1
BROM Hold. Choose the number of BROM hold cycles introduced.
BROM Hold: 0 (default)
1
2
3
Vector Base Register. Enter the contents of the 32 bit Vector Base Register. The
default value is 0x00000000.
After choosing the options, you are ready to acquire and disassemble data. If you
have any problems acquiring data, refer to information on basic operations in
your online help or in the user manual.
2- 20
TMS444 SH7750 Microprocessor Software Support
Viewing an Example of Disassembled Data
A demonstration system file (or demonstration reference memory) is provided on
your software disk to view an example of how your SH7750 microprocessor bus
cycles looks when they are disassembled. Viewing this system file is not a
requirement for preparing the module for use and you can view it without
connecting the logic analyzer to your target system.
Information on basic operations describes how to view the file.
Acquiring and Viewing Disassembled Data
TMS444 SH7750 Microprocessor Software Support
2- 21
Acquiring and Viewing Disassembled Data
2- 22
TMS444 SH7750 Microprocessor Software Support
Reference
Reference:Tables
Symbol Tables
This section lists the symbol tables and channel assignment tables for disassembly and timing.
The TMS444 SH7750 support supplies two symbol-table files. The SH7750_Ctrl
file replaces specific Control-channel group values with symbolic values when
Symbolic is the radix for the channel group.
Table 3--1 shows the definitions for name, bit pattern and meaning of the Control
group symbols in file SH7750_Ctrl.
Table 3- 1: SH7750_Ctrl group symbol table definitions
Control group value
RESET~ RAS~
MRESET~ RD/CASS~
Symbol
RESET 0 XXX XXX Reset
MANUAL RESET X0XX XXX Manual reset
WRITE 110X XX0 Write
BUS START 110X XXX Bus start
READ 11XX XX1 Read
WRITE 11XX XX0 Write
BS~ RD/WR~
RDY~
Description
Information on basic operations describes how to use symbolic values for
triggering and for displaying other channel groups symbolically, such as for the
Address channel group.
TMS444 SH7750 Microprocessor Software Support
3- 1
Reference: Tables
Table 3--2 shows the definitions for name, bit pattern, and meaning of the
ChipSelect group symbols.
Table 3- 2: SH7750_ChipSelect group symbol table definitions
ChipSelect group value
MD3CE2A~ MD4CE2B~ CS3~
Symbol
NO DEVICE X X111 1111 No device
CS0~ XX111 1110 CS0~
CS1~ X X111 1101 CS1~
CS2~ X X111 1011 CS2~
CS3~ XX1110111 CS3~
CS4~ X X110 1111 CS4~
CS5~ X X101 1111 CS5~
CS5~ 0 1111 1111 CS5~
CS6~ X X011 1111 CS6~
CS6~ 1 0111 1111 CS6~
MORE DEVICES X XXXX XXXX MORE DEVICES
CS6~ CS2~
CS5~ CS1~
CS4~ CS0~
Description
Channel Assignment Tables
Channel assignments shown in Table 3--3 through Table 3--17 use the following
conventions:
H All signals are required by the support unless indicated otherwise.
H Channels are shown starting with the most significant bit (MSB) descending
to the least significant b it (LSB).
H Channel group assignments are for all modules unless otherwise noted.
H A tilde (~) following a signal name indicates an active low signal.
Table 3--3 displays the order in which the channel group assignments are
displayed.
Table 3- 3: Channel assignment groups
Group name Display radix
Address Hexadecimal
Data_Hi Hexadecimal
3- 2
TMS444 SH7750 Microprocessor Software Support
Reference: Tables
Table 3- 3: Channel assignment groups (Cont.)
Group name Display radix
Data_Lo Hexadecimal
Control Symbolic
ChipSelect Symbolic
WE_CAS BIN
Misc OFF
Mode OFF
SDRAM OFF
SRAM OFF
BROM OFF
PCMCIA OFF
Table 3--4 shows the channel assignments for the logic analyzer Address group
and the microprocessor signal to which each channel connects. By default, this
channel group is displayed in hexadecimal.
Table 3- 4: Address group channel assignments
Bit order Section:channel SH7750 support channel name
25 A3:1 A25
24 A3:0 A24
23 A2:7 A23
22 A2:6 A22
21 A2:5 A21
20 A2:4 A20
19 A2:3 A19
18 A2:2 A18
17 A2:1 A17
16 A2:0 A16
15 A1:7 A15
14 A1:6 A14
13 A1:5 A13
12 A1:4 AA
11 A1:3 A11
10 A1:2 A10
TMS444 SH7750 Microprocessor Software Support
3- 3
Reference: Tables
Table 3- 4: Address group channel assignments (Cont.)
Bit order SH7750 support channel nameSection:channel
9 A1:1 A9
8 A1:0 A8
7 A0:7 A7
6 A0:6 A6
5 A0:5 A5
4 A0:4 A4
3 A0:3 A3
2 A0:2 A2
1 A0:1 A1
0 A0:0 A0
Table 3--5 shows the probe section and channel assignments for the Data_Hi
group and the microprocessor signal to which each channel connects. By default,
this channel group is displayed in hexadecimal.
Table 3- 5: Data_Hi group channel assignments
Bit order Section:channel SH7750 support channel name
31 E3:7 D63
30 E3:6 D62
29 E3:5 D61
28 E3:4 D60
27 E3:3 D59
26 E3:2 D58
25 E3:1 D57
24 E3:0 D56
23 E2:7 D55
22 E2:6 D54
21 E2:5 D53
20 E2:4 D52
3- 4
19 E2:3 D51
18 E2:2 D50
17 E2:1 D49
16 E2:0 D48
TMS444 SH7750 Microprocessor Software Support
Table 3- 5: Data_Hi group channel assignments (Cont.)
Bit order SH7750 support channel nameSection:channel
15 E1:7 D47
14 E1:6 D46
13 E1:5 D45
12 E1:4 D44
11 E1:3 D43
10 E1:2 D42
9 E1:1 D41
8 E1:0 D40
7 E0:7 D39
6 E0:6 D38
5 E0:5 D37
4 E0:4 D36
Reference: Tables
3 E0:3 D35
2 E0:2 D34
1 E0:1 D33
0 E0:0 D32
Table 3--6 shows the probe section and channel assignments for the Data_Lo
group and the microprocessor signal to which each channel connects. By default,
this channel group is displayed in hexadecimal.
Table 3- 6: Data_Lo group channel assignments
Bit order Section:channel SH7750 support channel name
31 D3:7 D31
30 D3:6 D30
29 D3:5 D29
28 D3:4 D28
27 D3:3 D27
26 D3;2 D26
25 D3:1 D25
24 D3:0 D24
23 D2:7 D23
22 D2:6 D22
TMS444 SH7750 Microprocessor Software Support
3- 5
Reference: Tables
Table 3- 6: Data_Lo group channel assignments (Cont.)
Bit order SH7750 support channel nameSection:channel
21 D2:5 D21
20 D2:4 D20
19 D2:3 D19
18 D2:2 D18
17 D2:1 D17
16 D2:0 D16
15 D1:7 D15
14 D1:6 D14
13 D1:5 D13
12 D1:4 D12
11 D1:3 D11
10 D1:2 D10
9 D1:1 D9
8 D1:0 D8
7 D0:7 D7
6 D0:6 D6
5 D0:5 D5
4 D0:4 D4
3 D0:3 D3
2 D0:2 D2
1 D0:1 D1
0 D0:0 D0
Table 3--7 shows the probe section and channel assignments for the Control
group and the microprocessor signal to which each channel connects. By default,
this channel group is displayed as symbols. The symbol table file name is
SH7750_Ctrl.
Table 3- 7: Control group channel assignments
Bit order Section:channel SH7750 support channel name
6 Q0 RESET~
5 C2:0 MRESET~
4 Clock:2 BS~
3- 6
TMS444 SH7750 Microprocessor Software Support
Reference: Tables
Table 3- 7: Control group channel assignments (Cont.)
Bit order SH7750 support channel nameSection:channel
3 Clock:3 RDY~
2 Clock:1 RAS~
1 C2:2 RD/CASS~
0 C2:1 RD/WR~
Table 3--8 shows the probe section and channel assignments for the ChipSelect
group and the microprocessor signal to which each channel connects. By default,
this channel group is displayed as binary.
Table 3- 8: ChipSelect group channel assignments
Bit order Section:channel SH7750 support channel name
8 C2:6 MD3CE2A~
7 C2:7 MD4CE2B~
6 C1:6 CS6~
5 C1:5 CS5~
4 C1:4 CS4~
3 C1:3 CS3~
2 C1:2 CS2~
1 C1:1 CS1~
0 C1:0 CS0~
Table 3--9 shows the probe section and channel assignments for the logic
analyzer WE_CAS group and the microprocessor signal to which each channel
connects. By default, this channel group is displayed in binary.
Table 3- 9: WE_CAS group channel assignments
Bit order Section:channel SH7750 support channel name
7 C0:7 WE/CAS7~
6 C0:6 WE/CAS6~
5 C0:5 WE/CAS5~
4 C0:4 WE/CAS4~
3 C0:3 WE/CAS3~
2 C0:2 WE/CAS2~
TMS444 SH7750 Microprocessor Software Support
3- 7
Reference: Tables
Table 3- 9: WE_CAS group channel assignments (Cont.)
Bit order SH7750 support channel nameSection:channel
1 C0:1 WE/CAS1~
0 C0:0 WE/CAS0~
Table 3--10 shows the probe section and channel assignments for the logic
analyzer Misc group and the microprocessor signal to which each channel
connects. By default, this channel group is not visible.
Table 3- 10: Misc group channel assignments
Bit order Section:channel SH7750 support channel name
7 Clock:0 CKIO
6 Qual:3 DACK1
5 Qual:2 DACK0
4 A3:3 DREQ1~
3 A3:2 DREQ0~
2 A3:5 DRAK1
1 A3:4 DRAK0
0 C1:7 NMI
Table 3--11 shows the probe section and channel assignments for the logic
analyzer Mode group and the microprocessor signal to which each channel
connects. By default, this channel group is not visible.
Table 3- 11: Mode group channel assignments
Bit order Section:channel SH7750 support channel name
8 C3:3 MD8~
7 C3:2 MD7~
6 C3:1 MD6~
5 C3:0 MD5~
4 C2:7 MD4CE2B~
3- 8
3 C2:6 MD3CE2A~
2 C2:5 MD2~
1 C2:4 MD1~
0 C2:3 MD0~
TMS444 SH7750 Microprocessor Software Support
Reference: Tables
Table 3--12 shows the probe section and channel assignments for the logic
analyzer SDRAM group and the microprocessor signal to which each channel
connects. By default, this channel group is not visible.
Table 3- 12: SDRAM group channel assignments
Bit order Section:channel SH7750 support channel name
3 Clock:1 RAS~
2 C2:2 RD/CASS~
1 Clock:2 BS~
0 C2:1 RD/WR~
Table 3--13 shows the probe section and channel assignments for the logic
analyzer SRAM group and the microprocessor signal to which each channel
connects. By default, this channel group is not visible.
Table 3- 13: SRAM group channel assignments
Bit order Section:channel SH7750 support channel name
3 Clock:2 BS~
2 C2:1 RD/WR~
1 C2:2 RD/CASS~
0 Clock:3 RDY~
Table 3--14 shows the probe section and channel assignments for the logic
analyzer BROM group and the microprocessor signal to which each channel
connects. By default, this channel group is not visible.
Table 3- 14: BROM group channel assignments
Bit order Section:channel SH7750 support channel name
3 Clock:2 BS~
2 Clock:3 RDY~
1 C2:1 RD/WR~
0 C2:2 RD/CASS~
TMS444 SH7750 Microprocessor Software Support
3- 9
Reference: Tables
Table 3--15 shows the probe section and channel assignments for the logic
analyzer PCMCIA group and the microprocessor signal to which each channel
connects. By default, this channel group is not visible.
Table 3- 15: PCMCIA group channel assignments
Bit order Section:channel SH7750 support channel name
10 Clock:2 BS~
9 Clock:3 RDY~
8 C2:1 RD/WR~
7 C2:2 RD/CASS~
6 C0:1 WE/CAS1~
5 C0:2 WE/CAS2~
4 C0:3 WE/CAS3~
3 C0:7 WE/CAS7~
2 C2:6 MD3CE2A~
1 C2:7 MD4CE2B~
0 C3:1 MD6
Table 3--16 shows the probe section and channel assignments for the clock
probes (not part of any group) and the SH7750 signal to which each channel
connects.
Table 3- 16: Clock channel assignments
SH7750 support
Logic analyzer
section & probe
Clock:3 RDY~ C5
Clock:2 BS~ D6
Clock:1 RAS~ A6
Clock:0 CKIO A5
package channel
name
AMP Mictor pin
number
3- 10
TMS444 SH7750 Microprocessor Software Support
Reference: Tables
Table 3--17 shows the probe section and qualifier channel assignments.
Table 3- 17: Qualifier channel assignments
SH7750 support
Logic analyzer
section & probe
QUAL:3 DACK1 E5
QUAL:2 DACK0 E6
QUAL:1 -- -- -- -- -- -- -- --
QUAL:0 RESET~ D5
package channel
name
AMP Mictor pin
number
Since the acquisition is Clock by Clock, Clock:2-0, C2:3-0 and QUAL:3-0, are
used as Data, not as qualifiers.
TMS444 SH7750 Microprocessor Software Support
3- 11
Reference: Tables
CPU To Mictor Connections
For design purposes, you may need to make connections between the CPU and
the Mictor pins of the P6434 Mass Termination Probe. Refer to the P6434 Mass
Termination Probe manual, Tektronix part number 070-9793-XX, for more
information on mechanical specifications. Tables 3--19 through 3--22 show the
CPU pin to Mictor pin connections.
NOTE. To preserve signal quality in the target system, it is recommended that a
180 Ω resistor is connected in series between each ball pad of the CPU and each
pin of the Mictor connector. The resistor must be within 1/2 inch of the ball pad
of the CPU.
The recommended pin assignment is the AMP pin assignment, because the AMP
circuit board layout model and other commercial CAD packages use the Amp
numbering scheme. See Table 3--18.
Table 3- 18: Recommended pin assignments for a Mictor connector
(component side)
Graphic column Text column
Recommended. This pin assignment is the industry
Recommended
Pin 1
Pin 37
AMP Pin Assignment
Pin 2
Pin 38
standard and is what we recommend that you use.
Table 3- 19: CPU to Mictor connections for AMP Mictor A pins
QFP208
Logic analyzer
channel
NC 1 -- --
AMP Mictor A
pin number
SH7750 support channel
name
Package pin
number
3- 12
NC 2 -- --
NC 3 -- --
NC 4 -- --
CLOCK1 6 RAS~ 93
TMS444 SH7750 Microprocessor Software Support
Reference: Tables
Table 3- 19: CPU to Mictor connections for AMP Mictor A pins (Cont.)
QFP208
Logic analyzer
channel
CLOCK0 5 CKIO 77
A3:7 7 BREQ/BSACK~ 52
A3:6 9 -- --
A3:5 11 DRAK1 85
A3:4 13 DRAK0 86
A3:3 15 DREQ1~ 107
A3:2 17 DREQ0~ 106
A3:1 19 A25 180
A3:0 21 A24 179
A2:7 23 A23 176
AMP Mictor A
pin number
SH7750 support channel
name
Package pin
number
A2:6 25 A22 175
A2:5 27 A21 174
A2:4 29 A20 173
A2:3 31 A19 172
A2:2 33 A18 171
A2:1 35 A17 62
A2:0 37 A16 63
A1:7 8 A15 64
A1:6 10 A14 67
A1:5 12 A13 68
A1:4 14 A12 71
A1:3 16 A11 72
A1:2 18 A10 73
A1:1 20 A9 74
A1:0 22 A8 75
A0:7 24 A7 76
A0:6 26 A6 80
A0:5 28 A5 81
A0:4 30 A4 82
A0:3 32 A3 83
A0:2 34 A2 84
TMS444 SH7750 Microprocessor Software Support
3- 13
Reference: Tables
Table 3- 19: CPU to Mictor connections for AMP Mictor A pins (Cont.)
QFP208
Logic analyzer
channel
A0:1 36 A1 189
A0:0 38 A0 186
AMP Mictor A
pin number
SH7750 support channel
name
Package pin
number
Table 3- 20: CPU to Mictor connections for AMP Mictor C pins
QFP208
Logic analyzer
channel
NC 1 -- --
NC 2 -- --
NC 3 -- --
AMP Mictor C
pin number
SH7750 support channel
name
Package pin
number
NC 4 -- --
CLOCK3 5 RDY~ 1
QUAL1 6 -- --
C3:7 7 BACK/BSREQ~ 51
C3:6 9 CKE 55
C3:5 11 STATUS1 191
C3:4 13 STATUS0 190
C3:3 15 MD8/RTS2~ 166
C3:2 17 MD7/TXD 167
C3:1 19 MD6/IOIS16~ 92
C3:0 21 MD5/RAS2~ 183
C2:7 23 MD4/CE2B~ 182
C2:6 25 MD3/CE2A~ 181
C2:5 27 MD2/RXD2 151
C2:4 29 MD1/TXD2 150
C2:3 31 MD0/SCK 149
C2:2 33 RD~/CASS~/FRAME~ 94
3- 14
C2:1 35 RD/WR~ 95
C2:0 37 SCK2/MRESET~ 168
C1:7 8 NMI 156
C1:6 10 CS6~ 7
TMS444 SH7750 Microprocessor Software Support
Reference: Tables
Table 3- 20: CPU to Mictor connections for AMP Mictor C pins (Cont.)
QFP208
Logic analyzer
channel
C1:5 12 CS5~ 6
C1:4 14 CS4~ 5
C1:3 16 CS3~ 89
C1:2 18 CS2~ 90
C1:1 20 CS1~ 4
C1:0 22 CS0~ 3
C0:7 24 WE7~/CAS7~/DQM7/REG~ 101
C0:6 26 WE6~/CAS6~/DQM6 98
C0:5 28 WE5~/CAS5~/DQM5~ 58
C0:4 30 WE4~/CAS4~/DQM4~ 59
AMP Mictor C
pin number
SH7750 support channel
name
Package pin
number
C0:3 32 WE3~/CAS3~/DQM3~/ICIOWR~ 97
C0:2 34 WE2~/CAS2~/DQM2~/ICIORD~ 96
C0:1 36 WE1~/CAS1~/DQM1 60
C0:0 38 WE0~/CAS0~/DQM0 61
Table 3- 21: CPU to Mictor connections for AMP Mictor D pins
QFP208
Logic analyzer
channel
NC 1 -- --
NC 2 -- --
NC 3 -- --
NC 4 -- --
CLOCK2 6 BS~ 8
QUAL0 5 RESET~ 2
D3:7 7 D31 124
D3:6 9 D30 122
AMP Mictor D
pin number
SH7750 support channel
name
Package pin
number
D3:5 11 D29 120
D3:4 13 D28 116
D3:3 15 D27 112
D3:2 17 D26 110
TMS444 SH7750 Microprocessor Software Support
3- 15
Reference: Tables
Table 3- 21: CPU to Mictor connections for AMP Mictor D pins (Cont.)
QFP208
Logic analyzer
channel
D3:1 19 D25 108
D3:0 21 D24 103
D2:7 23 D23 102
D2:6 25 D22 104
D2:5 27 D21 109
D2:4 29 D20 111
D2:3 31 D19 115
D2:2 33 D18 119
D2:1 35 D17 121
D2:0 37 D16 123
AMP Mictor D
pin number
SH7750 support channel
name
Package pin
number
D1:7 8 D15 33
D1:6 10 D14 35
D1:5 12 D13 37
D1:4 14 D12 41
D1:3 16 D11 45
D1:2 18 D10 47
D1:1 20 D9 49
D1:0 22 D8 53
D0:7 24 D7 54
D0:6 26 D6 50
D0:5 28 D5 48
D0:4 30 D4 46
D0:3 32 D3 42
D0:2 34 D2 38
D0:1 36 D1 36
D0:0 38 D0 34
3- 16
TMS444 SH7750 Microprocessor Software Support
Table 3- 22: CPU to Mictor connections for AMP Mictor E pins
Logic analyzer
channel
NC 1 -- --
NC 2 -- --
NC 3 -- --
NC 4 -- --
QUAL3 5 DACK1 185
QUAL2 6 DACK0 184
E3:7 7 D63 146
E3:6 9 D62 142
E3:5 11 D61 140
E3:4 13 D60 138
AMP Mictor E
pin number
SH7750 support channel
name
Reference: Tables
QFP208
Package pin
number
E3:3 15 D59 134
E3:2 17 D58 132
E3:1 19 D57 130
E3:0 21 D56 128
E2:7 23 D55 127
E2:6 25 D54 129
E2:5 27 D53 131
E2:4 29 D52 133
E2:3 31 D51 137
E2:2 33 D50 139
E2:1 35 D49 141
E2:0 37 D48 145
E1:7 8 D47 11
E1:6 10 D46 15
E1:5 12 D45 17
E1:4 14 D44 19
E1:3 16 D43 23
E1:2 18 D42 25
E1:1 20 D41 27
E1:0 22 D40 29
E0:7 24 D39 30
TMS444 SH7750 Microprocessor Software Support
3- 17
Reference: Tables
Table 3- 22: CPU to Mictor connections for AMP Mictor E pins (Cont.)
QFP208
Logic analyzer
channel
E0:6 26 D38 28
E0:5 28 D37 26
E0:4 30 D36 24
E0:3 32 D35 20
E0:2 34 D34 18
E0:1 36 D33 16
E0:0 38 D32 12
AMP Mictor E
pin number
SH7750 support channel
name
Package pin
number
3- 18
TMS444 SH7750 Microprocessor Software Support
Reference: Tables
Channel Assignments with AMP Mictor Connector diagrams for SH7750 QFP208 Package
The Figures 3--1 through 3 --4 show the channel assignments with the AMP
Mictors for the SH7750 QFP208 package.
Channel Assignment Diagram for AMP Mictor A
Figure 3- 1: Channel assignments for AMP Mictor A
TMS444 SH7750 Microprocessor Software Support
3- 19
Reference: Tables
Channel Assignment Diagram for AMP Mictor C
Figure 3- 2: Channel assignments for AMP Mictor C
3- 20
TMS444 SH7750 Microprocessor Software Support
Channel Assignment Diagram for AMP Mictor D
Reference: Tables
Figure 3- 3: Channel assignments for AMP Mictor D
TMS444 SH7750 Microprocessor Software Support
3- 21
Reference: Tables
Channel Assignment Diagram for AMP Mictor E
Figure 3- 4: Channel assignments for AMP Mictor E
3- 22
TMS444 SH7750 Microprocessor Software Support
Specifications
Specifications
Specification Tables
This section contains information regarding the specifications of the support.
Table 4--1 lists the electrical requirements the target system must produce for the
support to acquire correct data.
Table 4- 1: Electrical specifications
Characteristics Requirements
Target system clock rate
SH7750 specified clock rate Max 100 MHz
SH7750 tested clock rate Max 66 MHz
Minimum setup time required
Logic analyzer 2.5 ns
Minimum hold time required
Logic analyzer 0ns
TMS444 SH7750 Microprocessor Software Support
4- 1
Specifications
4- 2
TMS444 SH7750 Microprocessor Software Support
Replaceable Parts List
Replaceable Parts List
This section contains a list of the replaceable components and modules for the
TMS444 SH7750 support. Use this list to identify and order replacement parts.
Parts Ordering Information
Replacement parts are available through your local Tektronix field office or
representative.
Changes to Tektronix products are sometimes made to accommodate improved
components as they become available and to give you the benefit of the latest
improvements. Therefore, when ordering parts, it is important to include the
following information in your order:
H Part number
H Instrument type or model number
H Instrument serial number
H Instrument modification number, if applicable
If you order a part that has been replaced with a different or improved part, your
local Tektronix field office or representative will contact you concerning any
change in part number.
Using the Replaceable Parts List
The tabular information in the Replaceable Parts List is arranged for quick
retrieval. Understanding the structure and features of the list will help you find
all of the information you need for ordering replacement parts. The following
table describes the content of each column in the parts list.
TMS444 SH7750 Microprocessor Software Support
5- 1
Replaceable Parts List
Parts list column descriptions
Column Column name Description
1 Figure & index number Items in this section are referenced by figure and index numbers to the exploded view
illustrations that follow.
2 Tektronix part number Use this part number when ordering replacement parts from Tektronix.
3 and 4 Serial number Column three indicates the serial number at which the part was first effective. Column four
indicates the serial number at which the part was discontinued. No entry indicates the part is
good for all serial numbers.
5 Qty This indicates the quantity of parts used.
6 Name & description An item name is separated from the description by a colon (:). Because of space limitations, an
item name may sometimes appear as incomplete. Use the U.S. Federal Catalog handbook
H6-1 for further item name identification.
7 Mfr. code This indicates the code of the actual manufacturer of the part.
8 Mfr. part number This indicates the actual manufacturer’s or vendor’s part number.
Abbreviations
Chassis Parts
Mfr. Code to Manufacturer
Cross Index
Abbreviations conform to American National Standard ANSI Y1.1--1972.
Chassis-mounted parts and cable assemblies are located at the end of the
Replaceable Parts List.
The table titled Manufacturers Cross Index shows codes, names, and addresses
of manufacturers or vendors of components listed in the parts list.
5- 2
TMS444 SH7750 Microprocessor Software Support
Replaceable Parts List
Manufacturers cr oss index
Mfr.
code
80009 TEKTRONIX, INC. P.O. BOX 500 BEAVERTON, OR, 97077-0001
Manufacturer Address City, state, zip code
Replaceable parts list
Fig. &
index
number
Tektronix part
number
071-1048-00 1 MANUAL,TECH INSTRUCTIONS,SH7750;TMS444 80009 071-1048-00
Serial no.
effective
Serial no.
discont’d
Qty Name & description
STANDARD ACCESSORIES
Mfr.
code
Mfr. part number
TMS444 SH7750 Microprocessor Software Support
5- 3
Replaceable Parts List
5- 4
TMS444 SH7750 Microprocessor Software Support
Index
Index
A
About this manual set, vii
Acquiring data, 2--5
Acquisition setup, 2--2
Address, Tektronix, viii
Address group, channel assignments, 3--3
All display format, 2--6
cycle type definitions, 2--6
Alternate bus master, 1--3
AMP, pin assignment recommended, 3--12
AMP Mictor connector diagrams, 3--19
AMX setting, 2--20
AMXEXT setting, 2--20
Application, logic analyzer configuration, 1--1
AREA 0 WAIT BY RDY~, 2-- 18
AREA 0 WAIT STATES, 2 --16
AREA 1 WAIT BY RDY~, 2-- 19
AREA 1 WAIT STATES, 2 --17
AREA 2 WAIT BY RDY~, 2-- 19
AREA 2 WAIT STATES, 2 --17
AREA 3 WAIT BY RDY~, 2-- 19
AREA 3 WAIT STATES, 2 --17
AREA 4 WAIT BY RDY~, 2-- 19
AREA 4 WAIT STATES, 2 --18
AREA 5 WAIT STATES, 2 --18
AREA 5 WAIT BY RDY~, 2-- 19
AREA 6 WAIT BY RDY~, 2-- 19
AREA 6 WAIT STATES, 2 --18
AREA0 SRAM bus width , 2--14
AREA1 SRAM bus width , 2--14
AREA2 SRAM bus width , 2--14
AREA3 SRAM bus width , 2--15
AREA4 SRAM bus width , 2--15
AREA5 SRAM bus width , 2--15
AREA6 SRAM bus width , 2--15
C
Channel assignments
Address group, 3--3
BROM group, 3--9
ChipSelect group, 3--7
clocks, 3--10
Control group, 3--6
Data_Hi group, 3--4
Data_Lo group, 3--5
Misc group, 3--8
Mode group, 3--8
PCMCIA group, 3--10
SDRAM group, 3--9
SRAM group, 3--9
WE_CAS group, 3--7
Channel groups, 2--2
visibility, 2--5
ChipSelect group, channel assignments, 3--7
ChipSelect group--, symbol table, 3--2
Clock channel assignments, 3--10
Channel Groups, 1--2
Clock rate, 1--2
target system, 4--1
Clocking, custom, 2--2
how data is acquired, 2--2
Connecting to a target system, 1--4
Connections, CPU to Mictor, 3--12
Connector diagrams , 3--19
Contacting Tektronix, viii
Control group
channel assignments, 3--6
symbol table, 3--1
CPU to Mictor connections, 3--12
Custom clocking, 2--2
how data is acquired, 2--2
Cycle types, 2--6
B
Basic operations, where to find information, vii
BROM bus width , 2--15
BROM group, channel assignments, 3--9
BROM hold, 2--20
BROM setup, 2--20
Bus cycles, displayed cycle types, 2--6
TMS444 SH7750 Microprocessor Software Support
D
Data
acquiring, 2--5
disassembly formats, 2--10
All, 2--6
Data cache, 1--3
Index- 1
Index
Data display, changing, 2--11
Data_Hi group, channel assignments, 3--4
Data_Lo group, channel assignments, 3--5
Definitions
disassembler, vii
information on basic operations, vii
logic analyzer, vii
Demonstration file, 2-- 21
Disassembled data
cycle type definitions, 2--6
viewing, 2--5
viewing an example, 2--21
Disassembler
definition, vii
logic analyzer configuration, 1--1
setup, 2--1
Disassembly di splay options, 2--12
Disassembly Format Definition overlay, 2 --11
Disassembly property pa ge, 2--11
Display formats
All, 2--6
No Idles/Waits , 2 --10
E
Electrical specifications, 4--1
clock rate, 4--1
Exception labels, 2-- 12
F
Functionality not supported, 1--3, 1--4
H
Hold time, minimum, 4 --1
I
Installing support software, 2--1
Instruction Cache, 1-- 2
L
Logic analyzer
configuration for disassembler, 1--1
definition, vii
software compatibility, 1 --1
logic analyzer, configuration for the application, with a
TLA 700 series, 1--1
M
Manual
conventions, vii
how to use the set, vii
Memory types, 1--3
Memory types , 2-- 13
Micro Specific Fields
AMX setting, 2--20
AMXEXT setting, 2--20
AREA 0 WAIT BY RDY~, 2-- 18
AREA 0 WAIT STATES, 2 --16
AREA 1 WAIT BY RDY~, 2-- 19
AREA 1 WAIT STATES, 2 --17
AREA 2 WAIT BY RDY~, 2-- 19
AREA 2 WAIT STATES, 2 --17
AREA 3 WAIT BY RDY~, 2-- 19
AREA 3 WAIT STATES, 2 --17
AREA 4 WAIT BY RDY~, 2-- 19
AREA 4 WAIT STATES, 2 --18
AREA 5 WAIT BY RDY~, 2-- 19
AREA 5 WAIT STATES, 2 --18
AREA 6 WAIT BY RDY~, 2-- 19
AREA 6 WAIT STATES, 2 --18
AREA0 SRAM bus width , 2--14
AREA1 SRAM bus width , 2--14
AREA2 SRAM bus width , 2--14
AREA3 SRAM bus width , 2--15
AREA4 SRAM bus width , 2--15
AREA5 SRAM bus width , 2--15
AREA6 SRAM bus width , 2--15
BROM bus width , 2--15
BROM hold, 2--20
BROM setup , 2--20
Memory types, 2--13
PCMCIA--AREA 5 bus, 2--15
PCMCIA--AREA 6 bus , 2--16
SDRAM bus width , 2--15
Vector Base Register, 2--20
Microprocessor, specific clocking and how data is
acquired, 2--2
Mictor to CPU connections, 3--12
Misc group, channel assignments, 3--8
Mode group, channel assignments, 3--8
Index- 2
TMS444 SH7750 Microprocessor Software Support
Index
N
No Idles/Waits display format, 2-- 10
Nonintrusive acquisition, 1--2
P
PCMCIA group, channel assignments, 3--10
PCMCIA--AREA 5 bus, 2--15
PCMCIA--AREA 6 bus , 2--16
Phone number, Tektronix, viii
Pin assignment, AMP recommended, 3--12
Product support, contact information, vi ii
R
Reference memory, 2--21
Reset, target system hardware, 1--2
Restrictions, 1--1
S
SDRAM bus width, 2--15
SDRAM group, channel assignments, 3--9
Service support, contact information, viii
Set up time, minimum, 4--1
Setups
disassembler, 2--1
support, 2--1
Specifications, electrical, 4--1
SRAM group, channel assignments, 3--9
Support, setup, 2--1
Support setup, 2--1
Symbol table
ChipSelect channel group, 3--2
Control channel group, 3--1
System file, demonstration, 2-- 21
T
Table conventions, channel assignments, 3--2
Target system hardware reset, 1--2
Technical support, contact information, viii
Tektronix, contacting, viii
Terminology, vii
Timing Display Format, 1--3
Timing display format, 2 --5
U
URL, Tektronix, viii
V
Vector Base Register, 2--20
Viewing disassembled data, 2--5
W
WE_CAS group, channel a ssignments, 3--7
Web site address, Tektronix, viii
TMS444 SH7750 Microprocessor Software Support
Index- 3
Index
Index- 4
TMS444 SH7750 Microprocessor Software Support
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