Instruction Manual
TMS 231
MC3X0 Microprocessor Support
071-0891-00
www.tektronix.com
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TEKTRONIX and TEK are registered trademarks of T ektronix, Inc.
SOFTWARE WARRANTY
T ektronix warrants that the media on which this software product is furnished and the encoding of the programs on
the media will be free from defects in materials and workmanship for a period of three (3) months from the date of
shipment. If a medium or encoding proves defective during the warranty period, T ektronix will provide a
replacement in exchange for the defective medium. Except as to the media on which this software product is
furnished, this software product is provided “as is” without warranty of any kind, either express or implied.
T ektronix does not warrant that the functions contained in this software product will meet Customer’s
requirements or that the operation of the programs will be uninterrupted or error-free.
In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration
of the warranty period. If T ektronix is unable to provide a replacement that is free from defects in materials and
workmanship within a reasonable time thereafter, Customer may terminate the license for this software product
and return this software product and any associated materials for credit or refund.
THIS WARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER WARRANTIES, EXPRESS
OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’
RESPONSIBILITY TO REPLACE DEFECTIVE MEDIA OR REFUND CUSTOMER’S PAYMENT IS
THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS
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TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH
DAMAGES.
Table of Contents
Getting Started
Operating Basics
General Safety Summary v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preface vii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Manual Conventions vii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contacting T ektronix viii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Support Package Description 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Analyzer Software Compatibility 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Analyzer Configuration 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Requirements and Restrictions 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Limitation of the Support 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functionality Not T ested 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connecting the Logic Analyzer to a System Under T est 1–2. . . . . . . . . . . . . . . . . . .
Setting Up the Support 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Installing the Support Software 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Group Definitions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Support Package Setups 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocking 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Custom Clocking 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acquiring and Viewing Disassembled Data 2–9. . . . . . . . . . . . . . . . . . . . .
Acquiring Data 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing Disassembled Data 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Display Format 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Display Format 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Display Format 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Flow Display Format 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subroutine Display Format 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Changing How Data is Displayed 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optional Display Selections 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Micro-Specific Fields 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Marking Cycles 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing an Example of Disassembled Data 2–16. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifications
Specification T ables 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Replaceable Parts
Parts Ordering Information 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the Replaceable Parts List 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS231 MC3X0 Microprocessor Support
i
Table of Contents
Reference
Index
Symbol Table 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Assignments 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU To Mictor Connections 5–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ii
TMS231 MC3X0 Microprocessor Support
List of Figures
Table of Contents
Figure 2–1: MC3X0 _RIM sample point and master sample point 2–3. .
Figure 2–2: MC3X0 _EIM sample point and master sample point 2–5. .
Figure 2–3: MC3X0 _CORE(MLB) sample point and master
sample point 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2–4: Hardware display format 2–11. . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5–1: Pin assignments for a Mictor connector
(component side) 5–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS231 MC3X0 Microprocessor Support
iii
Table of Contents
List of Tables
Table 2–1: Description of special characters in the display 2–9. . . . . . . .
Table 2–2: Cycle type labels and definitions 2–10. . . . . . . . . . . . . . . . . . . .
Table 2–3: Interrupt and exception labels 2–15. . . . . . . . . . . . . . . . . . . . . .
Table 3–1: Electrical specifications 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5–1: MC3X0 _Ctrl group symbol table definitions 5–1. . . . . . . . . .
Table 5–2: Address channel group assignments 5–3. . . . . . . . . . . . . . . . .
Table 5–3: Data channel group assignments 5–4. . . . . . . . . . . . . . . . . . . .
Table 5–4: Proc_Mode channel group assignments 5–5. . . . . . . . . . . . . .
Table 5–5: Control channel group assignments 5–5. . . . . . . . . . . . . . . . . .
Table 5–6: Chip_Select channel group assignments 5–6. . . . . . . . . . . . . .
Table 5–7: Interrupt channel group assignments 5–6. . . . . . . . . . . . . . . .
Table 5–8: Misc channel group assignments 5–6. . . . . . . . . . . . . . . . . . . .
Table 5–9: Clock and Qualifier channel assignments 5–7. . . . . . . . . . . . .
Table 5–10: Signals required for clocking and disassembly 5–8. . . . . . . .
Table 5–11: Signals not required for clocking and disassembly 5–9. . . . .
Table 5–12: CPU to Mictor connections for clock and qualifiers 5–11. . .
Table 5–13: CPU to Mictor connections for Mictor A pins 5–11. . . . . . . .
Table 5–14: CPU to Mictor connections for Mictor D pins 5–12. . . . . . . .
Table 5–15: CPU to Mictor connections for Mictor C pins 5–13. . . . . . . .
iv
TMS231 MC3X0 Microprocessor Support
General Safety Summary
Review the following safety precautions to avoid injury and prevent damage to
this product or any products connected to it. To avoid potential hazards, use this
product only as specified.
While using this product, you may need to access other parts of the system. Read
the General Safety Summary in other system manuals for warnings and cautions
related to operating the system.
Symbols and Terms
T erms in this Manual. These terms may appear in this manual:
WARNING. Warning statements identify conditions or practices that could result
in injury or loss of life.
CAUTION. Caution statements identify conditions or practices that could result in
damage to this product or other property.
T erms on the Product. These terms may appear on the product:
DANGER indicates an injury hazard immediately accessible as you read the
marking.
WARNING indicates an injury hazard not immediately accessible as you read the
marking.
CAUTION indicates a hazard to property including the product.
Symbols on the Product. The following symbols may appear on the product:
CAUTION
Refer to Manual
TMS231 MC3X0 Microprocessor Support
v
General Safety Summary
vi
TMS231 MC3X0 Microprocessor Support
Preface
Manual Conventions
This instruction manual contains specific information about the TMS231 MC3X0
microprocessor support package and is part of a set of information on how to
operate this product on compatible Tektronix logic analyzers.
If you are familiar with operating microprocessor support packages on the logic
analyzer for which the TMS231 MC3X0 support was purchased, you will only
need this instruction manual to set up and run the support.
If you are not familiar with operating microprocessor support packages, you will
need to supplement this instruction manual with information on basic operations
to set up and run the support. See Manual Conventions below for more information.
This manual uses the following conventions:
H The term “disassembler” refers to the software that disassembles bus cycles
into instruction mnemonics and cycle types.
H The phrase “information on basic operations” refers to your online help or a
user manual covering the basic operations of microprocessor support.
TMS231 MC3X0 Microprocessor Support
vii
Preface
Contacting Tektronix
Phone 1-800-833-9200*
Address Tektronix, Inc.
Department or name (if known)
14200 SW Karl Braun Drive
P.O. Box 500
Beaverton, OR 97077
USA
Web site www.tektronix.com
Sales support 1-800-833-9200, select option 1*
Service support 1-800-833-9200, select option 2*
Technical support Email: techsupport@tektronix.com
1-800-833-9200, select option 3*
1-503-627-2400
6:00 a.m. – 5:00 p.m. Pacific time
* This phone number is toll free in North America. After office hours, please leave a
voice mail message.
Outside North America, contact a Tektronix sales office or distributor; see the
Tektronix web site for a list of offices.
viii
TMS231 MC3X0 Microprocessor Support
Getting Started
Getting Started
This section contains information on the TMS231 MC3X0 microprocessor
support package and on connecting your logic analyzer to your system under test.
Support Package Description
The TMS231 MC3X0 microprocessor support package displays disassembled
data from systems based on the MCORE MC3X0 microprocessor.
To use this support efficiently, you need to have the items listed in the information on basic operations and M3X0 User Manual, M340 Specification v1.1,
11/20/98.
Information on basic operations also contains a general description of support.
Logic Analyzer Software Compatibility
The floppy disk label on the microprocessor support states which version of logic
analyzer software this support is compatible with.
Logic Analyzer Configuration
The TMS231 MC3X0 support requires a minimum of one 102-channel module.
Requirements and Restrictions
You should review the general requirements and restrictions of microprocessor
support packages as they pertain to your system under test.
You should also review electrical specifications in Specifications on page 3–1 as
they pertain to your system under test, as well as the following descriptions of
other MC3X0 support requirements and restrictions.
System Clock Rate
The operating speeds that the MC3X0
microprocessor are listed on Table 3–1. These specifications were valid at the
time this manual was printed. Please contact your Tektronix Sales Representative
for current information on the fastest devices supported.
support can acquire data from the MC3X0
TMS231 MC3X0 Microprocessor Support
1–1
Getting Started
NonIntrusive Acquisition
Disabling the Instruction
Cache
Acquiring microprocessor bus cycles is nonintrusive to the system under test.
That is, the MC3X0 support does not intercept, modify, or present signals back to
the system under test.
To display disassembled acquired data, you must disable the internal instruction
cache. Disabling the cache makes all instruction prefetches visible on the bus so
they can be acquired and displayed disassembled.
Limitation of the Support
8 Bit Mode
Multiple Instructions
In 8 bit mode if the Data comes in higher than 3 bytes D[31:24], D[23:16] and
D[15:8] it is not supported.
If multiple Branch instructions and MultiRead/Write instructions are entering the
fetch queue then the TMS231 MC3X0 support may not disassemble correctly. In
these cases the Mark Opcode Option can be used for correct disassembly.
Functionality Not Tested
H RIM mode
H 16 bit Upper and Lower modes
H 8 bit mode
Since the modes for RIM, 16 bit Upper and Lower, and 8 bit are not tested, even
though they are supported, the disassembly may be incorrect.
Connecting the Logic Analyzer to a System Under Test
You can use channel probes, clock probes, and leadsets with a commercial test
clip (or adapter) to make connections between the logic analyzer and your system
under test.
1–2
TMS231 MC3X0 Microprocessor Support
Getting Started
To connect the probes to MC3X0 signals in the system under test using a test
clip, follow these steps:
1. Power off your system under test. It is not necessary to power off the logic
analyzer.
CAUTION. To prevent static damage, handle the microprocessor, the probes, and
the logic analyzer module components only in a static-free environment. Static
discharge can damage these components.
Always wear a grounding wrist strap, heel strap, or similar device while
handling the microprocessor.
2. To discharge your stored static electricity, touch the ground connector located
on the back of the logic analyzer. If you are using a test clip, touch any of the
ground pins on the clip to discharge stored static electricity from the test clip.
CAUTION. To prevent damage to the pins on the microprocessor, place the system
under test on a horizontal surface before connecting the test clip.
3. Place the system under test on a horizontal static-free surface.
4. Use Tables 5–2 through 5–12 beginning on page 5–3 to connect the channel
probes to MC3X0 signal pins on the test clip or in the system under test.
Use leadsets to connect at least one ground lead from each channel probe and
the ground lead from each clock probe to ground pins on your test clip.
TMS231 MC3X0 Microprocessor Support
1–3
Getting Started
1–4
TMS231 MC3X0 Microprocessor Support
Operating Basics
Setting Up the Support
The information in this section is specific to the operations and functions of the
TMS231 MC3X0 microprocessor support on any Tektronix logic analyzer for
which it can be purchased.
Before you acquire and display disassembled data, you need to load the support
and specify setups for clocking and triggering as described in the information on
basic operations in your logic analyzer online help. The microprocessor support
provides default values for each of these setups as well as user-definable settings.
Installing the Support Software
NOTE. Before you install any software, it is recommended that you verify that the
microprocessor support software is compatible with the logic analyzer software.
To install the TMS231 MC3X0 software on your Tektronix logic analyzer, follow
these steps:
1. Insert the floppy disk in the disk drive.
2. Click the Windows Start button, point to Settings, and click Control Panel.
3. In the Control Panel window, double-click Add/Remove Programs.
4. Follow the instructions on the screen for installing the software from the
To remove or uninstall software, close all windows, and then follow the above
instructions and select Uninstall.
Channel Group Definitions
The software automatically defines channel groups for the support. The channel
groups for the TMS231 MC3X0 support are Address, Data, Control, Chip Select,
Proc_Mode, Interrupt, and Misc. The channel group tables begin on page 5–1.
floppy disk.
TMS231 MC3X0 Microprocessor Support
2–1
Setting Up the Support
Support Package Setups
The TMS231 MC3X0 software installs MC3X0 support package setup file.
Clocking
MC3X0 Setup
Options
This setup provides disassembly support. Signals are displayed as they appear
electrically on the front side bus.
The TMS231 MC3X0 support offers a microprocessor-specific clocking mode
for the MC3X0 microprocessor. This clocking mode is the default selection
whenever you load the TMS231 MC3X0 support.
Disassembly is not correct when using the Internal or External clocking modes.
Information on basic operations in your online help describes in more detail how
to use these clock selections for general purpose analysis.
H Internal clocking is used for timing and is based on the clock generated by a
Tektronix logic analyzer. You can configure the clock rate from 50 ms down
to 4 ns resolution.
H External clocking is used when you configure the clocking of data based on
logical combinations of clocks and qualifiers.
Custom Clocking
When Custom is selected, the Custom Clocking Options menu has the subtitle
MC3X0
also displayed.
The TMS231 MC3X0 support has three clocking options.
H MC3X0
H MC3X0
H MC3X0 _CORE(MLB)
Microprocessor Clocking Support added, and the clocking options are
_RIM
_EIM
2–2
TMS231 MC3X0 Microprocessor Support
Setting Up the Support
MC3X0 _RIM
After loading the MC3X0
support and choosing one of the previous clocking
options, the following disassembly support selections are available. These
Disassembly support selections are defined based on the actual control signals
available to the system under test
.
Disassembly support selections:
H Use Control Signals Default (most accurate disassembly)
H Clock Edge With R/W~
H Clock Edge Without R/W~
Use Control Signals (Default). The Use Control Signals selection acquires signals
(RST~, OE~, TA~ and SHS~) with the greatest amount of accuracy. Signals are
sampled at every clock edge when the control signals are active. The master
strobe occurs when the clock signal line changes from low to high. Figure 2–1
shows the sample point and master sample point for acquiring the signals.
CLKOUT
ADDRESS
EB [3:0]~
RST~
SHS~
TA~
OE~
DATA (Read)
DATA (Write)
Sample Point
for EB
Sample Point for
Address, Data, Control
and
Master Point
Figure 2–1: MC3X0 _RIM sample point and master sample point
TMS231 MC3X0 Microprocessor Support
2–3
Setting Up the Support
Clock Edge With R/W~. The Clock Edge With R/W~ is best used when you want
to distinguish a read cycle from a write cycle, even though extra data is saved
that may cause errors in the disassembly. With this selection, signals are acquired
at every clock cycle without any qualifier. On every falling edge Byte Enable
signals are sampled and on every rising edge Address, Control, and Data signals
are sampled and saved.
Clock Edge Without R/W~. The Clock Edge Without R/W~ is best used when you
have not aquired control signals for acquisition.
Signals are acquired at every clock cycle without any qualifier. On every falling
edge Byte Enable signals are sampled and on every rising edge Address, Control
and Data signals are sampled and saved. This selection does not distinguish a
read cycle from a write cycle so extra data is saved that may cause errors in the
disassembly.
2–4
TMS231 MC3X0 Microprocessor Support
Setting Up the Support
MC3X0 _EIM
Use Control Signals (Default). The Use Control Signals selection acquires signals
with the greatest amount of accuracy. Signals are sampled at every rising clock
edge when the control signals (RST~, OE~ and R/W~) are active. The master
strobe occurs when the clock signal line changes from low to high. Figure 2–2
shows the sample point and master sample point for acquiring the signals.
CLKOUT
ADDRESS
EB [3:0]~
RST~
R/W~ (Read)
R/W~ (Write)
OE~
DATA (Read)
DATA (Write)
Sample Point
for EB
Sample Point for
Address, Data, Control
and
Master Point
Figure 2–2: MC3X0 _EIM sample point and master sample point
Clock Edge With R/W~. The Clock Edge With R/W~ is best used when you want
to distinguish a read cycle from a write cycle; unfortunately, this selection saves
extra data causing errors in the disassembly. With this selection, signals are
acquired at every clock cycle without any qualifier. On every falling edge Byte
Enable signals are sampled and on every rising edge Address, Control, and Data
signals are sampled and saved.
TMS231 MC3X0 Microprocessor Support
2–5
Setting Up the Support
Clock Edge Without R/W~. The Clock Edge Without R/W~ is best used when you
have not acquired control signals for acquisition.
Signals are acquired at every clock cycle without any qualifier. On every falling
edge Byte Enable signals are sampled and on every rising edge the Address,
Control and Data signals are sampled and saved. This selection does not
distinguish a read cycle from a write cycle, extra data is saved that may cause
errors in the disassembly.
MC3X0_CORE(MLB)
Use Control Signals (Default). The Use Control Signals selection acquires signals
with the greatest amount of accuracy. Signals are sampled at every rising clock
edge when the control signals (RST~, TREQ~ and TA~) are active. The master
strobe occurs when the clock signal line changes from low to high. Figure 2–3
shows the sample point and master sample point for acquiring the signals.
CLKOUT
ADDRESS
EB [3:0]~
RST~
TREQ~
TA~
DATA (Read)
2–6
DATA (Write)
Sample Point for
Address and
Control
Sample Point for
Data and Master Point
Figure 2–3: MC3X0 _CORE(MLB) sample point and master sample point
Clock Edge With R/W~. The Clock Edge With R/W~selection is best used when
you want to distinguish a read cycle from a write cycle; unfortunately, this
selection saves extra data causing errors in the disassembly. With this selection,
signals are acquired at every clock cycle without any qualifier. On every falling
edge, Address and Control signals are sampled and on every rising edge Data
signals are sampled and saved.
TMS231 MC3X0 Microprocessor Support
Setting Up the Support
Clock Edge Without R/W~. The Clock Edge Without R/W~ is best used when you
have not acquired control signals for acquisition.
Signals are acquired at every clock cycle without any qualifier. On every falling
edge Address and Control signals are sampled and on every rising edge Data
signals are sampled and saved. This selection does not distinguish a read cycle
from a write cycle, so extra data is saved that may cause errors in the disassembly.
Setup and Hold Time. You can change the Setup and Hold time window of all the
signal groups. The default Setup time is 2.5 ns and the Hold time is 0 ns. The
Setup and Hold that you defined has precedence over any default Setup and Hold
time.
TMS231 MC3X0 Microprocessor Support
2–7
Setting Up the Support
2–8
TMS231 MC3X0 Microprocessor Support
Acquiring and Viewing Disassembled Data
Acquiring Data
Once you load the TMS231 MC3X0 support, choose a clocking mode, and specify
the trigger, you are ready to acquire and disassemble data.
If you have any problems acquiring data, refer to information on basic operations
in your logic analyzer online help or Appendix A: Error Messages and
Disassembly Problems in your logic analyzer user manual.
Viewing Disassembled Data
You can view disassembled data in six display formats: Timing, State, Hardware,
Software, Control Flow, and Subroutine. The information on basic operations
describes how to select the disassembly display formats.
NOTE. Selections in the Disassembly property page (the Disassembly Format
Definition overlay) must be set correctly for your acquired data to be disassembled correctly. Refer to Changing How Data is Displayed on page 2–12.
The default display format displays the Address, Data, Control, Proc_Mode,
ChipSelect, and Interrupt channel group values for each sample of acquired data
along with Sample, Mnemonic, and Timestamp.
Any channel group or display column can be made visible by selecting the Add
column option in the Disassembly property page.
The disassembler displays special characters and strings in the instruction
mnemonics to indicate significant events. Table 2–1 lists these special characters
and strings and gives a definition of what they represent.
T able 2–1: Description of special characters in the display
Character or string displayed Definition
#
> Indicates that there is sufficient room on the screen to show
>> On the TLA 700 Indicates that the instruction was manually marked as a
Indicates an immediate value.
all available data.
program fetch.
TMS231 MC3X0 Microprocessor Support
2–9
Acquiring and Viewing Disassembled Data
T able 2–1: Description of special characters in the display (cont.)
Character or string displayed Definition
t
Indicates the number shown is in decimal, such as #12t.
Timing Display Format
Hardware Display Format
****
Indicates that there is insufficient data available for complete
disassembly of the instruction; the number of asterisks
indicates the width of the data that is unavailable. Each two
asterisks represent one byte.
The Timing-Waveform display format file is provided for the TLA 700 Series
support. The timing-waveform display format file sets up and displays the
following waveforms:
CLKOUT
Address (busform)
Data (busform)
RST~
R/W~
OE~
EB~[0:3]
CS~[1:4]
In Hardware display format, the disassembler displays certain cycle type labels in
parentheses. Table 2–2 lists cycle type labels and gives a definition of the cycle
they represent. Reads to interrupt and exception vectors are labeled with the
vector name.
2–10
T able 2–2: Cycle type labels and definitions
Cycle Type
( RESET )
( DATA RETRIEVAL ERROR ) Indicates invalid DATA READ cycle
( READ ) Indicates DATE READ cycle
( WRITE ) Indicates DATE WRITE cycle
( EXTENSION)
( FLUSH )
( READ or WRITE )
( UNKNOWN )
Definition
Indicates system RESET
Indicates an extension to a preceding instruction opcode
Indicates a cycle was fetched but not executed
Indicates a noninstruction sequence when R/W~ is not
used
Indicates a combination of control bits are unexpected or
unrecognized
TMS231 MC3X0 Microprocessor Support
Acquiring and Viewing Disassembled Data
Figure 2–4 shows an example of a Hardware display.
Software Display Format
Control Flow Display
Format
Figure 2–4: Hardware display format
The Software display format displays only the first fetch of executed instructions.
Flushed cycles and extensions are not shown, even though they are part of the
executed instruction. Read extensions are used to disassemble the instruction, but
they are not displayed as a separate cycle in the Software display format. Data
reads and writes are not displayed.
The Control Flow display format displays only the first fetch of instructions that
cause a branch in the addressing and special cycles to change the flow of control.
Instructions that generate a change in the flow of control in the MC3X0
microprocessor are as follows:
BF Branch on condition false
BR Branch
BT Branch on condition true
JMP Jump
JMPI Jump indirect
TMS231 MC3X0 Microprocessor Support
2–11
Acquiring and Viewing Disassembled Data
Subroutine Display
Format
The Subroutine display format displays only the first fetch of subroutine call or
return instructions. It can display conditional subroutine calls if they are
considered to be taken.
Instructions that generate a subroutine call or a return in the MC3X0 microprocessor are as follows:
BSR Branch on subroutine
JSR Jump to subroutine
JMP Jump
JSRI Jump to subroutine indirect
RTE Return from exception
RFI Return from interrupt
BKPT Break Point
TRAP Trap
Changing How Data is Displayed
Common fields and features allow you to further modify displayed data to suit
your needs. You can make common and optional display selections in the
Disassembly property page (the Disassembly Format Definition overlay).
Optional Display
Selections
You can make optional selections for acquired disassembled data. In addition to
the common selections (described in the information on basic operations), you
can change the displayed data in the following ways:
Show: Hardware (default)
Software
Control Flow
Subroutine
Highlight: Software (default)
Control Flow
Subroutine
None
Disasm Across Gaps: No (default)
Yes
2–12
TMS231 MC3X0 Microprocessor Support
Acquiring and Viewing Disassembled Data
Micro-Specific Fields
Endian Mode. Indicate the MC3X0 processor configuration for viewing data from
memory in the following order:
Little Endian (default)
Big Endian
Interface. Select the interface type:
RIM (default)
EIM
CORE(MLB)
Data Port Width. Indicate the data port width:
32-bit port (default)
16-bit port (D15:D0)
16-bit port (D31:D16)
8-bit port (D7:D0)
R/W~ Signal. Indicate whether the R/W~ signal is available:
Available (default)
Not Available
CS Mode. Indicate whether the Chip select CS[0:5] signals are available in the
system:
CS Available (default)
Not Available
Vector Base Register. Enter the base address of the Interrupt Vector table:
0x00000000 (default)
RIM CS1 Base Address. Enter the base address for the Chip select (CS1) for RIM
Interface:
0x00000000 (default)
RIM CS2 Base Address. Enter the base address for the Chip select (CS1) for RIM
Interface:
0x00000000 (default)
TMS231 MC3X0 Microprocessor Support
2–13
Acquiring and Viewing Disassembled Data
БББББББББББББББББББББ
БББББББББББББББББББББ
БББББББББББББББББББББ
Á
БББББББББББББББББББББ
Á
БББББББББББББББББББББ
БББББББББББББББББББББ
БББББББББББББББББББББ
БББББББББББББББББББББ
БББББББББББББББББББББ
RIM CS3 Base Address. Enter the base address for the Chip select (CS1) for RIM
Interface:
0x00000000 (default)
RIM CS4 Base Address. Enter the base address for the Chip select (CS1) for RIM
Interface:
0x00000000 (default)
Marking Cycles
TMS231 MC3X0 support allows marks on potential instruction fetch cycles
The
(which includes read extensions and flush cycles.) Cycle marks are not available
if the cursor is placed on other cycle marks. To place a cycle mark use the Mark
Opcode button. The Mark Opcode button functions when disassembly is
available.
If the cycle being marked, is not a potential instruction fetch cycle (which
includes read extensions and flush cycles), the Mark Opcode selections are
replaced by a note indicating that “An Opcode Mark cannot be placed at the
selected data sample.”
When a cycle is marked, this character, >>, is displayed immediately to the left
of the Mnemonics column. Cycles can be unmarked by using the Undo Mark
selection, which removes this character, >>. If more than one set of sequences are
marked, then the you can undo the marks using the Remove all Marks option.
The following cycle marks are available for instruction fetch cycles in the 8 bit
Data Port:
Opcode
Extension
Flush
Read
ÁÁÁÁ
Write
Undo Mark
Marks the cycle as an instruction opcode
Marks the cycle as an extension to an instruction opcode
Marks the cycle as a flushed cycle
Marks the cycle as a read cycle (if the R/W~ signal is not available)
ББББББББББББББББББББ
Marks the cycle as a write cycle (if the R/W~ signal is not available)
Removes all marks from the current sample
The following cycle marks are available for instruction fetch cycles in the 16 bit
Data Port:
Opcode
Read
Write
Marks the cycle as an instruction opcode
Marks the cycle as a read cycle (if the R/W~ signal is not available)
Marks the cycle as a write cycle (if the R/W~ signal is not available)
2–14
TMS231 MC3X0 Microprocessor Support
Acquiring and Viewing Disassembled Data
Á
Á
Displaying Exception
Labels
Flush
Undo Mark
Marks the cycle as a flushed cycle
Removes all marks from the current sample
The following cycle marks are available for instruction fetch cycles in the 32 bit
Data Port:
Opcode_Opcode
Opcode_Flush
Flush_Opcode
Extension
Flush
Read
ÁÁÁÁ
Write
Undo Mark
Marks the cycle as an instruction opcode and opcode
Marks the cycle as an instruction opcode and flush
Marks the cycle as a flush and instruction opcode
Marks the cycle as an extension to an instruction opcode
Marks the cycle as a flushed cycle
Marks the cycle as a read cycle (if the R/W~ signal is not available)
ББББББББББББББББББББ
Marks the cycle as a write cycle (if the R/W~ signal is not available)
Removes all marks from the current sample
The disassembler can display TMS231 MC3X0 exception labels. The exception
table must reside in external memory for interrupt and exception cycles to be
visible to the disassembler.
You can enter the table prefix in the Exception Prefix field. The Exception Prefix
field provides the disassembler with the offset address; enter a three-digit
hexadecimal value corresponding to the prefix of the exception table.
These fields are located in the Disassembly property page (Dissembled Format
Definition overlay).
Table 2–3 lists the
TMS231 MC3X0 interrupt and exception labels.
T able 2–3: Interrupt and exception labels
Vector
Number
0 0x000 (RESET)
1 0x004 (MISALIGNED ACCESS)
2 0x008 (ACCESS ERROR)
3 0x00C (DIVIDE BY ZERO)
4 0x010 (ILLEGAL INSTRUCTION)
5 0x014 (PRIVILEGE VIOLATION)
6 0x018 (TRACE EXCEPTION)
7 0x01C (BREAKPOINT EXCEPTION)
Offset Displayed interrupt or exception name
TMS231 MC3X0 Microprocessor Support
2–15
Acquiring and Viewing Disassembled Data
T able 2–3: Interrupt and exception labels (Cont.)
Vector
Number
8 0x020 (UNRECOVERABLE ERROR)
9 0x024 (Idly4 ERROR)
10 0x028 (INT AUTOVECTOR)
11 0x02C (FINT AUTOVECTOR)
12 0x030 (RESERVED (HAI))
13 0x034 (RESERVED (FP))
14 0x038 (TLB INST MISS EXCEPTION)
15 0x03C (TLB DATA MISS EXCEPTION)
16 to190x040 to
0x04C
20 to300x050 to
0x078
31 0x07C (SYSTEM DESCRIPTOR POINTER)
32 to
127
0x080 to
0x1FC
Displayed interrupt or exception nameOffset
(TRAP #0 TO 3 INSTRUCTION VECTOR)
(RESERVED)
(RESERVED)
Viewing an Example of Disassembled Data
A demonstration system file (or demonstration reference memory) is provided on
your MC3X0 software support disk so you can see an example of how your
MC3X0 microprocessor bus cycles and instruction mnemonics look when they
are disassembled. Viewing the system file is not a requirement for preparing the
module for use. You can view the system file without connecting the logic
analyzer to your system under test.
2–16
TMS231 MC3X0 Microprocessor Support
Specifications
Specifications
Specification Tables
This section contains information regarding the specifications of the
TMS231 MC3X0
Tables 3–1 list the electrical requirements that the system under test must
produce for the TMS231 MC3X0 support to acquire correct data.
T able 3–1: Electrical specifications
Characteristics Requirements
System under test clock rate
Maximum specified clock rate: 100 MHz
Tested clock rate
Minimum setup time required 2.5 ns
Minimum hold time required 0 ns
* Please contact your Tektronix Sales Representative for current information on the
tested clock rate.
microprocessor support.
*
100 MHz
TMS231 MC3X0 Microprocessor Support
3–1
Specifications
3–2
TMS231 MC3X0 Microprocessor Support
Replaceable Parts
Replaceable Parts
This section contains a list of the replaceable components for the
TMS231 MC3X0 hardware support product.
Parts Ordering Information
Replacement parts are available through your local Tektronix field office or
representative.
Changes to Tektronix products are sometimes made to accommodate improved
components as they become available and to give you the benefit of the latest
improvements. Therefore, when ordering parts, it is important to include the
following information in your order:
H Part number
H Instrument type or model number
H Instrument serial number
H Instrument modification number, if applicable
If you order a part that has been replaced with a different or improved part, your
local Tektronix field office or representative will contact you concerning any
change in part number.
Change information, if any, is located at the rear of this manual.
Using the Replaceable Parts List
The tabular information in the Replaceable Parts List is arranged for quick
retrieval. Understanding the structure and features of the list will help you find
all of the information you need for ordering replacement parts. The following
table describes the content of each column in the parts list.
TMS231 MC3X0 Microprocessor Support
4–1
Replaceable Parts
Parts list column descriptions
Column Column name Description
1 Figure & index number Items in this section are referenced by figure and index numbers to the exploded view
illustrations that follow.
2 Tektronix part number Use this part number when ordering replacement parts from Tektronix.
3 and 4 Serial number Column three indicates the serial number at which the part was first effective. Column four
indicates the serial number at which the part was discontinued. No entries indicates the part is
good for all serial numbers.
5 Qty This indicates the quantity of parts used.
6 Name & description An item name is separated from the description by a colon (:). Because of space limitations, an
item name may sometimes appear as incomplete. Use the U.S. Federal Catalog handbook
H6-1 for further item name identification.
7 Mfr. code This indicates the code of the actual manufacturer of the part.
8 Mfr. part number This indicates the actual manufacturer’s or vendor’s part number.
Abbreviations
Chassis Parts
Mfr. Code to Manufacturer
Cross Index
Abbreviations conform to American National Standard ANSI Y1.1–1972.
Chassis-mounted parts and cable assemblies are located at the end of the
Replaceable Electrical Parts List.
The table titled Manufacturers Cross Index shows codes, names, and addresses
of manufacturers or vendors of components listed in the parts list.
4–2
TMS231 MC3X0 Microprocessor Support
Manufacturers cross index
Mfr.
code
TK2548 XEROX CORPORATION 14181 SW MILLIKAN WA Y BEAVERT ON, OR 97005
Manufacturer Address City, state, zip code
Replaceable parts list
Fig. &
index
number
Tektronix
part number
071-0891-00
Serial no.
effective
Serial no.
discont’d
Qty Name & description Mfr. code Mfr. part number
STANDARD ACCESSORIES
1 MANUAL, TECH: INSTRUCTIONS, MC3X0, TMS231 TK2548
Replaceable Parts
071-0891-00
TMS231 MC3X0 Microprocessor Support
4–3
Replaceable Parts
4–4
TMS231 MC3X0 Microprocessor Support
Reference
Reference: Tables
This section lists the Symbol table and the Channel group tables for disassembly
and timing.
Symbol Table
Table 5–1 lists the name, bit pattern, and meaning for the symbols in the file
MC3X0_Ctrl, the Control channel group symbol table.
T able 5–1: MC3X0 _Ctrl group symbol table definitions
Control group value
R/W~ EB3~
Symbol
RESET 0 X X X XX XXXX RESET
DATA_RETR_ERR 1 0 X X XX XXXX Data Retrieval Error
WRITE 1 1 0 X XX XXXX Data Write
READ 1 1 1 X XX XXXX Data Read
UNKNOWN X X X X XX XXXX Unknown
RST~ TSIZ0 EB1~
TEA~ OE~ EB0~
TSIZ1 EB2~
Meaning
TMS231 MC3X0 Microprocessor Support
5–1
Reference:Tables
Channel Assignments
Channel assignments listed in Tables 5–2 through 5–8 use the following
conventions:
H All signals are required by the support unless indicated otherwise.
H Channels are listed starting with the most significant bit (MSB), descending
to the least significant bit (LSB).
H Channel group assignments are for all modules unless otherwise noted.
H A tilde symbol (~) following a signal name indicates an active low signal.
H An equals symbol (=) following a signal name indicates that it is double
probed.
H The module in the lower-numbered slot is referred to as the HI module and
the module in the lower-numbered slot is referred to as the LO module.
The portable logic analyzer has the lower-numbered slots on the top, and the
benchtop logic analyzer has the lower-numbered slots on the left.
The channel assignment groups are displayed in the following order:
Group name Display radix
Address Hexadecimal
Data Hexadecimal
Mnemonic None
Control Symbolic
Chip_select BIN
Proc_Mode BIN
Interrupt BIN
Misc Off
5–2
TMS231 MC3X0 Microprocessor Support
Reference:Tables
Table 5–2 lists the probe section and channel assignments for the Address group
and the microprocessor signal to which each channel connects. By default the
Address channel group assignments are displayed in hexadecimal.
T able 5–2: Address channel group assignments
Bit order Section:channel MC3X0 signal name
31 A3:7 A31
30 A3:6 A30
29 A3:5 A29
28 A3:4 A28
27 A3:3 A27
26 A3:2 A26
25 A3:1 A25
24 A3:0 A24
23 A2:7 A23
22 A2:6 A22
21 A2:5 A21
20 A2:4 A20
19 A2:3 A19
18 A2:2 A18
17 A2:1 A17
16 A2:0 A16
15 A1:7 A15
14 A1:6 A14
13 A1:5 A13
12 A1:4 A12
11 A1:3 A11
10 A1:2 A10
9 A1:1 A9
8 A1:0 A8
7 A0:7 A7
6 A0:6 A6
5 A0:5 A5
4 A0:4 A4
3 A0:3 A3
2 A0:2 A2
1 A0:1 A1
0 A0:0 A0
TMS231 MC3X0 Microprocessor Support
5–3
Reference:Tables
Table 5–3 lists the probe section and channel assignments for the Data group and
the microprocessor signal to which each channel connects. By default the Data
channel group assignments are displayed in hexadecimal.
T able 5–3: Data channel group assignments
Bit order Section:channel MC3X0 signal name
31 D3:7 D31
30 D3:6 D30
29 D3:5 D29
28 D3:4 D28
27 D3:3 D27
26 D3:2 D26
25 D3:1 D25
24 D3:0 D24
23 D2:7 D23
22 D2:6 D22
21 D2:5 D21
20 D2:4 D20
19 D2:3 D19
18 D2:2 D18
17 D2:1 D17
16 D2:0 D16
15 D1:7 D15
14 D1:6 D14
13 D1:5 D13
12 D1:4 D12
11 D1:3 D11
10 D1:2 D10
9 D1:1 D9
8 D1:0 D8
7 D0:7 D7
6 D0:6 D6
5 D0:5 D5
4 D0:4 D4
3 D0:3 D3
2 D0:2 D2
1 D0:1 D1
0 D0:0 D0
5–4
TMS231 MC3X0 Microprocessor Support
Reference:Tables
Table 5–4 lists the probe section and channel assignments for the Proc_Mode
group and the microprocessor signal to which each channel connects. The default
radix of the Proc_Mode group is Binary on the logic analyzer.
T able 5 –4: Proc_Mode channel group assignments
Bit order Section:channel MC3X0 signal name
10 C2:7 PSTAT3
9 C2:6 PSTAT2
8 C2:5 PSTAT1
7 C2:4 PSTAT0
6 C3:6 TC2
5 C3:5 TC1
4 C3:4 TC0
3 C1:7 SEQ~
2 C1:2 BIGEND~
1 C1:0 IFETCH
0 C1:6 BURST~\BAA~
Table 5–5 lists the probe section and channel assignments for the Control group
and the microprocessor signal to which each channel connects. The default radix
of the Control group is Symbolic on the logic analyzer. The symbol table file
name is MC3X0_Ctrl.
T able 5–5: Control channel group assignments
Bit order Section:channel MC3X0 signal name
9 C2:3 RST~
8 C3:7 TEA~
7 C2:2 R/W~
6 C3:3 TSIZ1
5 C3:2 TSIZ0
4 C2:1 OE~*
3 C0:7 EB3~*
2 C0:6 EB2~*
1 C0:5 EB1~*
0 C0:4 EB0~*
* Indicates the signal is supported by RIM and EIM interface
TMS231 MC3X0 Microprocessor Support
5–5
Reference:Tables
By default, Chip_Select channel group assignments in Table 5–6 are shown
displayed as binary.
T able 5–6: Chip_Select channel group assignments
Bit order Section:channel MC3X0 signal name
5 C1:5 CS5~
4 C1:4 CS4~*
3 C0:3 CS3~*
2 C0:2 CS2~*
1 C0:1 CS1~*
0 C0:0 CS0~
* Indicates the signal is supported by RIM and EIM interface
[
Indicates the signal is supported by EIM interface
[
[
By default, Interrupt channel group assignments in Table 5–7 are displayed as
binary.
T able 5–7: Interrupt channel group assignments
Bit order Section:channel MC3X0 signal name
1 C3:1 FINT~
0 C3:0 INT~
By default, Misc channel group assignments listed in Table 5–8 are not
displayed.
T able 5–8: Misc channel group assignments
Bit order Section:channel MC3X0 signal name
5 Clock:3 TREQ~
4 C2:0 TBUSY~
3 C1:3 ABORT~
2 Clock:2 SHS~
5–6
1 Clock:1 TA~
0 C1:1 RSTOUT~
TMS231 MC3X0 Microprocessor Support
Reference:Tables
Table 5–9 lists the probe section and clock and qualifier channel assignments.
The clock probes are not part of any group.
T able 5–9: Clock and Qualifier channel assignments
MC3X0 signal
Section:channel
CLK:0 CLKOUT –
CLK:1 TA~ –
CLK:2 SHS~ –
CLK:3 TREQ~ –
C2:0 TBUSY~ –
C2:1 OE~ –
C2:2 R/W~ –
C2:3 RST~ –
QUAL:0 Not used 102 & 136 channel
QUAL:1 Not used 102 & 136 channel
QUAL:2 Not used 136 channel only
QUAL:3 Not used 136 channel only
name
Comments
Acquisition Setup. The TMS231 MC3X0 support affects the logic analyzer setup
menus (and submenus) by modifying existing fields and adding micro-specific
fields.
The TMS231 MC3X0 support adds the selection MC3X0 to the Load Support
Package dialog box, under the File pulldown menu. After the MC3X0 support is
loaded, the Custom clocking mode selection in the module Setup menu is
enabled.
TMS231 MC3X0 Microprocessor Support
5–7
Reference:Tables
Table 5–10 lists the signals required for Clock and Disassembly.
T able 5–10: Signals required for clocking and disassembly
Section:channel MC3X0 signal name
A31–A24 A3
A23–A16 A2
A15–A8 A1
A7–A0 A0
D31–D24 D3
D23–D16 D2
D15–D8 D1
D7–D0 D0
CLKOUT Clock:0
TA~ Clock:1
SHS~ Clock:2
TREQ~ Clock:3
CS5~ C1:5
CS4~ C1:4
CS3~ C0:3
CS2~ C0:2
CS1~ C0:1
CS0~ C0:0
RST~ C2:3
TEA~ C3:7
R/W~ C2:2
TSIZ1 C3:3
TSIZ0 C3:2
OE~ C2:1
EB3~ C0:7
EB2~ C0:6
EB1~ C0:5
5–8
EB0~ C0:4
PSTAT3 C2:7
PSTAT2 C2:6
PSTAT1 C2:5
TMS231 MC3X0 Microprocessor Support
T able 5–10: Signals required for clocking and disassembly (cont.)
Section:channel MC3X0 signal name
PSTAT0 C2:4
TC2 C3:6
TC1 C3:5
TC0 C3:4
SEQ~ C1:7
BIGEND~ C1:2
IFETCH C1:0
BURST~\BAA~ C1:6
FINT~ C3:1
INT~ C3:0
Reference:Tables
Table 5–11 lists the signals not required for Clock and Disassembly.
T able 5–11: Signals not required for clocking and
disassembly
Section:channel MC3X0 signal name
TBUSY~ C2:0
ABORT~ C1:3
RSTOUT~ C1:1
TMS231 MC3X0 Microprocessor Support
5–9
Reference:Tables
CPU To Mictor Connections
To probe the microprocessor you need to make connections between the CPU
and the Mictor pins of the P6434 Mass Termination Probe. Refer to the P6434
Mass Termination Probe manual, Tektronix part number 070-9793-xx, for more
information on mechanical specifications. Tables 5–12 through 5–14 list the
CPU pin to Mictor pin connections.
Tektronix uses a counterclockwise pin assignment. Pin 1 is located at the top left,
and pin 2 is located directly below it. Pin 20 is located on the bottom right, and
pin 21 is located directly above it.
AMP uses an odd side-even side pin assignment. Pin 1 is located at the top left,
and pin 3 is located directly below it. Pin 2 is located on the top right, and pin 4
is located directly below it (see Figure 5–1).
NOTE. When designing Mictor connectors into your system under test, always
follow the Tektronix pin assignment.
Tektronix Pinout AMP Pinout
Pin 1
Pin 19
Pin 38
Pin 20
Pin 1
Pin 37
Pin 2
Pin 38
Figure 5–1: Pin assignments for a Mictor connector (component side)
CAUTION. To protect the CPU and the inputs of the module, it is recommended
that a 180 W resistor be connected in series between each ball pad of the CPU
and each pin of the Mictor connector. The resistor must be within 1/2 inch of the
ball pad of the CPU.
5–10
TMS231 MC3X0 Microprocessor Support
T able 5–12: CPU to Mictor connections for clock and qualifiers
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Reference:Tables
Tektronix
LA channel
Clock:3
Clock:2 QUAL
Clock:1 QUAL
Clock:0 CLK
QUAL:3
QUAL:2
QUAL:1
БББББ
QUAL:0
MC3X0
signal name
TREQ~
SHS~
TA~
CLKOUT
––
––
––
ÁÁÁÁ
––
БББББ
C
mictor
pin number
C3
D36
A36
A3
––
––
––
––
T able 5–13: CPU to Mictor connections for Mictor A pins
Tektronix
Logic analyzer
channel
A0:0
MC3X0
signal name
A0
mictor A
pin number
A20
AMP
mictor C
pin number
C5
D6
A6
A5
––
––
––
БББББ
––
AMP
mictor A
pin number
A38
A0:1
A0:2
A0:3
A0:4
БББББ
A0:5
A0:6
A0:7
A1:0
A1:1
A1:2
A1:3
БББББ
A1:4
A1:5
A1:6
A1:7
A2:0
A1
A2
A3
A4
ÁÁÁÁ
A5
A6
A7
A8
A9
A10
A11
ÁÁÁÁ
A12
A13
A14
A15
A16
A21
A22
A23
A24
БББББ
A25
A26
A27
A28
A29
A30
A31
БББББ
A32
A33
A34
A35
A19
A36
A34
A32
A30
БББББ
A28
A26
A24
A22
A20
A18
A16
БББББ
A14
A12
A10
A8
A37
TMS231 MC3X0 Microprocessor Support
5–11
Reference:Tables
ББББББ
ББББББ
ББББББ
ББББББ
ББББББ
ББББББ
Á
Á
ББББББ
Á
Á
Á
ББББББ
ББББББ
ББББББ
ББББББ
ББББББ
ББББББ
Á
Á
ББББББ
Á
Á
Á
ББББББ
БББББББББ
БББББББББ
БББББББББ
БББББББББ
Á
Á
Á
БББББББББ
Á
Á
БББББББББ
БББББББББ
БББББББББ
БББББББББ
БББББББББ
T able 5–13: CPU to Mictor connections for Mictor A pins (cont.)
Logic analyzer
channel
A2:1
A2:2
A2:3
A2:4
A2:5
A2:6
A2:7
БББББ
A3:0
A3:1
A3:2
A3:3
A3:4
A3:5
A3:6
БББББ
A3:7
MC3X0
signal name
A17
A18
A19
A20
A21
A22
A23
БББББ
A24
A25
A26
A27
A28
A29
A30
БББББ
A31
Tektronix
mictor A
pin number
A18
A17
A16
A15
A14
A13
A12
ÁÁÁÁ
A11
A10
A9
A8
A7
A6
A5
ÁÁÁÁ
A4
AMP
mictor A
pin number
A35
A33
A31
A29
A27
A25
A23
БББББ
A21
A19
A17
A15
A13
A11
A9
БББББ
A7
5–12
T able 5–14: CPU to Mictor connections for Mictor D pins
LA channel
D0:0
D0:1
D0:2
D0:3
D0:4
ÁÁÁÁ
D0:5
D0:6
D0:7
D1:0
D1:1
MC3X0
signal name
D0
D1
D2
D3
D4
БББББ
D5
D6
D7
D8
D9
Tektronix
mictor D
pin number
D20
D21
D22
D23
D24
ÁÁÁ
D25
D26
D27
D28
D29
AMP
mictor D
pin number
D38
D36
D34
D32
D30
D28
D26
D24
D22
D20
TMS231 MC3X0 Microprocessor Support
БББББББ
T able 5–14: CPU to Mictor connections for Mictor D pins (cont.)
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
Á
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
Á
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
Á
ÁÁÁÁ
Reference:Tables
LA channel
D1:2
D1:3
D1:4
D1:5
D1:6
D1:7
D2:0
ÁÁÁÁ
D2:1
D2:2
D2:3
D2:4
D2:5
D2:6
D2:7
ÁÁÁÁ
D3:0
MC3X0
signal name
D10
D11
D12
D13
D14
D15
D16
БББББ
D17
D18
D19
D20
D21
D22
D23
БББББ
D24
Tektronix
mictor D
pin number
D30
D31
D32
D33
D34
D35
D19
ÁÁ
D18
D17
D16
D15
D14
D13
D12
ÁÁ
D11
AMP
mictor D
pin number
D18
D16
D14
D12
D10
D8
D37
ББББББББ
D35
D33
D31
D29
D27
D25
D23
ББББББББ
D21
D3:1
D3:2
D3:3
D3:4
D3:5
D3:6
ÁÁÁÁ
D3:7
D25
D26
D27
D28
D29
D30
БББББ
D31
D10
D9
D8
D7
D6
D5
ÁÁ
D4
D19
D17
D15
D13
D11
D9
ББББББББ
D7
T able 5–15: CPU to Mictor connections for Mictor C pins
Tektronix
LA channel
C3:7
C3:6
C3:5
MC3X0
signal name
TEA~
TC2
TC1
mictor C
pin number
C4
C5
C6
AMP
mictor C
pin number
C7
C9
C11
TMS231 MC3X0 Microprocessor Support
5–13
Reference:Tables
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
T able 5–15: CPU to Mictor connections for Mictor C pins (cont.)
LA channel
C3:4
C3:3
C3:2
C3:1
C3:0
C2:7
C2:6
ÁÁÁÁ
C2:5
C2:4
C2:3 (Qual)
C2:2 (Qual)
C2:1 (Qual)
C2:0 (Qual)
C1:7
ÁÁÁÁ
C1:6
MC3X0
signal name
TC0
TSIZ1
TSIZ0
FINT~
INT~
PSTAT3
PSTAT2
ББББББ
PSTAT1
PSTAT0
RST~
R/W~
OE~
TBUSY~
SEQ~
ББББББ
BURST~\BAA~
Tektronix
mictor C
pin number
C7
C8
C9
C10
C11
C12
C13
ÁÁ
C14
C15
C16
C17
C18
C19
C35
ÁÁ
C34
AMP
mictor C
pin number
C13
C15
C17
C19
C21
C23
C25
БББББББ
C27
C29
C31
C33
C35
C37
C8
БББББББ
C10
C1:5
C1:4
C1:3
C1:2
C1:1
C1:0
ÁÁÁÁ
C0:7
C0:6
C0:5
C0:4
C0:3
C0:2
C0:1
ÁÁÁÁ
C0:0
CS5~
CS4~
ABORT~
BIGEND~
RSTOUT~
IFETCH
ББББББ
EB3~
EB2~
EB1~
EB0~
CS3~
CS2~
CS1~
ББББББ
CS0~
C33
C32
C31
C30
C29
C28
ÁÁ
C27
C26
C25
C24
C23
C22
C21
ÁÁ
C20
C12
C14
C16
C18
C20
C22
БББББББ
C24
C26
C28
C30
C32
C34
C36
БББББББ
C38
5–14
TMS231 MC3X0 Microprocessor Support
Index
Index
A
About this manual set, vii
Acquiring data, 2–9
Address, T ektronix, viii
Address group, channel assignments, 5–3
Application, logic analyzer configuration, 1–1
B
Bus cycles, displayed cycle types, 2–10
C
Channel assignments
address group, 5–3
Chip_Select, 5–6
clocks and qualifiers, 5–7
Control, 5–5
data group, 5–4
Interrupt, 5–6
Misc group, 5–6
Proc_Mode, 5–5
Channel groups, 2–1
visibility , 2–9
Chip_Select, channel assignments, 5–6
Clock channel assignments, 5–7
Clock rate, 1–1
SUT, 3–1
Clocking, custom, 2–2
Clocking Options
external clocking, 2–2
internal clocking, 2–2
Connections
CPU to Mictor, 5–10
no probe adapter, 1–2
Contacting T ektronix, viii
Control, channel assignments, 5–5
Control flow display format, 2–11
Control group, symbol table, 5–1
CPU to Mictor connections, 5–10
CS mode, 2–13
Custom clocking, 2–2
Cycle types, 2–10
D
Data
acquiring, 2–9
disassembly formats
control Flow, 2-11
hardware, 2-10
software, 2-11
subroutine, 2-12
timingĆDisplay, 2-10
Data display , changing, 2–12
Data group, channel assignments, 5–4
Data Port Width, 2–13
Definitions
disassembler, vii
information on basic operations, vii
Demonstration file, 2–16
Disassembled data
cycle type definitions, 2–10
viewing, 2–9
viewing an example, 2–16
Disassembler
definition, vii
logic analyzer configuration, 1–1
setup, 2–1
Disassembly format definition overlay, 2–12
Disassembly property page, 2–12
Display formats
control Flow, 2–11
hardware, 2–10
software, 2–11
special characters, 2–9
subroutine, 2–12
timing-Display, 2–10
E
Electrical specifications, 3–1
clock rate, 3–1
Endian mode, 2–13
H
Hardware display format, 2–10
cycle type definitions, 2–10
Hold time, minimum, 3–1
TMS231 MC3X0 Microprocessor Support
Index–1
Index
I
Installing support software, 2–1
Interface, 2–13
Interrupt, channel assignments, 5–6
L
Logic analyzer
configuration for disassembler, 1–1
configuration for the application, 1–1
software compatibility, 1–1
M
Manual
conventions, vii
how to use the set, vii
Mark Cycle function, 2–14
Mark Opcode function, 2–14
Marking cycles, definition of, 2–14
Micro Specific Fields
CS mode, 2–13
Data Port Width, 2–13
endian mode, 2–13
interface, 2–13
R/W~ signal, 2–13
RIM CS base addresses, 2–13
vector base register, 2–13
Mictor to CPU connections, 5–10
Misc group, channel assignments, 5–6
without a probe adapter, 1–2
RIM CS Base Addresses, 2–13
S
Service support, contact information, viii
Set up time, minimum, 3–1
Setups
disassembler, 2–1
support, 2–1
Signals not required for Clocking and Disassembly, 5–9
Signals required for Clocking and Disassembly, 5–8
Software display format, 2–11
Special characters displayed, 2–9
Specifications, 3–1
electrical, 3–1
Subroutine display format, 2–12
Support, setup, 2–1
Support package setups
disassembly, 2–2
timing, 2–2
Support setup, 2–1
Symbol table, control channel group, 5–1
System file, demonstration, 2–16
T
T echnical support, contact information, viii
T ektronix, contacting, viii
T erminology, vii
Timing-display format, 2–10
P
Phone number, Tektronix, viii
Probe adapter, not using one, 1–2
Proc_Mode, channel assignments, 5–5
Product support, contact information, viii
R
R/W~Signal, 2–13
Reference, channel assignments, 5–2
Reference memory, 2–16
Restrictions, 1–1
Index–2
U
URL, T ektronix, viii
V
Vector base register, 2–13
Viewing disassembled data, 2–9
W
Web site address, T ektronix, viii
TMS231 MC3X0 Microprocessor Support
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