Instruction Manual
TMS 204
68040, 68EC040 & 68LC040 Microprocessor Support
070-9822-00
There are no current European directives that
apply to this product. This product provides
cable and test lead connections to a test object of
electronic measuring and test equipment.
Warning
The servicing instructions are for use by
qualified personnel only. To avoid personal
injury, do not perform any servicing unless you
are qualified to do so. Refer to all safety
summaries prior to performing service.
Copyright T ektronix, Inc. All rights reserved. Licensed software products are owned by Tektronix or its suppliers and are
protected by United States copyright laws and international treaty provisions.
Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the
Rights in T echnical Data and Computer Software clause at DFARS 252.227-7013, or subparagraphs (c)(1) and (2) of the
Commercial Computer Software – Restricted Rights clause at F AR 52.227-19, as applicable.
T ektronix products are covered by U.S. and foreign patents, issued and pending. Information in this publication supercedes
that in all previously published material. Specifications and price change privileges reserved.
Printed in the U.S.A.
T ektronix, Inc., P.O. Box 1000, Wilsonville, OR 97070–1000
TEKTRONIX and TEK are registered trademarks of T ektronix, Inc.
SOFTWARE WARRANTY
T ektronix warrants that the media on which this software product is furnished and the encoding of the programs on
the media will be free from defects in materials and workmanship for a period of three (3) months from the date of
shipment. If a medium or encoding proves defective during the warranty period, T ektronix will provide a
replacement in exchange for the defective medium. Except as to the media on which this software product is
furnished, this software product is provided “as is” without warranty of any kind, either express or implied.
T ektronix does not warrant that the functions contained in this software product will meet Customer’s
requirements or that the operation of the programs will be uninterrupted or error-free.
In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration
of the warranty period. If T ektronix is unable to provide a replacement that is free from defects in materials and
workmanship within a reasonable time thereafter, Customer may terminate the license for this software product
and return this software product and any associated materials for credit or refund.
THIS WARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER WARRANTIES, EXPRESS
OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’
RESPONSIBILITY TO REPLACE DEFECTIVE MEDIA OR REFUND CUSTOMER’S PAYMENT IS
THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS
WARRANTY. TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT,
SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER
TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH
DAMAGES.
HARDWARE WARRANTY
T ektronix warrants that the products that it manufactures and sells will be free from defects in materials and
workmanship for a period of one (1) year from the date of shipment. If a product proves defective during this
warranty period, T ektronix, at its option, either will repair the defective product without charge for parts and labor,
or will provide a replacement in exchange for the defective product.
In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration
of the warranty period and make suitable arrangements for the performance of service. Customer shall be
responsible for packaging and shipping the defective product to the service center designated by T ektronix, with
shipping charges prepaid. Tektronix shall pay for the return of the product to Customer if the shipment is to a
location within the country in which the T ektronix service center is located. Customer shall be responsible for
paying all shipping charges, duties, taxes, and any other charges for products returned to any other locations.
This warranty shall not apply to any defect, failure or damage caused by improper use or improper or inadequate
maintenance and care. T ektronix shall not be obligated to furnish service under this warranty a) to repair damage
resulting from attempts by personnel other than T ektronix representatives to install, repair or service the product;
b) to repair damage resulting from improper use or connection to incompatible equipment; c) to repair any
damage or malfunction caused by the use of non-T ektronix supplies; or d) to service a product that has been
modified or integrated with other products when the effect of such modification or integration increases the time
or difficulty of servicing the product.
THIS WARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER WARRANTIES, EXPRESS
OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’
RESPONSIBILITY TO REPAIR OR REPLACE DEFECTIVE PRODUCTS IS THE SOLE AND
EXCLUSIVE REMEDY PROVIDED TO THE CUST OMER FOR BREACH OF THIS WARRANTY.
TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT , SPECIAL,
INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER TEKTRONIX OR
THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.
Table of Contents
Getting Started
Operating Basics
General Safety Summary v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Service Safety Summary vii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preface: Microprocessor Support Documentation ix. . . . . . . . . . . . . . . .
Manual Conventions ix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Analyzer Documentation x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contacting T ektronix x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Support Description 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Analyzer Software Compatibility 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Analyzer Configuration 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Requirements and Restrictions 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuring the Probe Adapter 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connecting to a System Under T est 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PGA Probe Adapter 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Without a Probe Adapter 1–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Up the Support 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Group Definitions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocking Options 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Symbols 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acquiring and Viewing Disassembled Data 2–5. . . . . . . . . . . . . . . . . . . . .
Acquiring Data 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing Disassembled Data 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Display Format 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Display Format 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Flow Display Format 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subroutine Display Format 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Changing How Data is Displayed 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optional Display Selections 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Marking Cycles 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Displaying Exception Vectors 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing an Example of Disassembled Data 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifications
Probe Adapter Description 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifications 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Assignments 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
How Data is Acquired 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Custom Clocking 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocking Options 3–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alternate Microprocessor Connections 3–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signals On the Probe Adapter 3–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
i
Table of Contents
Extra Channels 3–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maintenance
Probe Adapter Circuit Description 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Replacing Signal Leads 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Replacing Protective Sockets 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Replaceable Electrical Parts
Parts Ordering Information 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the Replaceable Electrical Parts List 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Replaceable Mechanical Parts
Parts Ordering Information 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the Replaceable Mechanical Parts List 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . .
Index
ii
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
List of Figures
Table of Contents
Figure 1–1: Jumper location on the probe adapter 1–3. . . . . . . . . . . . . . .
Figure 1–2: Placing a microprocessor into a PGA probe adapter 1–5. . .
Figure 1–3: Connecting probes to a PGA probe adapter 1–6. . . . . . . . . .
Figure 1–4: Placing a PGA probe adapter onto the SUT 1–7. . . . . . . . . .
Figure 2–1: Hardware display format 2–7. . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3–1: Minimum clearance of the PGA probe adapter 3–4. . . . . . . .
Figure 3–2: 68040 bus timing 3–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
iii
Table of Contents
List of Tables
Table 1–1: Supported microprocessors 1–1. . . . . . . . . . . . . . . . . . . . . . . .
Table 1–2: 68040 signal connections for channel probes 1–8. . . . . . . . . .
Table 1–3: 68040 signal connections for clock probes 1–10. . . . . . . . . . . . .
Table 2–1: Control group symbol table definitions 2–2. . . . . . . . . . . . . . .
Table 2–2: Special characters in the display and meaning 2–6. . . . . . . . .
Table 2–3: Cycle type definitions 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2–4: Interrupt vectors 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3–1: Jumper positions 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3–2: Electrical specification 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3–3: Environmental specification 3–3. . . . . . . . . . . . . . . . . . . . . . . .
Table 3–4: Certifications and compliances 3–4. . . . . . . . . . . . . . . . . . . . . .
Table 3–5: Address group channel assignments 3–6. . . . . . . . . . . . . . . . . .
Table 3–6: Data group channel assignments 3–7. . . . . . . . . . . . . . . . . . . . .
Table 3–7: Control group channel assignments 3–8. . . . . . . . . . . . . . . . . .
Table 3–8: Interrupt group channel assignments 3–8. . . . . . . . . . . . . . . . .
Table 3–9: Cache group channel assignments 3–9. . . . . . . . . . . . . . . . . . .
Table 3–10: Misc group channel assignments 3–9. . . . . . . . . . . . . . . . . . . .
Table 3–11: Clock channel assignments 3–10. . . . . . . . . . . . . . . . . . . . . . . . .
Table 3–12: 68040 signals on J670 3–12. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3–13: Extra module sections and channels 3–13. . . . . . . . . . . . . . . .
iv
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
General Safety Summary
Review the following safety precautions to avoid injury and prevent damage to
this product or any products connected to it. To avoid potential hazards, use this
product only as specified.
Only qualified personnel should perform service procedures.
While using this product, you may need to access other parts of the system. Read
the General Safety Summary in other system manuals for warnings and cautions
related to operating the system.
To Avoid Fire or
Personal Injury
Connect and Disconnect Properly . Do not connect or disconnect probes or test
leads while they are connected to a voltage source.
Observe All Terminal Ratings. To avoid fire or shock hazard, observe all ratings
and marking on the product. Consult the product manual for further ratings
information before making connections to the product.
Do not apply a potential to any terminal, including the common terminal, that
exceeds the maximum rating of that terminal.
Do Not Operate Without Covers. Do not operate this product with covers or panels
removed.
Avoid Exposed Circuitry. Do not touch exposed connections and components
when power is present.
Do Not Operate With Suspected Failures. If you suspect there is damage to this
product, have it inspected by qualified service personnel.
Do Not Operate in Wet/Damp Conditions.
Do Not Operate in an Explosive Atmosphere.
Keep Product Surfaces Clean and Dry .
Provide Proper Ventilation. Refer to the manual’s installation instructions for
details on installing the product so it has proper ventilation.
Symbols and Terms
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
T erms in this Manual. These terms may appear in this manual:
WARNING. Warning statements identify conditions or practices that could result
in injury or loss of life.
v
General Safety Summary
CAUTION. Caution statements identify conditions or practices that could result in
damage to this product or other property.
T erms on the Product. These terms may appear on the product:
DANGER indicates an injury hazard immediately accessible as you read the
marking.
WARNING indicates an injury hazard not immediately accessible as you read the
marking.
CAUTION indicates a hazard to property including the product.
Symbols on the Product. The following symbols may appear on the product:
WARNING
High Voltage
Protective Ground
(Earth) T erminal
CAUTION
Refer to Manual
Double
Insulated
vi
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
Service Safety Summary
Only qualified personnel should perform service procedures. Read this Service
Safety Summary and the General Safety Summary before performing any service
procedures.
Do Not Service Alone. Do not perform internal service or adjustments of this
product unless another person capable of rendering first aid and resuscitation is
present.
Disconnect Power. To avoid electric shock, disconnect the main power by means
of the power cord or, if provided, the power switch.
Use Care When Servicing With Power On. Dangerous voltages or currents may
exist in this product. Disconnect power, remove battery (if applicable), and
disconnect test leads before removing protective panels, soldering, or replacing
components.
To avoid electric shock, do not touch exposed connections.
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
vii
Service Safety
viii
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
Preface: Microprocessor Support Documentation
This instruction manual contains specific information about the TMS 204 68040
microprocessor support and is part of a set of information on how to operate this
product on compatible Tektronix logic analyzers.
If you are familiar with operating microprocessor supports on the logic analyzer
for which the TMS 204 68040 support was purchased, you will probably only
need this instruction manual to set up and run the support.
If you are not familiar with operating microprocessor supports, you will need to
supplement this instruction manual with information on basic operations to set up
and run the support.
Information on basic operations of microprocessor supports is included with each
product. Each logic analyzer has basic information that describes how to perform
tasks common to supports on that platform. This information can be in the form
of online help, an installation manual, or a user manual.
This manual provides detailed information on the following topics:
H Connecting the logic analyzer to the system under test
Manual Conventions
H Setting up the logic analyzer to acquire data from the system under test
H Acquiring and viewing disassembled data
H The TMS 204 68040 probe adapter
This manual uses the following conventions:
H The phrase “information on basic operations” refers to online help, an
installation manual, or a basic operations of microprocessor supports user
manual.
H In the information on basic operations, the term XXX or P54C used in field
selections and file names can be replaced with 68040A. This is the name of
the microprocessor in field selections and file names you must use to operate
the 68040 support.
H The term System Under Test (SUT) refers to the microprocessor-based
system from which data will be acquired.
H The term logic analyzer refers to the Tektronix logic analyzer for which this
product was purchased.
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
ix
Preface: Microprocessor Support Documentation
H The term module refers to a 102/136-channel or a 96-channel module.
Logic Analyzer Documentation
A description of other documentation available for each type of Tektronix logic
analyzer is located in the corresponding module user manual. The user manual
provides the information necessary to install, operate, maintain, and service the
logic analyzer and associated products.
Contacting Tektronix
Product
Support
Service
Support
For other
information
To write us Tektronix, Inc.
For application-oriented questions about a Tektronix measurement product, call toll free in North America:
1-800-TEK-WIDE (1-800-835-9433 ext. 2400)
6:00 a.m. – 5:00 p.m. Pacific time
Or, contact us by e-mail:
tm_app_supp@tek.com
For product support outside of North America, contact your
local Tektronix distributor or sales office.
Contact your local Tektronix distributor or sales office. Or, visit
our web site for a listing of worldwide service locations.
http://www.tek.com
In North America:
1-800-TEK-WIDE (1-800-835-9433)
An operator will direct your call.
P.O. Box 1000
Wilsonville, OR 97070-1000
x
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
Getting Started
Getting Started
Support Description
This chapter provides information on the following topics:
H The TMS 204 68040 microprocessor support
H Logic analyzer software compatibility
H Your 68040 system requirements
H 68040 support restrictions
H How to configure the probe adapter
H How to connect to the System Under Test (SUT)
The TMS 204 microprocessor support disassembles data from systems that are
based on the Motorola 68040 microprocessor. The support runs on a compatible
Tektronix logic analyzer equipped with a 102/136-channel module, or a
96-channel module.
Refer to information on basic operations to determine how many modules and
probes your logic analyzer needs to meet the minimum channel requirements for
the TMS 204 microprocessor support.
Table 1–1 shows the microprocessors and packages from which the TMS 204
support can acquire and disassemble data.
T able 1–1: Supported microprocessors
Name Package
68040 PGA
68EC040 PGA
68LC040 PGA
A complete list of standard and optional accessories is provided at the end of the
parts list in the Replaceable Mechanical Parts chapter.
To use this support efficiently, you need to have the items listed in the information on basic operations as well as the 68040 Microprocessor User’s Manual,
Motorola, 1989.
Information on basic operations also contains a general description of supports.
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
1–1
Getting Started
Logic Analyzer Software Compatibility
The label on the microprocessor support floppy disk states which version of logic
analyzer software the support is compatible with.
Logic Analyzer Configuration
To use the 68040 support, the Tektronix logic analyzer must be equipped with at
least a 102/136-channel module or a 96-channel module. The module must be
equipped with enough probes to acquire channel and clock data from signals in
your 68040-based system.
Refer to information on basic operations to determine how many modules and
probes the logic analyzer needs to meet the channel requirements.
Requirements and Restrictions
You should review the general requirements and restrictions of microprocessor
supports in the information on basic operations as they pertain to your SUT.
You should also review electrical, environmental, and mechanical specifications
in the Specifications chapter in this manual as they pertain to your system under
test, as well as the following descriptions of other 68040 support requirements
and restrictions.
System Clock Rate. The TMS 204 support product supports the 68040 microprocessor at speeds of up to 33 MHz
Hardware Reset. If a hardware reset occurs in your 68040 system during an
acquisition, the disassembler might acquire an invalid sample.
Cache Invalidation. Correct disassembly is not guaranteed for microprocessor
systems that run cache invalidations concurrent with burst cycles.
Dynamic Bus Sizing. When the Bus Size Control signals (BS16# or BS8#) are
asserted, the 68040 microprocessor allows the bus width to be changed for extra
cycles (when more than one cycle is required for a transaction). The disassembler
does not support changing the bus size for extra cycles. To keep the disassembler
synchronized, Use Mark Opcode as described in the Operating Basics chapter.
1
.
1–2
1
Specification at time of printing. Contact your logic analyzer sales representative for
current information on the fastest devices supported.
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
Data Reads and Writes. The dissassembler will not link data reads and writes with
the instruction which causes them.
Locked Bus Cycles. The dissasembler will not identify locked bus cycles.
Configuring the Probe Adapter
Disabling the cache makes all instruction prefetches visible on the bus so they
can be acquired and disassembled. The probe adapter contains a jumper you can
use to disable the 68040 cache.
With the cache jumper in the NORM position, the SUT controls the cache and
the CDIS~ signal is not affected.
With the cache jumper in the DIS position, the CDIS~ signal connects to a
332 Ω pull-down resistor on the probe adapter which disables the cache. You
should also cut or remove pin T5 from the protective socket on the underside of
the probe adapter to prevent contention with the driving signal.
Getting Started
Figure 1–1 shows the location of J990 on the probe adapter.
Figure 1–1: Jumper location on the probe adapter
J990
Connecting to a System Under Test
Before you connect to the SUT, you must connect the probes to the module. Your
SUT must also have a minimum amount of clear space surrounding the micro-
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
1–3
Getting Started
processor to accommodate the probe adapter. Refer to the Specifications chapter
in this manual for the required clearances.
The channel and clock probes shown in this chapter are for a 102/136-channel
module. Your probes will look different if you are using a 96-channel module.
The general requirements and restrictions of microprocessor supports in the
information on basic operations shows the vertical dimensions of a channel or
clock probe connected to square pins on a circuit board.
PGA Probe Adapter
To connect the logic analyzer to a SUT using a PGA probe adapter, follow these
steps:
1. Turn off power to your SUT. It is not necessary to turn off power to the logic
analyzer.
CAUTION. Static discharge can damage the microprocessor, the probe adapter,
the probes, or the module. To prevent static damage, handle all of the above only
in a static-free environment.
Always wear a grounding wrist strap or similar device while handling the
microprocessor and probe adapter.
2. To discharge your stored static electricity, touch the ground connector located
on the back of the logic analyzer. Then, touch any of the ground pins of the
probe adapter to discharge stored static electricity from the probe adapter.
3. Place the probe adapter onto the antistatic shipping foam to support the probe
as shown in Figure 1–2. This prevents the circuit board from flexing and the
socket pins from bending.
4. Remove the microprocessor from your SUT.
1–4
5. Line up the pin A1 indicator on the probe adapter board with the pin A1
indicator on the microprocessor.
CAUTION. Failure to correctly place the microprocessor into the probe adapter
might permanently damage the microprocessor once power is applied.
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
Getting Started
6. Place the microprocessor into the probe adapter as shown in Figure 1–2.
Microprocessor
Probe adapter
Foam
Figure 1–2: Placing a microprocessor into a PGA probe adapter
7. Connect the channel and clock probes to the probe adapter as shown in
Figure 1–3. Match the channel groups and numbers on the probe labels to the
corresponding pins on the probe adapter. Match the ground pins on the
probes to the corresponding pins on the probe adapter.
8. Line up the pin A1 indicator on the probe adapter board with the pin A1
indicator on your SUT.
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
1–5
Getting Started
Channel probe
Hold the channel probes by the podlet
holder when connecting them to the
probe adapter. Do not hold them by
the cables or necks of the podlets.
Foam
Figure 1–3: Connecting probes to a PGA probe adapter
Clock probe
Probe adapter
9. Place the probe adapter onto the SUT as shown in Figure 1–4.
NOTE. You might need to stack one or more replacement sockets between the SUT
and the probe adapter to provide sufficient vertical clearance from adjacent
components. However, keep in mind that this might increase loading, which can
reduce the electrical performance of your probe adapter.
1–6
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
SUT socket
Getting Started
Without a Probe Adapter
Figure 1–4: Placing a PGA probe adapter onto the SUT
You can use channel probes, clock probes, and leadsets with a commercial test
clip (or adapter) to make connections between the logic analyzer and your SUT.
To connect the probes to 68040 signals in the SUT using a test clip, follow these
steps:
1. Turn off power to your SUT. It is not necessary to turn off power to the logic
analyzer.
CAUTION. Static discharge can damage the microprocessor, the probes, or the
module. To prevent static damage, handle all of the above only in a static-free
environment.
Always wear a grounding wrist strap or similar device while handling the
microprocessor.
2. To discharge your stored static electricity, touch the ground connector located
on the back of the logic analyzer. If you are using a test clip, touch any of the
ground pins on the clip to discharge stored static electricity from it.
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
1–7
Getting Started
CAUTION. Failure to place the SUT on a horizontal surface before connecting the
test clip might permanently damage the pins on the microprocessor.
3. Place the SUT on a horizontal static-free surface.
4. Use Table 1–2 to connect the channel probes to 68040 signal pins on the test
clip or in the SUT.
Use leadsets to connect at least one ground lead from each channel probe and
the ground lead from each clock probe to ground pins on your test clip.
5. Align pin 1 or A1 of your test clip with the corresponding pin 1 or A1 of the
68040 microprocessor in your SUT and attach the clip to the microprocessor.
T able 1–2: 68040 signal connections for channel probes
Section:channel 68040 signal Section:channel 68040 signal
A3:7 A31 D3:7 D31
A3:6 A30 D3:6 D30
A3:5 A29 D3:5 D29
A3:4 A28 D3:4 D28
A3:3 A27 D3:3 D27
A3:2 A26 D3:2 D26
A3:1 A25 D3:1 D25
A3:0 A24 D3:0 D24
A2:7 A23 D2:7 D23
A2:6 A22 D2:6 D22
A2:5 A21 D2:5 D21
A2:4 A20 D2:4 D20
A2:3 A19 D2:3 D19
A2:2 A18 D2:2 D18
A2:1 A17 D2:1 D17
A2:0 A16 D2:0 D16
A1:7 A15 D1:7 D15
A1:6 A14 D1:6 D14
1–8
A1:5 A13 D1:5 D13
A1:4 A12 D1:4 D12
A1:3 A1 1 D1:3 D11
A1:2 A10 D1:2 D10
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
T able 1–2: 68040 signal connections for channel probes (cont.)
Section:channel 68040 signalSection:channel68040 signal
A1:1 A9 D1:1 D9
A1:0 A8 D1:0 D8
A0:7 A7 D0:7 D7
A0:6 A6 D0:6 D6
A0:5 A5 D0:5 D5
A0:4 A4 D0:4 D4
A0:3 A3 D0:3 D3
A0:2 A2 D0:2 D2
A0:1 A1 D0:1 D1
A0:0 A0 D0:0 D0
C3:7 BG_L~ C2:7 BCLK_B*
C3:6 TT1 C2:6 R/W~
Getting Started
C3:5 MI~ C2:5 LOCK~
C3:4 TM2 C2:4 TM0
C3:3 SIZ0 C2:3 TM1
C3:2 TT0 C2:2 TEA~
C3:1 TCI~ C2:1 TA~
C3:0 SIZ1 C2:0 TS~
C1:7 TLN1 C0:7 TIP~*
C1:6 IPL2~ C0:6 IPL0~
C1:5 AVEC~ C0:5 RSTI~*
C1:4 SC1 C0:4 UP A1*
C1:3 TLN0 C0:3 MDIS~*
C1:2 IPL1~ C0:2 IPEND~
C1:1 TB1~* C0:1 CDIS~
C1:0 SC0 C0:0 UP A0*
* Signal not required for disassembly.
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
1–9
Getting Started
Table 1–3 shows the clock probes, and the 68040 signal to which they must
connect for disassembly to be correct.
T able 1–3: 68040 signal connections for clock probes
Section:channel 68040 signal
CK:3 BCLK
CK:2 not connected
CK:1 BG~
CK:0 TIP~
1–10
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
Operating Basics
Setting Up the Support
This section provides information on how to set up the support. Information
covers the following topics:
H Channel group definitions
H Clocking options
H Symbol table files
Remember that the information in this section is specific to the operations and
functions of the TMS 204 68040 support on any Tektronix logic analyzer for
which it can be purchased. Information on basic operations describes general
tasks and functions.
Before you acquire and disassemble data, you need to load the support and
specify setups for clocking, and triggering as described in the information on
basic operations. The support provides default values for each of these setups,
but you can change them as needed.
Channel Group Definitions
Clocking Options
The disassembler automatically defines channel groups for the support product.
The channel groups for the 68040 support are Address, Data, Control, Intr,
Cache, and Misc.
The TMS 204 support offers a microprocessor-specific clocking mode for the
68040 microprocessor. This clocking mode is the default selection whenever you
load the 68040A support.
A description of how cycles are sampled by the module using the support and
probe adapter is found in the Specifications chapter.
Disassembly will not be correct with the Internal or External clocking modes.
Information on basic operations describes how to use these clock selections for
general purpose analysis.
The clocking options for the TMS 204 support are: 68040 Address / Data Bus
Mode, and Alternate Bus Master Cycles.
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
2–1
Setting Up the Support
68040 Address / Data Bus
Mode
Alternate Bus Master
Cycles
Symbols
The 68040 has a multiplexed bus mode that supports the generation of a
multiplexed address/data bus. When used in this mode, the address and data bus
can be hard-wired together to form a single 32-bit address/data bus at the
microprocessor (CPU) with address and data information time-multiplexed on
the bus.
You select the 68040 address/data bus mode by selecting Multiplexed in the field.
The default selection is Non-Multiplexed.
NOTE. If you select the Multiplexed mode, you should remove the channels
connected to the data signals to reduce loading.
An alternate bus master cycle is defined as the 68040 giving up the bus to an
alternate device (a DMA device or another microprocessor). These types of
cycles are acquired when you select Included.
The TMS 204 support supplies one symbol table file. The 68040A_Ctrl file
replaces specific Control channel group values with symbolic values when
Symbolic is the radix for the channel group.
Table 2–1 shows the name, bit pattern, and meaning for the symbols in the file
68040A_Ctrl, the Control channel group symbol table.
T able 2–1: Control group symbol table definitions
Control group value
LOCK~ MI~
Symbol
LPSTOP_ACK
LPSTOP_ERROR
BKPT_ACK
BKPT_ERROR
INT_ACK
SPUR_INTR
BUS_ERROR
BUS_RETRY
PREFETCH?
BG~ TM2 TS~ TEA~
TT1 TM1 TA~ SIZ1
TT0 TM0 R/W~ SIZ0
Meaning
LPSTOP Acknowledge cycle
LPSTOP Error – 68040 mode
Breakpoint acknowledge cycle
Breakpoint error
Interrupt acknowledge cycle
Spurious interrupt
Bus error
Bus error and retry
Probable instruction or extension
2–2
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
T able 2–1: Control group symbol table definitions (cont.)
Control group value
BG~ TM2 TS~ TEA~
Symbol Meaning
MMU_DA TA_RD
MMU_DA TA_WR
MMU_DA TA
MMU_PROG_RD
MMU_PROG_WR
MMU_PROG
RMW_READ
RMW_WRITE
RMW*
DA TA_SP_RD_16
DA TA_SP_READ
DA TA_SP_WR_16
DA TA_SP_WRITE
PROG_SP_READ
PROG_SP_WRITE
CACHE_PUSH
AL T_ACC_READ
AL T_ACC_WRITE
AL T_ACC
AL T_BUS_READ
AL T_BUS_WRITE
AL T_BUS*
READ
WRITE
SUPER_DAT A–16*
SUPR_DA TA*
SUPR_PROG*
SUPERVISR*
U_DA TA_16*
USER_DATA*
USER_PROG*
USER*
TT1 TM1 TA~ SIZ1
TT0 TM0 R/W~ SIZ0
LOCK~ MI~
MMU table search data read cycle
MMU table search data write cycle
Any MMU table search data access
MMU table search program read cycle
MMU table search program write cycle
Any MMU table search program access
Read portion of locked RMW cycle
Write portion of locked RMW cycle
Any portion of locked RMW cycle
Data space read cycle – MOVE16
Data space read cycle
Data space write cycle – MOVE16
Data space write cycle
Program space read cycle
Program space write cycle
Data cache push access
Alternate access read cycle
Alternate access write cycle
Any alternate access cycle
Alternate bus master read cycle
Alternate bus master write cycle
Any alternate bus master cycle
Any read cycle
Any write cycle
Supervisor data space access – MOVE16
Supervisor data space access
Supervisor program space access
Any supervisor access
User data space access – MOVE16
User data space access
User program space access
Any user space access
Setting Up the Support
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
2–3
Setting Up the Support
T able 2–1: Control group symbol table definitions (cont.)
Control group value
BG~ TM2 TS~ TEA~
Symbol Meaning
DA TA_SPACE_16*
DA TA_SPAC*
PROG_SPACE*
TT1 TM1 TA~ SIZ1
TT0 TM0 R/W~ SIZ0
LOCK~ MI~
Any data space access – MOVE16
Any data space access
Any program space access
* Symbols used only for triggering; they are not displayed.
Information on basic operations describes how to use symbolic values for
triggering, and displaying other channel groups symbolically, such as the Address
channel group.
2–4
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
Acquiring and Viewing Disassembled Data
This section describes how to acquire data and view it disassembled. Information
covers the following topics:
H Acquiring data
H Viewing disassembled data in various display formats
H Cycle type labels
H How to change the way data is displayed
H How to change disassembled cycles with the mark cycles function
Acquiring Data
Once you load the 68040A support, choose a clocking mode and specify the
trigger, you are ready to acquire and disassemble
If you have any problems acquiring data, refer to information on basic operations
in your online help or Appendix A: Error Messages and Disassembly Problems in
the basic operations user manual, whichever is available.
data.
Viewing Disassembled Data
You can view disassembled data in four different display formats: Hardware,
Software, Control Flow, and Subroutine. The information on basic operations
describes how to select the disassembly display formats.
NOTE. Selections in the Disassembly property page (the Disassembly Format
Definition overlay) must be set correctly for your acquired data to be disassembled correctly.
The default display format shows the Address, Data, and Control channel group
values for each sample of acquired data.
The disassembler displays special characters and strings in the instruction
mnemonics to indicate significant events. Table 2–2 shows the special characters
and strings displayed by the 68040 disassembler and gives a definition of what
they represent.
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
2–5
Acquiring and Viewing Disassembled Data
T able 2–2: Special characters in the display and meaning
Character or string displayed Meaning
m The instruction was manually marked as a program fetch
** Indicates there is insufficient data available for complete
# Indicates an immediate value
t Indicates the number shown is in decimal, such as #12t
* ILLEGAL INSTRUCTION * Decoded as an illegal instruction
A-LINE OPCODE Displayed for an A-Line trap instruction
F-LINE OPCODE Displayed for an F-Line trap instruction
disassembly of the instruction; the number of asterisks will
indicate the width of the data that is unavailable. Two
asterisks represent a byte.
Hardware Display Format
In Hardware display format, the disassembler displays certain cycle type labels in
parentheses. Table 2–3 shows these cycle type labels and gives a definition of the
cycle they represent. Reads to interrupt and exception vectors will be labeled
with the vector name.
T able 2–3: Cycle type definitions
Cycle type Definition
( LPSTOP BROADCAST )* The 68040 enters an LPSTOP cycle
( BREAKPOINT ACK )* A breakpoint acknowledge cycle
( INT ACK LEVEL: n )* An interrupt acknowledge cycle
( SPURIOUS INTERRUPT ) The 68040 signals a spurious interrupt
( BUS ERROR ) A bus cycle error
( BUS ERROR RETRY ) A bus cycle error retry
( MMU TABLE READ ) A search and read cycle of the MMU table
( MMU TABLE WRITE ) A search and write cycle of the MMU table
( RMW READ ) The read portion of a read-modify-write cycle
( RMW WRITE ) The write portion of a read-modify-write cycle
( READ ) Any read cycle
2–6
( WRITE ) Any write cycle
( CACHE PUSH ) The 68040 writes cache to memory
( ALTERNATE ACCESS READ ) An alternate access read cycle
( ALTERNATE ACCESS WRITE ) An alternate access write cycle
( ALT BUS MASTER: READ ) An alternate bus master read cycle
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
Acquiring and Viewing Disassembled Data
T able 2–3: Cycle type definitions (cont.)
Cycle type Definition
( ALT BUS MASTER: WRITE ) An alternate bus master write cycle
( UNKNOWN ) An unexpected or unrecognized combination of bits.
( PREFETCH IGNORED )* A burst fill to the instruction cache that is not executed
( CACHE BURST FILL )* A burst fill to the data cache
( EXTENSION )* A fetch cycle computed to be an opcode extension
( FLUSH )* A fetch cycle computed to be an opcode flush
* Computed cycle types.
Figure 2–1 shows an example of the Hardware display.
1 2 3 4 5 6
Sequence Address Data Mnemonic Timestamp
-------------------------------------------------------------------------------T 0 00000000--00015000--(-RESET:-STACK-POINTER-)-----------(S)------------
1 00000004 F2000102 ( RESET: PROGRAM COUNTER ) (S) 780 ns
2 F2000102 4E73207C MOVEA.L #000003FC,A0 (S) 720 ns
3 F2000104 000003FC ( EXTENSION ) (S) 600 ns
4 F2000108 20BCF200 MOVE.L #F2000100,(A0) (S) 660 ns
5 F200010E 0100207C MOVEA.L #00000000,A0 (S) 600 ns
6 F2000110 00000000 ( EXTENSION ) (S) 900 ns
7 000003FC F2000100 ( WRITE ) (S) 120 ns
8 F2000114 4E7B8801 MOVEC A0,VBR (S) 600 ns
9 F2000118 207C0000 ( FLUSH ) (S) 660 ns
10 F200011C 110430BC ( FLUSH ) (S) 600 ns
11 F2000118 207C0000 MOVEA.L #00001104,A0 (S) 600 ns
12 F200011E 110430BC MOVE.W #0000,(A0) (S) 600 ns
13 F2000122 0000207C MOVEA.L #00001108,A0 (S) 660 ns
14 F2000124 00001108 ( EXTENSION ) (S) 600 ns
15 00001104 0000---- ( WRITE ) (S) 120 ns
16 F2000128 30BC0000 MOVE.W #0000,(A0) (S) 600 ns
17 F200012C 207C0000 MOVEA.L #00001110,A0 (S) 600 ns
18 00001108 0000---- ( WRITE ) (S) 120 ns
19 F2000132 111030BC MOVE.W #0000,(A0) (S) 600 ns
20 F2000136 0000207C MOVEA.L #0000110C,A0 (S) 600 ns
Figure 2–1: Hardware display format
1
Sample Column. Lists the memory locations for the acquired data.
2
Address Group. Lists data from channels connected to the 68040 Address
bus.
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
2–7
Acquiring and Viewing Disassembled Data
3
Data Group. Lists data from channels connected to the 68040 Data bus.
4
Mnemonic Column. Lists the disassembled instructions and cycle types.
5
The disassembler displays an (S) or (U) in the mnemonic column to indicate
the mode in which the microprocessor is operating, Supervisor or User.
6
Timestamp. Lists the timestamp values when a timestamp selection is made.
Information on basic operations describes how you can select a timestamp.
Software Display Format
Control Flow Display
Format
The Software display format shows only the first fetch of executed instructions.
Flushed cycles and extensions are not shown, even though they are part of the
executed instruction. Read extensions will be used to disassemble the instruction,
but will not be displayed as a separate cycle in the Software display format. Data
reads and writes are not displayed.
The Software display format also shows the following cycles:
H Reset cycle
H Halt cycle
H Bus Error cycle
H Special cycles: Breakpoint Ack, Int Ack, Internal Reg Access, Reset Vector
H Reads from the vector table that appear due to servicing interrupts or traps.
H Illegal instructions will be displayed
H Unknown cycle types; the disassembler does not recognize the Control group
value
The Control Flow display format shows only the first fetch of instructions that
change the flow of control.
2–8
The Control Flow display format also shows the following cycles:
H Bus error cycle
H Bus error retry cycle
H Spurious interrupts
H The special cycles: Breakpoint Ack, Int Ack, LPSTOP Broadcast, and
Emulated instructions which cause exceptions.
H Reset vector
H Reads from the exception table that appear due to servicing exceptions
H Illegal instructions
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
Acquiring and Viewing Disassembled Data
H Unknown cycle types; the disassembler does not recognize the Control group
value
Instructions that generate a subroutine call or a return in the 68040 microprocessor are as follows:
BRKPT BSR ILLEGAL
JSR LPSTOP RESET
RTD RTE RTR
RTS STOP TRAP
Instructions that might generate a subroutine call or a return in the 68040
microprocessor are as follows:
CHK CHK2 DIVS
DIVSL DIVU DIVUL
TRAPcc TRAPV
Instructions that generate a change in the flow of control in the 68040
microprocessor are as follows:
Subroutine Display
Format
The Subroutine display format shows only the first fetch of subroutine call and
return instructions. It will display conditional subroutine calls if they are
considered to be taken.
The Subroutine display format also shows the following cycles:
H Bus error cycle
H Bus error retry cycle
H Spurious interrupt
H The special cycles: Breakpoint Ack, Int Ack, LPSTOP Broadcast, and
Emulated instructions which cause exceptions.
H Illegal instructions
H Unknown cycle types; the disassembler does not recognize the Control group
value
Instructions that generate a subroutine call or a return in the 68040 microprocessor are as follows:
BRKPT BSR ILLEGAL
JSR LPSTOP RESET
RTD RTE RTR
RTS STOP TRAP
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
2–9
Acquiring and Viewing Disassembled Data
Instructions that might generate a subroutine call or a return in the 68040
microprocessor are as follows:
CHK CHK2 DIVS
DIVSL DIVU DIVUL
TRAPcc TRAPV
Changing How Data is Displayed
There are fields and features that allow you to further modify displayed data to
suit your needs. You can make selections unique to the 68040 support to do the
following tasks:
H Change how data is displayed across all display formats
H Change the interpretation of disassembled cycles
H Display exception vectors
Optional Display
Selections
Marking Cycles
You can make optional display selections for aquire disassembled data to help
you analyze the data. You can make the selections in the Disassembly property
page (the Disassembly Format Definition overlay).
In addition to the common display options (described in the information on basic
operations), you can change the displayed data in the following ways:
H Specify the starting address of the vector base register
H Specify the size of the vector table
The 68040 support has two additional fields: Interrupt Table Address, and
Interrupt Table Size. These fields appear in the area indicated in the information
on basic operations.
Vector Base Register. You can specify the starting address of the vector base
register in hexadecimal. The default starting address is 0x00000000.
Vector Table Size. You can specify the size of the vector table in hexadecimal.
The default size is 0x400.
The disassembler has a Mark Opcode function that allows you to change the
interpretation of a cycle type. Using this function, you can select a cycle and
change it to one of the following cycle types:
2–10
H Opcode (the first byte of an instruction)
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
Acquiring and Viewing Disassembled Data
H Extension (a subsequent byte of an instruction)
H Flush (an opcode or extension that is fetched but not executed)
H Anything (any valid opcode, extension or flush)
H Read (marks a memory reference read as data)
Mark selections are as follows:
OPCODE Any
OPCODE Any
OPCODE FLUSH
FLUSH FLUSH
FLUSH OPCODE
READ READ
EXTENSION EXTENSION
EXTENSION OPCODE
EXTENSION FLUSH
Displaying Exception
Vectors
Undo Marks
Information on basic operations contains more details on marking cycles.
The disassembler can display exception vectors. You can select to display the
interrupt vectors for Real, Virtual, or Protected modes in the Interrupt Table field.
(Selecting Virtual is equivalent to selecting Protected.)
You can relocate the table by entering the starting address in the Interrupt Table
Address field. The Interrupt Table Address field provides the disassembler with
the offset address; enter an eight-digit hexadecimal value corresponding to the
offset of the base address of the exception table. The Interrupt Table Size field
lets you specify a three-digit hexadecimal size for the table.
You can make the selections in the Disassembly property page (the Disassembly
Format Definition overlay).
Interrupt cycle types are computed and cannot be used to control triggering.
When the 68040 microprocessor processes an interrupt, the disassembler displays
the type of interrupt, if known.
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
2–11
Acquiring and Viewing Disassembled Data
Table NO TAG lists the 68040 exception vectors.
T able 2–4: Interrupt vectors
Exception
number
0 0000 RESET: INITIAL INTERRUPT STACK POINTER
1 0004 RESET: INITIAL PROGRAM COUNTER
2 0008 ACCESS FAULT
3 000C ADDRESS ERROR
4 0010 ILLEGAL INSTRUCTION
5 0014 INTEGER DIVIDE BY ZERO
6 0018 CHK, CHK2 INSTRUCTION
7 001C FTRAPcc, TRAPcc, TRAPV INSTRUCTIONS
8 0020 PRIVILEGE VIOLATION
9 0024 TRACE
10 0028 LINE 1010 EMULATOR
11 002C LINE 111 1 EMULATOR
12 0030 UNASSIGNED, RESERVED
13 0034 NOT USED BY MC68040
14 0038 FORMAT ERROR
15 003C UNINITIALIZED INTERRUPT
16–23 0040–005C UNASSIGNED, RESERVED
24 0060 SPURIOUS INTERRUPT
25 0064 LEVEL 1 INTERRUPT AUTO VECTOR
26 0068 LEVEL 2 INTERRUPT AUTO VECTOR
27 006C LEVEL 3 INTERRUPT AUTO VECTOR
28 0070 LEVEL 4 INTERRUPT AUTO VECTOR
29 0074 LEVEL 5 INTERRUPT AUTO VECTOR
30 0078 LEVEL 6 INTERRUPT AUTO VECTOR
31 007C LEVEL 7 INTERRUPT AUTO VECTOR
32–47 0080–00BC TRAP #0–15 INSTRUCTION VECTORS
48 00CO FP BRANCH OR SET ON UNORDERED
49 00C4 FP INEXACT RESULT
50 00C8 FP DIVIDE BY ZERO
51 00CC FP UNDERFLOW
52 00DO FP OPERAND ERROR
53 00D4 FP OVERFLOW
54 00D8 FP SIGNALING NAN
Location in IV* table
(in hexadecimal)
Displayed interrupt name
CONDITION
2–12
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
T able 2–4: Interrupt vectors (cont.)
Acquiring and Viewing Disassembled Data
Exception
number
55 00DC FP UNIMPLEMENTED DAT A TYPE
56 00EO NOT USED BY MC68040
57 00E4 NOT USED BY MC68040
58 00E8 NOT USED BY MC68040
59–63 00EC–00FC UNASSIGNED, RESERVED
64–255 0100–03FC USER DEFINED VECTORS (192)
* IV means interrupt vector.
Location in IV* table
(in hexadecimal)
Viewing an Example of Disassembled Data
A demonstration system file (or demonstration reference memory) is provided so
you can see an example of how your 68040 microprocessor bus cycles and
instruction mnemonics look when they are disassembled. Viewing the system file
is not a requirement for preparing the module for use. You can view the system
file without connecting the logic analyzer to your SUT.
Information on basic operations describes how to view the file.
Displayed interrupt name
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
2–13
Acquiring and Viewing Disassembled Data
2–14
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
Specifications
Specifications
This chapter contains the following information:
H Probe adapter description
H Specification tables
H Dimensions of the probe adapter
H Channel assignment tables
H Description of how the module acquires 68040 signals
H List of other accessible 68040 signals and extra acquisition channels
Probe Adapter Description
The probe adapter is a nonintrusive piece of hardware that allows the logic
analyzer to acquire data from a 68040 microprocessor in its own operating
environment with little effect, if any, on that system. Information on basic
operations contains a figure showing the logic analyzer connected to a typical
probe adapter. Refer to that figure while reading the following description.
Configuration
The probe adapter consists of a circuit board and a socket for a 68040
microprocessor. The probe adapter connects to the microprocessor in the SUT.
Signals from the microprocessor-based system flow from the probe adapter to the
channel groups and through the probe signal leads to the module.
All circuitry on the probe adapter is powered from the SUT.
The probe adapter accommodates the Motorola 68040, 68EC040, and 68LC040
microprocessors in a PGA package.
Disabling the cache makes all instruction prefetches visible on the bus so they
can be acquired and disassembled. The probe adapter contains a jumper you can
use to disable the 68040 cache.
With the cache jumper in the NORM position, the SUT controls the cache and
the CDIS~ signal is not affected.
With the cache jumper in the DIS position, the CDIS~ signal connects to a 332 Ω
pull-down resistor on the probe adapter which disables the cache. To prevent
contention with the driving signal, cut or remove pin T5 from the protective
socket on the underside of the probe adapter.
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
3–1
Specifications
Specifications
Table 3–1 shows the jumper positions.
T able 3–1: Jumper positions
Jumper Positions
J990 (PGA) 1–2 (NORM)
3–4 (DIS)
These specifications are for a probe adapter connected to a compatible Tektronix
logic analyzer, and the SUT. Table 3–2 shows the electrical requirements the
SUT must produce for the support to acquire correct data
In Table 3–2, for the 102/136-channel module, one podlet load is 20 k in
parallel with 2 pF. For the 96-channel module, one podlet load is 100 k in
parallel with 10 pF.
T able 3–2: Electrical specification
Characteristics Requirements
SUT DC power requirements
Voltage 4.75-5.25 VDC
Current I max (calculated) 210 mA
I typ (measured) 146 mA
SUT clock
Clock rate Min. 16.67 MHz
Max. 33 MHz
Minimum setup time required*
All other signals 5 ns
Minimum hold time required*
BG~ 5 ns
All other signals 0 ns
Specification
AC load DC load
Measured typical SUT signal loading
Address 4 pF + podlet (1) podlet
Data 6 pF + podlet (1) podlet
TIP~ 9 pF + (2) podlets (2) podlets
CDIS~, TBI~, TM2, TLN0–1, A VEC 7 pF + podlet (1) podlet
3–2
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
Specifications
T able 3–2: Electrical specification (cont.)
Characteristics Requirements
BCLK, BG~ 11 pF + podlet 20R6–5 + (1) podlet
RSTI~ 11 pF + podlet (1) podlet
Other signals 5 pF + podlet (1) podlet
* Signal setup and hold times are in relation to the rising edge of BCLK.
Table 3–3 shows the environmental specifications.
T able 3–3: Environmental specification
Characteristic Description
Temperature
Maximum operating +50°C (+122°F)*
Minimum operating 0°C (+32°F)
Non-operating –55°C to + 75°C (–67°F to +167°F)
Humidity
Altitude
Operating 4.5 km (15,000 ft) maximum
Non-operating 15 km (50,000 ft) maximum
Electrostatic immunity The probe adapter is static sensitive
* Not to exceed 68040 thermal considerations. Forced air cooling may be required
across the CPU.
[
Designed to meet Tektronix standard 062-2847-00 class 5.
10% to 95% relative humidity[
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
3–3
Specifications
71 mm
(2.80 in)
14 mm
(.550 in)
24 mm (.975 in)
43 mm
(1.70 in)
7 mm (.26 in)
Pin A1
99 mm (3.90 in)
Figure 3–1: Minimum clearance of the PGA probe adapter
Table 3–4 shows the certifications and compliances that apply to the probe
adapter.
T able 3–4: Certifications and compliances
EC Compliance There are no current European Directives that apply to this product.
Pollution Degree 2 Do not operate in environments where conductive pollutants might be present.
3–4
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
Specifications
Channel Assignments
Channel assignments shown in Table 3–5 through Table 3–11 use the following
conventions:
H All signals are required by the support unless indicated otherwise.
H Channels are shown starting with the Most Significant Bit (MSB) descending
to the Least Significant Bit (LSB).
H Channel group assignments are for all modules unless otherwise noted.
H A tilde (~) following a signal name indicates an active low signal
H An equals sign (=) following a signal name indicates that it is double probed.
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
3–5
Specifications
Table 3–5 shows the probe section and channel assignments for the Address
group, and the microprocessor signal to which each channel connects. By default
this channel group is displayed in hexadecimal.
T able 3–5: Address group channel assignments
Bit
order
31 A3:7 A31
30 A3:6 A30
29 A3:5 A29
28 A3:4 A28
27 A3:3 A27
26 A3:2 A26
25 A3:1 A25
24 A3:0 A24
23 A2:7 A23
22 A2:6 A22
21 A2:5 A21
20 A2:4 A20
19 A2:3 A19
18 A2:2 A18
17 A2:1 A17
16 A2:0 A16
15 A1:7 A15
14 A1:6 A14
13 A1:5 A13
12 A1:4 A12
11 A1:3 A11
10 A1:2 A10
9 A1:1 A9
8 A1:0 A8
7 A0:7 A7
6 A0:6 A6
5 A0:5 A5
4 A0:4 A4
3 A0:3 A3
2 A0:2 A2
1 A0:1 A1
0 A0:0 A0
Section:channel 68040 signal name
3–6
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
Specifications
Table 3–6 shows the probe section and channel assignments for the Data group,
and the microprocessor signal to which each channel connects. By default this
channel group is displayed in hexadecimal.
T able 3–6: Data group channel assignments
Bit
order
31 D3:7 D31
30 D3:6 D30
29 D3:5 D29
28 D3:4 D28
27 D3:3 D27
26 D3:2 D26
25 D3:1 D25
24 D3:0 D24
23 D2:7 D23
22 D2:6 D22
21 D2:5 D21
20 D2:4 D20
19 D2:3 D19
18 D2:2 D18
17 D2:1 D17
16 D2:0 D16
15 D1:7 D15
14 D1:6 D14
13 D1:5 D13
12 D1:4 D12
11 D1:3 D11
10 D1:2 D10
9 D1:1 D9
8 D1:0 D8
7 D0:7 D7
6 D0:6 D6
5 D0:5 D5
4 D0:4 D4
3 D0:3 D3
2 D0:2 D2
1 D0:1 D1
0 D0:0 D0
Section:channel 68040 signal name
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
3–7
Specifications
Table 3–7 shows the probe section and channel assignments for the Control
group, and the microprocessor signal to which each channel connects. By default
this channel group is displayed symbolically.
T able 3–7: Control group channel assignments
Section:
Bit order
13 C3:7 BG_L~
12 C3:6 TT1
11 C3:2 TT0
10 C3:4 TM2
9 C2:3* TM1
8 C2:4 TM0
7 C2:5 LOCK~
6 C2:0* TS~
5 C2:1* TA~
4 C2:6 R/W~
3 C3:5 MI~
2 C2:2* TEA~
1 C3:0 SIZ1
0 C3:3 SIZ0
* Denotes a qualifier channel.
channel
68040 signal name
3–8
Table 3–8 shows the section and channel assignments for the Interrupt group, and
the microprocessor signal to which each channel connects for both the probe
adapters. By default this channel group is displayed in binary.
T able 3–8: Interrupt group channel assignments
Section:
Bit Order
4 C1:5 AVEC~
3 C0:2 IPEND~
2 C1:6 IPL2~
1 C1:2 IPL1~
0 C0:6 IPL0~
channel
68040 signal name
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
Specifications
Table 3–9 shows the section and channel assignments for the Cache group, and
the microprocessor signal to which each channel connects for the probe adapter.
By default this channel group is displayed symbolically.
T able 3–9: Cache group channel assignments
Section:
Bit order
5 C1:7 TLN1
4 C1:3 TLN0
3 C1:4 SC1
2 C1:0 SC0
1 C3:1 TCI~
0 C0:1 CDIS~
Channel
68040 signal name
Table 3–10 shows the section and channel assignments for the Misc group, and
the microprocessor signal to which each channel connects for the probe adapter.
By default this channel group is not visible
T able 3–10: Misc group channel assignments
Section:
Bit Order
6 C2:7 BCLK_B
5 C0:5 RSTI~
4 C0:4 UPA1
3 C0:0 UPA0
2 C0:7 TIP~
1 C1:1 TBI~
0 C0:3 MDIS~
channel
68040 signal name
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
3–9
Specifications
Table 3–11 shows the section and channel assignments for the clock probes (not
part of any group) and the microprocessor signal to which each channel connects.
T able 3–11: Clock channel assignments
Section:
channel
CK:0 TIP~
CK:1 BG~
CK:2 not connected
CK:3 BCLK
68040 Signal Name
The channels in Table 3–11 are used only to clock in data. These channels are not
acquired or displayed. To acquire data from any of the signals shown in Table
3–11, you must connect another channel probe to the signal. This technique is
called double probing. An equals sign (=) following a signal name indicates that
it is already double probed.
How Data is Acquired
Custom Clocking
This part of this chapter explains how the module acquires 68040 signals using
the TMS 204 software and probe adapter. This part also provides additional
information on microprocessor signals accessible on or not accessible on the
probe adapter, and on extra acquisition channels available for you to use for
additional connections.
A special clocking program is loaded to the module every time you load the
68040 support. This special clocking is called Custom.
With custom clocking, the module logs in signals from multiple groups of
channels at different times when they are valid on the 68040 bus. The module
then sends all the logged-in signals to the trigger machine and to the acquisition
memory of the module for storage.
In custom clocking, the module Clocking State Machine (CSM) generates one
master sample for each 68040 bus cycle, no matter how many clock cycles are
contained in the bus cycle.
3–10
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
Specifications
Figure 3–2 shows the sample points and the master sample point for 68040 bus
timing.
Block
Address
Data
Out
(Read)
Data Out
(Write)
T1 T2
BG
Sample point 1
A0–A31
TM0–TM1
TS~
IPL0~–IPL2~
IPEND~
UPA0,UPA1
SC0,SC1
BG_L~
CDIS~
MDIS~
RST1~
Master sample point[
Sample Point 2
D0–D31
TCI~
TA~
TT0~,TT1~
R/W
TEA
SIZ0,SIZ1
TB1~
M1~
TIP~
AVEC~
LOCK~
BCLK OR
BCLK_B
[Channels not set up in a channel group by the TMS 204 software are logged with the Master sample.
Figure 3–2: 68040 bus timing
Clocking Options
The clocking algorithm for the 68040 support has several variations: Alternate
Bus Master Cycles Excluded, and Alternate Bus Master Cycles Included.
The 68040A software provides four modes for acquiring data. You can select the
clocking modes by selecting the appropriate fields in the Clock menu.
68040 Address/Data Bus Mode. The 68040 has a multiplexed bus mode that
supports the generation of a multiplexed address/data bus. When used in this
mode, the address and data bus can be hard-wired together to form a single 32-bit
address/data bus at the microprocessor (CPU) with address and data information
time–multiplexed on the bus.
You select the 68040 address/data bus mode by selecting Multiplexed in the field.
The default selection is Non-Multiplexed.
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
3–11
Specifications
NOTE. If you select the Multiplexed mode, you should remove the channels
connected to the data signals to reduce loading.
Alternate Bus Master Cycles Included. An alternate Bus Master Cycle is defined as
the 68040 giving up the bus to an alternate device (a DMA device or another
microprocessor). These types of cycles are acquired when you select Included.
Alternate Bus Master Cycles Excluded. Alternate Bus Master Cycles are not
acquired.
Alternate Microprocessor Connections
You can connect to microprocessor signals that are not required by the support so
you can do more advanced timing analysis. These signals might or might not be
accessible on the probe adapter board. The following paragraphs and tables list
signals that are or are not accessible on the probe adapter board.
Signals On the Probe
Adapter
For a list of signals required or not required for disassembly, refer to the channel
assignment tables beginning on page 3–5.
The probe adapter board contains pins for microprocessor signals that are not
acquired by the TMS 204 support. You can connect extra channels to these pins,
because they can be useful for general purpose analysis.
These channels are not defined in any channel group and data acquired from
them is not displayed. To display data, you will need to define a channel group.
Table 3–12 shows the microprocessor signals available on J670 of the probe
adapter.
T able 3–12: 68040 signals on J670
Pin number Signal name Pin number Signal name
1 GND 10 DLE
2 CIOUT 11 BG~
3 TDO 12 PST1
4 TDI 13 PST2
5 TRST~ 14 PST0
6 RSTO~ 15 PST3
7 TCK 16 BB~
3–12
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
T able 3–12: 68040 signals on J670 (cont.)
Pin number Signal namePin numberSignal name
8 TMS 17 BR~
9 PCLK 18 LOCKE~
Specifications
Extra Channels
Table 3–13 lists extra sections and channels that are left after you have connected
all the probes used by the support. You can use these extra channels to make
alternate SUT connections.
T able 3–13: Extra module sections and channels
Module Section: channels
102-channels None
136-channels E3:7-0, E2:7-0, E1:7-0, E0:7-0
96-channels None
These channels are not defined in any channel group and data acquired from
them is not displayed. To display data, you will need to define a channel group.
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
3–13
Specifications
3–14
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
WARNING
The following servicing instructions are for use only by qualified personnel. To
avoid injury, do not perform any servicing other than that stated in the operating
instructions unless you are qualified to do so. Refer to all Safety Summaries
before performing any service.
Maintenance
Maintenance
This section contains information on the following topics:
H Probe adapter circuit description
H Replacing signal leads
H Replacing protective sockets
Probe Adapter Circuit Description
The TMS 204 probe adapter accommodates the Motorola 68040, 68EC040, or
68LC040 microprocessor in a 179-pin PGA package. The probe adapter contains
one PAL that latches BG~ (a hardware pipeline) and reduces the load on the
clock by buffering BCLK.
Replacing Signal Leads
Information on basic operations describes how to replace signal leads (individual
channel and clock probes).
Replacing Protective Sockets
Information on basic operations describes how to replace protective sockets.
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
4–1
Maintenance
4–2
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
Replaceable Electrical Parts
Replaceable Electrical Parts
This chapter contains a list of the replaceable electrical components for the
TMS 204 68040 microprocessor support. Use this list to identify and order
replacement parts.
Parts Ordering Information
Replacement parts are available through your local Tektronix field office or
representative.
Changes to Tektronix products are sometimes made to accommodate improved
components as they become available and to give you the benefit of the latest
improvements. Therefore, when ordering parts, it is important to include the
following information in your order:
H Part number
H Instrument type or model number
H Instrument serial number
H Instrument modification number, if applicable
If you order a part that has been replaced with a different or improved part, your
local Tektronix field office or representative will contact you concerning any
change in part number.
Change information, if any, is located at the rear of this manual.
Using the Replaceable Electrical Parts List
The tabular information in the Replaceable Electrical Parts List is arranged for
quick retrieval. Understanding the structure and features of the list will help you
find all of the information you need for ordering replacement parts. The
following table describes each column of the electrical parts list.
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
5–1
Replaceable Electrical Parts
Parts list column descriptions
Column Column name Description
1 Component number The component number appears on diagrams and circuit board illustrations, located in the diagrams
section. Assembly numbers are clearly marked on each diagram and circuit board illustration in the
Diagrams section, and on the mechanical exploded views in the Replaceable Mechanical Parts list
section. The component number is obtained by adding the assembly number prefix to the circuit
number (see Component Number illustration following this table).
The electrical parts list is arranged by assemblies in numerical sequence (A1, with its subassemblies
and parts, precedes A2, with its subassemblies and parts).
Chassis-mounted parts have no assembly number prefix, and they are located at the end of the
electrical parts list.
2 Tektronix part number Use this part number when ordering replacement parts from Tektronix.
3 and 4 Serial number Column three indicates the serial number at which the part was first effective. Column four indicates
the serial number at which the part was discontinued. No entry indicates the part is good for all serial
numbers.
5 Name & description An item name is separated from the description by a colon (:). Because of space limitations, an item
name may sometimes appear as incomplete. Use the U.S. Federal Catalog handbook H6-1 for
further item name identification.
6 Mfr. code This indicates the code number of the actual manufacturer of the part.
7 Mfr. part number This indicates the actual manufacturer’s or vendor’s part number.
Abbreviations
Component Number
List of Assemblies
Chassis Parts
Mfr. Code to Manufacturer
Cross Index
Abbreviations conform to American National Standard ANSI Y1.1–1972.
Component number
A23A2R1234 A23 R1234
Assembly number Circuit number
Read: Resistor 1234 (of Subassembly 2) of Assembly 23
A2
Subassembly number
(optional)
A list of assemblies is located at the beginning of the electrical parts list. The
assemblies are listed in numerical order. When a part’s complete component
number is known, this list will identify the assembly in which the part is located.
Chassis-mounted parts and cable assemblies are located at the end of the
Replaceable Electrical Parts List.
The table titled Manufacturers Cross Index shows codes, names, and addresses of
manufacturers or vendors of components listed in the parts list.
5–2
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
Replaceable Electrical Parts
Manufacturers cross index
Mfr.
code
TK1462 YAMAICHI ELECTRONICS CO L TD
TK2058 TDK CORPORATION OF AMERICA 1600 FEEHANVILLE DRIVE MOUNT PROSPECT, IL 60056
09969 DALE ELECTRONICS INC EAST HIGHWAY 50
01295 TEXAS INSTRUMENTS INC
22526 BERG ELECTRONICS INC (DUPONT) 857 OLD TRAIL RD ETTERS PA 17319
26742 METHODE ELECTRONICS INC 7447 W WILSON AVE CHICAGO IL 60656–4548
50139 ALLEN–BRADLEY CO
53387 3M COMPANY
58050 TEKA PRODUCTS INC 45 SALEM ST PROVIDENCE RI 02907
63058 MCKENZIE TECHNOLOGY 910 PAGE AVENUE FREMONT CA 94538
80009 TEKTRONIX INC 14150 SW KARL BRAUN DR
Manufacturer Address City , state, zip code
2ND FLOOR NEW KYOEI
BLDG 17–11
SEMICONDUCTOR GROUP
ELECTRONIC COMPONENTS
ELECTRONIC PRODUCTS DIV
3–CHROME SHIBAURA
MINATO–KU
P O BOX 180
13500 N CENTRAL EXPY
PO BOX 655303
1414 ALLEN BRADLEY DR EL PASO TX 79936
3M AUSTIN CENTER AUSTIN TX 78769–2963
PO BOX 500
TOKYO JAPAN
YANKTON SD 57078
DALLAS TX 75262–5303
BEAVERT ON OR 97077–0001
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
5–3
Replaceable Electrical Parts
Replaceable electrical parts list
Component
number
A1 671–2551–00 CIRCUIT BD ASSY:68040/68EC040 PROBE ADAPTER,
A1C280 283–5004–00 CAP,FXD,CERAMIC:MLC;0.1UF,10%,25V,X7R,1206 TK2058 C3216X7R1E104K–
A1C340 283–5004–00 CAP,FXD,CERAMIC:MLC;0.1UF,10%,25V,X7R,1206 TK2058 C3216X7R1E104K–
A1C480 283–5004–00 CAP,FXD,CERAMIC:MLC;0.1UF,10%,25V,X7R,1206 TK2058 C3216X7R1E104K–
A1C530 283–5004–00 CAP,FXD,CERAMIC:MLC;0.1UF,10%,25V,X7R,1206 TK2058 C3216X7R1E104K–
A1C550 283–5004–00 CAP,FXD,CERAMIC:MLC;0.1UF,10%,25V,X7R,1206 TK2058 C3216X7R1E104K–
A1C740 283–5004–00 CAP,FXD,CERAMIC:MLC;0.1UF,10%,25V,X7R,1206 TK2058 C3216X7R1E104K–
A1C810 283–5004–00 CAP,FXD,CERAMIC:MLC;0.1UF,10%,25V,X7R,1206 TK2058 C3216X7R1E104K–
A1C880 283–5004–00 CAP,FXD,CERAMIC:MLC;0.1UF,10%,25V,X7R,1206 TK2058 C3216X7R1E104K–
A1J170 ––––––––––– CONN,HDR:PCB,;MALE,STR,2 X 40,0.1 CTR,0.235 53387 2480–6122–TB
A1J200 ––––––––––– CONN,HDR:PCB,;MALE,STR,2 X 40,0.1 CTR,0.235 53387 2480–6122–TB
A1J210 ––––––––––– CONN,HDR:PCB,;MALE,STR,2 X 40,0.1 CTR,0.235 53387 2480–6122–TB
A1J670 ––––––––––– CONN,HDR:PCB,;MALE,STR,1 X 36,0.1 CTR,0.230
A1J880 ––––––––––– CONN,HDR:PCB,;MALE,STR,2 X 40,0.1 CTR,0.235 53387 2480–6122–TB
A1J910 ––––––––––– CONN,HDR:PCB,;MALE,STR,2 X 40,0.1 CTR,0.235 53387 2480–6122–TB
A1J990 ––––––––––– CONN,HDR:PCB,;MALE,STR,2 X 40,0.1 CTR,0.235 53387 2480–6122–TB
A1P990 ––––––––––– CONN,SHUNT :SHUNT/SHORTING,;FEMALE,1 X 2,0.1
A1R980 321–5012–00 RES,FXD:THICK FILM;332 OHM,1%,0.125W,TC=100 50139 BCK3320FT
Tektronix
part number
Serial no.
effective
Serial no.
discont’d
Name & description
PGA179,SOCKETED;
Mfr.
code
80009 671255100
Mfr. part number
A1U380 160–8830–00 IC,DIGITAL:STTL,PLD;PAL,20R6,125MHZ,210MA,P
A1U540 ––––––––––– SOCKET,PCB:PCB,;179 POS,18 X 18,0.1 CTR,0.173 H X 0.183
5–4
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
RGM 156–6381–00
TAIL,GOLD/GOLD,PHOS BRZ,ACCOM0.015/0.026,PCB 0.024, P AT
1836
80009 160–8830–00
63058 PGA179H101B1–18
Replaceable Mechanical Parts
Replaceable Mechanical Parts
This chapter contains a list of the replaceable mechanical components for the
TMS 204 68040 microprocessor support. Use this list to identify and order
replacement parts.
Parts Ordering Information
Replacement parts are available through your local Tektronix field office or
representative.
Changes to Tektronix products are sometimes made to accommodate improved
components as they become available and to give you the benefit of the latest
improvements. Therefore, when ordering parts, it is important to include the
following information in your order:
H Part number
H Instrument type or model number
H Instrument serial number
H Instrument modification number, if applicable
If you order a part that has been replaced with a different or improved part, your
local Tektronix field office or representative will contact you concerning any
change in part number.
Change information, if any, is located at the rear of this manual.
Using the Replaceable Mechanical Parts List
The tabular information in the Replaceable Mechanical Parts List is arranged for
quick retrieval. Understanding the structure and features of the list will help you
find all of the information you need for ordering replacement parts. The
following table describes the content of each column in the parts list.
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
6–1
Replaceable Mechanical Parts
Parts list column descriptions
Column Column name Description
1 Figure & index number Items in this section are referenced by figure and index numbers to the exploded view illustrations
that follow.
2 Tektronix part number Use this part number when ordering replacement parts from Tektronix.
3 and 4 Serial number Column three indicates the serial number at which the part was first effective. Column four
indicates the serial number at which the part was discontinued. No entries indicates the part is
good for all serial numbers.
5 Qty This indicates the quantity of parts used.
6 Name & description An item name is separated from the description by a colon (:). Because of space limitations, an
item name may sometimes appear as incomplete. Use the U.S. Federal Catalog handbook H6-1
for further item name identification.
7 Mfr. code This indicates the code of the actual manufacturer of the part.
8 Mfr. part number This indicates the actual manufacturer’s or vendor’s part number.
Abbreviations
Chassis Parts
Abbreviations conform to American National Standard ANSI Y1.1–1972.
Chassis-mounted parts and cable assemblies are located at the end of the
Replaceable Electrical Parts List.
Mfr. Code to Manufacturer
Cross Index
The table titled Manufacturers Cross Index shows codes, names, and addresses of
manufacturers or vendors of components listed in the parts list.
Manufacturers cross index
Mfr.
code
TK2548 XEROX BUSINESS SERVICES
26742 METHODE ELECTRONICS INC 7447 W WILSON AVE CHICAGO IL 60656–4548
53387 3M COMPANY
58050 TEKA PRODUCTS INC 45 SALEM ST PROVIDENCE RI 02907
63058 MCKENZIE TECHNOLOGY 910 PAGE AVENUE FREMONT CA 94538
80009 TEKTRONIX INC 14150 SW KARL BRAUN DR
Manufacturer Address City , state, zip code
14181 SW MILLIKAN WA Y BEAVERTON OR 97077
DIV OF XEROX CORPORATION
3M AUSTIN CENTER AUSTIN TX 78769–2963
ELECTRONIC PRODUCTS DIV
BEAVERT ON OR 97077–0001
PO BOX 500
6–2
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
Replaceable Mechanical Parts
Replaceable mechanical parts list
Fig. &
index
number
1–0 010–0551–00 1 PROBE,ADAPTER:68040 & 68EC040,PGA179,PROBE
–1 671–2551–00 1 CIRCUIT BD ASSY:68040/68EC040 PROBE ADAPTER,
–2 131–5267–00 2 CONN,HDR:PCB,;MALE,STR,2 X 40,0.1 CTR,0.235 MLG X
–3 131–1857–00 1 CONN,HDR:PCB,;MALE,STR,1 X 36,0.1 CTR,0.230 MLG X
–4 136–1136–00 2 SOCKET,PCB:PCB,;179 POS,18 X 18,0.1 CTR,0.173 H X 0.183
Tektronix part
number
Serial no.
effective
Serial no.
discont’d
Qty Name & description
ADAPTER,LASI III;
PGA179,SOCKETED;
0.110 TAIL,30GOLD
(J170,J200,J210,880,J910,J990)
0.100 TAIL,GOLD
(J670)
TAIL,GOLD/GOLD,PHOS BRZ,ACCOM 0.015/0.026,PCB
0.024,PAT 1836
(U540)
Mfr.
code
80009 010055100
80009 671255100
53387 2480–6122–TB
58050 082–3644–SS10
63058 PGA179H101B1–18
Mfr. part number
–5 131–4356–00 1 CONN,SHUNT:SHUNT/SHOR TING,;FEMALE,1 X 2,0.1 CTR,
0.63 H,BLK,W/HANDLE,JUMPER
(P990)
STANDARD ACCESSSORIES
070–9822–00 1 MANUAL,TECH:INSTRUCTION,CHIP ,DISSASEMBLER,
TMS 204
070–9803–00 1 MANUAL, TECH:TLA 700 SERIES MICRO SUPPORT
INSTALLATION
OPTIONAL ACCESSORIES
070–9802–00 1 MANUAL, TECH:BASIC OPS MICRO SUP ON DAS/TLA 500
SERIES LOGIC ANALYZERS
26742 9618–302–50
80009 070–9822–00
80009 070–9803–00
80009 070–9802–00
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
6–3
Replaceable Mechanical Parts
5
2
3
Figure 1: 68040 PGA probe adapter exploded view
1
A01
4
6–4
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
Index
Index
A
about this manual set, ix
acquiring data, 2–5
Address group
channel assignments, 3–6
display column, 2–7
Alternate Bus Master cycles, 3–12
alternate connections
extra channel probes, 3–13
to other signals, 3–12
B
basic operations, where to find information, ix
bus cycles, displayed cycle types, 2–6
bus timing, 3–11
C
Cache group, channel assignments, 3–9
cache invalidation, 1–2
certifications, 3–4
channel assignments
Address group, 3–6
Cache group, 3–9
clocks, 3–10
Control group, 3–8
Data group, 3–7
Interrupt group, 3–8
Misc group, 3–9
channel groups, 2–1
clock channel assignments, 3–10
clock rate, 1–2
clocking, Custom, 2–1
how data is acquired, 3–10
clocking options
Address bus mode, 3–11
Alternate Bus Master cycles, 3–12
Data bus mode, 3–11
field names, 2–1
how data is acquired, 3–11
compliances, 3–4
connections
no probe adapter, 1–7
channel probes, 1–8
clock probes, 1–10
other microprocessor signals, 3–12
probe adapter to SUT, PGA, 1–4
Control Flow display format, 2–8
Control group
channel assignments, 3–8
symbol table, 2–2
Custom clocking, 2–1
how data is acquired, 3–10
cycle types, 2–6
D
data
acquiring, 2–5
disassembly formats
Control Flow, 2–8
Hardware, 2–6
Software, 2–8
Subroutine, 2–9
how it is acquired, 3–10
data display , changing, 2–10
Data group
channel assignments, 3–7
display column, 2–8
demonstration file, 2–13
disassembled data
cycle type definitions, 2–6
viewing, 2–5
viewing an example, 2–13
disassembler
logic analyzer configuration, 1–2
setup, 2–1
Disassembly Format Definition overlay, 2–10
Disassembly property page, 2–10
display formats
Control Flow, 2–8
Hardware, 2–6
Software, 2–8
special characters, 2–5
Subroutine, 2–9
dynamic bus sizing, 1–2
E
electrical specifications, 3–2
environmental specifications, 3–3
exception vectors, 2–11
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
Index–1
Index
H
Hardware display format, 2–6
cycle type definitions, 2–6
I
installing hardware. See connections
Interrupt group, channel assignments, 3–8
Interrupt Table Address field, 2–10
Interrupt Table Size field, 2–10
L
leads (podlets). See connections
logic analyzer
configuration for disassembler, 1–2
software compatibility, 1–2
M
manual
conventions, ix
how to use the set, ix
Mark Cycle function, 2–10
Mark Opcode function, 2–10
marking cycles, definition of, 2–10
microprocessor
package types supported, 1–1
specific clocking and how data is acquired, 3–10
Misc group, channel assignments, 3–9
Mnemonic display column, 2–8
hardware description, 3–1
jumper positions, 1–3, 3–1
not using one, 1–7
placing the microprocessor in, 1–5
R
reference memory, 2–13
Reset, SUT hardware, 1–2
restrictions, 1–2
without a probe adapter, 1–7
S
service information, 4–1
setups, disassembler, 2–1
signals
alternate connections, 3–12
extra channel probes, 3–13
Software display format, 2–8
special characters displayed, 2–5
specifications, 3–1
certifications, 3–4
channel assignments, 3–5
compliances, 3–4
electrical, 3–2
environmental, 3–3
Subroutine display format, 2–9
support setup, 2–1
SUT, definition, ix
SUT hardware reset, 1–2
symbol table, Control channel group, 2–2
P
probe adapter
alternate connections, 3–12
circuit description, 4–1
clearance, 1–3
adding sockets, 1–6
configuring, 1–3, 3–1
Index–2
T
terminology, ix
Timestamp display column, 2–8
V
viewing disassembled data, 2–5
TMS 204 68040, 68EC040 & 68LC040 Microprocessor Support Instruction Manual
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