Tektronix TMS109A Instruction Manual

Instruction Manual

TMS 109A
Socket 7 Microprocessor Support

071-0497-01

Warning

The servicing instructions are for use by
qualified personnel only. To avoid personal
injury, do not perform any servicing unless you
are qualified to do so. Refer to all safety
summaries prior to performing service.

Copyright E T ektronix, Inc. All rights reserved. Licensed software products are owned by Tektronix or its suppliers and are protected by United States copyright laws and international treaty provisions.

Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the
Rights in T echnical Data and Computer Software clause at DFARS 252.227-7013, or subparagraphs (c)(1) and (2) of the
Commercial Computer Software – Restricted Rights clause at F AR 52.227-19, as applicable.

T ektronix products are covered by U.S. and foreign patents, issued and pending. Information in this publication supercedes
that in all previously published material. Specifications and price change privileges reserved.

Printed in the U.S.A.

T ektronix, Inc., P.O. Box 1000, Wilsonville, OR 97070–1000
TEKTRONIX and TEK are registered trademarks of T ektronix, Inc.

SOFTWARE WARRANTY

T ektronix warrants that the media on which this software product is furnished and the encoding of the programs on
the media will be free from defects in materials and workmanship for a period of three (3) months from the date of
shipment. If a medium or encoding proves defective during the warranty period, T ektronix will provide a
replacement in exchange for the defective medium. Except as to the media on which this software product is
furnished, this software product is provided “as is” without warranty of any kind, either express or implied.
T ektronix does not warrant that the functions contained in this software product will meet Customer’s
requirements or that the operation of the programs will be uninterrupted or error-free.

In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration
of the warranty period. If T ektronix is unable to provide a replacement that is free from defects in materials and
workmanship within a reasonable time thereafter, Customer may terminate the license for this software product
and return this software product and any associated materials for credit or refund.

THIS WARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER WARRANTIES, EXPRESS
OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’
RESPONSIBILITY TO REPLACE DEFECTIVE MEDIA OR REFUND CUSTOMER’S PAYMENT IS
THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS
WARRANTY. TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT,
SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER
TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH
DAMAGES.

HARDWARE WARRANTY

T ektronix warrants that the products that it manufactures and sells will be free from defects in materials and
workmanship for a period of one (1) year from the date of shipment. If a product proves defective during this
warranty period, T ektronix, at its option, either will repair the defective product without charge for parts and labor,
or will provide a replacement in exchange for the defective product.

In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration
of the warranty period and make suitable arrangements for the performance of service. Customer shall be
responsible for packaging and shipping the defective product to the service center designated by T ektronix, with
shipping charges prepaid. Tektronix shall pay for the return of the product to Customer if the shipment is to a
location within the country in which the T ektronix service center is located. Customer shall be responsible for
paying all shipping charges, duties, taxes, and any other charges for products returned to any other locations.

This warranty shall not apply to any defect, failure or damage caused by improper use or improper or inadequate
maintenance and care. T ektronix shall not be obligated to furnish service under this warranty a) to repair damage
resulting from attempts by personnel other than T ektronix representatives to install, repair or service the product;
b) to repair damage resulting from improper use or connection to incompatible equipment; c) to repair any
damage or malfunction caused by the use of non-T ektronix supplies; or d) to service a product that has been
modified or integrated with other products when the effect of such modification or integration increases the time
or difficulty of servicing the product.

THIS WARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER WARRANTIES, EXPRESS
OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’
RESPONSIBILITY TO REPAIR OR REPLACE DEFECTIVE PRODUCTS IS THE SOLE AND
EXCLUSIVE REMEDY PROVIDED TO THE CUST OMER FOR BREACH OF THIS WARRANTY.
TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT , SPECIAL,
INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER TEKTRONIX OR
THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.

Table of Contents

Getting Started

General Safety Summary v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Service Safety Summary vii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Preface ix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Manual Conventions ix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contacting T ektronix x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Support Package Description 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Logic Analyzer Software Compatibility 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Logic Analyzer Configuration 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Requirements and Restrictions 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Functionality Not Supported 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Configuring the Probe Adapter 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MFG_TEST Jumper 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CLK Jumper 1–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Processor Selection Jumper 1–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D/P# Signal Jumper 1–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tracking Jumper 1–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Address Synthesis Jumper 1–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Connecting to a System Under T est 1–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Connect the P6434 Probes to the Probe Adapter 1–6. . . . . . . . . . . . . . . . . . . . .

Remove the Microprocessor 1–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Choose a Protective Socket 1–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Insert Probe Adapter 1–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Insert Microprocessor in the Probe Adapter 1–10. . . . . . . . . . . . . . . . . . . . . . . . .

Alternate Connections 1–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Applying and Removing Power 1–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Channel Assignments 1–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CPU To Mictor Connections 1–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating Basics

Setting Up the Support 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Channel Group Definitions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clocking Options 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Custom Clocking 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ClockingOptions 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Mode Differences 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Component Mode 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chip Set Mode 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Symbols 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Acquiring and Viewing Disassembled Data 2–9. . . . . . . . . . . . . . . . . . . . .

Acquiring Data 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Viewing Disassembled Data 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timing-Waveform Display Format 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Hardware Display Format 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TMS 109A Socket 7 Microprocessor Support

i

Table of Contents

Specifications

Software Display Format 2–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Control Flow Display Format 2–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Subroutine Display Format 2–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Changing How Data is Displayed 2–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Optional Display Selections 2–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Dual Microprocessors Execution Tracing 2–18. . . . . . . . . . . . . . . . . . . . . . . . . . .

Branch Trace Messages 2–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Out-Of-Order Fetches 2–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Speculative Prefetch Cycles 2–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Cache Invalidation Cycles 2–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Burst Cycles 2–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Management Mode (SMM) 2–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MMX Instruction Set 2–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3DNow! 2–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Marking Cycles 2–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Displaying Exception Vectors 2–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Viewing an Example of Disassembled Data 2–28. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Probe Adapter Description 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Specifications 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maintenance

Probe Adapter Circuit Description 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Replacing the Fuse 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Diagrams
Replaceable Electrical Parts

Parts Ordering Information 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Index

ii TMS 109A Socket 7 Microprocessor Support

List of Figures

Table of Contents

Figure 1–1: Jumper locations on the probe adapter 1–5. . . . . . . . . . . . . .

Figure 1–2: Connecting a probe to the probe adapter 1–7. . . . . . . . . . . . .

Figure 1–3: Protective sockets 1–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 1–4: Placing the socket and probe adapter onto the

system under test 1–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 1–5: Inserting a microprocessor into the probe adapter 1–10. . . . .

Figure 1–6: ITP and system reset pin locations on the probe adapter 1–12

Figure 1–7: Power jack location on the probe adapter 1–14. . . . . . . . . . . .

Figure 1–8: Pin assignments for a Mictor connector

(component side) 1–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 2–1: Nonpipelined single and Burst Transfer cycles 2–2. . . . . . . .

Figure 2–2: Pipelined cycles 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 2–3: Hardware display format 2–14. . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 2–4: Data displayed from the Primary and

Dual microprocessors 2–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 2–5: Disassembled data displayed from the Primary

microprocessor only 2–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 2–6: Disassembled data displayed from the Dual

microprocessor only 2–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 2–7: Display of target and source Branch Trace Messages 2–21. . .

Figure 2–8: Software display for the AMD Bus cycles 2–22. . . . . . . . . . . .

Figure 2–9: Hardware display for the AMD Bus cycles 2–23. . . . . . . . . . .

Figure 2–10: Speculative Prefetch cycles 2–24. . . . . . . . . . . . . . . . . . . . . . .

Figure 3–1: Dimensions of the probe adapter 3–4. . . . . . . . . . . . . . . . . . . .

Figure 4–1: Location of the fuse on the probe adapter 4–2. . . . . . . . . . . .

Figure 6–1: TMS 109A Socket 7 probe adapter exploded view 6–5. . . . .

TMS 109A Socket 7 Microprocessor Support

iii

Table of Contents

List of Tables

Table 1–1: Jumper positions and function 1–4. . . . . . . . . . . . . . . . . . . . . .

Table 1–2: ITP (J580) signal Information 1–11. . . . . . . . . . . . . . . . . . . . . .

Table 1–3: J260 jumper pin assignments 1–12. . . . . . . . . . . . . . . . . . . . . . .

Table 1–4: Address channel group assignments 1–14. . . . . . . . . . . . . . . . .

Table 1–5: Data channel group assignments 1–16. . . . . . . . . . . . . . . . . . . .

Table 1–6: Data_Lo channel group assignments 1–17. . . . . . . . . . . . . . . . .

Table 1–7: Control channel group assignments 1–18. . . . . . . . . . . . . . . . . .

Table 1–8: Data Size channel group assignments 1–19. . . . . . . . . . . . . . . .

Table 1–9: Cache channel group assignments 1–19. . . . . . . . . . . . . . . . . . .

Table 1–10: Misc channel group assignments 1–19. . . . . . . . . . . . . . . . . . .

Table 1–11: Clock channel group assignments 1–20. . . . . . . . . . . . . . . . . .

Table 1–12: Signals not required for clocking or disassembly 1–21. . . . . .

Table 1–13: Signals on the probe adapter but not acquired 1–21. . . . . . . .

Table 1–14: Signals not connected to probe adapter 1–21. . . . . . . . . . . . . .

Table 1–15: CPU to Mictor connections for Mictor A pins 1–23. . . . . . . .

Table 1–16: CPU to Mictor connections for Mictor D pins 1–24. . . . . . . .

Table 1–17: CPU to Mictor connections for Mictor E pins 1–25. . . . . . . .

Table 1–18: CPU to Mictor connections for Mictor C pins 1–27. . . . . . . .

Table 2–1: Control group symbol table definitions 2–5. . . . . . . . . . . . . . .

Table 2–2: Meaning of special characters in the display 2–10. . . . . . . . . .

Table 2–3: Cycle type definitions 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 2–4: Trace Processor and Other Processor field selections 2–19. . .

Table 2–5: Exception vectors for Real Addressing mode 2–26. . . . . . . . . .

Table 2–6: Exception vectors for Protected Addressing mode 2–27. . . . . .

Table 3–1: Electrical specifications 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3–2: Environmental specifications 3–3. . . . . . . . . . . . . . . . . . . . . . . .

Table 4–1: Socket 7 signal delays using the probe adapter 4–2. . . . . . . .

iv TMS 109A Socket 7 Microprocessor Support

General Safety Summary

Review the following safety precautions to avoid injury and prevent damage to
this product or any products connected to it. To avoid potential hazards, use this
product only as specified.

Only qualified personnel should perform service procedures.

While using this product, you may need to access other parts of the system. Read
the General Safety Summary in other system manuals for warnings and cautions
related to operating the system.

To Avoid Fire or Personal Injury

Use Proper Power Cord. Use only the power cord specified for this product and

certified for the country of use.
Connect and Disconnect Properly . Do not connect or disconnect probes or test

leads while they are connected to a voltage source.
Connect and Disconnect Properly . Connect the probe output to the measurement

instrument before connecting the probe to the circuit under test. Disconnect the
probe input and the probe ground from the circuit under test before disconnecting
the probe from the measurement instrument.

Ground the Product. This product is indirectly grounded through the grounding
conductor of the mainframe power cord. To avoid electric shock, the grounding
conductor must be connected to earth ground. Before making connections to the
input or output terminals of the product, ensure that the product is properly
grounded.

Observe All Terminal Ratings. To avoid fire or shock hazard, observe all ratings
and markings on the product. Consult the product manual for further ratings
information before making connections to the product.

Do not apply a potential to any terminal, including the common terminal, that
exceeds the maximum rating of that terminal.

Use Proper AC Adapter. Use only the AC adapter specified for this product.
Do Not Operate Without Covers. Do not operate this product with covers or panels

removed.

Use Proper Fuse. Use only the fuse type and rating specified for this product.
Avoid Exposed Circuitry. Do not touch exposed connections and components

when power is present.
Do Not Operate With Suspected Failures. If you suspect there is damage to this

product, have it inspected by qualified service personnel.

Do Not Operate in Wet/Damp Conditions.

TMS 109A Socket 7 Microprocessor Support

v

General Safety Summary

Do Not Operate in an Explosive Atmosphere.
Keep Product Surfaces Clean and Dry .
Provide Proper Ventilation. Refer to the manual’s installation instructions for

details on installing the product so it has proper ventilation.

Symbols and Terms

T erms in this Manual. These terms may appear in this manual:

WARNING. Warning statements identify conditions or practices that could result
in injury or loss of life.

CAUTION. Caution statements identify conditions or practices that could result in
damage to this product or other property.

T erms on the Product. These terms may appear on the product:
DANGER indicates an injury hazard immediately accessible as you read the

marking.
WARNING indicates an injury hazard not immediately accessible as you read the

marking.
CAUTION indicates a hazard to property including the product.
Symbols on the Product. The following symbols may appear on the product:

CAUTION

Refer to Manual

WARNING

High Voltage

Double

Insulated

Protective Ground

(Earth) Terminal

vi TMS 109A Socket 7 Microprocessor Support

Service Safety Summary

Only qualified personnel should perform service procedures. Read this Service
Safety Summary and the General Safety Summary before performing any service

procedures.
Do Not Service Alone. Do not perform internal service or adjustments of this

product unless another person capable of rendering first aid and resuscitation is
present.

Disconnect Power. To avoid electric shock, switch off the instrument power, then
disconnect the power cord from the mains power.

Use Care When Servicing With Power On. Dangerous voltages or currents may
exist in this product. Disconnect power, remove battery (if applicable), and
disconnect test leads before removing protective panels, soldering, or replacing
components.

To avoid electric shock, do not touch exposed connections.

TMS 109A Socket 7 Microprocessor Support

vii

Service Safety Summary

viii TMS 109A Socket 7 Microprocessor Support

Preface

This instruction manual contains specific information about the TMS 109A Sock­et 7 microprocessor support package and is part of a set of information on how to
operate this product on compatible Tektronix logic analyzers.

If you are familiar with operating microprocessor support packages on the logic
analyzer for which the TMS 109A Socket 7 support was purchased, you will only
need this instruction manual to set up and run the support.

If you are not familiar with operating microprocessor support packages, you will
need to supplement this instruction manual with information on basic operations
to set up and run the support.

NOTE. The disassembly software is optimized to decode instruction streams and
bus activities from Intel microprocessors and AMD-K6-2 therefore, the disassem­bler may not support unique characteristics of other manufacturers. However,
you can reliably conduct timing analysis of nonIntel Socket 7 processors. Consult
your Tektronix field office for future enhancements.

Manual Conventions

This manual uses the following conventions:
H The term “disassembler” refers to the software that decodes bus cycles into

instruction mnemonics and cycle types.

H A pound sign (#) following a signal name indicates an active low signal.
H The phrase “information on basic operations” refers to your online help.

TMS 109A Socket 7 Microprocessor Support

ix

Preface

Contacting Tektronix

Product
Support

Service
Support

For other
information

To write us

Website

For questions about using Tektronix measurement products, call
toll free in North America:
1-800-TEK-WIDE (1-800-835-9433 ext. 2400)
6:00 a.m. – 5:00 p.m. Pacific time

Or contact us by e-mail:
[e-mail]

For product support outside of North America, contact your
local Tektronix distributor or sales office.

Tektronix offers extended warranty and calibration programs as
options on many products. Contact your local Tektronix
distributor or sales office.

For a listing of worldwide service centers, visit our web site.
In North America:

1-800-TEK-WIDE (1-800-835-9433)
An operator will direct your call.

Tektronix, Inc.
P.O. Box 1000
Wilsonville, OR 97070-1000
USA

Tektronix.com

x

TMS 109A Socket 7 Microprocessor Support

Getting Started

Getting Started

This chapter contains information on the TMS 109A Socket 7 microprocessor
support package:

H How to configure the probe adapter
H How to connect to the system under test
H How to apply power to and remove power from the probe adapter

Support Package Description

The TMS 109A Socket 7 microprocessor support package disassembles data
from systems that are based on the Intel Pentium, low-power embedded Pentium
with MMX technology, AMD-K6-2 and Socket 7 microprocessor devices. The
support runs on a compatible Tektronix logic analyzer equipped with a 136-chan­nel module.

A complete list of standard and optional accessories is provided at the end of the
parts list in the Replaceable Parts List chapter.

To use this support efficiently, you must have the items listed in the information
on basic operations (in the online help) and the following items:

H Pentium Processors Family Developer’s Manual, Intel 1997(p/n to be

updated)

H AMD-K6-2 Processor, Data Sheet, AMD, 1999
Information on basic operations is also in your online help.

Logic Analyzer Software Compatibility

The label on the microprocessor support floppy disk states which version of logic
analyzer software the support is compatible with.

Logic Analyzer Configuration

To use the TMS 109A Socket 7 support package, the Tektronix logic analyzer
must be equipped with a 136-channel module at a minimum.

TMS 109A Socket 7 Microprocessor Support

1–1

Getting Started

Refer to information on basic operations to determine how many modules and
probes your logic analyzer needs to meet the minimum channel requirements for
the TMS 109A Socket 7 microprocessor support.

Requirements and Restrictions

You should review the general requirements and restrictions of microprocessor
supports in the information on basic operations as they pertain to your system
under test.

You should also review electrical, environmental, and mechanical specifications
in the Specifications chapter in this manual as they pertain to your system under
test, as well as the following descriptions of other Socket 7 support requirements
and restrictions.

System Clock Rate. The TMS 109A Socket 7 support can acquire data from the
Socket 7 microprocessors at bus speeds of up to 100 MHz; the tested clock speed
is 100 MHz. This specification is valid at the time this manual was printed.
Contact your Tektronix sales representative for current information on the fastest
devices supported.

System Under Test Power. Whenever the system under test is powered off, be sure
to remove power from the probe adapter. Refer to Applying and Removing Power
on page 1–13 for information on how to remove power from the probe adapter.

Disabling the Instruction Cache. To disassemble acquired data, you must disable
the internal instruction cache. Disabling the cache makes all instruction
prefetches visible on the bus so they can be acquired and disassembled.

Cache Invalidation Cycles. Cache Invalidation addresses are not acquired.

Bus Hold Cycles. Bus Hold cycles are not acquired while the RESET signal is

active.

AHOLD Signal. If the AHOLD signal is active (high) during a Writeback cycle (a
four cycle Burst Write), the acquired address is undefined.

Burst Cycles. The Socket 7 microprocessor expects the memory system to
increment addresses during a Burst cycle. When viewing disassembled data, the
disassembler synthesizes the addresses. When viewing state data, the addresses
appear to be identical.

1–2

TMS 109A Socket 7 Microprocessor Support

Getting Started

Probe Mode Cycles. Probe Mode cycles are not identified.

Directory T able and Descriptor Table Reads and Writes. These reads and writes are

not disassembled.

Bus Anomalies. Some combinations of instructions and operating modes of the
microprocessor can cause additional cycles to be fetched. This behavior is
unpredictable, not documented, and can cause the disassembler to operate
incorrectly with fetched cycles. This is most likely to occur during Floating Point
operations.

AMD-K6-2 processor has a out-of-order fetch mechanism. For fetches, AMD
always loads 32 bytes, starting from the most significant octabyte (octet) in the
block. For example these addresses 00, 08, 10, and18 would be fetched in this
order 18, 10, 08, and 00. Regardless of what the critical word is or if the cache is
enabled. For the disassembler to work properly it needs these 32 byte fetch
blocks or the disassembly will be incorrect.

Nonintrusive Acquisition. The Socket 7 microprocessor support will not intercept,
modify, or present signals back to the system under test.

Functionality Not Supported

Reads/Writes. The TMS 109A Socket 7 support package does not interpret

directory or descriptor tables for reads/writes. When long jumps and calls are
executed you may need to supply a code-segment size (see page 2–18), and the
first opcode byte using the Mark Opcode function (see page 2–25).

TMS 109A Socket 7 Microprocessor Support

1–3

Getting Started

Configuring the Probe Adapter

There are five jumpers on the probe adapter. Table 1–1 lists the jumper positions
and functions.

T able 1–1: Jumper positions and function

Probe adapter Position Function

J240
MFG_TEST

J250
CLK

J900
Proc Sel

J910
D/P#

J920
Tracking

J921
SYNTH

1–2

OPEN
1–2

2–3
1–2

2–3
1–2

OPEN

1–2
2–3

1–2
2–3

When the processor extends the clock speed to below 40 MHz, the jumpered pins 1-2
turn the phased lock loop into a buffer that disables the phased lock loop signal.

Default, phased look loop signal enabled
Extends the Socket 7 microprocessor system speed between 40–150 MHz

Extends the Socket 7 microprocessor system speed between 20–75 MHz
Supports microprocessors that do not have the D/P# pin.

Supports microprocessors that have the D/P# pin.
Acquires the D/P# signal from pin AE35 of the socket being probed.

Acquires the D/P# signal from an external source. If this jumper is left open, you must
route the D/P# signal to pin 1 of this jumper from an external source. This allows you to
probe your system from the Dual socket as long as the D/P# signal is accessible on the
system board. Ensure that the jumper J900 is in position 2–3 before routing the D/P#
signal to pin 1 of J910.

Enables tracking of burst and pipelined cycles while BOFF# and HLDA are asserted
Disables tracking of burst and pipelined cycles while BOFF# and HLDA are asserted.

This setting can be used if an external master’s signal timing is different from that of the
P54C.

Enable Address Synthesis (A(2:0) are derived from BE(7:0)#)
Disable Address Synthesis (A(2:0)=0)

1–4

MFG_TEST Jumper

To acquire data at frequencies below 40 MHz on the probe adapter, short the two
pins on J240. This disables the phased lock loop signal to all clocked compo­nents. Figure 1–1 shows the location of J240 on the probe adapter.

TMS 109A Socket 7 Microprocessor Support

Getting Started

CLK Jumper

The CLK jumper (J250 on the probe adapter) should be placed in the 40–150
MHz position to acquire data from a system running at or faster than 45 MHz.
The jumper should be placed in the 20–75 MHz position to acquire data from a
system running slower than 45 MHz. Figure 1–1 shows the location of J250 on
the probe adapter.

J240

MFG_TEST

J250

CLK

Processor Selection

Jumper

D/P# Signal Jumper

J900

Proc Sel

J910
D/P#

J920

Tracking

J921

SYNTH

Figure 1–1: Jumper locations on the probe adapter

Place the Processor Selection jumper, J900, in the 1–2 position to support
microprocessors that do not have the D/P# pin.

Place the Processor Selection jumper in the 2–3 position to support microproces­sors that have the D/P#. Figure 1–1 shows the location of J900 on the probe
adapter.

When the D/P# signal jumper J910 on the probe adapter is in the 1– 2 position,
the D/P# signal is acquired from pin AE35 of the socket being probed. Figure
1–1 shows the location of J910 on the probe adapter.

TMS 109A Socket 7 Microprocessor Support

1–5

Getting Started

When the jumper is open (not connected), the Socket 7 support acquires the D/P#
signal from an external source, and you will have to route the D/P# signal to pin
1 of this jumper externally. This allows you to probe your system from the dual
socket as long as the D/P# signal is accessible on the system under test.

Tracking Jumper

Address Synthesis

Jumper

The Tracking jumper J920 on the probe adapter (see Figure 1–1) does not need to
be moved from the default position (pins 1–2 connected).

The only time this jumper should be moved is when the tracking circuitry
malfunctions. An indication of such a malfunction is when you see activity on
the bus during a BOFF or HLDA cycle that is uncharacteristic of the Socket 7
microprocessor. When the jumper is in the 2–3 position, the circuitry on the
probe adapter does not track BOFF and HLDA cycles. A data sample will show
that such a cycle occurred, but it will not contain meaningful information.

When the Address Synthesis jumper (J921 on the probe adapter) is in position
1–2, A(2:0) is derived from the BE(7:0)# signals and stored in the acquisition
memory with the rest of the address.

When the jumper is in position 2–3, it disables address synthesis, A(2:0)=0.
Figure 1–1 shows the location of J921 on the probe adapter.

Connecting to a System Under Test

Before you connect to the system under test, you must connect the probes to the
module. Your system under test must also have a minimum amount of clearance
surrounding the microprocessor to accommodate the probe adapter. Refer to the
Specifications chapter in this manual for the required clearances.

Connect the P6434 Probes

to the Probe Adapter

1–6

To connect the logic analyzer to a system under test using a probe adapter, follow
these steps:

1. Power off your system under test. It is not necessary to power off the logic

analyzer.

CAUTION. To prevent static damage to the microprocessor, the probe adapter, the
probes, and the module, handle in a static-free environment. Static discharge can
damage all the above components.

Always wear a grounding wrist strap or similar device while handling the
microprocessor and probe adapter.

TMS 109A Socket 7 Microprocessor Support

Getting Started

2. To discharge your stored static electricity, touch the ground connector located

on the back of the logic analyzer. Then, touch any of the ground pins of the

probe adapter to discharge stored static electricity from the probe adapter.

3. Connect the P6434 probes to the probe adapter as shown in Figure 1–2.

Match the channel groups and numbers on the probe labels to the corre-

sponding pins on the probe adapter. Match the ground pins on the probes to

the corresponding pins on the probe adapter.

CAUTION. To prevent damage to the probe and probe adapter, always position the
probe perpendicular to the mating connector and gently connect the probe.
Incorrect handling of the P6434 probe while connecting it to the probe adapter
can result in damage to the probe or to the mating connector on the probe
adapter.

4. Position the probe tip perpendicular to the mating connector and gently

connect the probe (see Figure 1–2).

Push down to latch after

probe is connected

Pin 1

Pin 1

Figure 1–2: Connecting a probe to the probe adapter

Push down to latch after
probe is connected

5. When connected, push down the latch releases on the probe to set the latch.

Remove the

Microprocessor

6. Follow the procedure from the Socket 7 microprocessor vendor to remove

the microprocessor from the socket on your system under test.

TMS 109A Socket 7 Microprocessor Support

1–7

Getting Started

Choose a Protective

Socket

7. Choose the correct protective socket.
Choose the 321-pin or 296-pin protective socket depending on the processor

pinout (see Figure 1–3).

NOTE. Use one protective socket at a time. Do not install a protective socket
without removing all existing sockets from the system under test and from the
bottom of the probe adapter assembly.

For the 321 pin processor

Fro the 296 pin processor

Black holes
are no pins

Figure 1–3: Protective sockets

8. Align the A3 pin indicator on the protective socket with A3 pin of the socket

on your system under test.

9. Insert the protective socket into the system under test as shown in

Figure 1–4.

10. Align the A3 pin indicator on the probe adapter with the A3 pin indicator on

the installed protective socket.

1–8

TMS 109A Socket 7 Microprocessor Support

Getting Started

Insert Probe Adapter

11. Insert the probe adapter into the installed protective socket as shown in

Figure 1–4.

Pin A3

Pin A3

Protective
socket

System under test

Figure 1–4: Placing the socket and probe adapter onto the system under test

TMS 109A Socket 7 Microprocessor Support

1–9

Getting Started

CAUTION. To prevent permanent damage to the micropr ocessor once power is
applied, correctly place the microprocessor into the probe adapter.

Insert Microprocessor in

the Probe Adapter

12. Insert the microprocessor into the probe adapter as shown in Figure 1–5.

Microprocessor

Pin A3

System under test

Alternate Connections

ITP

1–10

Figure 1–5: Inserting a microprocessor into the probe adapter

13. Apply forced air cooling across the probe adapter to keep the components on

the probe adapter cool.

NOTE. Refer to the Intel document ITP700 Port Users Guide for more informa-
tion on the ITP interface.

The Socket 7 probe adapter provides an ITP square-pin header (J580) to connect
to the In-Target Probing (ITP) debugging hardware on the probe adapter as
shown in Figure 1–6 on page 1–12. Table 1–2 lists the signals on the connector
(J580). The ITP debugging hardware is not included with this TMS 109A Sock­et 7 hardware support package. Contact your microprocessor vendor for
information on how to obtain the ITP debugging hardware.

TMS 109A Socket 7 Microprocessor Support

Getting Started

NOTE. The ITP connection is implemented as a point-to-point connection. As
such, it cannot be used in a loopthrough mode for programming other Socket 7
modules.

Table 1–2 lists the pin-to-signal assignments of the In-Target Probe (ITP)
connector J580 on the probe adapter.

T able 1–2: ITP (J580) signal Information

Pin number Signal name

1 B_INIT
2 DBRESET
3 B_RESET
4 GND
5 –
6 +3.3 V
7 R_S#
8 GND
9 –
10 GND
11 PRDY
12 TDI
13 TDO
14 TMS
15 GND
16 TCK
17 GND
18 TRST#
19 –
20 –

These channels are not defined in any channel group and data acquired from
them is not displayed. To display data, you will need to define a channel group.

TMS 109A Socket 7 Microprocessor Support

1–11

Getting Started

J260, ITP
reset signal

J580, ITP
connector

Figure 1–6: ITP and system reset pin locations on the probe adapter

Optional System Reset. The ITP circuitry on the Interposer board does not allow

external ITP debugging hardware to induce a system reset through the
DBRESET# signal on the ITP connector. If you need to enable this feature, you
must provide the connection to your system under test. Table 1–3 lists the signals
on J260 and Figure 1–6 shows the location.

T able 1–3: J260 jumper pin assignments

Jumper pin number Socket 7 signal name

1 OC_DBRESET# (Open

Collector, active low version

of DBRESET)
2 NC
3 DBRESET

The probe adapter contains pins that allow you to connect the DBRESET (or the
active low, open collector version OC_DBRESET#) signal to your system under
test. Table 1–3 shows the pins and signals you can connect to on J260 on the
probe adapter.

When using these signals, you need to make sure that the system under test is not
driving the OC_DBRESET# or DBRESET signal.

1–12

Check that the R/S#, TDI, TMS, TCLK, and TRST# signals are not driven. If
this is not possible, you may clip these five pins on one of the sacrificial sockets

TMS 109A Socket 7 Microprocessor Support

provided with the probe adapter. Inserting this modified socket into your system
socket will isolate these signals on the probe adapter for use by the ITP cable.

Applying and Removing Power

A power supply for the Socket 7 probe adapter is included with the support. The
power supply provides +5 volts power to the probe adapter. The center connector
of the power jack connects to Vcc.

NOTE. Whenever the system under test is powered off, be sure to remove power
from the probe adapter.

To apply power to the Socket 7 probe adapter and system under test, follow these
steps:

CAUTION. To prevent possible permanent damage to the probe adapter and
Socket 7 microprocessor., use the +5 V power supply provided by Tektronix. Do
not mistake another power supply that looks similar for the +5 V power supply.

Getting Started

1. Connect the +5 V power supply to the jack on the probe adapter. Figure 1–7

shows the location of the jack on the probe adapter.

CAUTION. To prevent possible permanent damage to the Socket 7 microprocessor
and system under test, apply power to the probe adapter before applying power
to your system under.

2. Plug the power supply for the probe adapter into an electrical outlet.

3. Power on the system under test.

TMS 109A Socket 7 Microprocessor Support

1–13

Getting Started

Channel Assignments

Power jack

Figure 1–7: Power jack location on the probe adapter

Channel assignments shown in Tables 1–4 through 1–10 use the following
conventions:

H A pound sign (#) following a signal name indicates an active low signal.
H All signals are required by the support unless indicated otherwise.
H An equals sign (=) following a signal name indicates that it is double probed.
H Channels are shown starting with the most significant bit (MSB) descending

to the least significant bit (LSB).

The channel group assignment tables for disassembly and Timing are Address,
Data, Data_Lo, Control, DataSize, Cache, and Misc.

Table 1–4 lists the probe section and channel assignments for the Address group
and the microprocessor signal for each channel connect. By default the Address
channel group assignments are displayed in hexadecimal.

T able 1–4: Address channel group assignments

Bit
order

31 A3:7 A31

Section:channel

Socket 7
signal name

1–14

30 A3:6 A30
29 A3:5 A29
28 A3:4 A28

TMS 109A Socket 7 Microprocessor Support

T able 1–4: Address channel group assignments (Cont.)

Getting Started

Bit
order

27 A3:3 A27
26 A3:2 A26
25 A3:1 A25
24 A3:0 A24
23 A2:7 A23
22 A2:6 A22
21 A2:5 A21
20 A2:4 A20
19 A2:3 A19
18 A2:2 A18
17 A2:1 A17
16 A2:0 A16
15 A1:7 A15
14 A1:6 A14
13 A1:5 A13
12 A1:4 A12

Section:channel

Socket 7
signal name

11 A1:3 A11
10 A1:2 A10
9 A1:1 A9
8 A1:0 A8
7 A0:7 A7
6 A0:6 A6
5 A0:5 A5
4 A0:4 A4
3 A0:3 A3
2 A0:2 A2_D
1 A0:1 A1_D
0 A0:0 A0_D

Table 1–5 lists the probe section and channel assignments for the Data group and
the microprocessor signal for each channel connect. By default the Data channel
group assignments are displayed in hexadecimal.

TMS 109A Socket 7 Microprocessor Support

1–15

Getting Started

T able 1–5: Data channel group assignments

Bit
order

31 E3:7 D63
30 E3:6 D62
29 E3:5 D61
28 E3:4 D60
27 E3:3 D59
26 E3:2 D58
25 E3:1 D57
24 E3:0 D56
23 E2:7 D55
22 E2:6 D54
21 E2:5 D53
20 E2:4 D52
19 E2:3 D51
18 E2:2 D50
17 E2:1 D49
16 E2:0 D48

Section:channel

Socket 7
signal name

15 E1:7 D47
14 E1:6 D46
13 E1:5 D45
12 E1:4 D44
11 E1:3 D43
10 E1:2 D42
9 E1:1 D41
8 E1:0 D40
7 E0:7 D39
6 E0:6 D38
5 E0:5 D37
4 E0:4 D36
3 E0:3 D35
2 E0:2 D34
1 E0:1 D33
0 E0:0 D32

1–16

TMS 109A Socket 7 Microprocessor Support

Getting Started

Table 1–6 lists the probe section and channel assignments for the Data_Lo group
and the microprocessor signal for each channel connect. By default the Data_Lo
channel group assignments are displayed in hexadecimal.

T able 1–6: Data_Lo channel group assignments

Bit
order

31 D3:7 D31
30 D3:6 D30
29 D3:5 D29
28 D3:4 D28
27 D3:3 D27
26 D3:2 D26
25 D3:1 D25
24 D3:0 D24
23 D2:7 D23
22 D2:6 D22
21 D2:5 D21
20 D2:4 D20
19 D2:3 D19
18 D2:2 D18
17 D2:1 D17
16 D2:0 D16

Section:channel

Socket 7
signal name

15 D1:7 D15
14 D1:6 D14
13 D1:5 D13
12 D1:4 D12
11 D1:3 D11
10 D1:2 D10
9 D1:1 D9
8 D1:0 D8
7 D0:7 D7
6 D0:6 D6
5 D0:5 D5
4 D0:4 D4
3 D0:3 D3

TMS 109A Socket 7 Microprocessor Support

1–17

Getting Started

T able 1–6: Data_Lo channel group assignments (Cont.)

Bit
order

2 D0:2 D2
1 D0:1 D1
0 D0:0 D0

Section:channel

Socket 7
signal name

Table 1–7 lists the probe section and channel assignments for the Control group
and the microprocessor signal for each channel connect. The symbol table file
name is

SOCKET7_Ctrl. By default the Control channel group assignments are

displayed as symbols.

T able 1–7: Control channel group assignments

Bit
order

14 C0:7 D/P#
13 C3:0 INIT
12 C2:0 RESET_L
11 C3:6 PRDY

Section:channel

Socket 7
signal name

10 C3:5 BUSCHK#
9 C2:5 SMIACT#
8 C2:6 LOCK#
7 C0:6 SCYC
6 CLK2 LAST_D
5 C0:4 AHOLD
4 C2:2 HLDA
3 C2:1 BOFF#
2 C2:7 M/IO#
1 C3:7 D/C#
0 C3:3 LAST_D

# Indicates the channel is asserted low.

1–18

TMS 109A Socket 7 Microprocessor Support

Getting Started

Table 1–8 lists the probe section and channel assignments for the Data Size group
and the microprocessor signal for each channel connect. By default the Data Size
channel group assignments are not displayed.

T able 1–8: Data Size channel group assignments

Bit
order

7 C1:7 BE7#
6 C1:6 BE6#
5 C1:5 BE5#
4 C1:4 BE4#
3 C1:3 BE3#
2 C1:2 BE2#
1 C1:1 BE1#
0 C0:0 BE0#

# Indicates the channel is asserted LOW.

Section:channel

Socket 7
signal name

Table 1–9 lists the probe section and channel assignments for the Cache group
and the microprocessor signal for each channel connect. By default the Cache
channel group assignments are not displayed.

T able 1–9: Cache channel group assignments

Bit
order

Section:channel

C0:5 CACHE#

Socket 7
signal name

# Indicates the channel is asserted LOW.

Table 1–10 lists the probe section and channel assignments for the Misc group
and the microprocessor signal for each channel connect. By default the Misc
channel group assignments are not displayed.

T able 1–10: Misc channel group assignments

Bit
order

3 CLK3 CLK
2 C2:3 ADS#
1 C3:2 NA#

TMS 109A Socket 7 Microprocessor Support

Section:channel

Socket 7
signal name

1–19

Getting Started

T able 1–10: Misc channel group assignments (Cont.)

Bit
order

0 C3:4 BRDY#

# Indicates the channel is asserted LOW.

Section:channel

Socket 7
signal name

Table 1–11 lists the probe section and channel assignments for the clock probes
and the Socket 7 signal to which each channel connects.

T able 1–11: Clock channel group assignments

Socket 7

Section:channel

CLK:0 DVALID_D
CLK:1 PIPE_D
CLK:2 LAST_D
CLK:3 CLK
C2:0 RESET_L
C2:1 BOFF#
C2:2 HLDA

signal name

Description

C2:3 ADS#
QUAL:0 Not Used
QUAL:1 Not Used
QUAL:2 Not Used
QUAL:3 Not Used

# Indicates the channel is asserted low.

Acquisition Setup. The support will affect the logic analyzer setup menus and

submenus by modifying existing fields and adding micro-specific fields.
The TMS 109A Socket 7 microprocessor support will add the selections

SOCKET7_ to the Load Support Package dialog box, located under the File

pulldown menu. The
Once the

TMS 109A Socket 7 support has been loaded, the Custom clocking mode

SOCKET7_T supports timing.

selection in the module Setup menu is also enabled.

1–20

TMS 109A Socket 7 Microprocessor Support

Getting Started

Table 1–12 lists channel groups not required for clocking and disassembly.

T able 1–12: Signals not required for clocking or disassembly

Signal name TLA700 Channel

NA# C3:2
BRDY# C3:4
CACHE# C0:5

# Indicates the channel is asserted low.

Table 1–13 lists signals on the probe adapter but not acquired.

T able 1–13: Signals on the probe adapter but not acquired

Signal name AUX J580 Pin number

TDI 12
TDO 13
TMS 14
TCK 16
TRST# 18
INIT 1
R/S# 7
PRDY 11

# Indicates the channel is asserted low.

Table 1–14 lists signals not connected to probe adapter.

T able 1–14: Signals not connected to probe adapter

Signal name AUX J1700 Pin number

A20M# AK08
AP AK02
BREQ AJ01
EWBE# W03
IERR# P04
FRCMC# Y35

TMS 109A Socket 7 Microprocessor Support

1–21

Getting Started

T able 1–14: Signals not connected to probe adapter (Cont.)

Signal name AUX J1700 Pin number

ADSC# AM02
BRDYC# Y03
KEN# W05

# Indicates the channel is asserted low.

Channel Qual 0:3 is not attached to the probe adapter by default. You may
connect this channel to other signals of interest.

CPU To Mictor Connections

To probe the microprocessor you will need to make connections between the
CPU and the Mictor pins of the P6434 Mass Termination Probe. Refer to the
P6434 Mass Termination Probe manual, Tektronix part number 070-9793-xx, for
more information on mechanical specifications. Tables 1–15 through 1–17 show
the CPU pin to Mictor pin connections.

Tektronix uses a counterclockwise pin assignment. Pin 1 is located at the top left,
and pin 2 is located directly below it. Pin 20 is located on the bottom right, and
pin 21 is located directly above it.

AMP uses an odd side-even side pin assignment. Pin-1 is located at the top left,
and pin 3 is located directly below it. Pin 2 is located on the top right, and pin 4
is located directly below it (see Figure 1–8).

NOTE. When designing Mictor connectors into your system under test, always
follow the Tektronix pin assignment.

Tektronix Pinout AMP Pinout

Pin 1

Pin 19

Pin 38

Pin 20

Pin 1

Pin 37

Pin 2

Pin 38

Figure 1–8: Pin assignments for a Mictor connector (component side)

1–22

TMS 109A Socket 7 Microprocessor Support

T able 1–15: CPU to Mictor connections for Mictor A pins

Getting Started

Tektronix
Mictor A
pin number

1 1 GND GND GND
2 3 GND GND GND
3 5 CLOCK:0 DVALID_D DERIVED
4 7 A3:7 A31 AJ-33
5 9 A3:6 A30 AM-36
6 11 A3:5 A29 AK-34
7 13 A3:4 A28 AK-36
8 15 A3:3 A27 AG-33
9 17 A3:2 A26 AH-34
10 19 A3:1 A25 AJ-35
11 21 A3:0 A24 AG-35
12 23 A2:7 A23 AE-33
13 25 A2:6 A22 AH-36
14 27 A2:5 A21 AF-34
15 29 A2:4 A20 AL-21
16 31 A2:3 A19 AK-22
17 33 A2:2 A18 AL-23
18 35 A2:1 A17 AK-24
19 37 A2:0 A16 AL-25
20 38 A0:0 A0_D DERIVED
21 36 A0:1 A1_D DERIVED
22 34 A0:2 A2_D DERIVED
23 32 A0:3 A3 AL-35
24 30 A0:4 A4 AM-34
25 28 A0:5 A5 AK-32
26 26 A0:6 A6 AN-33
27 24 A0:7 A7 AL-33
28 22 A1:0 A8 AM-32
29 20 A1:1 A9 AK-30
30 18 A1:2 A10 AN-31
31 16 A1:3 A11 AL-31
32 14 A1:4 A12 AL-29
33 12 A1:5 A13 AK-28
34 10 A1:6 A14 AL-27
35 8 A1:7 A15 AK-26

AMP
Mictor A
pin number

LA channel

Socket 7
signal name

Socket 7
pin number

TMS 109A Socket 7 Microprocessor Support

1–23

Getting Started

T able 1–15: CPU to Mictor connections for Mictor A pins (Cont.)

Tektronix
Mictor A
pin number

36 6 CLOCK:1 PIPE_D DERIVED
37 4 GND GND GND
38 2 GND GND GND
39 39 GND GND GND
40 40 GND GND GND
41 41 GND GND GND
42 42 GND GND GND
43 43 GND GND GND
44 44 GND GND GND

AMP
Mictor A
pin number

LA channel

Socket 7
signal name

Socket 7
pin number

T able 1–16: CPU to Mictor connections for Mictor D pins

Tektronix
Mictor D
pin number

1 1 GND GND GND
2 3 GND GND GND
3 5 NC NC NC
4 7 D3:7 D31 C-17
5 9 D3:6 D30 D-20
6 11 D3:5 D29 C-19
7 13 D3:4 D28 D-22
8 15 D3:3 D27 C-21
9 17 D3:2 D26 D-24
10 19 D3:1 D25 C-23
11 21 D3:0 D24 C-27
12 23 D2:7 D23 D-26
13 25 D2:6 D22 A-31
14 27 D2:5 D21 C-29
15 29 D2:4 D20 B-30
16 31 D2:3 D19 D-28
17 33 D2:2 D18 A-33
18 35 D2:1 D17 C-31
19 37 D2:0 D16 B-32
20 38 D0:0 D0 K-34

AMP
Mictor D
pin number

LA channel

Socket 7
signal name

Socket 7
pin number

1–24

TMS 109A Socket 7 Microprocessor Support

T able 1–16: CPU to Mictor connections for Mictor D pins (Cont.)

Getting Started

Tektronix
Mictor D
pin number

21 36 D0:1 D1 G-35
22 34 D0:2 D2 J-35
23 32 D0:3 D3 G-33
24 30 D0:4 D4 F-36
25 28 D0:5 D5 F-34
26 26 D0:6 D6 E-35
27 24 D0:7 D7 E-33
28 22 D1:0 D8 D-34
29 20 D1:1 D9 C-37
30 18 D1:2 D10 C-35
31 16 D1:3 D11 B-36
32 14 D1:4 D12 D-32
33 12 D1:5 D13 B-34
34 10 D1:6 D14 C-33
35 8 D1:7 D15 A-35
36 6 CLOCK:2 LAST_D DERIVED
37 4 GND GND GND
38 2 GND GND GND
39 39 GND GND GND
40 40 GND GND GND
41 41 GND GND GND
42 42 GND GND GND
43 43 GND GND GND
44 44 GND GND GND

AMP
Mictor D
pin number

LA channel

Socket 7
signal name

Socket 7
pin number

T able 1–17: CPU to Mictor connections for Mictor E pins

Tektronix
Mictor E
pin number

1 1 GND GND GND
2 3 GND GND GND
3 5 QUAL:3 NC NC
4 7 E3:7 D63 N-03
5 9 E3:6 D62 M-04

TMS 109A Socket 7 Microprocessor Support

AMP
Mictor E
pin number

LA channel

Socket 7
signal name

Socket 7
pin number

1–25

Getting Started

T able 1–17: CPU to Mictor connections for Mictor E pins (Cont.)

Tektronix
Mictor E
pin number

6 11 E3:5 D61 L-03
7 13 E3:4 D60 L-05
8 15 E3:3 D59 K-04
9 17 E3:2 D58 J-05
10 19 E3:1 D57 J-03
11 21 E3:0 D56 H-04
12 23 E2:7 D55 G-03
13 25 E2:6 D54 E-01
14 27 E2:5 D53 G-05
15 29 E2:4 D52 E-03
16 31 E2:3 D51 F-04
17 33 E2:2 D50 D-02
18 35 E2:1 D49 E-05
19 37 E2:0 D48 D-04
20 38 E0:0 D32 C-15
21 36 E0:1 D33 D-16
22 34 E0:2 D34 C-13
23 32 E0:3 D35 D-14
24 30 E0:4 D36 C-11
25 28 E0:5 D37 D-12
26 26 E0:6 D38 C-09
27 24 E0:7 D39 D-10
28 22 E1:0 D40 D-08
29 20 E1:1 D41 A-05
30 18 E1:2 D42 E-09
31 16 E1:3 D43 B-04
32 14 E1:4 D44 D-06
33 12 E1:5 D45 C-05
34 10 E1:6 D46 E-07
35 8 E1:7 D47 C-03
36 6 QUAL:2 NC NC
37 4 GND GND GND
38 2 GND GND GND
39 39 GND GND GND
40 40 GND GND GND

AMP
Mictor E
pin number

LA channel

Socket 7
signal name

Socket 7
pin number

1–26

TMS 109A Socket 7 Microprocessor Support

T able 1–17: CPU to Mictor connections for Mictor E pins (Cont.)

Getting Started

Tektronix
Mictor E
pin number

AMP
Mictor E
pin number

LA channel

Socket 7
signal name

Socket 7
pin number

41 41 GND GND GND
42 42 GND GND GND
43 43 GND GND GND

T able 1–18: CPU to Mictor connections for Mictor C pins

Tektronix
Mictor C
pin number

1 1 GND GND GND
2 3 GND GND GND
3 5 CLOCK:3 CLK AK-18
4 7 C3:7 D/C
5 9 C3:6 PRDY AC-05
6 11 C3:5 BUSCHK
7 13 C3:4 BRDY
8 15 C3:3 W/R
9 17 C3:2 NA
10 19 C3:1 BRDY
11 21 C3:0 INIT AA-33
12 23 C2:7 M/IO
13 25 C2:6 LOCK
14 27 C2:5 SMIACT
15 29 C2:4 W/R
16 31 C2:3 ADS
17 33 C2:2 HLDA DERIVED
18 35 C2:1 BOFF
19 37 C2:0 RESET_L DERIVED
20 38 C0:0 RESET_L= AK-20
21 36 C0:1 BOFF
22 34 C0:2 HLDA
23 32 C0:3 ADS
24 30 C0:4 AHOLD V-04
25 28 C0:5 CACHE
26 26 C0:6 SCYS AL-17

AMP
Mictor C
pin number

LA channel

Socket 7
signal name

#

#

#

#

#

#=

#

#

#

#=

#

#

#=
=

#=

#

Socket 7
pin number

AK-04

AL-07
DERIVED
DERIVED
Y-05
X-04

T-04
AH-04
AG-03
AM-06
DERIVED

DERIVED

Z-04
AJ-3
AJ-05

DERIVED

TMS 109A Socket 7 Microprocessor Support

1–27

Getting Started

T able 1–18: CPU to Mictor connections for Mictor C pins (Cont.)

Tektronix
Mictor C
pin number

27 24 C0:7 D/P
28 22 C1:0 BE0
29 20 C1:1 BE1
30 18 C1:2 BE2
31 16 C1:3 BE3
32 14 C1:4 BE4
33 12 C1:5 BE5
34 10 C1:6 BE6
35 8 C1:7 BE7

AMP
Mictor C
pin number

LA channel

Socket 7
signal name

#

#
#
#
#
#
#
#
#

Socket 7
pin number

DERIVED
AL-09
AK-10
AL-11
AK-12
AL-13
AK-14
AL-15

AK-16
36 6 NC – NC
37 4 NC GND GND
38 2 NC GND GND
39 39 GND GND GND
40 40 GND GND GND
41 41 GND GND GND
42 42 GND GND GND
43 43 GND GND GND

#

Indicates the channel is asserted low.

= Indicates double probing

1–28

TMS 109A Socket 7 Microprocessor Support

Operating Basics

Setting Up the Support

This section provides information on how to set up the support. Information
covers the following topics:

H Channel group definitions
H Clocking options
H Symbol table files

Remember that the information in this section is specific to the operations and
functions of the TMS 109A Socket 7 support on any Tektronix logic analyzer for
which it can be purchased. Information on basic operations describes general
tasks and functions.

Before you acquire and disassemble data, you need to load the support and
specify setups for clocking and triggering as described in the information on
basic operations. The support provides default values for each of these setups,
but you can change them as needed.

Channel Group Definitions

Clocking Options

Custom Clocking

The software automatically defines channel groups for the support. The channel
groups for the Socket 7 support are Address, Data, Data_Lo, Control, DataSize,
Cache, and Misc.

A special clocking program is loaded to the module every time you load the
SOCKET7_ support. This special clocking is called Custom.

With Custom clocking, the module logs in signals from multiple groups of
channels at different times as they become valid on the Socket 7 bus. The module
then sends all the logged-in signals to the trigger machine and to the memory of
the module for storage.

In Custom clocking, the module clocking state machine (CSM) generates one
master sample for each microprocessor bus cycle, no matter how many clock
cycles are contained in the bus cycle.

TMS 109A Socket 7 Microprocessor Support

2–1

Setting Up the Support

CLK

Latched

ADS#

Delayed

Latched

Address
Delayed

Data

LAST_D

DVALID_D

Figure 2–1 shows two typical bus cycles: a single cycle transfer followed by a
burst transfer. The ADS#, Address and Data signal forms are delayed by two
CLK cycles. This diagram also shows the timing relationships of LAST_D and
DVALID_D, the signals synthesized by sequential logic in the PALs.

Sample point 1

A31-A0

M/IO#

D/C#

W/R#

ADS#

AHOLD

CACHE#

BE7#–BE0#

SCYC
HLDA

RESET

D/P#

[Channels not set up in a channel group by the TMS 109A Socket 7 software are logged with the Master sample.

Master sample[

D63-D0

All other control

signals

Sample point 1

A31-A0

M/IO#

D/C#
W/R#

ADS#

AHOLD

CACHE#

BE7#–BE0#

SCYC
HLDA

RESET

D/P#

Master sample[

D63-D0

All other

control signals

Master sample[

D63-D0

All other

control signals

Figure 2–1: Nonpipelined single and Burst Transfer cycles

Relative to real time, nondelayed Socket 7 microprocessor signals, the first
sample point in a cycle occurs two clocks after the ADS# signal is asserted. The
second (and subsequent, if the cycle is a burst) sample point occurs two clocks
after the BRDY# or BRDYC# signal.

Master sample[

D63-D0

All other

control signals

Master sample[

D63-D0

All other

control signals

Figure 2–2 shows a single cycle transfer pipelined into another single cycle
transfer. The ADS#, Address and Data signal forms are delayed by two CLK
cycles. This diagram also shows the timing relationships of D_LAST,

2–2 TMS 109A Socket 7 Microprocessor Support

CLK

Latched

ADS#

Delayed

Address

Delayed

Data

LAST_D

DVALID_D

PIPE_D

Setting Up the Support

DVALID_D, and PIPE_D, which are the signals synthesized by sequential logic
in the PALs.

Sample point 1

A31-A0

M/IO#

D/C#
W/R#
ADS#

AHOLD

CACHE#

BE7#–BE0#

SCYC
HLDA

RESET

[Channels not set up in a channel group by the TMS 109A Socket 7 software are logged with the Master sample.

Master sample[

D63-D0

All other

control signals

Sample point 1

A31-A0

M/IO#

D/C#

W/R#

ADS#

AHOLD

CACHE#

BE7#–BE0#

SCYC
HLDA

RESET

Figure 2–2: Pipelined cycles

With relationship to real-time, nondelayed, Socket 7 microprocessor signals, the
first sample point in a cycle occurs two clocks after the ADS# signal is asserted.
When the ADS# signal is asserted again to pipeline a second cycle into the first,
the first sample point for that second cycle occurs three clocks after the last
BRDY# or BRDYC# signal is returned from the first outstanding cycle.

Master sample[

D63-D0

All other

control signals

ClockingOptions

The clocking algorithm for the Socket 7 microprocessor has two variations:
Alternate Bus Master Cycles Excluded and Alternate Bus Master Cycles
Included.

TMS 109A Socket 7 Microprocessor Support

2–3

Setting Up the Support

Alternate Bus Master Cycles Excluded. Whenever the HLDA signal is high, no bus
cycles are logged in. Only bus cycles driven by the microprocessor (HLDA low)
will be logged in. Backoff cycles (caused by the BOFF# signal) are stored.

Alternate Bus Master Cycles Included. All bus cycles, including alternate bus
master cycles and backoff cycles, are logged in.

When the HLDA signal is high, the microprocessor has given up the bus to an
alternate device. The design of the Socket 7 microprocessor system affects what
data will be logged in. The module only samples the data at the pins of the
microprocessor. To properly log in bus activity, any buffers between the
microprocessor and the alternate bus master must be enabled and pointing at the
Socket 7 microprocessor.

There are three possible Socket 7 microprocessor system designs and clocking
interactions when an alternate bus master has control of the bus. The three
different possibilities are listed below (in each case, the HLDA signal is logged
in as a high level):

H If the alternate bus master drives the same control lines as the Socket 7

microprocessor, and the Socket 7 microprocessor sees these signals, the bus
activity is logged in like normal bus cycles except that the HLDA signal is
high.

H If none of the control lines are driven or if the Socket 7 microprocessor can

not see them, the module will still clock in an alternate bus master cycle. The
information on the bus, one clock prior to the HLDA signal going low, is
logged in. If the ADS# signal goes low on the same clock when the HLDA
signal goes low, the address that gets logged in will be the next address, not
the address that occurred one clock before the HLDA signal went low.

H If some of the Socket 7 microprocessor control lines are visible (but not all),

the module logs in the signals it determines are valid from the control signals
and logs in the remaining bus signals one clock cycle prior to the HLDA
signal going low. If the ADS# signal goes low on the same clock that the
HLDA signal goes low, the next address will be logged instead of the
previously saved address.

When the BOFF# signal goes low (active), a backoff cycle has been requested,
and the Socket 7 microprocessor gives up the bus on the next clock cycle. The
module aborts the bus cycle that it is currently logging in (the Socket 7
microprocessor will restart this cycle once the BOFF# signal goes high). A
backoff cycle will be logged in using one of the three interactions described for
the HLDA signal (except that the BOFF# signal is stored as a low-level signal in
each of the cases).

2–4 TMS 109A Socket 7 Microprocessor Support

Mode Differences

Setting Up the Support

The Socket 7 microprocessor can operate in either Component or Chip Set mode.

Component Mode

Chip Set Mode

In Component mode (stand alone), the microprocessor interfaces directly to the
system bus.

The Socket 7 microprocessor, C5C cache controller, and the C8C cache memory
(SRAM) can be combined to form a chip set or enhanced design. The two cache
devices connect to the system bus and a memory bus controller interfaces to the
microprocessor and cache devices.

The behavior of the Socket 7 microprocessor is affected when operating in Chip
Set mode. The TMS 109A Socket 7 software and probe adapter still supports the
Socket 7 microprocessor in this mode.

There are also two new signals: BRDYC# (pin L3) and ADSC# (pin N4).
In Component mode, the BRDYC# signal is seen as a “no connect” pin. The

TMS 109A Socket 7 probe adapter uses the BRDYC# signal for clocking when it
is active. The probe adapter has a pullup resistor on this line to hold it inactive
when the Socket 7 is in Chip-Set mode. The BRDYC# signal can be probed on
C1:0.

In Component mode, the ADSC# signal is seen as a “no connect” pin and is not
used for clocking by the probe adapter.

Symbols

The TMS 109A Socket 7 support supplies one symbol table file. The SOCK­ET7_Ctrl file replaces specific Control channel group values with symbolic
values when Symbolic is the radix for the channel group.

Table 2–1 shows the name, bit pattern, and meaning for the symbols in the file
SOCKET7_Ctrl, the Control channel group symbol table.

T able 2–1: Control group symbol table definitions

Control group value

D/P# BUSCHK# LAST_D M/IO#

Symbol

    

    

    

INIT SMIACT# AHOLD D/C#

IRESET_L LOCK# HLDA W/R#

TMS 109A Socket 7 Microprocessor Support

PRDY SCYC BOFF3#

Meaning

Reset
Primary processor opcode read
Dual processor opcode read

2–5

Setting Up the Support

T able 2–1: Control group symbol table definitions (cont.)

Control group value

D/P# BUSCHK# LAST_D M/IO#

INIT SMIACT# AHOLD D/C#

Symbol Meaning

IRESET_L LOCK# HLDA W/R#

FETCH* XX0 XXX1 XXX0 1100

P_LOCK_RD 0X0 XXX0 XXX0 1X10

D_LOCK_RD 1X0 XXX0 XXX0 1X10

LOCK_RD* XX0 XXX0 XXX0 1X10

P_LOCK_WR 0X0 XXX0 XXX0 1X11

D_LOCK_WR 1X0 XXX0 XXX0 1X11

LOCK_WR* XX0 XXX0 XXX0 1X11

P_MEM_RD 0X0 XXXX XXX0 1110

D_MEM_RD 1X0 XXXX XXX0 1110

MEM_RD* XX0 XXXX XXX0 1110

P_MEM_WR 0X0 XXXX XXX0 1111

D_MEM_WR 1X0 XXXX XXX0 1111

MEM_WR* XX0 XXXX XXX0 1111

P_I/O_RD 0X0 XXXX XXX0 1010

D_I/O_RD 1X0 XXXX XXX0 1010

I/O_RD* XX0 XXXX XXX0 1010

P_I/O_WR 0X0 XXXX XXX0 1011

D_I/O_WR 1X0 XXXX XXX0 1011

I/O_WR* XX0 XXXX XXX0 1011

P_MEM_R/W* 0X0 XXXX XXX0 111X

D_MEM_R/W* 1X0 XXXX XXX0 111X

MEM_R/W* XX0 XXXX XXX0 111X

P_I/O_R/W* 0X0 XXXX XXX0 101X

D_I/O_R/W* 1X0 XXXX XXX0 101X

I/O_R/W* XX0 XXXX XXX0 101X

P_READ* 0X0 XXXX XXX0 1X10

D_READ* 1X0 XXXX XXX0 1X10

READ* XX0 XXXX XXX0 1X10

P_WRITE* 0X0 XXXX XXX0 1X11

D_WRITE* 1X0 XXXX XXX0 1X11

WRITE* XX0 XXXX XXX0 1X11

P_INT_ACK 0X0 XXXX XXX0 1000

PRDY SCYC BOFF3#

Opcode read
Primary processor locked read cycle
Dual processor locked read cycle
Locked read cycle
Primary processor locked write cycle
Dual processor locked write cycle
Locked write cycle
Primary processor nonopcode read
Dual processor nonopcode read
Read from memory, nonopcode
Primary processor write to memory
Dual processor write to memory
Write to memory
Primary processor I/O read cycle
Dual processor I/O read cycle
I/O read cycle
Primary processor I/O write cycle
Dual processor I/O write cycle
I/O write cycle
Any primary processor read or write
Any dual processor read or write
Any memory read or write cycle
Any primary processor I/O cycle
Any dual processor I/O cycle
Any I/O read or write cycle
Any primary processor read cycle
Any dual processor read cycle
Any read cycle
Any primary processor write cycle
Any dual processor write cycle
Any write cycle
Primary processor int. acknowledge

2–6 TMS 109A Socket 7 Microprocessor Support

T able 2–1: Control group symbol table definitions (cont.)

Control group value

D/P# BUSCHK# LAST_D M/IO#

INIT SMIACT# AHOLD D/C#

Symbol Meaning

IRESET_L LOCK# HLDA W/R#

D_INT_ACK 1X0 XXXX XXX0 1000

INT_ACK* XX0 XXXX XXX0 1000

P_SPECIAL 0X0 XXXX XXX0 1001

D_SPECIAL 1X0 XXXX XXX0 1001

SPECIAL* XX0 XXXX XXX0 1001

P_RESERVE 0X0 XXXX XXX0 1101

D_RESERVE 1X0 XXXX XXX0 1101

RESERVE* XX0 XXXX XXX0 1101

ALT_B_MTR XX0 XXXX XXX1 XXXX

BOFF XX0 XXXX XXXX 0XXX

P_BUSCHCK 0X0 X0XX XXX0 1XXX

D_BUSCHCK 1X0 X0XX XXX0 1XXX

BUSCHCK* 0X0 X0XX XXX0 1XXX

P_LOCKED 0X0 X1X0 XXXX XXXX

D_LOCKED 1X0 X1X0 XXXX XXXX

LOCKED* XX0 X1X0 XXXX XXXX

P_SPLTCYC* 0X0 X1X0 1XXX XXXX

D_SPLTCYC* 1X0 X1X0 1XXX XXXX

SPLTCYC* XX0 X1X0 1XXX XXXX

P_SMM* 0X0 XX0X XXXX XXXX

D_SMM* 1X0 XX0X XXXX XXXX

SMM* XX0 XX0X XXXX XXXX

PRIMARY* 0XX XXXX XXXX XXXX

DUAL* 1XX XXXX XXXX XXXX

*

Symbols used only for triggering; they are not displayed.

PRDY SCYC BOFF3#

Dual processor int. acknowledge
Interrupt acknowledge cycle
Primary processor special cycle
Dual processor special cycle
Special cycle
Primary processor reserved
Dual processor reserved
Reserved
Alternate bus master cycle
Backoff cycle
Primary processor buscheck
Dual processor buscheck
Buscheck
Any primary processor locked cycle
Any dual processor locked cycle
Any locked cycle
Primary processor split cycle
Dual processor split cycle
Split cycle
The primary processor is in smm
The dual processor is in smm
Either processor is in smm
Any primary processor cycle
Any dual processor cycle

Setting Up the Support

Information on basic operations describes how to use symbolic values for
triggering and for displaying other channel groups symbolically, such as the
Address channel group.

TMS 109A Socket 7 Microprocessor Support

2–7

Setting Up the Support

2–8 TMS 109A Socket 7 Microprocessor Support

Acquiring and Viewing Disassembled Data

This section describes how to acquire data and view it disassembled. Information
covers the following topics and tasks:

H Acquire data
H View disassembled data in various display formats
H Cycle type labels
H Change the way data is displayed
H Change disassembled cycles with the mark cycles function

NOTE. The disassembly software is optimized to decode instruction streams and
bus activities from Intel microprocessors and AMD-K6-2; therefore, the
disassembler may not support unique characteristics of other manufacturers.
However, you can reliably conduct timing analysis of nonIntel Socket 7
processors and use the high-level source debug capabilities of a Tektronix logic
analyzer. Consult your Tektronix field office for future enhancements.

Acquiring Data

Once you load the SOCKET7_ support, choose a clocking mode, and specify the
trigger, you are ready to acquire and disassemble

If you have any problems acquiring data, refer to information on basic operations
in your online help or Appendix A: Error Messages and Disassembly Pr oblems in
the basic operations user manual.

Viewing Disassembled Data

You can view disassembled data in five display formats: Timing, Hardware,
Software, Control Flow, and Subroutine. The information on basic operations
describes how to select the disassembly display formats.

NOTE. Selections in the Disassembly property page (the Disassembly Format
Definition overlay) must be set correctly for your acquired data to be disas­sembled correctly. Refer to Changing How Data is Displayed on page 2–17.

data.

TMS 109A Socket 7 Microprocessor Support

2–9

Acquiring and Viewing Disassembled Data

The default display format shows the Address, Data, Data_Lo, and Control
channel groups for each sample of acquired data. The Data and Data_Lo groups
are shown in one column.

The disassembler displays special characters and strings in the instruction
mnemonics to indicate significant events. Table 2–2 shows these special
characters and strings, and gives a definition of what they represent.

T able 2–2: Meaning of special characters in the display

Character or string displayed Meaning

#

>

The pound sign is used to indicate an immediate value. This
is somewhat dependent upon the target microprocessor
assembler notation.

There is insufficient room on the screen to show all available
data.

&

»

t

****

*

c

–

( FLUSH )

(16) or (32)

SMM

The instruction was manually marked as a program fetch.
This instruction fetch cycle has been manually marked by the

user (TLA 700).
This indicates the given number is in decimal. Example: #12t

(for 0xC in hexadecimal)
Indicates there is insufficient data available for complete

disassembly of the instruction; the number of asterisks
indicates the width of the data that is unavailable. Each two
asterisks represent one byte.

A single asterisk at the beginning of the instruction implies
the cycle is an out–of–order fetch. It is located in the first
character to the left of the mnemonic.

A lower–case “c” is used to indicate a cache invalidation
cycle. It is located in the second character to the left of the
mnemonic.

A dash “–” is used to indicated that this cycle was issued by
the “other” microprocessor , (Primary, or Dual, based on user
selection).

The instruction has been flushed from the microprocessor’s
internal instruction queue.

Indicates that the fetch is from a 16- or 32-bit code segment
size, and disassembled accordingly. If the mnemonic fills the
entire column width, the (16) or (32) will not be displayed.

Indicates a System management mode cycle.

2–10

(MMX)

(3DNow!)

Indicates an MMX instruction; appears at the end of the
mnemonic.

Indicates an 3DNow! instruction; appears at the end of the
mnemonic.

TMS 109A Socket 7 Microprocessor Support

Acquiring and Viewing Disassembled Data

T able 2–2: Meaning of special characters in the display (cont.)

Character or string displayed Meaning

??

<more>

This notation will be placed in a mnemonic field if the
disassembler views the operand invalid for the instruction.
For example, there is not a control register named “CR7”.
Thus if the operand byte would indicate the register “CR7”,
“(??)” will be placed to the right of the instruction string:
“MOV CR7,EAX (??)”.

For Software Mode, if there are more than eight lines of text
to be displayed for a cycle due to out-of-order fetching, the
eighth line will have the text string “<more>” displayed at the
right. This text WILL overlay any other text on the line (it has
the highest priority).

Logic analyzer software does not allow more than 32 channels in each channel
group. Therefore, two channel groups are used to acquire 64-bit wide Socket 7
microprocessor data.

To handle the display of disassembled data from both data groups, the
disassembler may display more than one line for each data sample. For samples
with two display lines, data displayed under the Data column of the first line is
from the Data_Lo group (D31-0); data displayed under the Data column of the
second line is from the Data group (D63-32). Figure 2–3 on page 2–14 shows
examples of multiple display lines used to display Data_Lo and Data group
information.

The disassembler synthesizes the A2-A0 signals.

Aborting Lengthy Disassembly . When acquiring data from two microprocessors,
the disassembler might take a long time to display disassembled data. This could
be caused by the combination of selections in the Trace Processor and Other
Processor fields in the Disassembly property page (Disassembly Format
Definition overlay).

An example where this might occur is when the Trace Processor field is set to
DUAL, and the Other Processor field is set to Suppress. If the acquisition data
only contains data from the Primary microprocessor, then the disassembler might
take a long time to display disassembled cycle types or instruction mnemonics.

TMS 109A Socket 7 Microprocessor Support

2–11

Acquiring and Viewing Disassembled Data

Timing-Waveform Display

Format

Hardware Display Format

In the Timing-Waveform display format, the display is set up to show the
following waveforms:

CLK D/C# RESET
Address M/IO# HLDA
DataData_Lo NA# BOFF#
ADS# CACHE# AHOLD
D/P# BRDY#
W/R# LOCK#

In Hardware display format, the disassembler displays certain cycle type labels in
parentheses (see Figure 2–9 on page 2–23). Table 2–3 shows these cycle type
labels and gives a definition of the cycle they represent. Reads to interrupt and
exception vectors will be labeled with the vector name.

The disassembler always displays at least one line of information. Because
fetches should have valid data for the Data and Data_Lo groups, most fetches
should use at least two display lines. For example, a fetch cycle can show both an
instruction and a READ EXTENSION, or FLUSH (or both).

T able 2–3: Cycle type definitions

Label Description

( RESET )

( MEM READ )

( LOCKED MEM READ )

( MEM WRITE )

( LOCKED MEM WRITE )

( IO READ )

( IO WRITE )

( INT ACK )

( SHUTDOWN )

( CACHE FLUSH )

( HALT )

( WRITE-BACK )

( FLUSH ACK )

( BRANCH TRACE: TARGET )

( BRANCH TRACE: SOURCE )

( STOP GRANT ACK )

A reset cycle
A nonlocked memory read cycle that is not an opcode fetch
A locked memory read cycle that is not an opcode fetch
Any nonlocked memory write
Any locked memory write
Read from an I/O port
Write to an I/O port
Interrupt acknowledge cycle
Shutdown/special bus cycle; BE7:BE0 = 11111110
Cache flush/special bus cycle; BE7:BE0 = 1 1111101
Halt/special bus cycle; BE7:BE0 = 11 111011
Write back/special bus cycle; BE7:BE0 = 11 110111

Flush Ack/special bus cycle; BE7:BE0 = 1 110111 1
Branch Trace Message/special bus cycle; BE7:BE0 = 1101 1111
Branch Trace Message/special bus cycle; BE7:BE0 = 1101 1111

Stop Grant cycle; cycle type is HAL T/SPECIAL;

BE7:BE0 = 1111101 1

2–12

TMS 109A Socket 7 Microprocessor Support

T able 2–3: Cycle type definitions (Cont.)

Label Description

( RESERVED )

Reserved

Acquiring and Viewing Disassembled Data

( ALTERNATE BUS MASTER )

( BACK OFF )

( UNKNOWN )

( BURST LINE FILL )*

( BACKOFF/BURST FLUSH )*

( EXTENSION )*

( FLUSH )*

( DUAL FETCH )

( PRIMARY FETCH )

* Computed cycle types.

Bus is released to an Alternate Bus Master
Back Off bus cycle
An invalid/unknown bus cycle
Fetch cycle computed to be a burst fill. The data is fetched but

will not be executed, it is part of a 32 byte fetch. It will possibly
be stored in cache.

Burst/Fetch cycle computed to be flushed due to a back off
Fetch cycle computed to be an opcode extension
Fetch cycle computed to be flushed
Nondisassembled fetch cycle from the Dual processor
Nondisassembled fetch cycle from the Primary processor

TMS 109A Socket 7 Microprocessor Support

2–13

Acquiring and Viewing Disassembled Data

Figure 2–3 shows an example of the Hardware display.

1 2 3

Sample Address Data Mnemonic Timestamp

-------------------------------------------------------------------------------­000388AE FF33F633 XOR EDI,EDI (32)

15 000408A0 C033CB00 - ( DUAL FETCH ) 100 ns

000408A4 C933DB33 - ( DUAL FETCH )

4
5

16 000388B0 ABFFE1C3 RETS (32) 100 ns

000388B4 B6EFFFEF ( FLUSH )

17 000408A8 ED33D233 - ( DUAL FETCH ) 100 ns

000408AC FF33F633 - ( DUAL FETCH )

18 000388B8 FFB7D7FA ( FLUSH ) 100 ns

000388BC FFFFFDFF ( FLUSH )

19 000408B0 BDDF26C3 - ( DUAL FETCH ) 100 ns

000408B4 FF27FFBF - ( DUAL FETCH )

20 000207F4 00000005 ( MEM READ ) 100 ns
21 000408B8 5DBE5FED - ( DUAL FETCH ) 100 ns

000408BC 7FFEFBFB - ( DUAL FETCH )

22 000388C0 44875050 ( FLUSH ) 100 ns

000388C4 04870824 ( FLUSH )

23 000307F4 00000005 - ( MEM READ ) 100 ns
24 00038800 00009DE8 ( FLUSH ) 100 ns

00038805 000EBE00 MOV ESI,#0000000E (32)

25 000408C0 44875050 - ( DUAL FETCH ) 100 ns

000408C4 04870824 - ( DUAL FETCH )

6 7

Figure 2–3: Hardware display format

1

Sample Column. Lists the memory locations for the acquired data.

2

Address Group. Lists data from channels connected to the Socket 7 address
bus.

3

Data Column. Lists data from channels connected to D63-D32 and/or
D31-D0 of the Socket 7 microprocessor data bus. Refer to the general
description of viewing disassembled data for information on how the
disassembler determines when to display information for the Data group.

4

This part of the sample is displaying data from channels connected to
D31-D0 of the Socket 7 microprocessor data bus.

5

This part of the sample is displaying data from channels connected to
D63-D32 of the Socket 7 microprocessor data bus.

6

Mnemonic Column. Lists the disassembled instructions and cycle types.

7

Timestamp. Lists the timestamp values when a timestamp selection is made.
Information on basic operations describes how you can select a timestamp.

2–14

TMS 109A Socket 7 Microprocessor Support

Acquiring and Viewing Disassembled Data

Software Display Format

Control Flow Display

Format

The Software display format shows only the first fetch of executed instructions.
Flushed cycles and extensions are not shown, even though they are part of the
executed instruction. Read extensions will be used to disassemble the instruction,
but will not be displayed as a separate cycle in the Software display format. Data
reads and writes are not displayed (see Figure 2–8 on page 2–22).

Out-of-order fetches are shown in the order the fetches are executed. An asterisk
indicates an out-of-order fetch. The sample number of the out-of-order fetch will
not be displayed if the previously executed instruction has a higher sample
number. The sample number of the out-of-order fetch will be displayed if the
previously executed instruction has a smaller sample number.

Since you cannot place the cursor on an instruction without a sample number,
you will not be able to scroll to some out-of-order fetch instructions. To scroll to
these instructions, you will have to switch to the Hardware display format. You
also cannot mark an out-of-order fetch in software mode; you must switch to
hardware mode.

The Control Flow display format shows only the first fetch of instructions that
change the flow of control.

Instructions that generate a change in the flow of control in the Socket 7
microprocessor are as follows:

CALL IRET RET
INT JMP RSM

Instructions that might generate a change in the flow of control in the Socket 7
microprocessor are as follows:

BOUND JL/JNGE JNP/JPO
DIV JLE/JNG JNS
IDIV JNB/JAE/JNC JO
INTO JNBE/JA JP/JPE
JB/JNAE/JC JNE/JNZ JS
JBE/JNA JNL/JGE LOOP
JCXZ/JECXZ JNLE/JG LOOPNZ/LOOPNE
JE/JZ JNO LOOPZ/LOOPE

If a conditional jump branches to an address that is reached sequentially (no
address break in the fetch sample), the disassembler cannot determine if the
branch was taken. If there are two conditional jump instructions close together
that branch to the same fetch line, then the disassembler may not be able to
determine which conditional jump was actually taken. You can use the mark
cycle function to correct the disassembly. Refer to Marking Cycles later in this
section.

TMS 109A Socket 7 Microprocessor Support

2–15

Acquiring and Viewing Disassembled Data

MMX. Instructions that generate a trap in the flow of control in the Socket 7
microprocessor are as follows:

INT IRET RSM
CALL RET

Instructions that might generate a conditional trap in the flow of control in the
Socket 7 microprocessor are as follows:

EMMS MOVD MOVQ PACKSSD
PACKSSWB PACKUSWB PADDB PADDD
PADDSB PADDSW PADDUSB PADDUSW
PADDW PAND PANDN PCMPEQB
PCMPEQD PCMPEQW PCMPGTB PCMPGTD
PCMPGTW PMADDWD PMULHW PMULLW
POR PSLLD PSLLQ PSLLW
PSRAD PSRAW PSRLD PSRLQ
PSRLW PSUBB PSUBD PSUBSB
PSUBSW PSUBUSB PSUBUSW PSUBW
PUNPCKHBW PUNPCKHDQ PUNPCKHWD PUNPCKLBW
PUNPCKLDQ PUNPCKLWD PXOR

Subroutine Display

Format

The Subroutine display format shows only the first fetch of subroutine call and
return instructions. It will display conditional subroutine calls if they are
considered to be taken.

Instructions that generate a subroutine call or a return in the Socket 7 micropro­cessor are as follows:

CALL INT IRET
RET RSM

Instructions that might generate a subroutine call or a return in the Socket 7
microprocessor are as follows:

BOUND DIV IDIV INTO

MMX. Instructions that generate a trap in the flow of control in the Socket 7
microprocessor are as follows:

INT IRET RSM
CALL RET

Instructions that might generate a conditional trap in the flow of control in the
Socket 7 microprocessor are as follows:

2–16

EMMS MOVD MOVQ PACKSSDW
PACKSSWB PACKUSWB PADDB PADDD
PADDSB PADDSW PADDUSB PADDUSW

TMS 109A Socket 7 Microprocessor Support

PADDW PAND PANDN PCMPEQB
PCMPEQD PCMPEQW PCMPGTB PCMPGTD
PCMPGTW PMADDWD PMULHW PMULLW
POR PSLLD PSLLQ PSLLW
PSRAD PSRAW PSRLD PSRLQ
PSRLW PSUBB PSUBD PSUBSB
PSUBSW PSUBUSB PSUBUSW PSUBW
PUNPCKHBW PUNPCKHDQ PUNPCKHWD PUNPCKLBW
PUNPCKLDQ PUNPCKLWD PXOR

Changing How Data is Displayed

There are common fields and features that allow you to further modify displayed
data to suit your needs. You can make common and optional display selections in
the Disassembly property page (the Disassembly Format Definition overlay).

You can make selections unique to the Socket 7 support to do the following
tasks:

Acquiring and Viewing Disassembled Data

Optional Display

Selections

H Change how data is displayed across all display formats
H Change the interpretation of disassembled cycles
H Display exception vectors

NOTE. All information defined in these fields pertain to the microprocessor that is
being traced.

You can make optional selections for disassembled

data. In addition to the

common selections (described in the information on basic operations), you can
change the displayed data in the following ways:

H Specify the code segment size
H Choose an interrupt table
H Specify the starting address of the interrupt table
H Specify the size of the interrupt table
H Select to trace the Primary or Dual microprocessor
H Choose whether to display or suppress the hardware cycles from the

microprocessor not being traced

TMS 109A Socket 7 Microprocessor Support

2–17

Acquiring and Viewing Disassembled Data

The Socket 7 support has six additional fields: Code Segment Size, Interrupt
Table, Interrupt Table Address, Interrupt Table Size, Trace Processor, and Other
Processor. These fields appear in the area indicated in the information on basic
operations.

Code Segment Size. You can select the default code size: 32-bit or 16-bit. The
default code size is 16 bit.

Interrupt Table. You can specify if the interrupt table is Real, Virtual, or Protected.
(Selecting Virtual is equivalent to selecting Protected.) The default is Real.

Interrupt Table Address. You can specify the starting address of the interrupt table
in hexadecimal. The default starting address is 0x00000000.

Interrupt Table Size. You can specify the size of the interrupt table in hexadecimal.
The default size is 0x400.

Dual Microprocessors

Execution Tracing

Trace Processor. You can select to disassemble data from the Primary or Dual

microprocessor. The default is Primary.

Processor. You can specify either Intel or AMD depending on the socket7
processor that is under test. The
both these microprocessor venders.

Other Processor. The “other” microprocessor is the one not being traced (not
selected in the Trace Processor field). You can select to display or to suppress its
bus cycles.

When acquiring data from a system under test with two microprocessors, the
disassembler can trace the execution flow of one microprocessor and display the
hardware cycle types of the microprocessor not being traced. This means that the
software disassembles only the instructions executed from the microprocessor
being traced.

You can trace instructions from either the Primary microprocessor or the Dual
microprocessor. You can also choose to display or not display (suppress) data
from the microprocessor not selected in the Trace Processor field of the
Disassembly property page (Disassembly Format Definition overlay).

TMS 109A Socket 7 support has been tested with

2–18

To set up the mode of tracing, you need to set the Trace Processor and Other
Processor fields in the Disassembly property page. Table 2–4 shows the
combinations of Trace Processor and Other Processor field selections and their
effects.

TMS 109A Socket 7 Microprocessor Support

Acquiring and Viewing Disassembled Data

T able 2–4: Trace Processor and Other Processor field selections

Trace processor Other processor Effect

Primary Suppress Disassemble the Primary microprocessor only
Primary Display Cycles Disassemble the Primary microprocessor and

display the hardware cycles of the Dual

microprocessor
Dual Suppress Disassemble the Dual microprocessor only
Dual Display Cycles Disassemble the Dual microprocessor and

display the hardware cycles of the Primary

microprocessor

Figure 2–4 shows disassembled data from the Primary microprocessor and
hardware cycles from the other microprocessor. A hyphen to the left of the
mnemonic indicates data from the other microprocessor.

Sample Address Data Mnemonic Control

-------------------------------------------------------------------------------­16 000388B0 ABFFE1C3 RETS (32) P_FETCH

000388B4 B6EFFFEF ( FLUSH ) P_FETCH

17 000408A8 ED33D233 - ( DUAL FETCH ) D_FETCH

000408AC FF33F633 - ( DUAL FETCH ) D_FETCH

18 000388B8 FFB7D7FA ( FLUSH ) P_FETCH

000388BC FFFFFDFF ( FLUSH ) P_FETCH

19 000408B0 BDDF26C3 - ( DUAL FETCH ) D_FETCH

000408B4 FF27FFBF - ( DUAL FETCH ) D_FETCH
20 000207F4 00000005 ( MEM READ ) P_MEM_RD
21 000408B8 5DBE5FED - ( DUAL FETCH ) D_FETCH

000408BC 7FFEFBFB - ( DUAL FETCH ) D_FETCH
22 000388C0 44875050 ( FLUSH ) P_FETCH

000388C4 04870824 ( FLUSH ) P_FETCH
23 000307F4 00000005 - ( MEM READ ) D_MEM_RD
24 00038800 00009DE8 ( FLUSH ) P_FETCH

00038805 000EBE00 MOV ESI,#0000000E (32) P_FETCH

25 000408C0 44875050 - ( DUAL FETCH ) D_FETCH

000408C4 04870824 - ( DUAL FETCH ) D_FETCH
26 0003880A 0AB90000 MOV ECX,#0000000A (32) P_FETCH

0003880F F3000000 REPZ (32) P_FETCH

Figure 2–4: Data displayed from the Primary and Dual microprocessors

TMS 109A Socket 7 Microprocessor Support

2–19

Acquiring and Viewing Disassembled Data

Figure 2–5 shows disassembled data from the Primary microprocessor only. Data
from the Dual microprocessor is suppressed and not displayed.

Sample Address Data Mnemonic Control

-------------------------------------------------------------------------------­16 000388B0 ABFFE1C3 RETS (32) P_FETCH

000388B4 B6EFFFEF ( FLUSH ) P_FETCH

18 000388B8 FFB7D7FA ( FLUSH ) P_FETCH

000388BC FFFFFDFF ( FLUSH ) P_FETCH
20 000207F4 00000005 ( MEM READ ) P_MEM_RD
22 000388C0 44875050 ( FLUSH ) P_FETCH

000388C4 04870824 ( FLUSH ) P_FETCH
24 00038800 00009DE8 ( FLUSH ) P_FETCH

00038805 000EBE00 MOV ESI,#0000000E (32) P_FETCH
26 0003880A 0AB90000 MOV ECX,#0000000A (32) P_FETCH

0003880F F3000000 REPZ (32) P_FETCH
28 00038810 003668AD LODSD (32) P_FETCH

00038811 003668AD PUSH #00000036 (32) P_FETCH

00038816 026A0000 PUSH #02 (32) P_FETCH
30 00038818 4668026A PUSH #02 (32) P_FETCH

0003881A 4668026A PUSH #00000046 (32) P_FETCH

0003881F 6A000000 PUSH #02 (32) P_FETCH

Figure 2–5: Disassembled data displayed from the Primary microprocessor only

Figure 2–6 shows disassembled data from the Dual microprocessor only. Data
from the Primary microprocessor is suppressed and not displayed.

Sample Address Data Mnemonic Control

-------------------------------------------------------------------------------­17 000408A8 ED33D233 XOR EDX,EDX (32) D_FETCH

000408AA ED33D233 XOR EBP,EBP (32) D_FETCH
000408AC FF33F633 XOR ESI,ESI (32) D_FETCH
000408AE FF33F633 XOR EDI,EDI (32) D_FETCH

19 000408B0 BDDF26C3 RETS (32) D_FETCH

000408B4 FF27FFBF ( FLUSH ) D_FETCH

21 000408B8 5DBE5FED ( FLUSH ) D_FETCH

000408BC 7FFEFBFB ( FLUSH ) D_FETCH
23 000307F4 00000005 ( MEM READ ) D_MEM_RD
25 000408C0 44875050 ( FLUSH ) D_FETCH

000408C4 04870824 ( FLUSH ) D_FETCH
27 00040800 00009DE8 ( FLUSH ) D_FETCH

00040805 000EBE00 MOV ESI,#0000000E (32) D_FETCH
29 0004080A 0AB90000 MOV ECX,#0000000A (32) D_FETCH

0004080F F3000000 REPZ (32) D_FETCH

Figure 2–6: Disassembled data displayed from the Dual microprocessor only

2–20

TMS 109A Socket 7 Microprocessor Support

Acquiring and Viewing Disassembled Data

Branch Trace Messages

Out-Of-Order Fetches

The disassembler interprets the information on the Address and Data Bus of
Branch Trace Messages (BTMs) by reconstructing the address of the source or
target of the branch instruction. Depending on which type of BTM is in use,
either fast or normal, one or two BTMs will appear on the bus. The disassembler
tracks BTMs as they appear on the bus. Figure 2–7 shows how the disassembler
displays these cycles.

Sample Address Data Mnemonic Control

-------------------------------------------------------------------------------­4 000207F4 00000005 ( MEM WRITE) P_MEM_WR
6 00038810 003868AD ( FLUSH ) P_FETCH

00038814 026A0000 ( FLUSH ) P_FETCH

8 000388A2 20------ ( BRANCH TRACE: TARGET ) P_SPECIAL

10 00038800 08------ ( BRANCH TRACE: SOURCE ) P_SPECIAL
14 00038818 33C03300 ( FLUSH ) P_FETCH

00038810 68C933DB ( FLUSH ) P_FETCH

Figure 2–7: Display of target and source Branch Trace Messages

The Socket 7 microprocessor can prefetch cycles out of ascending order. For
example, a branch to address 1008 could cause the following sample of addresses
across the bus: 1008, 1000, 1018, and 1010. The data at address 1008 is
executed, but the data at address 1000 is not. The data at addresses 1018 and
1010 are executed, but the data at address 1010 is executed before the data at

1018.
An example of the Intel fetched order versus the executed order is shown below.

Fetched Order Executed Order
1008 1008
1000 1010
1018 1018
1010

The AMD socket has an out-of-order bus. An example of the AMD fetched order
versus the executed order is shown below.

Fetched Order Executed Order
1018 1000
1010 1008
1008 1010
1000 1018

In the Hardware display format, the out-of-order fetches are displayed in the
order they are fetched. They will be properly disassembled and identified by an
asterisk (*) to the left of the instruction (see Figure 2–9 on page 2–23).

TMS 109A Socket 7 Microprocessor Support

2–21

Acquiring and Viewing Disassembled Data

In the Hardware display format, you can determine the executed order of the
out-of-order fetches by looking at the address of the out-of-order cycles and the
subsequent cycles. Fetch cycles always have the sample numbers displayed.

In the Software display format, out-of-order fetches are displayed in the order
they were executed (see Figure 2–8). If the previously executed instruction had a
larger sample number than the out-of-order fetch, the sample number will not be
displayed. If the previous sample number is smaller than the out-of-order fetch,
the sample number will be displayed. To mark an instruction without a sample
number, switch to the Hardware display format (see Figure 2–9 on page 2–23).

Figure 2–8: Software display for the AMD Bus cycles

2–22

TMS 109A Socket 7 Microprocessor Support

Acquiring and Viewing Disassembled Data

Figure 2–9: Hardware display for the AMD Bus cycles

Speculative Prefetch

Cycles

TMS 109A Socket 7 Microprocessor Support

Speculative prefetch cycles can occur when the Socket 7 microprocessor fetches
instructions that have been previously executed. To minimize prefetch delays, the
Socket 7 microprocessor predicts the outcome of the branch instruction and starts
prefetching at that address. When the branch instruction is executed, the target
address is determined. If the Socket 7 microprocessor predicted the target address
correctly, then the needed code has already been fetched. If it did not correctly
predict the target address, then the speculative prefetch cycles that had been
fetched will be flushed and fetching will begin at the target address.

Figure 2–10 shows an example of speculative prefetch cycles. The previous time
(not shown) that the JNE instruction was executed, the branch was taken and the
new target address was 0x3893D. The microprocessor assumed that the address
would be 0x3893D and so started fetching at 0x38938 (which contains
0x3893D). Cycles at samples 746 and 748 are speculative prefetch cycles. When
the instruction was executed, the microprocessor determined that the branch was

2–23

Acquiring and Viewing Disassembled Data

not taken, flushed the speculative prefetch cycles, and started fetching at
0x38988 (sample 750), which contained the next instruction after the JNE.

Sample Address Data Mnemonic Control

--------------------------------------------------------------------------------

734 000207D8 00000008 ( MEM READ ) P_MEM_RD
736 000207E8 00000046 ( MEM READ ) P_MEM_RD
738 00038988 000000BA ( FLUSH ) P_FETCH

740 00038990 20C2619D ( FLUSH ) P_FETCH

742 00038998 CDBFDE6F ( FLUSH ) P_FETCH

744 000389A0 FFFFEDAE ( FLUSH ) P_FETCH

746 00038938 DB9BFF33 ( FLUSH ) P_FETCH

748 00038940 6D8A0000 ( FLUSH ) P_FETCH

750 00038988 000000BA MOV EDX,#00000000 (32) P_FETCH

00038986 B575C90F JNE 0003893D (32) P_FETCH

0003898C 24558900 ( FLUSH ) P_FETCH

00038994 6FBF6D00 ( FLUSH ) P_FETCH

0003899C FFEFFFF7 ( FLUSH ) P_FETCH

000389A4 F6FFF7EF ( FLUSH ) P_FETCH

0003893C 0002A3E3 ( FLUSH ) P_FETCH

00038944 204D8A10 ( FLUSH ) P_FETCH

0003898D 24558900 MOV 24[EBP],EDX (32) P_FETCH

Cache Invalidation Cycles

Burst Cycles

Figure 2–10: Speculative Prefetch cycles

NOTE. The microprocessor also has a Branch Target Buffer and often performs
speculative prefetching of branch target addresses (no matter if they are taken or
are not taken). The disassembler usually interprets the correct flow of execution
but cannot do so deterministically.

Cache Invalidation cycles are needed to keep the microprocessor cache contents
consistent with external memory. On a nonburst cycle that is also a Cache
Invalidation cycle, the data and address will be valid as probed. On a burst cycle
that is also a Cache Invalidation cycle, the data will be valid, but the addresses
will not be valid as probed and the software will try to calculate the address from
the surrounding cycles. Fetch cycles are disassembled. A letter c to the left of the
mnemonic indicates a Cache Invalidation cycle, where the AHOLD signal was
active.

On all burst cycles, only the first cycle contains a valid address. The Socket 7
microprocessor does not increment the address for a burst. The disassembler
calculates the remaining burst cycle addresses for display.

System Management

2–24

Mode (SMM)

The Socket 7 microprocessor provides a special mode called System Manage­ment Mode where the Socket 7 microprocessor CPU executes code from a

TMS 109A Socket 7 Microprocessor Support

Acquiring and Viewing Disassembled Data

separate, alternate memory space called SMRAM. The disassembler uses
information from the SMIACT# signal to determine when the Socket 7 micropro­cessor is operating in this mode.

MMX Instruction Set

3DNow!

Marking Cycles

The Socket 7 microprocessor includes the MMX instruction set. Since these
instructions are potential subroutine instructions, the disassembler checks to see
if an interrupt level 6 (illegal opcode) or 7 (device not available) occurred. If an
interrupt 6 or 7 occurs, the interrupt will flush the bus.

When the disassembler detects that an instruction is from the MMX set, it
displays an (MMX) to the right of the mnemonic.

MMX instructions are disassembled whether or not the microprocessor is set up
to execute them.

The Socket 7 microprocessor includes the 3DNow! instruction set which support

AMD-K6-2. When the disassembly detects that an instruction is from the 3DNow!

set, it displays (3DNow!) to the right of the mnemonics.

The disassembler has a Mark Opcode function that allows you to change the
interpretation of a cycle type. Using this function, you can select a cycle and
change it to one of the following cycle types:

H Opcode & Flush Previous (marks the first word of an instruction and the

lower bytes of this cycle as flushed)

H Opcode ( marks the first word of an instruction)

s

H Flush to end (flushes the current byte to the high end of the sample)
H Flush (marks an opcode or extension that is fetched but not executed)
H Undo (clears all marks on this byte)
H Flush Cycle (the entire cycle was fetched, but not executed (opcode or

extension))
H 16-bit or 32-bit default segment size
Mark selections are as follows:

Lo: -- -- -- 00

Lo: -- -- 11 --

Lo: -- 22 -- --

Lo: 33 -- -- --

Hi: -- -- -- 44

Hi: -- -- 55 --

Hi: -- 66 -- --

TMS 109A Socket 7 Microprocessor Support

2–25

Acquiring and Viewing Disassembled Data

Hi: 77 -- -- -­FLUSH CYCLE
16Ćbit Default Segment Size
32Ćbit Default Segment Size
Undo marks on this cycle

You can use the Mark Opcode function to specify the default segment size mode
(16-bit or 32-bit) for the cycle. The segment size selection changes the cycle the
cursor is on and the remaining cycles to the end of memory or to the next mark.

The default segment size of the cycle is independent of any prefix override bytes
in the particular fetch. For example, if you mark cycle 455 with a default size of
32 bits, but there are address/operand override prefixes in the instruction, the
default size will be 32 bits but the size of the instruction will be 16 bits.

Only one selection can be made at a time. If the you want to mark both the
opcode and default size of a particular cycle, it must be done in two different
steps.

When marking opcodes of out-of-order fetches, and displaying in Software
mode, and an out-of-order fetch does not have a sequence number, you must
switch to hardware mode to mark that sequence. See Out-Of-Order Fetches on
page 2–21 and Software Display Format on page 2–15.

Displaying Exception

Vectors

Information on basic operations contains more details on marking cycles.

The disassembler can display exception vectors. You can select to display the
interrupt vectors for Real, Virtual, or Protected modes in the Interrupt Table field.
(Selecting Virtual is equivalent to selecting Protected.)

You can relocate the table by entering the starting address in the Interrupt Table
Address field. The Interrupt Table Address field provides the disassembler with
the offset address; enter an eight-digit hexadecimal value corresponding to the
offset of the base address of the exception table. The Interrupt Table Size field
lets you specify a three-digit hexadecimal size for the table.

You can make these selections in the Disassembly property page (the Disassem­bly Format Definition overlay).

Table 2–5 lists the Socket 7 exception vectors for the Real Addressing mode.

T able 2–5: Exception vectors for Real Addressing mode

Exception
number

0 0000
1 0004
2 0008

Location in IV* table

(in hexadecimal)

Displayed interrupt name

DIVIDE ERROR

DEBUG EXCEPTIONS

NMI INTERRUPT

2–26

TMS 109A Socket 7 Microprocessor Support

Acquiring and Viewing Disassembled Data

T able 2–5: Exception vectors for Real Addressing mode (cont.)

Exception
number

3 000C
4 0010
5 0014
6 0018
7 001C
8 0020
9 0024
10 0028
11 002C
12 0030
13 0034
14-15 0038-003C
16 0040
17-31 0044-007C
32-255 0080-03FC

* IV means interrupt vector.

Location in IV* table

(in hexadecimal)

Displayed interrupt name

 

  

  

 

  

 







 

 



 



 

Table 2–6 lists the Socket 7 exception vectors for the Protected Addressing
mode.

T able 2–6: Exception vectors for Protected Addressing mode

Exception
number

0 0000
1 0008
2 0010
3 0018
4 0020
5 0028
6 0030
7 0038
8 0040
9 0048
10 0050
11 0058

TMS 109A Socket 7 Microprocessor Support

Location in IDT*
(in hexadecimal)

Displayed exception name

 

 

 

 

  

  

 

  

 



 

  

2–27

Acquiring and Viewing Disassembled Data

T able 2–6: Exception vectors for Protected Addressing mode (cont.)

Exception
number

12 0060
13 0068
14 0070
15 0078
16 0080
17 0088
18 0090

19-31 0090-00F8
32-255 0100-07F8

* IDT means interrupt descriptor table.

Location in IDT*
(in hexadecimal)

Viewing an Example of Disassembled Data

A demonstration system file (or demonstration reference memory) is provided so
you can see an example of how your Socket 7 microprocessor bus cycles and
instruction mnemonics look when they are disassembled. Viewing the system file
is not a requirement for preparing the module for use and you can view it without
connecting the logic analyzer to your system under test.

Displayed exception name

 

 

 



 

 

 



 

2–28

Information on basic operations describes how to view the file.

TMS 109A Socket 7 Microprocessor Support

Specifications

Specifications

This chapter contains the following information:

H Probe adapter description
H Specification tables
H Dimensions of the probe adapter

Probe Adapter Description

The probe adapter is nonintrusive hardware that allows the logic analyzer to
acquire data from a microprocessor in its own operating environment with little
effect, if any, on that system. Information on basic operations contains a figure
showing the logic analyzer connected to a typical probe adapter. Refer to that
figure while reading the following description.

The probe adapter consists of a circuit board and two sockets for a Socket 7
microprocessor. The probe adapter connects to the microprocessor in the system
under test. Signals from the microprocessor-based system flow from the probe
adapter to the channel groups and through the probe signal leads to the module.

All circuitry on the probe adapter is powered from the supplied power adapter.
The probe adapter accommodates the Intel Pentium, low-power embedded

Pentium with MMX technology, and Socket 7 microprocessors devices.

TMS 109A Socket 7 Microprocessor Support

3–1

Specifications

Specifications

These specifications are for a probe adapter connected between a compatible
Tektronix logic analyzer and a system under test. Table 3–1 shows the electrical
requirements the system under test must produce for the support to acquire
correct data.

In Table 3–1 one podlet load is 20 kW in parallel with 2 pF.

T able 3–1: Electrical specifications

Characteristics Requirements

System under test DC power requirements

Voltage 4.75 – 5.25 VDC
Current I maximum (calculated) 1.8 A

I typical (measured)1.2 A

Probe adapter power supply requirements

Voltage 90 – 265 VAC
Current 1.1 A maximum at 100 VAC
Frequency 47 – 63 Hz
Power 25 W maximum

System under test clock

Clock rate
Tested cock rate

Maximum 100 MHz

Maximum 100 MHz
Minimum setup time required 3.0 ns
Minimum hold time required 0 ns

AC load DC load

Measured typical SUT signal loading

CLK
ADS#, ADSC#, W/R#, BRDY#, HLDA,

BE7–0#, BOFF#
RESET 5 pF 1 22LV10
All other signals 2 pF 1 22LV10

25 pF 1 CDC2510B|| (500ohms+30pF)

5 pF 1 22LV10

3–2

TMS 109A Socket 7 Microprocessor Support

Table 3–2 shows the environmental specifications.

T able 3–2: Environmental specifications*

Characteristic Description

Temperature

Specifications

Maximum operating
Minimum operating 0° C (+32° F)

Non-operating –55° C to +75° C (–67° to +167° F)
Humidity 10 to 95% relative humidity
Altitude

Operating 4.5 km (15,000 ft) maximum

Non-operating 15 km (50,000 ft) maximum
Electrostatic immunity The probe adapter is static sensitive

* Designed to meet Tektronix standard 062-2847-00 class 5.

[

Not to exceed Socket 7 microprocessor thermal considerations. Forced air cooling
might be required across the CPU.

+50° C (+122° F)[

TMS 109A Socket 7 Microprocessor Support

3–3

Specifications

Figure 3–1 shows the dimensions of the probe adapter.

51.05 mm
(2.010 in)

40.64 mm
(1.600 in)

118.87 mm
(4.680 in)

Pin A3

6.60 mm (.260 in)

Figure 3–1: Dimensions of the probe adapter

121.41 mm
(4.780 in)

3–4

TMS 109A Socket 7 Microprocessor Support

WARNING

The following servicing instructions are for use only by qualified personnel. To
avoid injury, do not perform any servicing other than that stated in the operating
instructions unless you are qualified to do so. Refer to all Safety Summaries
before performing any service.

Maintenance

Maintenance

This chapter contains information on the following topics:

H Probe adapter circuit description
H How to replace a fuse

Probe Adapter Circuit Description

The active components on the probe adapter are: five GAL 22V10D PALs for
signal synthesis, one LM3940ISX for 5 V to 3.3 V conversion, and one
PPL-Buffer and one PLL (phase locked loop) low-skew clock generator for clock
distribution with buffer.

The PALs implement three sequential state machines that monitor the Socket 7
microprocessor bus and generate three important signals:

H PIPED_D indicates Socket 7 microprocessor bus pipelining is occurring
H LAST_D indicates the end of a Socket 7 microprocessor bus cycle
H DVALID_D indicates valid data is present on the Socket 7 microprocessor

data bus

These signals are required for the Clocking State Machine (CSM) of the logic
analyzer to accurately strobe addresses and data information from the Socket 7
microprocessor bus.

The CSM is tightly linked to the processor bus T-states and is synchronized to the
Socket 7 microprocessor on a clock by clock basis. It is possible that unpredict­able bus behavior by an alternate bus master may cause the bus tracking
machines to lose track of the bus. If this occurs, the bus tracking mechanism will
automatically re-synchronize and reset itself when the Socket 7 microprocessor
exits bus back off or bus hold.

If resynchronizing and reseting the bus tracking machines is not adequate,
jumper J920 will disable the bus tracking PALs during any alternate bus master
(HLDA) cycle or back off (BOFF #) cycle. If you disable the bus tracking PALs,
acquisition of back off or hold cycles are inhibited, and one sample containing
unusable information is recorded to show a cycle occurred.

A 20-pin connector, Intel In-Target Probe (ITP), is located on the probe adapter.
Your system under test has system reset circuitry that can not be accessed
through the SPGA socket, but you may connect the DBRESET signal (or the
active low, open collector version OC_DBRESET*) to your system reset
circuitry externally.

TMS 109A Socket 7 Microprocessor Support

4–1

Maintenance

A PLL clock generator is used to provide eight, zero-delay copies of the Socket 7
microprocessor CLK input that are distributed to the PALs. Lock time after VCC
is a 500 mS maximum, the clock is stable before any Socket 7 microprocessor bus
cycles start. Table 4–1 lists Socket 7 signal delays when using the probe adapter.

T able 4–1: Socket 7 signal delays using the probe adapter

Signal name Hardware CLK delays Firmware CLK delays

Replacing the Fuse

A31:3, D63:0, BE7-0#,
D/C#, M/IO#, PRDY,
LOCK#, BUSCHK#,
SMIACT#, INIT , SCYC,
D/P#, AHOLD

HLDA, ADS#, BRDY# 2 0
BOFF# 2 1
RESET, NA# 1 0
W/R# 2 1

0 2

If the fuse on the Socket 7 probe adapter opens (burns out), you can replace it
with a 5 A, 125 V fuse. Figure 4–1 shows the location of the fuse on the probe
adapter board.

Fuse

Figure 4–1: Location of the fuse on the probe adapter

4–2 TMS 109A Socket 7 Microprocessor Support

Diagrams

Diagrams and Circuit Board Illustrations

This section contains the troubleshooting procedures, block diagrams, circuit board
illustrations, component locator tables, waveform illustrations, and schematic diagrams.

Symbols

Graphic symbols and class designation letters are based on ANSI Standard Y32.2-1975.
Abbreviations are based on ANSI Y1.1-1972.

Logic symbology is based on ANSI/IEEE Standard 91-1984 in terms of positive logic.
Logic symbols depict the logic function performed and can differ from the manufacturer’s
data.

The Tilde (~) after a signal name indicates that the signal performs its intended function
when in the low state.

Other standards used in the preparation of diagrams by Tektronix, Inc., include the
following:

H Tektronix Standard 062-2476 Symbols and Practices for Schematic Drafting
H ANSI Y14.159-1971 Interconnection Diagrams
H ANSI Y32.16-1975 Reference Designations for Electronic Equipment

Locator Grid

Function Block Title

Internal Screw Adjustment

Onboard Jumper

Digital Ground

Refer to Assembly

& Diagram Number

Offboard Connector

Active Low Signal

Signal From

Another Diagram,

Same Board

A

B

12 3

Component Locator Diagrams

The schematic diagram and circuit board component location illustrations have grids
marked on them. The component lookup tables refer to these grids to help you locate a
component. The circuit board illustration appears only once; its lookup table lists the
diagram number of all diagrams on which the circuitry appears.

Some of the circuit board component location illustrations are expanded and divided into
several parts to make it easier for you to locate small components. To determine which
part of the whole locator diagram you are looking at, refer to the small locator key shown
below. The gray block, within the larger circuit board outline, shows where that part fits
in the whole locator diagram. Each part in the key is labeled with an identifying letter that
appears in the figure titles under component locator diagrams.

4

  
 

Power Termination

Component on back of board

Strap
Panel Control

Female Coaxial
Connector

Heat Sink
Decoupled Voltage

Diagram Number
Assembly Number

Diagram Name

H MIL-HDBK-63038-1A Military Standard Technical Manual Writing Handbook

Component Values

Electrical components shown on the diagrams are in the following units unless noted
otherwise:

Capacitors: Values one or greater are in picofarads (pF).

Values less than one are in microfarads (F).

Resistors: Values are in Ohms (W).

Graphic Items and Special Symbols Used in This Manual

Each assembly in the instrument is assigned an assembly number (for example A5). The
assembly number appears in the title on the diagram, in the lookup table for the schematic
diagram, and corresponding component locator illustration. The Replaceable Electrical
Parts list is arranged by assembly in numerical sequence; the components are listed by
component number.

Section of Circuit

Board Shown

A B

DC

TMS 109A Socket 7 Hardware Support

5–1

5–2

TMS 109A Socket 7 Hardware Support

TMS 109A Socket 7 Microprocessor Support

5–3

5–4

A1 Socket 7 Circuit Board (Front)

COMPONENT NUMBER EXAMPLE



A23 A2 R1234





#     "
!$      



  








A1 Socket 7 Circuit Board (Back)

TMS 109A Socket 7 Microprocessor Support

21 34 65

12

10

6

8

4

30

11

7

3

1617181920

151413

9

5

28

29

25

31

P_ADDRESS<31..3>

2A1<

29

5

A

41

22
18
15

43

B

20
16
13
11

47
45

38
36
34
32
31
29
27
25

24
21
17

C

14
10
9
50
48
44
40
39
37
35
33

30
28
26
23
19

12
8

U340

A3
A5
A7
A9
A11
A13
A15
A17
A19
A21
A23
A25
A27
A29
A31
A33
A35
A37
B2
B4
B6
B8
B10
B12
B14
B16
B18
B20
B22
B24
B26
B28
B30
B32
B34
B36
C1
C3

C7
C9
C11
C13
C15
C17
C19
C21
C23
C25
C27
C29
C31
C33
C35
C37
D2
D4
D6

D10
D12
D14
D16
D18
D20
D22
D24
D26
D28
D30
D32
D34
D36

A3
A5
A7
A9
A11
A13
A15
A17
A19
A21
A23
A25
A27
A29
A31
A33
A35
A37
B2
B4
B6
B8
B10
B12
B14
B16
B18
B20
B22
B24
B26
B28
B30
B32
B34
B36
C1
C3
C5
C7
C9
C11
C13
C15
C17
C19
C21
C23
C25
C27
C29
C31
C33
C35
C37
D2
D4
D6
D8
D10
D12
D14
D16
D18
D20
D22
D24
D26
D28
D30
D32
D34
D36

AN37

AN35

AN37

E3

E1

AN33

AN31

AN35

AN33

E3E1E7

E5

E5X2E7

AN29

AN31

AN29

E9

E9

AN27

AN25

AN27

E11

E11

E13

AN23

AN25

AN23

E13

E15

E15

AN21

AN19

AN21

E17

E17

E19

AN17

AN19

AN17

E19

E21

E21

AN15

AN13

AN15

E23

E23

E25

AN11

AN13

AN11

E25

E27

E27

AN9

AN9

E29

E29

AN7

AN7

E31

E31

AN5

E33

AN1

AN3

AN5

AN3

AN1

E33

E35

E37F2F4F6F34

E37

E35

AM36

AM34

AM36

AM34

AM32

AM30

AM28

AM32

AM30

AM28

F36G1G5G3G33

F36

F34

F6F4F2

AM26

AM24

AM26

AM24

AM22

AM20

AM22

AM20

G33

G5G3G1

AM18

AM16

AM18

AM16

G35H4H2

G37

G35

G37

AM12

AM14

AM14

AM12

H4

H2

AM10

AM8

AM6

AM4

AM10

AM8

AM6

H34

H36J1J5J3J33

H34

H36

AM4

AM2

AM2

J5J3J1

AL37

AL37

J33

AL35

AL33

AL35

AL33

J35K4K2

J37

J35

J37

AL31

AL29

AL31

K4

K2

AL27

AL29

K34

AL25

AL27

AL25

K34

K36L1L5

K36

AL23

AL23

AL21

AL19

AL21

L3

L5L3L1

AL19

24

AL17

AL17

L33

L33

AL15

AL15

L35

L35

18

AL13

AL13

L37M4M2

L37

202216

AL11

AL11

M2

AL9

AL9

M4

3

AL7

AL7

M34

M34

AL3

AL5

AL5

AL3

M36N1N3

M36

AL1

AL1

AK36

AK34

AK36

N5N3N1

N33

AK32

AK34

AK32

N33N5N35

N35

AK28

AK30

AK30

N37

N37

AK28

14

AK24

AK26

AK22

AK20

AK26

AK24

AK22

AK20

P34

P4P2P36Q1Q3

P34

Q1

P4D8P2

P36

15

27

AK18

AK16

AK18

Q3

Q5

17

AK14

AK16

AK14

Q33Q5Q35

Q33

19

21

AK10

AK12

AK12

Q37

Q35

AK8

AK10

AK8

Q37

R2

AK6

R4

1

AK4

AJ37

AK2

AK6

AK4

AK2

AJ37

R34

R4R2R36S1S3

R34

R36

AJ35

AJ35

AJ31

AJ33

AJ33

S5S3S1

S33

AJ31

S33S5S35

AJ29

AJ27

AJ25

AJ23

AJ29

AJ27

AJ23

AJ25

S37

T4T2T36U5U33

T4C5T2

S35

S37

AJ21

AJ19

AJ15

AJ17

AJ13

AJ11

AJ21

AJ19

AJ13

AJ11

AJ15

AJ17

T34

U1U3U35V2V4

U5U3U1

T34

T36

U33

AJ9

AJ9

U35

AJ7

AJ7

U37

U37

11

AJ5

AJ5

V36

V36

12

AJ3

AJ3

V34

V34

AJ1

AJ1

V4

AH36

AH36

AH34

AH34

AH32

AH32

AH4

AH4

AH2

AH2

AG37

AG37

AG35

AG35

AG33

AG33

AG5

AG5

AG3

AG3

AG1

AG1

AF36

AF36

AF34

AF34

AF4

AF4

AF2

AF2

AE37

AE37

AE35

AE35

AE33

AE33

AE5

AE5

AE3

AE3

AE1

AE1

AD36

AD36

AD34

AD34

AD4

AD4

AD2

AD2

AC37

AC37

AC35

AC35

AC33

AC33

AC5

AC5

AC3

AC3

AC1

AC1

AB36

AB36

AB34

AB34

AB4

AB4

AB2

AB2

AA37

AA37

AA35

AA35

AA33

AA33

AA5

AA5

AA3

AA3

AA1

AA1

Z36

Z36

Z34

Z34

Z4

Z4

Z2

Z2

Y37

Y37

Y35

Y35

Y33

Y33

Y5

Y5

Y3

Y3

Y1

Y1

X36

X36

X34

X34

X4

X4
X2

W37

W37

W35

W35

W33

W33

W5

W5

W3

W3

W1

W1

V2

22
26

9

24
27

10

21

23

23

31

2

7

13

6
30

4

28

D

TMS 109A Socket 7 Microprocessor Support

8

33

323534

7

42

46

49

525354

6

4

5

3

51

1

55

56

2

0

59

58

57

606261

63

36

25

26

P_CONTROL<36..1>

P_DATA<63..0>

SOCKET7

A1

2A1<

2A1<

1

5–5

5–6

TMS 109A Socket 7 Microprocessor Support

21 34 65

P_CONTROL<36..1> R_CONTROL<36..1>

1D6>

A

B

C

D

P_DATA<63..0>

1D6>

P_ADDRESS<31..3>

1A6>

R_DATA<63..0>

R_ADDRESS<31..3>

R482

180 OHM

R781

63

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

R771

R770

R771

R771

R770

R761

R770

R761

R761

R761

R760

R760

R760

R760

R752

R752

R752

R682

R780

R682

R682

R781

R780

R682

R780

R781

R781

R771

3

81

4

63

5

54

6

63

7

72

8

72

9

54

10

81

11

63

12

54

13

81

14

72

15

63

16

54

17

81

18

72

19

63

20

72

21

81

22

81

23

63

24

81

25

72

26

54

27

63

28

54

29

72

30

72 81

31

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31 31

11

R482

R482

R481

R481

R480

R480

R480

R380

R380

R380

R480

R371

R371

R380

R371

R370

R371

R361

R370

R370

R370

R361

R361

R360

R361

R360

R360

R352

R360

R352 R531

R481

00

72

2

81

3

81

4

72

5

54

6

63

7

72

8

54

9

63

10

72

11

81

12

54

13

63

14

81

15

81

16

54

17

72

18

54

19

72

20

81

21

63

22

72

23

63

24

54

25

81

26

72

27

63

28

54

29

81

30

6363

54

C0820

C0750

1

1

2

2

.01UF

.01UF

1

2

R352

R352

R351

R351

R351

R351

R350

R350

R350

R340

R350

R340

R341

R341

R341

R340

R340

R341

R430

R430

R430

R431

R430

R431

R431

R431

R530

R530

R530

R531

R530

C0840

.01UF

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

60

61

62

63 63

59 59

+3.3V

C0850

1

2

.01UF

72

63

54

81

72

72

54

81

54

63

63

63

81

54

81

72

72

54

81

63

54

72

63

72

81

54

81

72

54

63

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

60

61 30

1

C0952
.1UF

2

R730

818163

63

54

81

81

63

81

54

81

63

72

81

54

63

81

72

63

54

81

72

63

72

54

63

81

72

63

54

63

54

81

54

C0721
.1UF

1

2

3

4

5

6

8

9

10

11

12

13

14

15

16

17

18

19

20

2121

22

24

25

26

27

28

29

30

313162

3232

1

C0950
.1UF

2

1

2

3

4

5

6

8

9

10

11

12

13

14

15

16

17

18

19

20

22

24

25

26

27

28

29

23 23

77

15 15

C0422
.1UF

212

1

C0520
.1UF

R631

R741

R533

R740

R630

R531

R730

R631

R730

R730

R630

R752

R751

R750

R750

R750

R750

R741

R741

R741

R751

R533

R533

R751

R533

R740

R630

R681

R580

R681

R681

R751

1

2

33

34

35

36

1

C0951
.1UF

2

180 OHM180 OHM180 OHM180 OHM

R580

72

R580

R482

R531

1

C0860
.1UF

2

33

63

34

54

35

72

36

5V => 3.3V CONVERTER

C0620

U230
LM3940

IN OUT

GND2GND1

24

C420

47UF

31

1

C421

47UF

2

VCC

1

1

2

C0930
.1UF

2

1

C330
.1UF

2

VCC

J110

1

+3.3V

1

1

C0881
.1UF

2

2

2
3

C0720
.1UF

5A
120V

1

2

F200

C0880
.1UF

21

CR310

1

2

C0861
.1UF

1

2

1

2

POWER ON

C0423
.1UF

CR320
LED1SMA

13

1

2

0.47UF

C0920
.1UF

C410

1

2

1

2

R0320
475 OHMS

1

.1UF

2

+3.3V

1A

4A1< 3A1<

4B1<

4B1<

TMS 109A Socket 7 Microprocessor Support

RES_PACK

A1

1

2

5–7

5–8

TMS 109A Socket 7 Microprocessor Support

21 34 65

2A6>

A

MFG_TEST

B

C

D

R_CONTROL<36..1>

+3.3V

1

2

3.32K

J240

2

1

1

2

3.32K

+3.3V

R0820

4.75K

NORM

R0840

SYNTH

J921

213

R240

3.32K

J920

+3.3V

1

2

R250

SYNTH_EN

213

ALT_INH

+3.3V

1

R0940

3.32K

2

FREQ SELECTOR

+3.3V

1

2

J250

213

40-150MHZ

27

20-75MHZ

13
14
28
25
6

23

D_P#

U850
74FCT388915T

5

FBCK

7

SYNC0

11

SYNC1

6

REFSEL

18

PLLEN

4

RST_OE

12

FRQSEL

9

LF Q3

8

AVCC

10

AGND

+3.3V

1

C830

10UF

2

J910

IF PROBING FROM THE DUAL SOCKET,

2

1

D/P# FROM THE PRIMARY SOCKET TO
PIN#2 OF THIS JUMPER EXTERNALLY.

BOFF#
RESET
KEN#
CACHE#
NA#

1

C0940

.1 UF

2

R0710

10K

JUMPER AND ROUTE-REMOVE THE

1

2

LCK

2XQ

Q0
Q1
Q2

Q4
Q5

Q/2

+3.3V

1 NS DELAY

19

26

14
16
21
23
28
2

25

U930

74FCT807FULSSOP

1

1

C0941

.1 UF

2

3
4
5
6

4C5<

7
9
10
11
12
13
16

2

OUT1
OUT2
OUT3
OUT4
OUT5

IN

OUT6
OUT7
OUT8
OUT9

OUT10

U820
22LV10_4PLCCSKT

27

IO

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

ICLK

LATCH

26

IO

25

IO

24

IO

23

IO

21

IO

20

IO

19

IO

18

IO

17

IO

PROC SELECTION

J900

3

R0830

5

R0831

7

R0832

9

R0930

11

R0941

12

R0942

14

R0842

16
18

R0841

19

R0821

L_NA#
L_CACHE#

CACHE_PR#

L_KEN#
L_RESET
L_BOFF#

BOFFF_PR#

213

D_ADDRESS<2..0>

U860

82.5

21
21
21
21
21
21
21

21
21

1

W_R# SW_R#

5

ADS#

11

ADSC#

29

+3.3V

1

R0532
10K

2

BRDY#

4

BRDYC#

30

HLDA

2

3
4

5

12

4C5<

U620
22LV10_4PLCCSKT

3

IN

4

IN

5

IN

6

IN

7

IN

9

IN

10

IN

11

IN

12

IN

13

IN

16

IN

2

ICLK

RW_ADS

3
4
5
6
7

4B5<

9
10
11
12
13
16

2

R0870

100

100PF

IO
IO
IO
IO
IO
IO
IO
IO
IO
IO

U520
22LV10_4PLCCSKT

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

ICLK

RST

C0970

27
26
25
24
23
21
20
19
18
17

IO
IO
IO
IO
IO
IO
IO
IO
IO
IO

1

2
1

2

SW_R_P#
L_W_R#

ADS1_PR#

L_ADS#

P_BRDY#

27

RST

26

RSTA

25
24
23
21

L_BRDY#
20
19
18
17

L_HLDA#

+3.3V

1

R0970

10K

2

6

7

4B2<

4D2<

8

9

U880
22LV10_4PLCCSKT

3

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

ICLK

BTRACK

IO
IO
IO
IO
IO
IO
IO
IO
IO
IO

4
5
6
7
9
10
11
12
13
16

2

14
7
15
16
17
18
19
20
21
22

27
26
25
24
23
21
20
19
18
17

RESET
INIT
BE7#
BE6#
BE5#
BE4#
BE3#
BE2#
BE1#
BE0#

D_DVALID

22LV10_4PLCCSKT

3
4
5
6
7
9
10
11
12
13
16

2

R680
1K

10 35

D_LAST

11 36

D_PIPE

12

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

ICLK

27

IO

26

IO

25

IO

24

IO

23

IO

21

IO

20

IO

19

IO

18

IO

17

IO

+3.3V

21

R_S#

31

PRDY

2

TDI

32

TDO

33

TMS

34

TCK

TRST#

R261
10K

OC_DBRESET#

R260
221

R280

10K

21

1

2

B_RESET
B_INIT

L_A2

L_A1

L_A0

27.4
R0880

21

R0881

21

R0632

21

R581

21

1

+3.3V

1

2

3

2

2

1

0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

DBRESET

Q270

J580

J260

231

4B1<

TMS 109A Socket 7 Microprocessor Support

D_CONTROL<12..1>

LOGIC

A1

4A1<

3

5–9

5–10

TMS 109A Socket 7 Microprocessor Support

21 34 65

A

R_CONTROL<36..1>

2A6>

D_CONTROL<12..1>

3D6>

R_DATA<63..0>

2A6>

R_ADDRESS<31..0>

2A6>

D_ADDRESS<2..0>

3A6>

B

J890

1

3C5<>

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16

3
4
5
6
7
8
9
10
11
12
13
14
15

D_DVALID

3A6<>
3A6<>
3A6<>

R_A<31>
R_A<30>
R_A<29>
R_A<28>
R_A<27>
R_A<26>
R_A<25>
R_A<24>
R_A<23>
R_A<22>
R_A<21>
R_A<20>
R_A<19>
R_A<18>
R_A<17>
R_A<16>
L_A0
L_A1
L_A2
R_A<3>
R_A<4>
R_A<5>
R_A<6>
R_A<7>
R_A<8>
R_A<9>
R_A<10>
R_A<11>
R_A<12>
R_A<13>
R_A<14>
R_A<15>

10

0

C

1
2

12

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

39

GND1

40

GND2

41

GND3

42

GND4

43

GND5

11

R_D<31>

31

R_D<30>

30

R_D<29>

29

R_D<28>

28

R_D<27>

27

R_D<26>

26

R_D<25>

25

R_D<24>

24

R_D<23>

23

R_D<22>

22

R_D<21>

21

R_D<20>

20

R_D<19>

19

R_D<18>

18

R_D<17>

17

R_D<16>

16

R_D<0>

0

R_D<1>

1

R_D<2>

2

R_D<3>

3

R_D<4>

4

R_D<5>

5

R_D<6>

6

R_D<7>

7

R_D<8>

8

R_D<9>

9

R_D<10>

10

R_D<11>

11

R_D<12>

12

R_D<13>

13

R_D<14>

14

R_D<15>

15

3C5<> 3C5<>

D_LASTD_PIPE

J390

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

39
40
41
42
43

GND2
GND3
GND4
GND5

GND1

R_D<63>

63

R_D<62>

62

R_D<61>

61

R_D<60>

60

R_D<59>

59

R_D<58>

58

R_D<57>

57

R_D<56>

56

R_D<55>

55

R_D<54>

54

R_D<53>

53

R_D<52>

52

R_D<51>

51

R_D<50>

50

R_D<49>

49

R_D<48>

48

R_D<32>

32

R_D<33>

33

R_D<34>

34

R_D<35>

35

R_D<36>

36

R_D<37>

37

R_D<38>

38

R_D<39>

39

R_D<40>

40

R_D<41>

41

R_D<42>

42

R_D<43>

43

R_D<44>

44

R_D<45>

45

R_D<46>

46

R_D<47>

47

J500

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

39
40
41
42
43

GND2
GND3
GND4
GND5

GND1

1
2

3
3C4<>
3B4<>

6

4

7

8

9

10

5
3B4<>
3C4<>
3C3<>
3C3<>

14

13

12

11

26
3C3<>

24

22

21

20

19

18

17

16

15

CLK
D/C#
PRDY#
BUSCHK#
L_BRDY#
L_W_R#
NA#
BRDY#
INIT
M/IO#
LOCK#
SMIACT#
W_R#
L_ADS#
L_HLDA#
L_BOFF#
L_RESET
RESET
BOFF#
HLDA
ADS#
AHOLD
L_CACHE#
SCYC
D/P#
BE0#
BE1#
BE2#
BE3#
BE4#
BE5#
BE6#
BE7#

1

8
6

7
9
4
3

2

5

J700

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

39
40
41
42
43

GND2
GND3
GND4
GND5

GND1

D

TMS 109A Socket 7 Microprocessor Support

MICTOR DMICTOR A

MICTOR CMICTOR E

A1

MICTOR

4

5–11

5–12

TMS 109A Socket 7 Microprocessor Support