Service Manual
Tektronix Logic Analyzer Module
(TLA7Nx, LTA7Px, & TLA7Qx)
071-0864-01
Warning
The servicing instructions are for use by qualified
personnel only. To avoid personal injury, do not
perform any servicing unless you are qualified to
do so. Refer to all safety summaries prior to
performing service.
www.tektronix.com
Copyright © Tektronix, Inc. All rights reserved.
Tektronix products are covered by U.S. and foreign patents, issued and pending. Information in this publication supercedes
that in all previously published material. Specifications and price change privileges reserved.
Tektronix, Inc., 14200 SW Karl Braun Drive, Beaverton, OR 97077
TEKTRONIX and TEK are registered tradem arks of Tektronix, Inc.
MagniVu and PowerFlex are registered trademarks of Tektronix, Inc.
WARRANTY
Tektronix warrants that the products that it manufactures and sells will be free from defects in materials and workmanship
for a period of one (1) year from the date of shipment. If a product proves defective during this warranty period, Tektronix,
at its option, either will repair the defective produc t without charge for parts and labor, or will provide a replacement in
exchange for the defective product.
In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration of the
warranty period and make suitable arrangements for the performance of service. Customer shall be responsible for
packaging and shipping the defective product to the service center designated by Tektronix, with shipping charges prepaid.
Tektronix shall pay for the return of the product to Customer if the shipment is to a locat ion within the c ountry in which the
Tektronix service center is located. Customer shall be responsible for paying all shipping charges, duties, taxes, and any
other charges for products returned to any other locations.
This warranty shall not apply to any defect, failure or damage caused by improper use or improper or inadequate
maintenance and care. Tektronix shall not be obligated to furnish service under this warranty a) to repair damage resulting
from attempts by personnel other than Tektronix representative s to install, re pair or service the product; b) to repair
damage resulting from improper use or connection to incompatible equipment; c) to repair any damage or malfunction
caused by the use of non-Tektronix supplies; or d) to service a product that has been modified or integrated with other
products when the effect of such modification or integration increases the time or difficulty of servicing the product.
THIS W ARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER WARRANTIES, EXPRESS OR
IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’ RESPONSIBILITY TO
REPAIR OR REPLACE DEFECTIVE PRODUCTS IS THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO
THE CUSTOMER FOR BREACH OF THIS WARRANTY. TEKTRONIX AND ITS VENDORS WILL NOT BE
LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE
OF WHETHER TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH
DAMAGES.
Table of Contents
Specifications
Operating Information
General Safety Summary vii...................................
Service Safety Summary ix....................................
Preface xi...................................................
Manual Structure xi................................................
Manual Conventions xii..............................................
Related Manuals xiii.................................................
Contacting Tektronix xiv.............................................
Introduction xv..............................................
Adjustment and Certification Interval xv................................
Strategy for Servicing xv.............................................
Service Offerings xvi................................................
Product Description 1--1..............................................
Characteristic Tables 1--1.............................................
Installation 2--1.....................................................
Software Installation and Removal 2--2..................................
Operating Information 2--4............................................
Merged Modules 2--10.................................................
Merging Rules 2--10.................................................
Theory of Operation
Block Level Description 3--1....................................
Performance Verification
Performance V erification: Logic Analyzer Module 4--1..............
Summary Verification 4--1.............................................
Test Equipment 4--3..................................................
Functional Verification 4--4............................................
LA Module Certification 4--10..........................................
Performance Verification Instructions 4--10................................
Performance Verification Tests 4--16.....................................
Performance V erification: Adjustment/V erification Fixture 4--21.......
Test Equipment 4--21..................................................
Functional Verification 4--21............................................
Certification 4--25....................................................
Performance Verification 4--25..........................................
Test Procedures 4--27..................................................
Calibration Data Report 4--37....................................
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
i
Table of Contents
Adjustment Procedures
Maintenance
Logic Analyzer Module Adjustment Procedures 5--1................
Prerequisites 5--1....................................................
Merged Modules 5--2.................................................
Using the Software 5--3...............................................
Test Equipment 5--3..................................................
Adjustment Instructions 5--4...........................................
Tests Performed 5--5.................................................
Adjustment Procedures 5--6............................................
Self Calibration 5-- 6..................................................
Completing the Adjustment Steps 5--9...................................
Adjustment/Verification Fixture Adjustments 5--11..................
Adjustment/Verification Fixture Adjustment 5--11...........................
Related Maintenance Procedures 6--1....................................
Preventing Electrostatic Discharge 6--1..................................
Inspection and Cleaning 6--2...........................................
Removal and Installation Procedures 6--5.........................
Preparation 6--5.....................................................
Tools Required 6--5..................................................
Torque Requirements 6--5.............................................
Injector/Ejector Handles 6--6...........................................
Cover 6--7..........................................................
Daughter Boards 6--11.................................................
Local Processor Unit Board 6--13.......................................
Acquisition Board 6--17................................................
Fuses 6--22..........................................................
Rear EMI Gaskets 6-- 24................................................
Troubleshooting 6--27...........................................
Service Level 6--27...................................................
Required Documentation 6--28..........................................
Check for Common Problems 6--28......................................
Eliminate Other Problem Sources 6--30...................................
Troubleshoot the Logic Analyzer Module 6--31.............................
Adjustment After Repair 6-- 38..........................................
Overview of Procedures 6--39...........................................
Repackaging Instructions 6--41...................................
Packaging 6--41......................................................
Shipping to the Service Center 6--41......................................
Storage 6--42........................................................
Options
ii
TLA7N1, TLA7N2, TLA7N3 and TLA7N4 Options 7--1....................
TLA7P2, TLA7P4, TLA7Q2 and TLA7Q4 Options 7--2.....................
Service Options 7--2..................................................
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Electrical Parts List
Diagrams
Mechanical Parts List
Table of Contents
Interconnection Block Diagram 9--1.....................................
Parts Ordering Information 10 --1.........................................
Using the Replaceable Parts List 10--2....................................
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
iii
Table of Contents
List of Figures
Figure 2--1: Logical address switches 2--2..........................
Figure 2--2: Front panel of the logic analyzer module 2--5............
Figure 2--3: Location of modules in a two way merge 2--11............
Figure 2--4: Location of modules in a three way merge 2--12...........
Figure 4--1: Calibration/certification procedure flow chart 4--2.......
Figure 4--2: Probe functional verification test setup 4--8..............
Figure 4--3: Activity Monitor 4--9................................
Figure 4--4: Adjustment/verification fixture connections and
jumper locations 4--16.......................................
Figure 4--5: FPV_DC_Threshold test setup 4--17.....................
Figure 4--6: Initial FPV_Setup_0F test setup 4--18...................
Figure 4--7: Initial FPV_Hold_0F test setup 4--19....................
Figure 4--8: FPV_Maxsync test setup 4--20..........................
Figure 4--9: Adjustment/verification fixture detail 4--23...............
Figure 4--10: Probe tip adapter detail 4--26........................
Figure 4--11: Adjustment/verification fixture detail 4--28..............
Figure 5--1: P6434 probe detail 5--4...............................
Figure 5--2: Initial deskew test setup 5--8..........................
Figure 5--3: Adjustment/verification fixture circuit board layout 5--13...
Figure 6--1: Injector/ejector handle replacement 6--6................
Figure 6--2: Cover removal 6--8..................................
Figure 6--3: Feeding the merge cable through the cover 6--9..........
Figure 6--4: Seating the cover on the chassis 6--10....................
Figure 6--5: Daughter board replacement 6--12......................
Figure 6--6: LPU board removal 6--14..............................
Figure 6--7: Inserting LPU board tabs into front subpanel 6--15........
Figure 6--8: Crimping the interconnect cables 6--16..................
Figure 6--9: Removing the cables from the Acquisition board 6--18.....
Figure 6--10: Removing the Merge cable connector from the chassis 6--19
Figure 6--11: Removing the acquisition board from the chassis 6--20....
Figure 6--12: Fuse replacement 6--23...............................
Figure 6--13: Rear EMI gasket removal 6--25........................
Figure 6--14: Rear EMI gasket replacement 6--25....................
iv
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Table of Contents
Figure 6--15: Primary troubleshooting chart 6--35...................
Figure 9--1: Interconnections 9--1................................
Figure 9--2: Block diagram 9--2..................................
Figure 10--1: TLA700 Series Logic Analyzer Module exploded view 10--4
Figure 10--2: TLA700 Series LPU board exploded view 10--8..........
Figure 10--3: TLA700 Series Acquisition board exploded view 10--10....
Figure 10--4: Adjustment/verification fixture exploded view 10--13.......
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
v
Table of Contents
List of Tables
Table 1--1: LA module channel width and depth 1--2...............
Table 1--2: LA module clocking 1--2..............................
Table 1--3: LA module trigger system 1--4.........................
Table 1--4: LA module MagniVu feature 1--6......................
Table 1--5: LA module data handling 1--6.........................
Table 1--6: LA module input parameters with probes 1--7...........
Table 1--7: LA module mechanical 1--8...........................
T able 1--8: Merged modules 1--8.................................
T able 1--9: Atmospherics 1--8...................................
Table 1--10: Certifications and compliances 1--9....................
T able 1--11: Adjustment/verification fixture specifications 1--9........
Table 3--1: Local Processor Unit board fuses 3--2...................
Table 4--1: Test equipment 4--3..................................
Table 4--2: Logic Analyzer Module functional verification
procedures 4--4............................................
T able 4--3: LA Module performance verification tests 4--12...........
T able 4--4: LA Module characteristics indirectly checked by the
performance verification tests 4--12............................
T able 4--5: Adjustment/verification fixture performance
verification tests 4--25.......................................
T able 4--6: Adjustment/verification fixture jumper settings 4--28.......
T able 6--1: External inspection check list 6--3......................
T able 6--2: Internal inspection check list 6--3......................
Table 6--3: Tools required for circuit board replacement 6--5.........
Table 6--4: Local Processor Unit board fuses 6--22...................
Table 6--5: Acquisition board fuses 6--22...........................
Table 6--6: Failure symptoms and possible causes 6--29...............
Table 6--7: Diagnostic tests 6--36..................................
Table 6--8: Requirements after replacement 6--38....................
Table 6--9: Troubleshooting overview 6--39.........................
Table 7--1: TLA7N1, TLA7N2, TLA7N3 and TLA7N4 options 7--1....
Table 7--2: TLA7P2, TLA7P4, TLA7Q2 and TLA7Q4 options 7--2....
vi
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
General Safety Summary
Review the following safety precautions to avoid injury and prevent damage to
this product or any products connected to it. To avoid potential hazards, use this
product only as specified.
Only qualified personnel should perform service procedures.
While using this product, you may need to access other parts of the system. Read
the General Safety Summary in other system manuals for warnings and cautions
related to operating the instrument.
ToAvoidFireor
Personal Injury
Use Proper Power Cord. Use only the power cord specified for this product and
certified for the country of use.
Connect and Disconnect Properly. Do not connect or disconnect probes or test
leads while they are connected to a voltage source.
Ground the Product. This product is grounded through the grounding conductor
of the power cord. To avoid electric shock, the grounding conductor must be
connected to earth ground. Before making connections to the input or output
terminals of the product, ensure that the product is properly grounded.
Observe All Terminal Ratings. To avoid fire or shock hazard, observe all ratings
and markings on the product. Consult the product manual for further ratings
information before making connections to the product.
Connect the ground lead of the probe to earth ground only.
Do not apply a potential to any terminal, including the common terminal, that
exceeds the maximum rating of that terminal.
Replace Batteries Properly. R eplace batteries only with the proper type and rating
specified.
Do Not Operate Without Covers. Do not operate this product with covers or panels
removed.
Use Proper Fuse. Use only the fuse type and rating specified for this product.
Avoid Exposed Circuitry. Do not touch exposed connections and components
when power is present.
Do Not Operate With Suspected Failures. If you suspect there is damage to this
product, have it inspected by qualified service personnel.
Do Not Operate in Wet/Damp Conditions.
Do Not Operate in an Explosive Atmosphere.
Keep Product Surfaces Clean and Dry.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
vii
General Safety Summary
Provide Proper Ventilation. Refer to the manual’s installation instructions for
details on installing the product so it has proper ventilation.
Symbols and Terms
Terms in this Manual. These terms may appear in this manual:
WARNING. Warning statements identify conditions or practices that could result
in injury or loss of life.
CAUTION. Caution statements identify conditions or practices that could result in
damage to this product or other property.
Terms on the Product. These terms may appear on the product:
DANGER indicates an injury hazard immediately accessible as you read the
marking.
WARNING indicates an injury hazard not immediately accessible as you read the
marking.
CAUTION indicates a hazard to property including the product.
Symbols on the Product. The following symbols may appear on the product:
CAUTION
Refer to Manual
WARNING
High Voltage
Protective Ground
(Earth) Terminal
viii
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Service Safety Summary
Only qualified personnel should perform service procedures. Read this Service
Safety Summary and the General Safety Summary before performing any service
procedures.
Do Not Service Alone. Do not perform internal service or adjustments of this
product unless another person capable of rendering first aid and resuscitation is
present.
Disconnect Power. To avoid electric shock, disconnect the main power by means
of the power cord or, if provided, the power switch.
Use Care When Servicing With Power On. Dangerous voltages or currents may
exist in this product. Disconnect power, remove battery (if applicable), and
disconnect test leads before removing protective panels, soldering, or replacing
components.
To avoid electric shock, do not touch exposed connections.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
ix
Service Safety Summary
x
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Preface
Manual Structure
This is the service manual for the TLA7Nx/7Px/7Qx Logic Analyzer Module.
Read this preface to learn how this manual is structured, what conventions it
uses, and where you can find other information related to servicing this product.
Read the Introduction, which follows this preface, for important background
information needed before using this manual for servicing this product.
The Logic Analyzer Module (TLA7Nx/7Px/7Qx) Service Manual is divided into
chapters, which are made up of related subordinate topics. These topics can be
cross referenced as sections.
Be sure to read the introductions in the sections and subsections because they
contain information that you will need to do the service correctly and efficiently.
A brief description of each chapter follows:
H Specifications contains a product description of the logic analyzer module
and tables of the characteristics and descriptions that apply to it.
H Operating Information includes basic installation and operating instructions
at the level needed to safely operate and service the logic analyzer module.
For complete installation and configuration procedures, refer to the Tektronix
Logic Analyzer Family User Manual.
H Theory of Operation contains circuit descriptions that support general service
to the circuit board level.
H Performance Verification contains the performance verification procedures
for the logic analyzer module, logic analyzer module probes, and the
adjustment/verification fixture.
H Adjustment Procedures contains the adjustment procedures for the logic
analyzer module and the adjustment/verification fixture.
H Maintenance contains information and procedures for doing preventive and
corrective maintenance on the logic analyzer module. Included are instructions for cleaning, for removal and installation of replacement parts, and for
troubleshooting to the circuit board level.
H Options contains information on servicing any of the factory--installed
options that may be available for the logic analyzer module.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
xi
Preface
Manual Conventions
H Diagrams contains block diagrams and interconnection diagrams that are
useful when isolating failed circuit boards.
H Mechanical Parts List includes a table of all replaceable parts, their
descriptions, and their Tektronix part numbers.
This manual uses certain conventions that you should be familiar with before
attempting service.
Acquisition Board
Adjustment Procedures
Adjustment/Verification
Fixture
Certification Procedures
Daughter Board
Functional Verification
Procedures
The acquisition board is one of the circuit boards inside the logic analyzer
module. The circuit board receives and stores acquisition data from the probes
and works with the LPU board to provide logic analysis information to the
operator of the logic analyzer.
Adjustment procedures check for, and if necessary, correct any adjustment errors
discovered when performing functional or performance verification procedures.
The adjustment/verification fixture is a test fixture used to perform the adjustment, functional check, and performance verification procedures. Specifications
and replaceable parts information are documented in this service manual.
Certification procedures certify a product and provide a traceability path to
national standards.
The daughter board provides additional channels for the logic analyzer. Data
from these channels is sent to the acquisition board for processing with other
data from the acquisition board.
Functional verification procedures verify the basic functionality of the instrument. These procedures include power-on and extended diagnostics, self
calibration, as well as semi-automated or manual check procedures. These
procedures can be used as incoming inspection purposes. This manual provides
information on power-on and extended diagnostics and the self calibration.
xii
LPU Board
The Local Processor Unit (LPU) Board. The LPU board is one of the circuit
boards inside the logic analyzer module that provides the main communications
interface with the mainframe.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Preface
Maintenance Procedures
Modules
Performance Verification
Procedures
Replaceable Parts
Safety
Maintenance procedures are used for fault isolation and repair to the circuit board
level or to the replaceable part level.
Throughout this manual, the term “module” refers to a logic analyzer or DSO
unit that mounts inside a mainframe. A module is composed of circuit cards,
interconnecting cables, and a user-accessible front panel.
Performance verification procedures confirm that a product meets or exceeds the
performance requirements for each of the published specifications.
This manual refers to any field-replaceable assembly or mechanical part
specifically by its name or generically as a replaceable part. In general, a
replaceable part is any circuit board or assembly, such as the hard disk drive, or a
mechanical part, such as the I/O port connectors, that is listed in the replaceable
parts list.
Symbols and terms related to safety appear in the Safety Summary found at the
beginning of this manual.
Related Manuals
The following manuals are available as part of the TLA700 Series Logic
Analyzer documentation set. Refer to Optional Accessories on page 10--7 for part
numbers.
Manual Name Description Service use
Tektronix Logic Analyzer Family User
Manual
TLA715 Portable Mainframe Service
Manual
TLA721 Benchtop Mainframe and TLA7XM
Expansion Mainframe Service Manual
TLA7Dx/TLA7Ex Digitizing Oscilloscope
Service Manual
Provides operating information on the TLA
Series Logic Analyzer
Provides service information for the
portable mainframes
Provides service information for the
benchtop mainframe and expansion
mainframe
Provides service information for the
digitizing oscilloscope modules
Augments operating information found in
chapter 2 of this manual
Isolating and correcting failures in the
portable mainframe
Isolating and correcting failures in the
benchtop mainframe, controller, or expansion mainframe
Isolating and correcting failures in the DSO
module
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
xiii
Preface
Contacting Tektronix
Phone 1-800-833-9200*
Address Tektronix, Inc.
Department or name (if known)
14200 SW Karl Braun Drive
P.O. Box 500
Beaverton, OR 97077
USA
Web site www.tektronix.com
Sales support 1-800-833-9200, select option 1*
Service support
Technical support
* This phone number is toll free in North America. After office hours, pl ease leave a
voice mail message.
Outside North America, contact a Tektronix sales office or distributor; see the
Tektronix web site for a list of offices.
1-800-833-9200, select option 2*
Email: techsupport@tektronix.com
1-800-833-9200, select option 3*
1-503-627-2400
6:00 a.m. -- 5:00 p.m. Pacific time
xiv
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Introduction
This manual contains information needed to properly service the logic analyzer
module, as well as general information critical to safe servicing.
To prevent personal injury or damage consider the following requirements before
attempting service:
H The procedures in this manual should be performed only by a qualified
service person.
H Read the General Safety Summary and Service Safety Summary found at the
beginning of this manual.
When using this manual for servicing follow all warnings and cautions.
Adjustment and Certification Interval
Generally, you should perform the adjustments and certification (calibration)
described in the Performance Verification and Adjustment Procedures chapters
once per year, or following repairs that affect adjustment or calibration.
Strategy for Servicing
This manual contains information for corrective maintenance of this product:
H Supports isolation of faults to the failed circuit board or assembly level
shown in the replaceable parts list
H Supports removal and replacement of those boards or assemblies
H Supports removal and replacement of fuses, knobs, chassis, and other
mechanical parts listed in the replaceable parts list
This manual does not support component-level fault isolation and replacement.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
xv
Introduction
Service Offerings
Tektronix provides service to cover repair under warranty as well as other
services that are designed to meet your specific service needs.
Whether providing warranty repair service or any of the other services listed
below, Tektronix service technicians are well equipped to service the logic
analyzer module.
Warranty Repair Service
Calibration and Repair
Service
Service Options
Service Agreements
Tektronix warrants this product for one year from date of purchase. (The
warranty appears behind the title page in this manual.) Tektronix technicians
provide warranty service at most Tektronix service locations worldwide. The
Tektronix product catalog lists all service locations worldwide or you can visit us
on our Customer Services World Center web site at http://www.tek.com/Mea-
surement/Service. See our latest service offerings and contact us by email.
In addition to warranty repair, Tektronix Service offers calibration and other
services that provide cost-effective solutions to your service needs and qualitystandards compliance requirements. Our instruments are supported worldwide by
the leading-edge design, manufacturing, and service resources of Tektronix to
provide the best possible service.
The following services can be tailored to fit your requirements for calibration
and/or repair of the logic analyzer module.
Tektronix Service Options can be selected at the time you purchase your
instrument. You select these options to provide the services that best meet your
service needs.
If service options are not added to the instrument purchase, then service
agreements are available on an annual basis to provide calibration services or
post-warranty repair coverage for the logic analyzer module. Service agreements
may be customized to meet special turn-around time and/or on-site requirements.
xvi
Service On Demand
Self Service
Tektronix also offers calibration and repair services on a “per-incident” basis that
is available with standard prices for many products.
Tektronix supports repair to the replaceable-part level by providing for circuit
board exchange. Use this service to reduce down-time for repair by exchanging
circuit boards for remanufactured ones. Tektronix ships updated and tested
exchange boards. Each board comes with a 90-day service warranty.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Introduction
When you exchange circuit boards, you must supply the following information
to allow the board to be preconfigured to the proper PowerFlex level. You can
also return the repaired module to your local service center for configuration.
H Model number and serial number
H PowerFlex option upgrade number
H Firmware level
For More Information
Contact your local Tektronix service center or sales engineer for more information on any of the Calibration and Repair Services just described.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
xvii
Introduction
xviii
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Specifications
Product Description
This chapter provides a brief product description, specifications and characteristics of the logic analyzer module and the adjustmernt/verification fixture.
The logic analyzer module is designed to be used with either the benchtop
mainframe or portable mainframe in a TLA700 Series Logic Analyzer. The logic
analyzer module is used as a test and measurement tool for high-speed digital
timing and state acquisition across several channels.
Some of the key features of the logic analyzer module include the following:
H 100 MHz synchronous acquisition with a programmable setup and hold
window (PowerFlex configurable to 200 MHz)
H 250 MHz asynchronous full depth selections with selectable sampling rates
H 2 GHz asynchronous acquisition into a 2 K high resolution timing buffer
H 250 MHz trigger capability, plus special setup and hold violation triggering
and glitch triggering
Characteristic Tables
H Data correlation with other modules
This section lists the specifications for the logic analyzer module. All specifications are guaranteed unless noted Typical. Specifications that are marked with the
n symbol are checked directly (or indirectly) in the Performance Verification
chapter. The specifications apply to all versions of the logic analyzer module
unless otherwise noted.
The performance limits in this specification are valid with these conditions:
H The logic analyzer module must have been calibrated/adjusted at an ambient
temperature between +20° C and +30° C.
H The logic analyzer module must be in an environment with temperature,
altitude, humidity, and vibration within the operating limits described in
these specifications.
H The logic analyzer module must have had a warm-up period of at least 30
minutes.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
1- 1
Specifications
H The logic analyzer module must have had its signal-path-compensation
routine (self-calibration) last executed after at least a 30 minute warm-up
period.
Table 1- 1: LA module channel width and depth
Characteristic Description
Number of channels Product Channels
TLA7N1 32 data and 2 clock
TLA7N2, TLA7P2, TLA7Q2 64 data and 4 clock
TLA7N3, TLA7L3, TLA7M3 96 data, 4 clock, and 2 qualifier
TLA7N4, TLA7P4, TLA7Q4 128 data, 4 clock, and 4 qualifier
Acquisition memory depth Product Memory depth
TLA7L1, TLA7L2, TLA7L3, TLA7L4 32 K or 128 K samples
TLA7N1, TLA7N2, TLA7N3, TLA7N4 64 K or 256 K or 1 M or 4 M samples
TLA7P2, TLA7P4 16 M samples
TLA7Q2, TLAQP4 64 M samples
1
PowerFlex options
1
Table 1- 2: LA module clocking
Characteristic Description
Asynchronous clocking
n Internal sampling period
n Minimum recognizable word
(across all channels)
Synchronous clocking
Number of clock channels
Number of qualifier channels Product Qualifier channels
1
4 ns to 50 ms in a 1--2--5 sequence
2 ns in 2x Clocking mode
2
Channel-to-channel skew + sample uncertainty
Example: for a P6417 or a P6418 Probe anda4nssampleperiod=
1.6ns+4ns=5.6ns
3
Product Clock channels
TLA7N1 2
TLA7N2, TLA7P2, TLA7Q2 4
TLA7N3 4
TLA7N4, TLA7P4, TLA7Q4 4
TLA7N1 0
TLA7N2, TLA7P2, TLA7Q2 0
TLA7N3 2
1- 2
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Specifications
Table 1- 2: LA module clocking (Cont.)
Characteristic Description
TLA7N4, TLA7P4, TLA7Q4 4
n Setup and hold window size
(data and qualifiers)
Setup and hold window size
(data and qualifiers)
(Typical)
Setup and hold window range The setup and hold window can be moved for each channel group from +8.5 ns (Ts) to
n Maximum synchronous clock rate
4
Maximum window size = Maximum channel-to-channel skew + (2 x sample
uncertainty) + 0.4 ns
Maximum setup time = User interface setup time + 0.8 ns
Maximum hold time = User interface hold time + 0.2 ns
Maximum setup time for slave module of m erged pair =
User Interface setup time + 0.8 ns
Maximum hold time for slave module of m erged pair =
User Interface hold time + 0.7 ns
Examples: for a P6417 or a P6418 probe and user interface
setup and hold of 2.0/0.0 typical:
Maximum window size = 1.6 ns + (2 x 500 ps) + 0.4ns = 3.0 ns
Maximum setup time = 2.0 ns + 0.8 ns = 2.8 ns
Maximum hold time = 0.0 ns + 0.2 ns = 0.2ns
Channel-to-channel skew (typical) + (2 x sample uncertainty)
Example: for P6417 or P6418 Probe = 1 ns + (2 x 500 ps) = 2 ns
--7.0 ns (Ts) in 0.5 ns steps (setup time). Hold time follows the setup time by the setup
and hold window size.
200 MHz in full speed mode (5 ns minimum between active clock edges)
100 MHz in half speed mode (10 ns minimum between active clock edges)
Demux clocking
Demux Channels
TLA7N3, TLA7N4, TLA7P4, TLA7Q4,
Channels multiplex as follows:
A3(7:0) to D3(7:0)
A2(7:0) to D2(7:0)
A1(7:0) to D1(7:0)
A0(7:0) to D0(7:0)
TLA7N1, TLA7N2, TLA7P2, TLA7Q2 Channels multiplex as follows:
A3(7:0) to C3(7:0)
A2(7:0) to C2(7:0)
A1(7:0) to D1(7:0) TLA7N2, TLA7P2, TLA7Q2 only
A0(7:0) to D0(7:0) TLA7N2, TLA7P2, TLA7Q2 only
Time between DeMux clock edges
(Typical)
Time between DeMux store clock edges
(Typical)
Data Rate (Typical)
TLA7N1, TLA7N2, TLA7P2, TLA7Q2,
TLA7N3, TLA7N4, TLA7P4, TLA7Q4,
4
5 ns minimum between DeMux clock edges in full-speed mode
10 ns minimum between DeM ux clock edges in half-speed mode
4
10 ns minimum between DeMux master clock edges in full-speed mode
20 ns minimum between DeMux master clock edges in half-speed mode
400 MHz (200 MHz option required) half channel.
(Requires channels to be multiplexed. )
These multiplexed channels double the m emory depth.
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Specifications
Table 1- 2: LA module clocking (Cont.)
Characteristic Description
Clocking state machine
Pipeline delays Each channel group can be programmed with a pipeline delay of 0 through 3 active
clock edges.
1
It is possible to use storage control and only store data when it has changed (transitional storage).
2
Applies to asynchronous clocking only. Setup and hold window specification applies to synchronous clocking only.
3
Any or all of the clock channels may be enabled. For an enabled clock channel, either the rising, falling, or both edges
can be selected as the active clock edges. The clock channels are stored.
4
Full and half speed modes are controlled by PowerFlex options and upgrade kits.
Table 1- 3: LA module trigger system
Characteristic Description
Triggering resources
Word/Range recognizers 16 word recognizers. The word recognizers can be combined to f orm ful l width, double
bounded, range recognizers. The following selections are available:
16 word recognizers 0 range recognizers
13 word recognizers 1 range recognizer
10 word recognizers 2 range recognizers
7 word recognizers 3 range recognizers
4 word recognizers 4 range recognizers
Range recognizer channel order From most-significant probe group to least-significant probe group: C3 C2 C1 C0 E3
E2 E1 E0 A3 A2 D3 D2 A1 A0 D1 D0 Q3 Q2 Q1 Q0 CK3 CK2 CK1 CK0
Missing channels for modules with f ewer than 136 channels are omitted. When
merged, the range recognition extends across all the modules; the master module
contains the most-significant groups.
The master module is to the left (lower-numbered slot) of a merged pair.
The master module is in the center when three modules are merged. Slave module 1
is located to t he right of the master module, and slave module 2 is located to the left
of the master modul e.
Glitch detector
Minimum detectable glitch pulse wi dth
1,2
Each channel group can be enabled to detect a glitch
2.0 ns (single channel with P6417 or a P6418 probe)
(Typical)
Setup and hold violation detector
1,3
Each channel group can be enabled to detect a setup and hold violation. The range is
from 8 ns before the clock edge to 8 ns after the clock edge. The range can be
selected in 0.5 ns increments.
Transition detector
1- 4
1, 4
The setup and hold violation of each window can be individually programmed.
Each channel group can be enabled or disabled to detect a transition between the
current valid data sample and the previous valid data sample.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Table 1- 3: LA module trigger system (Cont.)
Characteristic Description
Specifications
Counter/Timers 2 counter/timers, 51 bits wi de, can be clocked up to 250 MHz.
Maximum count is 2
Maximum time is 9.007 X 10
51
.
6
seconds or 104 days.
Counters and timers can be set, reset, or tested and have zero reset lat ency.
Signal In 1 A backplane input signal
Signal In 2 A backplane input signal
Trigger In A backplane input signal that causes the main acquisition and the MagniVu
acquisition to trigger if they are not already triggered
Active trigger resources 16 maximum (excluding counter/timers)
Word recognizers are traded off one-by-one as Signal In 1, Signal In 2, glitch
detection, setup and hold detection, or transition detection resources are added.
Trigger States 16
n Trigger State sequence rate Same rate as valid data samples received, 250 MHz maximum
Trigger Machine Actions
Main acquisition trigger Triggers the main acquisition memory
Main trigger position Trigger position is programmable to any data sample (4 ns boundaries)
Increment counter Either of the two counter/timers used as counters can be incremented.
Start/Stop timer Either of the two counter/timers used as timers can be st arted or stopped.
Reset counter/timer Either of the two counter/timers can be reset.
When a counter/timer is used as a timer and is reset, the timer continues in the
started or stopped state that it was in prior to the reset.
Signal out A signal sent to the backplane to be used by other modules
Trigger out A trigger out signal sent to the backplane to trigger other modules
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Specifications
Table 1- 3: LA module trigger system (Cont.)
Characteristic Description
Storage control
Global storage Storage is allowed only when a specific condition is met. This condition can use any
of the trigger machine resources except for the counter/timers. Storage commands
defined in the current trigger state will override the global storage control.
Global storage can be used to start the acquisition with storage initially turned on
(default) or turned off.
By event Storage can be turned on or off; only the current sample can be stored. The event
storage control overrides any global storage commands.
Block storage When enabled, 31 samples are stored before and after the valid sample.
Block storage is disallowed when glitch storage or setup and hold v iolation is enabled.
Glitch violation storage The acquisition memory can be enabled to store glitch violation information with each
data sample when asynchronous clocking is used. The probe data storage size is
reduced by one half (the other half holds the violation information). The fastest
asynchronous clocking rate is reduced to 10 ns.
1
Each use of a glitch detector, setup and hold violation detector, or transition detector requires a trade-off of one word
recognizer resource.
2
Any glitch is subject to pulse width variation of up to the channel-to-channel skew specification + 0.5 ns.
3
For TLA7N1, TLA7N2, TLA7N3, TLA7N4, TLA7P2, TLA7P4, TLA7Q2, and TLA7Q4 Logic Analyzer modules, any setup
value is subject to variation of up to 1.8 ns; any hold value is subject to variation of up to 1.2 ns.
4
This mode can be used to create transitional storage selections where all channels are enabled.
Table 1- 4: LA module MagniVu feature
Characteristic Description
MagniVu memory depth 2016 samples per channel
MagniVu sampling period Data is asynchronously sampled and stored every 500 ps in a separate hi gh resoluti on
memory.
Table 1- 5: LA module data handling
Characteristic Description
Nonvolatile memory retention time
(Typical)
1- 6
Battery is integral to the NVRAM. Battery life is > 10 years.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Table 1- 6: LA module input parameters with probes
Characteristic Description
n Threshold Accuracy ±100 mV
Threshold range and step size Setable from +5 V to --2 V in 50 mV steps
Threshold channel selection 16 threshold groups assigned to channels.
P6417 and P6418 probes have two threshold settings, one for the clock/qualifier
channel and one for the data channels.
P6434 probes have four threshold settings, one for each of the clock/qualifier
channels and two for the data channel s (one per 16 data channels).
n Channel-to-channel skew ≤ 1.6 ns maximum (When merged, add 0.5 ns for the slave module.)
Channel-to-channel skew
(Typical)
Sample uncertainty
Asynchronous: Sample period
Synchronous: 500 ps
Probe input resistance
(Typical)
Probe input capacitance: P6417, P6434
(Typical)
Probe input capacitance: P6418
(Typical)
Minimum slew rate
(Typical)
Maximum operating signal 6.5 V
Probe overdrive:
P6417, P6418
P6434
Maximum nondestructive input signal to probe ±15 V
Minimum input pulse width signal
(single channel)
(Typical)
Delay time from probe tip to input probe
connector
(Typical)
≤ 1.0 ns typical (When merged, add 0.3 ns for the slave module.)
20 kΩ
2pF
1.4 pF data channels
2 pF CLK/Qual channels
0.2 V/ns
p-p
--3.5 V absolute input voltage minimum
6.5 V absolute input voltage maximum
±250 mV or ±25% of signal swing minimum required beyond threshold, whichever is
greater
±300 mV or ±25% of signal swing minimum required beyond threshold, whichever is
greater
±4 V maximum beyond threshold
2ns
7.33 ns
Specifications
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Specifications
Table 1- 7: LA module mechanical
Characteristic Description
Slot width Requires 2 mainframe slots
Weight
(Typical)
Overall dimensions
Height 262 mm (10.32 in)
Width 61 mm (2.39 in)
Depth 373 mm (14.7 in)
Probe cables
P6417 length 1.8 m (6 ft)
P6418 length 1.93 m (6 ft 4 in)
P6434 length 1.6 m (5 ft 2 in)
Mainframe interlock 1.4 ECL keying is implemented
5 lbs 10 oz. (2.55 kg) for TLA7N4, TLA7P4 or TLA7Q4
8 lbs (3.63 kg) for TLA7N4, TLA7P4 or TLA7Q4 packaged for domestic shipping
Table 1- 8: Merged modules
Characteristic Description
Number of modules that can be merged
together
Number channels after merge The sum of the data channels of both modules plus the CLK/QUAL channels (active
Merge system acquisition depth Channel depth is equal to the smallest depth of the modules.
Number of clock and qualifier channels after
merge
Merge system triggering resources Triggering resources are the same as a single module except that the widths of the
Refer to Merging Rules on page 2--10.
clocks for the merge system) of the master module plus the CLK/QUAL channels
(nonactive stored clock channels to the merge system).
Same number of clock and qualifier channels on the master module. The clock and
qualifier channels on the slave module have no effect on clocking and are only stored.
word/range recognizers, setup and hold violation detector, glitch detector, and
transition detector are increased to the merged channel width.
Table 1- 9: Atmospherics
Characteristic Description
Altitude
Operating To 10,000 ft. (3040 m) (derated 1_ C per 1000 ft (305 m) above 5000 ft (1524 m)
altitude)
Non-operating 40,000 ft. (12190 m)
Temperature
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Specifications
Table 1- 9: Atmospherics (Cont.)
Characteristic Description
Operating +5_ Cto+50_ C, 15_ C/hour maximum gradient, non-condensing (derated 1_ C/1000
ft. above 5000 ft altitude)
Non-operating -- 2 0 _ to +60_ C, 15_ C/hour maximum gradient, non-condensing
Relative Humidity
Operating and non-operating 20% to 80% relative humidity, non-condensing. Maximum wet bulb temperature: +29_
C (derates relative humidity to approximately 22% at +50_ C)
Non-operating 8% to 80% relative humidity, non-condensing. Maximum wet bulb temperature: +29_
C (derates relative humidity to approximately 22% at +50_ C)
Table 1- 10: Certifications and compliances
EC Declaration of Conformity -- EMC Meets intent of Directive 89/336/EEC for Electromagnetic Compatibility. Compliance
was demonstrated to the following specifications as listed in the Official Journal of the
European Communities:
EN 55011 Class A Radiat ed and Conducted Emissions
EN 50081-1 Emissions:
EN 60555-2 AC Power Line Harmonic Emissions
EN 50082-1 Immunity:
IEC 801-2 Electrostatic Discharge Immunity
IEC 801-3 RF Electromagnetic Field Immunity
IEC 801-4 Electrical Fast Transient/Burst Immunity
IEC 801-5 Power Line Surge Immunity
Table 1- 11: Adjustment/verification fixture specifications
Characteristic Description
Instrument characteristics
Number of data outputs
For P6417 Probes 18 grouped in two groups of eight and one group of two
For P6418 Probes 18 grouped in two groups of eight and one group of two
For P6434 Probes 36 grouped in one connector
Number of setup and hold clock outputs
For P6417 Probes Two grouped in one group of two
For P6418 Probes Two grouped in one group of two
For P6434 Probes One clock
Number of DC threshold outputs
For P6417 Probes 16 grouped in two groups of eight and one group of two
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Specifications
Table 1- 11: Adjustment/verification fixture specifications (Cont.)
Characteristic Description
For P6418 Probes 16 grouped in two groups of eight and one group of two
For P6434 Probes 36 grouped in one connector
External clock in External clock input provi ded by user t hrough a BNC connector
DC threshold input External input provided by user through a BNC connector
DC power in Provided by a wall transformer DC power supply (9 V to 12 V DC)
VDDDC level (typical) +5 V referenced to V
VDDto analog ground level (typical) +2 V referenced to ground (GND)
VDDswitcher noise (typical) 50 mV
(measured at C17)
p-p
n Internal clock frequency 50.065 MHz ±0.01%
Output electrical characteristics
Data/clock output amplitude 10K Motorola ECLinPS family outputs
DC threshold output Output equals user-applied input
Input requirements
External Clock input 1.0 V
centered around the fixture ground. Specification is valid between 5 MHz
p-p
and 210 MHz
DC power in 12 Volts DC at 1.5 A. Power is provided by one of the following power supply wall
plugs: 119-4855-00, 119-4856-00, 119-4859-00, and 119-4857-00
DC threshold input Input not greater than ±5 V ground referenced
Output timing
n Data output (channel-to-channel skew) 50 ps (all channels within 50 ps relative to each other)
n Setup clock output timing Adjusted for +3.0 ns (setup) ±100 ps, referenced to one of the data outputs
n Hold clock output timing Adjusted for 0.0 ns (hold) ±100 ps, referenced to one of the data outputs
Minimum data output pulse width Adjusted for 2.0 ns ±100 ps (jumpered in minimum pulse wi dth mode)
Fuse rating
Recommended replacement fuse 1.5 AF, 125 V, Tektronix part number 159-5009-00
EE
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TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Operating Information
This chapter provides brief operating information for performing maintenance.
The operating information is limited to the functions you need to perform the
procedures found in this document. You can find more detailed operating
instructions in the Tektronix Logic Analyzer Family User Manual andinthe
online help.
Installation
This section contains brief installation information and is provided for your
convenience. For detailed installation information, refer to the Tektronix Logic
Analyzer Family User Manual.
NOTE. Do not set the logic analyzer module logical address to 00. Logical
address 00 is reserved for the controller.
Dynamic Autoconfiguration With Dynamic Auto Configuration (Recommended)
selected (hexadecimal FF or decimal 255), the logic analyzer automatically sets
the address to an unused value. For example, if there are modules set to
addresses 01 and 02 already in your system, the resource manager will automatically assign the logic analyzer module an address other than 01 or 02.
Static Logical Address Static logical address selections set the address to a fixed
value. A static logical address ensures that the logic analyzer module address
remains fixed for compatibility with modules that require a specific address
value. Remember that each module within the logic analyzer must have a unique
address to avoid communication problems.
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Operating Information
Least-significant
digit
Most-significant
digit
Flash
programming
jumper pins
Figure 2- 1: Logical address switches
Merging Modules You can combine up to three logic analyzer modules to create a
single two- or three-wide module. This process is called merging modules. The
procedures for merging modules is described in the Tektronix Logic Analyzer
Family User Manual.
Software Installation and Removal
These procedures describe loading and unloading the performance verification
and adjustment software. Refer to the Tektronix Logic Analyzer Family User
Manual for information on installing or removing any other software. It is
recommended you have ≥10 MB of free space on the hard drive before installing
the software. The Performance Verification software is located on Disk 1 of the
Tektronix Logic Analyzer Family Application Software CD.
2- 2
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Operating Information
NOTE. This installation program uses parameters you supply to create a custom
start-up file in your hard disk directory.
The batch file enables the software to configure your instrument properly before
it runs the program.
1. Power on the instrument.
2. Exit the Application.
Verify PV/Adjust Software
Version
Verify Directories
Install the PV/Adjust
Software
If your logic analyzer already has PV/Adjust software loaded on it, you must
verify that the version is the same as the version printed on Disc 1 of the
Tektronix Logic Analyzer Family Application Software CD.
If the version of the PV/Adjust software loaded on your logic analyzer is an
earlier version, you must delete the earlier version before you can load the newer
version.
If your logic analyzer already has a directory named Tekcats or Temptek on the
hard drive, the software installation cannot be completed. Follow these instructions to verify the directory is not present:
1. Select Start → Search → For Files or Folders.
2. In the “Search for files or folders:” box, type “Tekcats” or “TempTek” and
then click the Search Now button fo search for either directory.
3. If either directory is found follow the instructions under Removing the
Software to remove the software and the directories.
Follow these instructions to install the PV/Adjust software.
1. Close all open windows on the desktop.
2. Insert Disk 1 of the Tektronix Logic Analyzer Family Application Software
CD in the CD-ROM drive.
3. Click the My Computer Icon and double-click the CD-ROM drive.
4. Double-click the TLA Performance Verification folder.
5. Double-click on the Logic Analyzer PV folder and then double-click the
Disk1 folder.
6. Double-click the Setup.exe icon to begin the installation program.
7. Follow the on-screen instructions to install the software on the hard disk.
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Operating Information
8. After the installation is complete, go back to the TLA Performance
Verification folder on the CD.
This completes the software installation procedure.
Removing the Software
Operating Information
Use the following procedure to remove the performance verification and
adjustment software from the instrument. These steps are necessary when you
want to upgrade the PV software.
1. Open Windows Explorer and then locate and select the C:\Tekcats folder.
2. Go to the File menu and select Delete to delete the folder.
3. Repeat steps 1 and 2 to find and delete the Temptek folder if it exists.
4. Select Start → Settings → Taskbar & S tart Menu.
5. Click the Advanced tab followed by the Advanced button.
6. Open the following directory path under Documents and Settings:
All Users → Start Menu → Programs
7. Locate and delete the TLA Performance Verification item.
This section provides a general description of the logic analyzer module.
2- 4
Front Panel
Figure 2--2 on page 2--5 shows the connectors and indicators on the front panel
of a 136 channel logic analyzer module. The 102, 68, and 34 channel versions
look and operate the same, but without the additional probe connectors.
Injector/Ejector Handles. The injector/ejector tabs are used to seat and unseat the
modules in the mainframe.
Probe Connectors. The probe connectors are color-coded to match the labels on
the probes.
Probe Retainer Mounting Holes. The threaded probe retainer mounting holes
provide a means of securely holding the probes in place.
Configuration Label. The configuration label indicates the speed and memory
depth of the logic analyzer module.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Operating Information
Injector/ejector handle
READY Indicator
ACCESSED Indicator
ARM’D Indicator
TRIG’D Indicator
Probe connectors
Configuration label
Probe retainer mounting
holes
Figure 2- 2: Front panel of the logic analyzer module
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2- 5
Operating Information
READY Indicator. The READY indicator lights continuously after the logic
analyzer module successfully completes the power-on process. If the indicator
fails to light within five seconds of power-on, an internal module failure may be
present.
ACCESSED Indicator. The ACCESSED indicator lights anytime the controller
accesses the logic analyzer module.
ARM’D Indicator. The ARM’D indicator lights when the logic analyzer module is
armed during an acquisition.
TRIG’D Indicator. The TRIG’D indicator lights when the logic analyzer module
triggers and stays on until the module finishes acquiring data.
Merge Cable Connectors
Rear Panel
The merge cable connectors (not shown) are located on the sides of the logic
analyzer module. The connectors are used to merge up to three logic analyzer
modules together to create a two- or three-wide logic analyzer module.
Two Merged Modules. When two modules are merged, the master module is on
the left (lower numbered slot) and the slave module is on the right.
Three Merged Modules. When three modules are merged, the master module is in
the center, and the slave modules are on the right and left of the master module.
Merge Cable Connector. The merge cable connector is located on the side panel of
the module. When the module is used by itself the merge cable is stored inside
the cover.
When you merge modules together, you must set up the merge connector so that
it mates with an adjacent logic analyzer module. Instructions for merging
modules are described in the Tektronix Logic Analyzer Family User Manual.
Four rear panel connectors (see Figure 2--1 on page 2--2) connect the logic
analyzer module to the backplane of the mainframe. The module receives power,
processor communication, and intermodule communication through these four
connectors.
2- 6
Logical Address Switches. Figure 2 --1 on page 2--2 shows the location of the
logical address switches.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Operating Information
Flash Programming Jumper Pins. Figure 2--1 on page 2--2 shows the location of
the two pins that are used when updating the firmware of the logic analyzer
module. You must jumper the pins when updating the flash image. The logic
analyzer module is shipped without a jumper installed on these pins. Refer to the
Tektronix Logic Analyzer Family User Manual for instructions on upgrading the
firmware.
Online Help
Diagnostics
Self Calibration
Most user information for operating the logic analyzer module is available
through the online help within the Tektronix Logic Analyzer Series application.
The logic analyzer module performs the power-on diagnostics each time you
power on the mainframe. The Calibration and Diagnostics property sheet appears
at power-on if one of the module diagnostics fails. You can also access the
diagnostics from the System menu. For additional diagnostics information, refer
to Calibration and Diagnostics Procedures, beginning on page 6--32.
In addition to the power-on diagnostics, you can also run the extended diagnostics or the self calibration.
NOTE. For best results, only run the diagnostics with probes disconnected from
the module.
Self calibration is an internal routine that optimizes performance. No external
equipment or user actions are needed to complete the procedure. The logic
analyzer module saves data generated by the self calibration in non-volatile
memory.
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Operating Information
NOTE. Performing the self calibration does not guarantee that all logic analyzer
module parameters operate within limits. Operation within limits is achieved by
performing the Adjustment Procedures. Proper operation may be confirmed by
performing the performance verification procedures in this same manual.
When to Perform the Self Calibration. You can run the self calibration at any time
during normal operation. To maintain measurement accuracy, perform the
self calibration if more than one year has elapsed since the last self calibration.
You can check the status of the self calibration in the Calibration and Diagnostics
property sheet.
If the logic analyzer module loses power during the self calibration, rerun the
self calibration following the next power-on. The self calibration data generated
before power was interrupted must be replaced with a complete set of new data.
For best results, always perform the self calibration after at least a 30 minute
warm-up.
Running the Self Calibration. The logic analyzer module may require several minutes to run the self calibration depending on the number of channels. Select
Calibration and Diagnostics property sheet from the System menu. Select the
Self Calibration tab page and select the logic analyzer module. Click on the Run
button to start the self calibration. Upon completing the self calibration the logic
analyzer module menu selection changes from Running to Calibrated.
Self Calibration for Merged Modules If you intend to merge modules, perform the
self calibration on each individual module first, then perform a self calibration on
the merged module set.
You can run the self calibration at any time during normal operation. To maintain
measurement accuracy, perform the self calibration if more than one year has
elapsed since the last self calibration.
You can check the status of the self calibration in the Calibration and Diagnostics
property sheet.
If the logic analyzer module loses power during the self calibration, rerun the self
calibration following the next power-on. The self calibration data generated
before power was interrupted must be replaced with a complete set of new data.
For best results, always perform the self calibration after at least a 30 minute
warm-up.
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Operating Information
The logic analyzer module may require several minutes to run the self calibration
depending on the number of channels. Select the Calibration and Diagnostics
property sheet from the System menu. Select the Self Calibration tab page and
select the logic analyzer module. Click the Run button to start the self calibration. Upon completing the self calibration, the logic analyzer module menu
selection changes from Running to Calibrated.
Menu Overview The logic analyzer is controlled by interactive windows through
the TLA application. The TLA application consists of the following windows:
H System Window. This window provides an overview of the entire logic
analyzer. Use this window to navigate through the logic analyzer.
The center of the System window displays icons that represent hardware
modules installed in the logic analyzer. The icons are linked to the other
windows in the logic analyzer.
H Setup Window. A setup window exists for each module in the logic analyzer.
It contains all of the setup information for the logic analyzer module such as
clocking, memory depth, threshold information, and channel information.
Menus and dialogs contain information to set up the window as needed.
For the DSO, the Setup window contains setup information for each DSO
channel such as the input voltage ranges, bandwidth, coupling, and
termination. It also contains horizontal setup information and a link to the
DSO Trigger window.
H Trigger Window. The Trigger window provides access to the logic analyzer
module or DSO module trigger setups. For either module, you can specify
various trigger events and trigger actions to help you capture the data that
you are interested in.
H Listing Data Window. The Listing Data window displays acquired data as
tabular text. Each column of data represents one group of data or other
logical data information, such as time stamps. Each row of data represents a
different time that the data was acquired; newer samples of data display
below older samples.
H Waveform Data Window. The Waveform Data window displays acquired
data as graphical waveforms. All defined channel groups display as busforms
for the logic analyzer and as individual analog channels for the DSO module.
H On/Off Buttons. These buttons enable or disable the operation of the
modules. Click the appropriate button to enable or disable the modules.
Refer to the online help for more information on the individual menus, icons,
and fields within each window. You may also want to refer to the Tektronix Logic
Analyzer Family User Manual for additional information.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
2- 9
Operating Information
Merged Modules
Merging Rules
A merged module set consists of a master module and one or two slave modules
connected together by a merge cable connector, and by signals on the local bus
of the mainframe backplane. The local bus sends the system clock of the master
module to the slave modules. Refer to the Tektronix Logic Analyzer Family User
Manual for detailed merging instructions.
The following LA module merging rules must be followed:
H Only modules with 102 channels or more can be merged.
H The modules must be physically adjacent, and physically connected.
H Modules of unequal clock rate cannot be merged. All maximum sync rates
must match for the entire merged set.
H Merged modules of unequal memory depths will assume the depth of the
shallowest module.
H When merging two modules of unequal channel widths, use the module with
the higher number of channels as the master module.
H When merging three modules of unequal channel widths, use the module
with the higher number of channels as the master module and use the module
with the fewest channels as slave two. Refer to Three Way Merge on page
2--12 for details.
H The modules should have the same firmware version.
H Two or three TLA7Nx, TLA7Px or TLA7Qx LA modules may be merged
together. Two TLA7Lx and TLA7Mx LA modules may be merged together.
TLA7Nx, TLA7Px, or TLA7Qx LA modules may not be merged with
TLA7Lx and TLA7Mx LA modules. (Even if they are connected together.)
H Merging operations may not be destructive to an established merged module
set. To merge a module to an established merged set, the established merged
set must first be unmerged through software. Unmerged modules are the only
potential candidates to add to a merged configuration.
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TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Operating Information
Two Way Merge
In a two way merge, the master module is on the left and the slave module is on
the right as shown in Figure 2--3.
Master
Module
Slave
Module
Figure 2- 3: Location of modules in a two way merge
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
2- 11
Operating Information
Three Way Merge
In a three way merge (TLA7Nx, TLA7Px or TLA7Qx LA modules only), the
master module is in the center. Slave module 1 is to the right of the master
module. Slave module 2 is on the left of the master module as shown in
Figure 2--4.
Slave
Module 2
Master
Module
Slave
Module 1
Figure 2- 4: Location of modules in a three way merge
2- 12
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Theory of Operation
The basic logic analyzer module consists of two main circuit boards: the LPU
(local processor unit) board and the acquisition board. The logic analyzer
modules with 102 or 136 channels also have one and two (respectively)
comparator daughter boards present. Up to eight probes acquire data from a
system under test and send it to the logic analyzer module for processing.
Block Level Description
The block level description provides an overview of each functional circuit
within the logic analyzer module. Except for the number of channels, the basic
operation is the same for each model.
The basic logic analyzer module consists of two main circuit boards: the Local
Processing Unit (LPU) board and the Acquisition board. The logic analyzer
modules with 102 or 136 channels also have one and two (respectively)
Comparator Daughter boards present. Up to eight probes acquire data from a
system-under-test and send it to the logic analyzer module for processing.
A single 102-channel or 136-channel logic analyzer module can be merged with
a second or third module to create a two- and three-module-wide logic analyzer.
Lower channel count modules do not support merging.
Local Processor Unit
Board
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
The Local Processor Unit board controls instrument hardware, signal acquisition,
power conditioning, and communications functions. Two 100-pin ribbon cables
provide interconnections with the acquisition board for power supplies, data and
control signals.
Processor System.The processor system contains a microprocessor that controls
the entire instrument. Commands and data sent to the instrument through the
mainframe pass through the communications interface, which resides on the bus.
The bus also routes data between the main processor system and the acquisition
board.
The processor system includes the instrument firmware. To facilitate upgrades,
the firmware resides in Flash ROM.
Communications Interface. The communications interface transfers commands
and data between the mainframe and the slot 0 controller. Signals pass between
the instrument and the mainframe through the rear connectors.
3- 1
Theory of Operation
Power Supplies.The Power Supplies receive +5 V , --5.2 V, +
12 V, and +24 V
from the mainframe through the rear connectors to power the logic analyzer
module. Fuses protect the mainframe from over-current conditions. Voltage
converters produce additional +5 V and +3.5 V supplies for use on the Acquisition board. The power connections to the Acquisition board are made through
one of the 100-pin ribbon cables and from the backplane.
Local Processor Unit Board Fuses. Table 3--1 lists the fuses on the Local
Processor Unit board and briefly describes their function.
Table 3- 1: Local Processor Unit board fuses
Fuse Voltage Purpose
F1780 +5 V Supplies the 5 V-to-3.5 V DC converter. The converter powers
the 3 V PALS and the 3 V ASICs on the Acquisition board. The
converter also enables the +
F1881 +5 V Supplies the microprocessor and the supporting circuitry.
F1681 +12 V Suppli es the Control IC and MOSFET drivers for the 5 V-to-3.5
V DC to DC converter.
F1983 -- 2 4 V Supplies the +24 V-to-5 V DC to DC converter. This +5 V output
powers the acquisition RAM on the Acquisition board.
24 V-to-5 V DC to DC converter.
Acquisition Board
F1981 +24 V Suppli es the +24 V-to-5 V DC to DC converter. This +5 V output
powers the acquisition RAM on the Acquisition board.
The acquisition board accepts input signals from the probes and converts them to
digital information. Two 100-pin ribbon cables provide interconnections with the
LPU board.
Clock Circuitry. The system clock is derived from the 10 MHz clock (from the
backplane) through a phase-locked loop. The acquisition run circuitry is
integrated with the clock circuitry to support time correlation.
Probe Interface. Acquisition data passes from the probe input circuitry to the
probe receivers. Each probe receiver receives 16 data signals and one clock/qualifier signal.
Two threshold voltages are generated for each probe input circuit (one for the
clock/qualifier signal and one for the 16 data signals). The threshold output
voltages are sent to the probe receiver . The threshold adjustment procedure,
performed by software, guarantees the accuracy of the reference voltages
provided to the probe receivers to achieve the desired low/high logic level
detection.
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TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Theory of Operation
Acquisition System. Acquired data from the probe interface is sent to the data
recognition circuitry. The data recognition circuitry analyzes the acquired data
and determines which data to qualify and send to the acquisition memory. It also
sends trigger event signals to the trigger and storage circuitry.
Trigger and Storage Control Circuitry. The trigger and storage control circuitry
works with the data recognition circuitry. The trigger circuitry determines when
to store data and when to trigger, controls counter/timers, and drives intermodule
signals. The storage circuitry receives information from the trigger circuitry to
determine when to start storing data and when to stop storing data.
Acquisition Memory. The acquisition memory stores acquired data. The acquisition memory can be set up to contain all data samples or it can be split to contain
data samples and glitch information.
When the acquisition memory is split, half of the memory depth is lost and the
logic analyzer module can only run at half speed. Each stored data sample takes
up two memory locations: one to store the actual data sample, and the other to
store the corresponding glitch information.
Daughter Boards
Probes
Backplane Interface. The backplane interface provides the interface with the
mainframe and the Acquisition board. The interface contains intermodule signals
that communicate with other modules. It also provides the 10 MHz reference
clock.
Local Processing Unit Interface. The LPU interface provides the interface between
the LPU circuit board and the acquisition board through two 100-pin ribbon
cables (W100 and W200).
Each comparator daughter board passes 32 data signals and 2 clock/qualifier
signals from the probes through two probe receiver ICs to the Acquisition board.
Each prove receiver also receives two threshold voltages (four threshold signals
total) from the Acquisition board. This results in 72 signal pins connecting each
Daughter board to the Acquisition board.
The 136-channel logic analyzer modules have two Daughter boards; the
102-channel logic analyzer modules have only one Daughter board. No Daughter
boards are present in 68-channel or 34-channel logic analyzer modules; the probe
input circuitry for these modules is present on the Acquisition board.
Each P6417 probe acquires 17 channels (16 data channels and one clock or
qualifier) of data.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
3- 3
Theory of Operation
Merged Modules
A merged module consists of a Master module and a Slave module connected
together by a merge cable connector and by signals on the local bus of the
mainframe backplane. The local bus sends the system clock of the Master
module to the Slave module. The two merged modules must be located in
adjacent slots.
The merge Cable Connector passes 26 signals between the two modules (16
trigger event signals, two storage control signals, foru valid sample clock iden
tification signals, and four data-login control signals).
3- 4
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Performance Verification: Logic Analyzer Module
This chapter contains procedures for functional verification, certification, and
performance verification procedures for the logic analyzer modules and the
adjustment/verification fixture. Generally, you should perform these procedures
once per year or following repairs that affect certification.
Summary V erification
Functional verification procedures verify the basic functionality of the instrument inputs, outputs, and basic instrument actions. These procedures include
power-on diagnostics, extended diagnostics, and manual check procedures.
These procedures can be used for incoming inspection purposes.
Certification procedures certify the accuracy of an instrument and provide a
traceability path to national standards. Calibration data reports are produced for
the logic analyzer modules as output from the performance verification and
adjustment software. For the adjustment/verification fixture, you can make
copies of the calibration data report included with this manual and then fill out
the report with the data that you obtain from the performance verification
procedures.
Performance verification procedures confirm that a product meets or exceeds the
performance requirements for the published specifications documented in the
Specifications chapter of this manual. Refer to Figure 4--1 on page 4--2 for a
graphic overview of the procedures.
Adjustment procedures check for, and if necessary, correct any adjustment errors
discovered when performing functional or performance verification procedures.
The adjustment procedures for the logic analyzer modules are controlled by
software while the procedures for the adjustment/verification fixture require
manual intervention. Some of the adjustment procedures for the logic analyzer
modules also require manual intervention to move probes or change test
equipment settings.
The performance verification and adjustment software is provided on the product
CD-ROM. If you have not already done so, refer to Software Installation and
Removal beginning on page 2--2 for instructions on installing the performance
verification and adjustment software.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
4- 1
Performance Verification: Logic Analyzer Module
Determine equipment
to certify.
Use
Tektronix-supplied
probes.
Go to appropriate
procedure(s).
Gather required test
equipment.
Is it OK
No
with customer to
remove/reconnect probes
from System
Under Test?
Select procedure.
Configure customer’s
mainframe and modules as
described in procedure.
Set up test equipment.
Yes
Allow all mainframes, modules and
equipment to warm up (30 minutes).
Load PV/Adjust
software.
Perform procedure
using software.
Do tests
pass?
No
Yes
Print Calibration
Data Report.
Create necessary
Calibration Certificate.
No
Are
all certifications
complete?
Repair or adjust
equipment as
required.
Figure 4- 1: Calibration/certification procedure flow chart
4- 2
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Yes
Done
Performance Verification: Logic Analyzer Module
Test Equipment
The procedures use external, traceable signal sources to directly test characteristics that are designated as checked (n)intheSpecifications chapter of this
manual. Table 4--1 shows the required equipment list; the equipment is required
for the performance verification procedures and adjustment procedures for the
logic analyzer modules and for the adjustment/verification fixture.
Table 4- 1: Test equipment
Item number and description Minimum requirements Example
1. Mainframe TLA700 Series Mainframe with a logic
analyzer module installed
2. Adjustment/verification fixture,
with one of the following
Power Supplies:
USA/CAN
Europe
Japan
United Kingdom
3. Oscilloscope 1 GHz bandwidth Delay time accuracy ±25
4. DSO probes Two required, with < one-inch ground leads Tektronix P6243 or P6245 probe, with accesso-
5. 1X probe One required, with < one-inch ground leads Tektronix P6101B probe, with accessories
6. Logic analyzer probes Two required Tektronix P6417 or P6418 Logic Analyzer probes
7. High density logic analyzer
probe (optional)
8. Frequency counter Frequency range: 1 GHz Tektronix DC508
9. Digital multimeter with leads DCV accuracy: 0.1% from --10 V to +100 V Tektronix DMM 900 Series
10. Connector, dual-banana Female BNC-to-dual banana Tektronix part number 103-0090-XX
11. Voltage reference Accuracy: ≤0.01% Data Precision 8200
12. Capacitor
13. Adapter, N-to-BNC Male type N-to-female BNC Tektronix part number 103-0045-XX
14. Shorting jumpers Strip of 10, 2-wide Tektronix part number 131-5829-XX
15. Cable, precision 50 Ω coaxial 50 Ω, 36 in, male-to-male BNC connectors Tektronix part number 012-0482-XX
16. Signal Generator 250 MHz Tektronix SG503
1
The capacitor is installed across the Data Precision 8200 output terminals to reduce noise. If your voltage reference
produces <4 mVp-p of noise, external noise reduction is not necessary.
1
12 V, 1.5 A
12 V, 1.5 A
12 V, 1.5 A
12 V, 1.5 A
ppm over any ≥ 1 ms interval
One required Tektronix P6434 Logic Analyzer probe
0.1 F, 200 V Tektronix part number 283-0189-XX
TLA721 Benchtop Mainframe or
TLA715 Portable Mainframe
Tektronix part number 671-3599-XX
Tektronix part numbers:
119-4855-XX
119-4856-XX
119-4859-XX
119-4857-XX
Tektronix TDS 784D
ries
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
4- 3
Performance Verification: Logic Analyzer Module
Functional Verification
This section contains instructions for performing the functional verification
procedures for the TLA7Nx, TLA7Px, and TLA7Qx Logic Analyzer modules;
functional verification procedures for the adjustment/verification fixture begin on
page 4--21. These procedures provide an easy way to check the basic functionality of the LA modules and probes.
Table 4--2 lists the functional verification procedures available for the logic
analyzer modules and probes.
Table 4- 2: Logic Analyzer Module functional verification procedures
Instrument Procedure
Single logic analyzer module Extended diagnostics No
Adjustment/verification
fixture required
Merged logic analyzer module Extended diagnostics
Merge diagnostics
P6417, P6418, and P6434
Logic Analyzer probe
Signal input check Ye s
No
No
If any check within this section fails, refer to the Troubleshooting section in the
Maintenance chapter of this manual for assistance. Failed tests indicate the
instrument needs to be serviced.
The functional verification procedure consists of the following parts:
H Module self tests and power-on diagnostics
H Single module procedure
H Merged module procedure
H Probe verification
This procedure provides a functional check only. If more detailed testing is
required, perform the Performance Verification Procedure after completing this
procedure.
4- 4
Perform these tests whenever you need to gain confidence that the instrument is
operating properly.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Performance Verification: Logic Analyzer Module
Test Equipment
Setup
Module Self Tests and
Power-On Diagnostics
You will need the following equipment to complete the functional verification
procedure:
H TLA700 Series Logic Analyzer mainframe with one LA module installed
(more modules are required to check the merged functionality)
H One adjustment/verification fixture with power supply
It is assumed that the LA module is properly installed and that all accessories are
connected. Refer to the Tektronix Logic Analyzer Family User Manual for
installation instructions.
Power on the instrument and allow a 30-minute warmup before continuing with
any procedures in this section.
During power-on, the installed modules perform an internal self test to verify
basic functionality. No external test equipment is required. The self tests require
only a few seconds per module to complete. The front-panel ARM’Dand
TRIG’D indicators blink during the self test. After testing completes, the front
panel indicators have the following states:
H READY — Green (on)
H ACCESSED — off
H ARM’D — off
H TRIG’D — off
Next, the power-on diagnostics are run. If any self tests or power-on diagnostics
fail, the instrument displays the Calibration and Diagnostics property sheet.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
4- 5
Performance Verification: Logic Analyzer Module
Single LA Module
Functional Verification
Procedure
The following procedure checks the basic functionality of a single LA module.
Functional verification consists of running the extended diagnostics.
NOTE. Running the extended diagnostics invalidates any acquired data. If you
want to save any of the acquired data, do so before running the extended
diagnostics.
Prerequisites Warm-up time: 30 minutes
Power-up diagnostics pass
SELF_CAL passes
Perform the following steps to complete the functional verification procedures.
Before beginning this procedure, be sure that no active signals are applied to the
instrument. Certain diagnostic tests will fail if signals are applied to the probe
during the test.
1. In the logic analyzer application, go to the System menu and select
Calibration and Diagnostics.
2. Click the Extended Diagnostics tab.
3. Select the top level test and click the Run button.
The diagnostics will perform each one of the tests listed in the menu under
the module selection. All tests that displayed an Unknown status will change
to a Pass or Fail status depending on the outcome of the tests.
4. Scroll through the test results and verify all tests pass.
NOTE. If Extended Diagnostics fail, run Self Cal for the LA module and then
rerun Extended Diagnostics.
4- 6
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Performance Verification: Logic Analyzer Module
Merged LA Module
Functional Verification
Procedure
The following procedure checks the basic operation of the merged modules.
NOTE. Running the extended diagnostics will invalidate any acquired data. If
you want to save any of the acquired data, do so before running the extended
diagnostics.
Prerequisites Warm-up time: 30 minutes
Merge cable installed between al l of the LA merged modules
Power-up diagnostics pass
SELF_CAL passes
Perform the following steps to complete the functional verification procedures.
Before beginning this procedure, be sure that no active signals are applied to the
instrument. Certain diagnostic tests will fail if signals are applied to the probe
during the test.
1. In the logic analyzer application, go to the System menu and select
Calibration and Diagnostics.
2. Click the Extended Diagnostics tab.
3. Select the top level test and click the Run button.
The diagnostics will perform each one of the tests listed in the menu under
the module selection. All tests that displayed an Unknown status will change
to a Pass or Fail status depending on the outcome of the tests.
4. Scroll through the test results and verify all tests pass.
NOTE. If Extended Diagnostics fail, run Self Cal for the LA modules and then
rerun Extended Diagnostics.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
4- 7
Performance Verification: Logic Analyzer Module
Logic Analyzer Probe
Functional Verification
Procedure
The following procedure checks the basic operation of the probes by verifying
that the probes recognize signal activity at the probe tips.
Equipment required Adjustment/verification fixture version (item 2 )
Prerequisites Warm-up time: 30 minutes
P6417, P6418 or P6434 probe connected
Test equipment connected as shown in Figure 4--2
Diagnostics and SELF_CAL pass
1
Do not mix probes; only one type of probe can be functionally verified at a time.
C2/C3/CK3
Channel/Group
Clock channel
Adjustment/verification
J5
J3
J1
fixture
J26
J2
1
Fixture supply
Figure 4- 2: Probe functional verification test setup
Perform the following steps to complete the probe functional verification:
1. Ensure that the jumper at J15 on the adjustment/verification fixture is in the
INT position to select the internal 50.065 MHz clock. See Figure 4--4 on
page 4--16 for location of J15.
2. Open the Setup window for the LA module.
3. Click the Set Thresholds button to display the Probe Threshold dialog box.
4. Adjust the threshold level to 700 mV for all channels.
5. Connect the acquisition probe to be tested to the C3/C2 channel group on the
LA module.
6. Refer to Figure 4--2 and connect the probe to J1 and J2 on the adjustment/
verification fixture. Ensure that you connect the ground side of the podlets to
the ground side of the adjustment/verification fixture connectors.
4- 8
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Performance Verification: Logic Analyzer Module
NOTE. These procedures assume the P6418 or P6417 probes are being used. If
you have a P6434 probe, use J5, the Data Out connector on the adjustment/verification fixture for verifying probe functionality. Observe proper polarity: pin 1
to pin 1.
7. Connect the single clock (CK n) or the qualifier (Q n) channel to one of the
J3 CLK OUT connector pairs on the adjustment/verification fixture.
8. Return to the Setup window and click the Show Activity button to display
the Activity Monitor.
9. Verify that the Activity Monitor shows activity on all probe channels
connected to the test fixture.
Figure 4--3 shows an example of the Activity Monitor. Note the signal
activity for clock CK3 and data channels for the C3(7-0) and C2(7-0) groups.
Also note that there is no activity on the other groups because the probe
podlets are not connected to a signal source (the channels are all high).
Figure 4- 3: Activity Monitor
10. Verify that none of the connected channels are stuck high or stuck low.
11. Disconnect the probe from the adjustment/verification fixture and module.
12. Repeat steps 5 through 11 for any remaining probes.
13. Close the Activity Monitor.
14. Return the threshold levels to their former values in the Probe Threshold
window.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
4- 9
Performance Verification: Logic Analyzer Module
LA Module Certification
Using the performance verification procedures, perform the DC Threshold test
and print the software-generated Calibration Data Report. Other module
specifications can also be verified by running the performance verification
procedures.
Performance Verification Instructions
This section contains information to verify the performance of the LA module.
Testing is performed using the performance verification and adjustment software.
The performance verification and adjustment software contains instructions and
control programs for testing each characteristic designated as checked (n)inthe
Specifications chapter of this manual.
As a general rule, these tests should be done once a year.
Prerequisites
These procedures ask for the serial number of the LA module under test. Before
installing the LA module in the mainframe, record the serial number and state
speed of the LA module.
Alternatively, you can access the module serial number and state speed through
the logic analyzer application. In the application, go to the System menu, select
System Properties, and then click the LA module tab. However, you must quit
the logic analyzer application before continuing with the performance verification procedures.
The tests in this section comprise an extensive, valid confirmation of performance and functionality when the following requirements are met:
H When multiple LA modules of the same model number are installed in the
mainframe, the performance verification and adjustment software will
address only the module in the highest-numbered slot.
If you are testing a TLA7Q4 module for example, move it to a higher slot
number than all other TLA7Q4 modules in the mainframe. This method
avoids unnecessary module warm-up time.
H When verifying the performance of merged modules using the same type of
individual modules, the individual modules must be physically separated
before continuing; refer to the Tektronix Logic Analyzer Family User Manual
for information on merging and unmerging modules.
4- 10
H The logic analyzer application must not be running.
H The performance verification and adjustment software must be loaded. Refer
to Software Installation and Removal on page 2--2.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Performance Verification: Logic Analyzer Module
H The LA module must be installed in a mainframe, operating for at least
30 minutes, and operating at an ambient temperature between +20_ C
and +30_ C.
H The LA module must have been last adjusted at an ambient temperature
between +20_ C and +30_ C.
H The logic analyzer must be in an operating environment within the limits
described in the Specifications section of the Tektronix Logic Analyzer
Family User Manual.
H When verifying the performance of merged modules consisting of different
types of individual modules, the merged module can be tested without
separation. The performance verification and adjustment software runs
independent of the logic analyzer application and does not recognize
configuration settings. It is unnecessary to unmerge modules through the
logic analyzer application before performing these procedures.
Procedure Overview
When using the performance verification and adjustment software, you will
connect external test equipment to the LA module in response to prompts on the
screen. You will connect the test signals and then instruct the program to
continue. The performance verification and adjustment software automatically
selects the module settings and determines the results of each test.
The results of the tests are recorded in a temporary file and are available upon
test completion for completing test records for certification. To obtain partial test
information you can also run individual tests or selected groups.
NOTE. The SELF_CAL test must run successfully before the other tests are
performed. The remaining tests can then be performed in any order.
Before testing an instrument following repair, you must first complete the
adjustment procedure.
The performance verification and adjustment software contains the tests shown
in Table 4--3. Each test verifies one or more parameters. All of the tests check
characteristics that are designated as checked (n)intheSpecifications chapter.
By running a full PV sequence, you will verify the performance of the LA
Module.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
4- 11
Performance Verification: Logic Analyzer Module
Table 4- 3: LA Module performance verification tests
Performance verification test name Specification tested
1. FPV_DC_THRESHOLD
2. FPV_SETUP_0F Setup time
3 FPV_HOLD_0F Hold time
4. FPV_MAXSYNC Maximum synchronous clock rate
1
Certifiable parameter
Table 4--4 lists the additional characteristics that are designated as checked (n)
in the Specifications chapter. These characteristics are indirectly tested by the
performance verification and adjustment software tests named in the table.
Table 4- 4: LA Module characteristics indirectly checked by the performance
verification tests
1
Threshold accuracy
Performance verification test name Specification tested
1. FPV_SETUP_0F Minimum recognizable word
2 FPV_HOLD_0F Minimum recognizable word
1,2
1,2
3. All tests Trigger state sequence rate
4. All tests, and Extended Diagnostics Internal sampling period
1
When the setup and hold time tests are both performed, the setup and hol d
3
window size is indirectly verified.
2
When the setup and hold time tests are both performed, the channel-to-channel
skew is indirectly verified.
3
When all of the tests are performed, including Extended Diagnostics, the
internal sampling period is indirectly verified.
In addition to the basic system setup, you will need some of the equipment
shown in Table 4--1 on page 4--3 to complete the performance verification
procedures.
Each procedure includes a table that calls out the equipment used. Use Table 4--1
for equipment specifications. If you substitute equipment, always choose
instruments that meet or exceed the minimum requirements specified.
4- 12
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Performance Verification: Logic Analyzer Module
Using the Software
The software consists of executable software files. Use the following steps to
start and run the software:
1. Allow the instruments to warm up for at least 30 minutes before beginning
the procedure.
2. Quit all applications including the TLA application.
3. Select Start → Programs → TLA Performance Verification.
4. To run the performance verification and adjustment software, select the
following:
H For the LA modules, select LA 7XX PV.
5. Follow the instructions on the screen to enter the name you want to appear in
the User Name field as shown below. This name will appear on the
Calibration Data Reports.
6. The program lists several different modules, referred to as DUT (Device
Under Test). Enter the number corresponding to the module type that you
want to test; then click Enter to continue.
The screen will display an error message if the DUT chosen does not match
the installed DUT.
7. Click Enter to continue.
8. Enter the complete serial number of the DUT (for example, B010100). Click
Enter to continue.
If you select no, a prompt asks you to enter the serial number again.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
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Performance Verification: Logic Analyzer Module
9. The program lists sequences for PV (performance verification) and ADJ
(adjustments). Enter a number to select which sequence you want and click
Enter to continue.
10. If an instrument is being tested, the program lists the different probe types
available for testing. Enter the appropriate number corresponding to your
probe and then click Enter to continue.
11. Enter the operating temperature in degrees C (entries in the range of 20 to 30
degrees are valid). Click Enter to continue.
12. Enter the operating humidity as a percentage (0% to 100% entries are valid).
Click Enter to continue.
13. Determine which sequence to run:
H RUN FULL SEQUENCE runs the entire sequence from beginning to
end. This is the recommended selection.
H RUN PARTIAL SEQUENCE runs part of the full sequence. The
sequence runs from the selected starting point to the end of the sequence.
Using the Interrupt Button
H SELECT TEST(S) runs only the selected tests. To run a single test, enter
the test number. To run multiple tests, enter a comma-separated list of
numbers or a hyphen-separated list of numbers.
Enter the number next to your choice and click Enter to continue.
14. Follow the on-screen instructions to connect and adjust test equipment.
15. When testing is completed, disconnect the test equipment.
While the program is running, you can interrupt the program to rerun a test, start
over, or to exit the program by clicking the Interrupt button (shown below).
The program will then provide a list of choices. Enter the number next to the
choice that you want and click Enter.
NOTE. If you interrupt a test before it has completed, you must restart the test to
obtain valid test data.
4- 14
Some tests such as Internal Cal do not allow interrupts. If you stop these tests
using more aggressive methods, you may have to reboot the instrument.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Performance Verification: Logic Analyzer Module
Obtaining Test Results
The results of all tests can be stored in a file on the hard disk. You can view the
test results, print the test results to a printer, or save the test results in another file
on the hard disk. The software stores the test results in a file containing the
module name and serial number (for example, TLA7Q4.B020123). The file is
located under the following path: C:\Tekcats\Rpt.
NOTE. If you want to save the content of the Report file, you must rename or
copy the Report file using the Windows file utilities such as Explorer.
The Report file will be overwritten the next time you run the performance
verification and adjustment software and print or view a new set of test data.
After completing a full or partial test sequence (or just before you exit the
program) you can generate the test data and write it to a file. You have the option
of printing the file, viewing the file on screen, or transferring the file to another
directory or host computer.
You can print the test data directly from the program. Ensure that a printer is
connected to your logic analyzer and follow the on-screen instructions to print
the test results.
If a printer is not available, you can view the test results directly from the screen,
or you can copy the test results to a different file or folder/host computer for
future use.
Field Adjust/PV Software
Housekeeping
Troubleshooting
The performance verification and adjustment software creates data log files (.dlf
files) that store program data. The .dlf files are used by the performance
verification and adjustment software to generate the view data and print out
options. Each .dlf file is identified by the product serial number; for example,
B010100.dlf. The files are stored in the Tekcats folder under each TLA7xx
folder. To conserve disk space, you must occasionally delete the .dlf files.
If any tests fail, use the following steps to troubleshoot the problems:
1. Check all test equipment for improper or loose connections.
2. Check that all test equipment is powered on and has the proper warm-up
time.
3. If you are using the adjustment/verification fixture, verify the LED is
lighted, the jumper positions match the on-screen instructions, and the
external connections are correct. (See Figure 4--4 for jumper locations.)
4. Rerun mainframe or module diagnostics and module adjustment.
5. Run the tests a second time to verify the failure.
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Performance Verification: Logic Analyzer Module
Performance Verification Tests
Use the following tables and figures to set up and execute each procedure.
NOTE. The illustrations in the following procedures show P6418 or P6417
probes. If you have a P6434 probe, use J14 on the adjustment/verification fixture
for the DC Threshold test; all other procedures using the P6434 probe use J5,
the Data Out connector. When using either type of probe, always observe correct
polarity (GND to GND, pin 1 to pin 1).
Threshold
External
Clock in
P6434
Threshold out
J14
J15
J10 J8
J22
J18
J26
J19
J17
J9
J11
DC in
in
P6417 and P6418 Threshold out
J6 J7
J20
J1
J16
J13
J2
J3
J5
J4
P6417
and
P6418
Data out
P6434
Data out
J17
Hold/Setup
select
SetupHold
clocked on falling edge
Jumper removed:
clocked on rising edge
J19
Jumper installed:
Ext/Int
Clock select
J15
IntExt
12345
J16
Deskew
Figure 4- 4: Adjustment/verification fixture connections and jumper locations
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TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Deskew
Probe
setup
6
J13
P6434
Deskew/Probe setup
1
Clock
Clock
GND
GND
J4
Setup/Hold
Clock out
Performance Verification: Logic Analyzer Module
LA Module Procedure 1:
FPV_DC_Threshold
This procedure verifies the DC Threshold Accuracy of the LA Module. This test
is performed once and applies to all channels of the module.
SW test name FPV_DC_Threshold
Equipment required
Prerequisites Warm-up time: 30 minutes
C2/C3/CK3
Channel/Group
Adjustment/verification fixture and fixture supply (item 2)
Voltage reference (item 11)
Precision BNC cable (item 15)
Dual banana-to-BNC adapter (item 10)
Capacitor, 0.1 F (item 12)
Test equipment connected as shown in Figure 4--5
Diagnostics and SELF_CAL pass
Voltage reference
+
--
0.1 F Capacitor
Adjustment/verification
fixture
J22
Dual banana-toBNC adapter
Fixture supply
BNC cable
J7
Figure 4- 5: FPV_DC_Threshold test setup
1. If the logic analyzer application is running, quit the application. Verify that
all of the prerequisites listed previously are met for the procedure.
2. Run the performance verification and adjustment software as described in
Using the Software on page 4--13. Run the C:\Tekcats\Tla_la program and
then select the correct module type and the PV test option.
3. Follow the on-screen instructions to run each portion of the test for each
parameter of the instrument.
4. Verify that all of the tests pass.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
J26
J14 Threshold out P6434
J6
4- 17
Performance Verification: Logic Analyzer Module
LA Module Procedure 2:
FPV_Setup_0F
This procedure verifies the setup time of the LA module.
SW test name FPV_Setup_0F
Equipment required
Prerequisites Warm-up time: 30 minutes
C2/C3/CK3
Channel/Group
Clock channel
Adjustment/verification fixture and fixture supply (item 2)
Test equipment connected as shown in Figure 4--6
Diagnostics and SELF_CAL pass
Adjustment/verification
J4
J5
J2
J1
fixture
Fixture supply
J26
Figure 4- 6: Initial FPV_Setup_0F test setup
1. If the logic analyzer application is running, quit the application and verify
that all of the prerequisites listed previously are met for the procedure.
2. Follow the on-screen instructions to run each portion of the test for each
parameter of the LA module.
3. Verify that all of the tests pass. If a test fails, run the Deskew routine as
described on page 5--8, then rerun the test.
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Performance Verification: Logic Analyzer Module
LA Module Procedure 3:
FPV_Hold_0F
This procedure verifies the hold time of the LA Module.
SW test name FPV_Hold_0F
Equipment required
Prerequisites Warm-up time: 30 minutes
C2/C3/CK3
Channel/Group
Clock channel
Adjustment/verification fixture and fixture supply (item 2)
Test equipment connected as shown in Figure 4--7
Diagnostics and SELF_CAL pass
Adjustment/verification
J4
J5
J2
J1
fixture
J26
Fixture supply
Figure 4- 7: Initial FPV_Hold_0F test setup
1. If the logic analyzer application is running, quit the application and verify
that all of the prerequisites listed previously are met for the procedure.
2. Follow the on-screen instructions to run each portion of the test for each
parameter of the LA module.
3. Verify that all of the tests pass. If a test fails, run the Deskew routine as
described on page 5--8, then rerun the test.
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Performance Verification: Logic Analyzer Module
LA Module Procedure 4:
FPV_Maxsync
This procedure checks the Maximum Synchronous Clock Rate and the Trigger
State Sequence Rate of the LA Module. This test is performed once and applies
to all channels of the module.
SW test name FPV_Maxsync
Equipment required
Prerequisites Warm-up time: 30 minutes
C2/C3/CK3
Channel/Group
Adjustment/verification fixture and fixture supply (item 2)
Sine wave generator (item 16)
BNC cable (item 15)
Adapter, N-to-BNC (item 13)
Test equipment connected as shown in Figure 4--8
Diagnostics and SELF_CAL pass
Sine wave generator
Type N-to-BNC
adapter
BNC cable
Adjustment/verification
J4
J5
fixture
J18
Fixture supply
Clock channel
J2
J26
J1
Figure 4- 8: FPV_Maxsync test setup
1. If the logic analyzer application is running, quit the application and verify
that all of the prerequisites listed previously are met for the procedure.
2. Follow the on-screen instructions to run the test.
3. Verify that all of the tests pass.
After completing the performance verification procedures, obtain a copy of the
test results and verify that all parameters are within the allowable specifications
as listed in the Specifications chapter of this manual.
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Performance Verification: Adjustment/Verification Fixture
This section contains the functional verification procedures, performance
verification procedures, and certification procedures for the adjustment/verification fixture. A calibration data report for the adjustment/verification fixture is
also available at the end of this chapter where you can record the certifiable
parameters.
Test Equipment
These procedures use external, traceable signal sources to directly test characteristics that are designated as checked (n)intheSpecifications chapter of this
manual. Table 4--1 on page 4--3 shows the required equipment list for the
procedures in this section. Each piece of equipment used in these procedures is
referenced by an item number to the equipment listed in Table 4--1.
Functional Verification
The functional verification procedure consists of the following checks:
Power Supply
H Basic power supply verification
H External clock input circuit verification
This procedure provides a functional check only. If more detailed testing is
required, perform the performance verification procedure, which begins on
page 4--25, after completing this procedure.
Use the following procedure to verify that the fixture power supply is functional.
1. Plug the fixture power supply included with the adjustment/verification
fixture into an appropriate socket and plug the DC connector into J26.
2. The LED adjacent to J26 should light. This indicates the input power supply
is functioning properly.
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Performance Verification: Ajustment/Verification Fixture
External Clock Input
Use the following procedure to verify the external clock input circuit is dividing
the input frequency by two and routing this clock signal to the proper output
connectors. This test provides a basic functionality check of the adjustment/verification fixture.
Parameter tested External clock input
Equipment
required
Prerequisites Warm-up time: 30 minutes for adjustment/verification fixture and test
Sine wave generator (item 16)
Precision BNC cable (item 15)
Oscilloscope (item 3)
Oscilloscope probe (item 4)
equipment
1. Set the jumper positions as called out in the table. R efer to Figure 4-- 9 on
page 4--23 for jumper locations.
Jumper Jumper name Jumper setting
J13 P6434 Setup & Hold/Deskew select Disconnected
J15 Clock selection EXT
J16 Deskew 1-2 and 4-5 connected
J17 Setup/hold select Disconnected
J19 Clock polarity select Disconnected
2. Connect the sine wave generator to J18, EXT CLK IN, on the adjustment/
verification fixture.
3. Set the generator output to 210 MHz, 1 V p-p.
4. Set up the oscilloscope by pressing Setup, Factory Setup, and then press OK
Confirm Factory Init to return the oscilloscope to default conditions.
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TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
R38 (VDDadjust )
Performance Verification: Ajustment/Verification Fixture
J10 (VDD)
Threshold
External
Clock in
J9 ( GND )
J8 (VEE)
DC in
in
J22
J18
Setup/Hold
J26
J17
select
SETUPHOLD
Jumper installed:
clocked on falling edge
Jumper removed:
clocked on rising edge
J19
J17
J19
J15
Ext/Int
Clock select
J15
INTEXT
J14
12345
J16
DESKEW
J6 J7
J16
J13
DESKEW
PROBE
SETUP
6
J13
P6434
Deskew/Probe setup
J20
J1
J2
J3
R321
J5
R39
J4
R127
1
Clock
Clock
R85
R67
Denotes ground
side of resistor
GND
GND
J4
Setup/Hold
Clock out
Figure 4- 9: Adjustment/verification fixture detail
5. Set up the oscilloscope as listed below.
a. Set up the CH1 Vertical menu as follows:
H Coupling DC/50 Ω
H Fine Scale 200 mV/div
H Position --3.32 div
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
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Performance Verification: Ajustment/Verification Fixture
b. Set up the Horizontal menu as follows:
H Time Base Main
H Record Length 5000
H Horizontal Scale Main Scale @ 5 ns/div
c. Set up the Trigger menu as follows:
H Source CH1
H Coupling DC
H Slope +
H Level 700 mV
H Mode Normal
d. Set up the Measure menu as follows:
H Select Measurement for CH1 Frequency
H Gating Off
e. Set up the Cursor menu as follows:
H Function Off
f. Set up the Acquire menu as follows:
H Acquisition Mode Sample
H Repetitive Signal On
6. Using the oscilloscope and the custom probe adapter shown in Figure 4--10
on page 4--26, verify that the output frequency at J1 pin-2 on the adjustment/
verification fixture is 105 MHz.
7. Press the Run/Stop button to stop the acquisition.
8. Disconnect the test equipment from the adjustment/verification fixture.
9. This completes the functional verification procedures for the adjustment/ver-
ification fixture.
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TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Certification
The internal system clock and clock output timing are checked for accuracy. The
adjustment/verification fixture accuracy is certifiable if these parameters meet
specifications.
The procedure is described in the performance verification section, beginning on
page 4--25. Make a copy of the Calibration Data Report at the end of this chapter
and then record the results on the copy.
Performance Verification
This section contains procedures to verify the accuracy of the adjustment/verification fixture.
Performance Verification: Ajustment/Verification Fixture
Prerequisites
Tests Performed
The tests in this section provide a valid confirmation of performance and
functionality when the following requirements are met:
H The adjustment/verification fixture must have been operating for a warm-up
period of at least 30 minutes, and must be operating at an ambient temperature between +20_ C and +30_ C.
H The adjustment/verification fixture must have been last adjusted at an
ambient temperature between +20_ C and +30_ C.
H The adjustment/verification fixture must be in an environment within the
same limits as for the logic analyzer, described in the Specifications section
of the Tektronix Logic Analyzer Family User Manual.
These tests should be performed once every two years.
Each test verifies one or more parameters.
Table 4- 5: Adjustment/verification fixture performance verification tests
Test name Specifi cati on tested
Power supply V
Internal clock frequency
Data skew
Hold time
Setup time
1
1
1
1
Certifiable parameter
1
DD
50.065 MHz
Less than 50 ps between any 2 channels
0.0 ns
+3.0 ns
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4- 25
Performance Verification: Ajustment/Verification Fixture
Custom Probe Tip Adapter
A custom probe tip adapter is used in these procedures to ensure signal integrity
when making precise measurements. The primary function of the custom probe
tip adapter is to minimize the length of the ground lead of the probe. Build the
custom probe tip adapter as shown in Figure 4--10.
Socket,
Tektronix P/N
131-0258-00
.025 in Berg pin,
Tektronix P/N
131-1426-00
Adjust this distance to span
a 1206 SMT component,
such as R85 on the adjust-
ment/verification fixture.
Solder pin to
socket frame
Figure 4- 10: Probe tip adapter detail
4- 26
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Test Procedures
Performance Verification: Ajustment/Verification Fixture
Refer to Figure 4--11 on page 4--28 for component and test point locations used
in the following procedures. Table 4--6 on page 4--28 describes the functions of
the jumpers used on the fixture for verifying the performance of the Tektronix
logic analyzers. The jumpers are also used in these procedures.
All procedures must be followed sequentially. If any single step fails or is out of
calibration, then upon retest, you must start at the first test and follow this
section through from start to finish sequentially.
Power Supply Checks
The following procedures check the DC power supply characteristics.
Parameter tested Power supply
Equipment
required
Prerequisites Warm-up time: 30 minutes for adjustment/verification fixture and test
DMM with test leads (item 9)
equipment
1. Plug the fixture supply into an appropriate AC outlet and connect the
DC plug to J26 on the adjustment/verification fixture.
2. Connect the DMM (--) lead to J8 (V
3. Connect the DMM (+) lead to J10 (V
).
EE
) and verify a voltage reading of
DD
+5.00 V ±100 mV.
4. Leave the (+) lead of the DMM connected to J10 (V
) and connect the
DD
DMM (--) lead to J9 (GND). Verify a voltage reading of +2.00 V ±30 mV.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
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Performance Verification: Ajustment/Verification Fixture
R38 (VDDadjust )
J10 (VDD)
Threshold
External
Clock in
J9 ( GND )
J8 (VEE)
DC in
in
J22
J18
Setup/Hold
J26
J17
select
SETUPHOLD
Jumper installed:
clocked on falling edge
Jumper removed:
clocked on rising edge
J19
J17
J19
J15
Ext/Int
Clock select
J15
INTEXT
J14
12345
J16
DESKEW
J6 J7
J20
J16
J13
DESKEW
PROBE
SETUP
6
J13
P6434
Deskew/Probe setup
J1
J2
J3
R321
J5
R39
J4
R127
1
Clock
Clock
R85
R67
Denotes ground
side of resistor
GND
GND
J4
Setup/Hold
Clock out
Figure 4- 11: Adjustment/verification fixture detail
Table 4- 6: Adjustment/verification fixture jumper settings
Jumper Jumper name Jumper function
J13 P6434 Deskew/probe
setup
J15 Clock selection Determines whether the internal clock (50.065 MHz) or the
J16 Deskew Selects between minimum or nominal pulse width
J17 Setup/hold select Determines whether checking setup time or hold time
J19 Clock polarity select Selects polarity of the clock for setup and hold testing
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TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Determines whether checking setup/hold or deskew for the
P6434 probe (J5)
external clock (J18, BNC) will drive the circuitry
Performance Verification: Ajustment/Verification Fixture
Verify Internal Clock
Frequency
Use the following procedure to verify the internal clock frequency.
Parameter tested Internal clock frequency
Equipment
required
Prerequisites Warm-up time: 30 minutes for adjustment/verification fixture and test
Frequency counter (item 8)
equipment
1. Set the jumper positions as listed in the table.
Jumper Jumper name Jumper setting
J13 P6434 Deskew/probe setup 3-5 connected
J15 Clock selection INT
J16 Deskew 2-3 and 4-5 connected
J17 Setup/hold select HOLD
J19 Clock polarity select Removed
2. Using the frequency counter, measure the oscillator frequency at pin J1-2.
The frequency should match what is listed on the Calibration Data report.
3. Record this measurement on the Calibration Data Report.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
4- 29
Performance Verification: Ajustment/Verification Fixture
Verify Data Output
Channel-to-Channel Skew
Use the following procedure to verify the channel-to-channel data skew.
Parameter tested Channel-to-channel data skew
Equipment
required
Prerequisites Warm-up time: 30 minutes for adjustment/verification fixture and test
Oscilloscope (item 3)
2 DSO probes (item 4)
Custom probe tip adapter (see Figure 4--10, page 4--26)
equipment
1. Set the jumper positions as listed in the following table.
Jumper Jumper name Jumper setting
J13 P6434 Deskew/probe setup 3-5 connected
J15 Clock selection INT
J16 Deskew 2-3 and 4-5 connected
J17 Setup/hold select HOLD
J19 Clock polarity select Removed
2. Set up the oscilloscope by pressing Setup, Factory Setup, and then OK Confirm Factory Init to return the oscilloscope to default conditions.
3. Set up the oscilloscope as listed below.
a. Set up the CH1 and CH2 Vertical menu as follows:
H Coupling DC/50 Ω
H Fine Scale 200 mV/div
H Position --3.00 div CH1
H Position --3.32 div CH2
b. Set up the Horizontal menu as follows:
H Time Base Main
H Record Length 5000
H Horizontal Scale Main Scale @ 2 ns/div
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TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Performance Verification: Ajustment/Verification Fixture
c. Set up the Trigger menu as follows:
H Source CH2
H Coupling DC
H Slope +
H Level 700 mV
H Mode Normal
d. Set up the Measure menu as follows:
H Select Measurement for CH1 Measure
H Gating On
e. Set up the Cursor menu as follows:
H Function V Bars
f. Set up the Acquire menu as follows:
H Acquisition Mode Average 90
H Repetitive Signal On
4. Connect CH2 of the oscilloscope to J4-2 on the adjustment/verification
fixture.
5. Select Deskew from the Vertical menu of the oscilloscope.
NOTE. Observe proper polarity when doing the following steps. See Figure 4--9
on page 4--23 to identify the ground side of the components being measured.
6. Connect the CH1 probe of the oscilloscope to the custom probe tip adapter
and measure the signal across R85.
7. Use the large knob at the upper right of the oscilloscope panel to adjust delay
until the leading edges of the two waveforms coincide and the displayed
value of CH1-CH2 delay is averaged around 0 ±25 ps.
8. Move the CH1 probe to R321, R67, and R39 and press the Run/Stop button
to start an acquisition. Verify that the CH1-CH2 delay between any two
measurements does not exceed 90 ps.
9. The maximum difference between the three measured values represents the
channel-to-channel skew. Record this difference on the Calibration Data
Report.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
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Performance Verification: Ajustment/Verification Fixture
Verify Hold Clock Output
Timing
Use the following procedure to verify the hold time.
Parameter tested Hold time
Equipment
required
Prerequisites Warm-up time: 30 minutes, adjustment/verification fixture and test
Oscilloscope (item 3)
2 DSO probes (item 4)
Custom probe tip adapter (see Figure 4--10, page 4--26)
equipment
1. Set the jumper positions as listed in the table.
Jumper Jumper name Jumper setting
J13 P6434 Deskew/probe setup 1-3 and 5-6 connected
J15 Clock selection INT
J16 Deskew 1-2 and 4-5 connected
J17 Setup/hold select HOLD
J19 Clock polarity select Disconnected
2. Set up the oscilloscope by pressing Setup, Factory Setup, and then OK
Confirm Factory Init to return the oscilloscope to default conditions.
3. Set up the oscilloscope as listed below.
a. Set up the CH1 Vertical menu as follows:
H Coupling DC/50 Ω
H Fine Scale 200 mV/div
H Position --3.00 div CH1
H Position --3.32 div CH2
b. Set up the Horizontal menu as follows:
H Time Base Main
H Record Length 5000
H Horizontal Scale Main Scale @ 2 ns/div
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TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Performance Verification: Ajustment/Verification Fixture
c. Set up the Trigger menu as follows:
H Source CH2
H Coupling DC
H Slope +
H Level 700 mV
H Mode Normal
d. Set up the Measure menu as follows:
H Select Measurement for CH1 Measure
H Gating On
e. Set up the Cursor menu as follows:
H Function V Bars
f. Set up the Acquire menu as follows:
H Acquisition Mode Average 90
H Repetitive Signal On
4. Connect the CH2 probe of the oscilloscope to J1-2 on the adjustment/verification fixture.
5. Select Deskew from the Vertical menu.
NOTE. Observe proper polarity when performing the following steps.
See Figure 4--9 on page 4--23 to identify the ground side of the components being
measured.
6. Connect the CH1 probe of the oscilloscope to the custom probe tip adapter
and measure the signal across R67.
7. Begin the acquisition by pressing the Run/Stop button.
8. Use the large knob at the upper right of the panel to adjust delay until the
leading edges of the two waveforms coincide and the displayed value of
CH1-CH2 delay is averaged around 0.
9. Connect the CH1 probe to R127. Verify the CH1-CH2 delay is averaged
around 0 ns ±100 ps.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
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Performance Verification: Ajustment/Verification Fixture
10. The CH1-CH2 delay represents the hold time at R127. Record the hold time
at R127 on the Calibration Data Report.
11. Connect the CH1 probe to R321. Verify the CH1-CH2 delay is averaged
around 0 ns ±100 ps.
12. The CH1-CH2 delay represents the hold time at R321. Record the hold time
at R321 on the Calibration Data Report.
Verify Setup Clock Output
Timing
Use the following procedure to verify the setup time.
Parameter tested Setup time
Equipment
required
Prerequisites Warm-up time: 30 minutes for adjustment/verification fixture and test
Oscilloscope (item 3)
2 DSO probes (item 4)
Custom probe tip adapter (see Figure 4--10, page 4--26)
equipment
1. Set the jumper positions as listed in the table.
Jumper Jumper name Jumper setting
J13 P6434 Deskew/probe setup 1-3 and 5-6 connected
J15 Clock selection INT
J16 Deskew 1-2 and 4-5 connected
J17 Setup/hold select SETUP
J19 Clock polarity select Disconnected
4- 34
2. Set up the oscilloscope by pressing Setup, Factory Setup, and then OK
Confirm Factory Init to return the oscilloscope to default conditions.
3. Set up the oscilloscope as listed below.
a. Set up the CH1 Vertical menu as follows:
H Coupling DC/50 Ω
H Fine Scale 200 mV/div
H Position --3.00 div CH1
H Position --3.32 div CH2
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Performance Verification: Ajustment/Verification Fixture
b. Set up the Horizontal menu as follows:
H Time Base Main
H Record Length 5000
H Horizontal Scale Main Scale @ 2 ns/div
c. Set up the Trigger menu as follows:
H Source CH2
H Coupling DC
H Slope +
H Level 700 mV
H Mode Normal
d. Set up the Measure menu as follows:
H Select Measurement for CH1 Measure
H Gating On
e. Set up the Cursor menu as follows:
H Function V Bars
f. Set up the Acquire menu as follows:
H Acquisition Mode Average 90
H Repetitive Signal On
4. Connect the CH2 probe of the oscilloscope to J1 pin-2 on the adjustment/
verification fixture.
5. Select Deskew from the Vertical menu of the oscilloscope.
NOTE. Observe proper polarity when doing the following steps. See Figure 4--9
on page 4--23 to identify the ground side of the components being measured.
6. Connect the CH1 probe of the oscilloscope to the custom probe tip adapter
and measure the signal across R67.
7. Press the Run/Stop button to stop the acquisition and read the measurement.
8. Use the large knob at the upper right of the panel to adjust delay until the
leading edges of the two waveforms coincide and the displayed value of
CH1-CH2 delay is averaged around 0.
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Performance Verification: Ajustment/Verification Fixture
9. Set one of the vertical cursors before the leading edge of the CH 2 pulse, and
the other cursor after the leading edge of the CH 1 pulse.
10. Connect the CH1 probe to R127. Verify the CH1-CH2 delay is averaged
around 3.0 ns ±100 ps.
11. The CH1-CH2 delay represents the setup time at R127. R ecord the setup
time at R127 on the Calibration Data Report.
12. Connect the CH1 probe to R321. Verify the CH1-CH2 delay is averaged
around 3.0 ns ±100 ps.
13. The CH1-CH2 delay represents the setup time at R321. Record the setup
time at R321 on the Calibration Data Report.
Verify External Clock Input
Use the following procedure to verify the external clock input.
Parameter tested External Clock Input
Equipment
required
Prerequisites Warm-up time: 30 minutes for adjustment/verification fixture and test
Frequency Counter (item 8)
Signal Generator (item 16)
Shorting Jumpers (item 14)
equipment
1. Set the jumper positions as listed in the table.
Jumper Jumper name Jumper setting
J13 P6434 Deskew/probe setup 1-3 and 5-6 connected
J15 Clock selection EXT
J16 Deskew 1-2 and 4-5 connected
J17 Setup/hold select SETUP
J19 Clock polarity select Disconnected
4- 36
2. Using the signal generator, insert a 225 MHz, 1 V
signal at J18 EXT CLK
p-p
IN.
3. Using the frequency counter, verify that the data is being output at a
112.5 MHz clocked rate at J1 and J2.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Calibration Data Report
Adjustment/Verification Fixture
Instrument model number:
Serial number: Certificate number:
Verification performed by: Verification date:
Test Data
Procedure
Characteristic Specification Tolerance
reference
Incoming data Outgoing data
Internal clock frequency 50.065 MHz ±.01 percent
(50.0600 MHz-
50.0700 MHz
Data Output
(Channel-to-Channel Skew)
Setup Clock Output (at R127) +3.0 ns ±100 ps Page 4--36, Step 10
Setup Clock Output (at R321) +3.0 ns ±100 ps Page 4--36, Step 12
Hold Clock Output (at R127) 0.0 ns ±100 ps Page 4--33, Step 9
Hold Clock Output (at R321) 0.0 ns ±100 ps Page 4--34, Step 11
50 ps Less than 50 ps Page 4--31, Step 8
Page 4--29, Step 2
)
Logic Analyzer Module Adjustment Procedures
This chapter contains procedures which use the performance verification and
adjustment software to adjust the TLA7Nx, TLA7Px, and TLA7Qx logic
analyzer modules to within factory specifications. The performance verification
and adjustment software contains instructions and control programs for adjusting
the instrument The software describes test equipment connections and settings,
selects setup parameters, and loads calibration constants into memory.
This chapter also contains adjustment procedures for the adjustment/verification
fixture which begin on page 5--11.
These procedures adjust the LA Module for conformance with the warranted
characteristics listed in the Specifications chapter of this manual.
Adjustments should be done after repair of the module or when performance
verification tests have failed.
Prerequisites
These procedures ask for the serial number of the instrument under test. Before
installing the modules in the mainframe, record the serial number of the LA
module.
You can also access the module serial number through the logic analyzer
application. In the application, go to the System menu, select System Properties,
and click on the LA instrument tab. You must quit the logic analyzer application
before continuing with the performance verification and adjustment software
procedures.
Only trained service technicians should perform this procedure after meeting the
following requirements:
H When multiple LA modules of the same model number are installed in the
mainframe, the performance verification and adjustment software will
address only the module in the highest-numbered slot. If you are testing a
TLA7Q4 module for example, move it to a higher slot number than all of the
other TLA7Q4 modules in the mainframe. This avoids unnecessary module
warm-up time.
H When adjusting merged modules using the same type of individual modules,
the individual modules must be physically separated.
H The logic analyzer application must not be running.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
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Logic Analyzer Module Adjustment Procedures
H The performance verification and adjustment software must be loaded. Refer
to Software Installation and Removal on page 2--2.
H The LA module must be installed in a Tektronix logic analyzer mainframe.
H The instrument requires a 30-minute warm-up time in a +20_ Cto+30_ C
environment before it is adjusted. Adjustments performed before the
operating temperature has stabilized may cause errors in performance.
Merged Modules
NOTE. Only modules with channel widths of 102 or 136 channels can be merged.
Up to three modules can be merged from the TLA7Nx, TLA7Px, and TLA7Qx
series modules.
When adjusting merged modules using the same type of individual modules, for
example, three TLA7Q4 modules, the individual modules must be separated
before continuing. See the Tektronix Logic Analyzer Family User Manual for
instructions on separating merged modules.
NOTE. The performance verification and adjustment software runs independent
of the logic analyzer application software and does not recognize configuration
settings. It is not necessary to unmerge modules through the application software
before performing these procedures on merged modules.
When adjusting merged modules using different types of individual modules, the
adjustment procedure can be done on the merged module without physical
separation.
NOTE. After all of the modules have been physically merged, run the self-calibration procedure on the merged modules. To run the self-calibration procedure, go
to the System menu, select Calibration and Diagnostics, and then click the Self
Calibration tab.
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TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Using the Software
Logic Analyzer Module Adjustment Procedures
This section describes how to perform adjustments using the performance
verification and adjustment software.
Performing the
Adjustments
Adjustment Sequences
and Dependencies
Adjustment After Repair
There are no manual adjustments for the LA Modules. Instead, the performance
verification and adjustment software adjusts the instrument hardware using
external test equipment connections that you provide in response to prompts on
the screen.
Upon successful completion of each adjustment, the performance verification
and adjustment software automatically loads the new calibration data into
memory.
The performance verification and adjustment software allows you to run groups
of adjustments, or sequences. A sequence consists of one or more individual
adjustments. Normally you will perform a RUN FULL SEQUENCE, which
executes each adjustment in the proper order.
The performance verification and adjustment software also provides instructions
for running each adjustment individually. However, you should only perform
individual adjustments while troubleshooting.
You must perform a full adjustment sequence following replacement of any
circuit board.
Test Equipment
In addition to the basic system setup, you will need some of the equipment
shown in Table 4--1 on page 4--3 to adjust the LA module.
Each procedure includes a table that calls out the equipment used. Use Table 4--1
to identify required equipment specifications. If you substitute equipment,
always choose instruments that meet or exceed the minimum requirements
specified.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
5- 3
Logic Analyzer Module Adjustment Procedures
Adjustment Instructions
This section describes how to perform adjustments using the performance
verification and adjustment software.
Using the PV/Adjust
Software
The performance verification and adjustment software contains instructions for
performing the adjustments. The basic steps for completing the procedures
follow:
1. Start the program, enter user and product identification information,
temperature, and humidity.
2. If you are using P6417 or P6418 probes, label one probe as the Reference
Probe, and the other probe as the Probe Under Test.
3. If you are using a P6434 probe, label the probe channel group identified as
the pin 38 side as Probe A. Label the probe channel group identified as the
pin 1 side as Probe B; refer to Figure 5--1.
Pin 1 label
5- 4
Recess on
pin1side
Beveled corners
End view
Pin1side
Pin38side
Figure 5- 1: P6434 probe detail
4. Select a full adjustment sequence.
5. Connect the test equipment.
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Pin38side
Beveled corners
Logic Analyzer Module Adjustment Procedures
6. Set up the test equipment for the output signals described by on-screen
instructions and by the connection illustration for each test.
7. Run each adjustment step as instructed by following the on-screen prompts.
8. After completing all the adjustment steps, view the results to confirm that
the adjustment was successful.
When a test passes, the software automatically loads new calibration data into
memory.
Troubleshooting
Tests Performed
If any adjustments fail, use the following steps to troubleshoot the problems:
H Check all test equipment for improper or loose connections.
H Check that all test equipment is powered on and has the proper warm-up
time.
H Verify the adjustment/verification fixture LED is lighted and the jumper
positions match the on-screen instructions, and the external connections are
correct.
H Rerun mainframe or module diagnostics and module self-cal.
H Run the adjustment procedures a second time to verify the failure.
The adjustment procedures check and adjust the following parameters of the
LA module:
H SELF_CAL, an internal routine in the logic analyzer application software
that adjusts acquisition thresholds, internal module signal timing, and
merged module signal timing.
H Deskew, an adjustment routine in the performance verification and adjust-
ment software which time-aligns all channels.
NOTE. Do not mix probe types (P6417, P6418, or P6434) when performing the
deskew procedure.
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Logic Analyzer Module Adjustment Procedures
Adjustment Procedures
Refer to the following procedures to identify the initial setup for each adjustment. Then follow the program instructions to complete the adjustments.
Self Calibration
Self calibration is an internal routine that optimizes performance at the current
ambient temperature to maximize measurement accuracy. No external equipment
or user actions are needed to complete the procedure. The LA module saves data
generated by the self calibration in nonvolatile memory. Passing self cal provides
a higher level of confidence of module functionality.
NOTE. Performing the self calibration does not guarantee that all parameters
operate within limits. Operation within limits is achieved by performing the
adjustment procedures. Verification of operation within limits is accomplished by
performing the performance verification procedures.
When to Perform the Self Calibration. You can run the self calibration at any time
during normal operation. To maintain measurement accuracy, perform the
self calibration if the following conditions occur:
H After repair and replacement of any circuit board.
H It has been a year since the last self calibration was run
H If you have just merged calibrated LA modules and received an out of
calibration on-screen message. You will need to run self calibration on the
merged modules.
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TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Logic Analyzer Module Adjustment Procedures
LA Adjustment
Procedure 1:
SELF_CAL
Perform the following steps to run the SELF_CAL routine. Before beginning
this procedure, be sure that no active signals are applied to the LA module.
Self calibration can fail if signals are applied to the probe during the procedure.
Prerequisites Warm-up time: 30 minutes
Power-up diagnostics pass
1. Ensure that the instrument has had a 30-minute warm up before attempting
the self calibration, and that the logic analyzer application is running.
2. Disconnect any probes connected to the LA module.
3. Select Calibration and Diagnostics from the System menu.
4. Select the Self Calibration tab page.
5. Select the LA module.
6. Click the Run button to start the self calibration.
The self calibration takes several minutes to complete, depending on the
number of channels in the module. Upon successfully completing the self
calibration, the module status changes from Running to Calibrated, and the
Date and Time field is set to the present.
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5- 7
Logic Analyzer Module Adjustment Procedures
LA Adjustment
Procedure 2:
Deskew
The deskew procedure calibrates and adjusts the timing alignment of the probe
data channels and receivers.
Perform the deskew procedure:
H Once a year.
H If you have replaced the LPU board (the probe constants are stored on the
LPU board).
This procedure checks and adjusts the time alignment of all channels. There are
no manual adjustments.
SW test name Deskew
Equipment
required
Prerequisites Warm-up time: 30 minutes
Adjustment/verification fixture and fixture supply (item 2 )
Two P6417 or P6418 Logic Analyzer probes (item 6), OR
One P6434 Logic Analyzer probe (item 7)
Test equipment connected as shown in Figure 5--2
Merged modules of the same type must be separated and deskewed
separately
Diagnostics and SELF_CAL pass
C2/C3/CK3
Channel/Group
Clock channel
Adjustment/verification
J5
J3
J1
fixture
J2
Fixture supply
J26
Figure 5- 2: Initial deskew test setup
1. If the logic analyzer application is running, quit the application.
2. Verify that all of the prerequisites listed previously are met for the procedure.
3. Load the performance verification and adjustment software, as described in
the Software Installation and Removal on page 2--2.
5- 8
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Logic Analyzer Module Adjustment Procedures
4. Run the performance verification and adjustment software. Run the
C:\Tekcats\Tla_la program, then select the correct module type and the
adjustment option.
NOTE. These procedures assume that P6418 or P6417 probes are used. If you
have a P6434 probe, use J5, the Data Out connector on the adjustment/verification fixture for performing the deskew test.
Observe proper polarity: pin 1 to pin 1.
5. Follow the on-screen prompts to perform the module deskew adjustment
procedure.
6. Verify no failures occur for each test.
If desired, you can print or save the results of the deskew adjustment operation.
However, this is not required for calibration. The file will be over-written when
the next adjustment or performance verification sequence is run.
Completing the Adjustment Steps
After completing the adjustments, obtain a copy of the test results and verify that
all tests passed. Run the Performance Verification Procedures to verify that the
all parameters are within the allowable specifications as listed in the Tektronix
Logic Analyzer Family User Manual.
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Logic Analyzer Module Adjustment Procedures
5- 10
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
Adjustment/Verification Fixture Adjustments
This section contains the adjustment procedures for the adjustment/verification
fixture. Most of the adjustments consist of moving jumpers or wires that change
the delays at specific locations on the board. Once these jumpers have been set
(soldered) you should rarely have to change them.
Each procedure includes a table that calls out the equipment used. Use Table 4--1
on page 4--3 to identify required equipment specifications. If you substitute
equipment, always choose instruments that meet or exceed the minimum
requirements specified.
Adjustment/Verification Fixture Adjustment
Equipment
Required
Prerequisites Warm-up time: 30 minutes for adjustment/verification fixture and test
1. Warm up the adjustment/verification fixture and all test equipment.
a. Connect the external power supply to fixture and perform the power
supply checks and other functional steps while allowing the fixture to
warm up for 20 minutes.
b. Turn on the oscilloscope, signal generator, and frequency counter. Allow
them to warm up for 20 minutes.
Adjustment/verification fixture and power supply (item 2)
Oscilloscope (item 3)
Two1MΩ 10X oscilloscope probe (item 4)
Frequency counter (item 8)
Signal generator (item 16)
1X Probe (item 5)
DMM with test leads (item 9)
Shorting jumpers (item 14)
equipment
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
5- 11
Adjustment/Verification Fixture Adjustment
Power Supply Checks
The following procedure checks the DC power supply. Refer to Figure 5--3 for
test point locations.
Parameter tested Power supply
Equipment
Required
Prerequisites Warm-up time: 30 minutes for adjustment/verification fixture and test
DMM with test leads (item 9)
equipment
2. Connect the DMM (--) lead to J8 (VEE).
3. Connect the DMM (+) lead to J10 (V
DD) and check for a voltage reading of
+5 V ± 0.10 V.
4. Connect the DMM negative (--) lead to J9 (GND).
5. Connect the DMM positive (+) lead to J10 (V
DD) and adjust R38 for a
voltage reading of +2.00 V ±10 mV.
5- 12
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
R38 (VDDadjust )
Adjustment/Verification Fixture Adjustment
J10 (VDD)
External
Clock in
J9 ( GND )
J8 (VEE)
J18
J26
J17
Hold/Setup
select
SetupHold
Jumper installed:
clocked on falling edge
Jumper removed:
clocked on rising edge
J19
J17
J19
J15
Ext/Int
Clock select
J14
J15
IntExt
12345
J16
Deskew
J6 J7
J20
J16
C17
GND
J13
Vcc
Deskew
Probe
setup
J13
P6434
Deskew/Probe setup
J1
J2
J3
R321
J5
R39
J4
R127
R85
R67
1
Clock
Clock
GND
GND
J4
Setup/Hold
Clock out
Figure 5- 3: Adjustment/verification fixture circuit board layout
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
5- 13
Adjustment/Verification Fixture Adjustment
Internal Clock Frequency
Check
The following procedure checks the internal clock frequency.
Parameter tested Internal Clock Frequency
Equipment
Required
Prerequisites Warm-up time: 30 minutes for adjustment/verification fixture and test
Adjustment/verification fixture and power supply (item 2)
Frequency counter (item 8)
Signal generator (item 16)
Shorting jumpers (item 14)
equipment
1. Set up the frequency counter as follows:
a. Right input (10 Hz -- 100 MHz)
b. Select Direct Resolution: 10 Hz
c. 1 M input termination
d. X1 Attenuation
2. Move one jumper on J16 to DESKEW (pins 2 and 3). Keep the other jumper
connected to pins 4 and 5.
3. Using the frequency counter, measure the oscillator frequency at J1. It will
measure 50.0650 MHz ±0.01% (50.0600 -- 50.0700).
5- 14
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module S ervice Manual
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