Up to 200 MHz State Acquisition
Analysis of Synchronous Digital
Circuits
Simultaneous State and Highspeed Timing Analysis Through
the Same Probe Pinpoints Elusive
Faults Without Double Probing
500 MHz Deep Timing Analysis
with Up to 8 Mb Per Channel
Glitch and Setup/Hold Triggering
and Display Finds and Displays
Elusive Hardware Problems
Transitional Storage Extends the
Signal Analysis Capture Time
Broad Processor and Bus Support
Full Range of General-Purpose
and High-density, Non-intrusive
Probes
Applications
Hardware Debug and Verification
Processor/Bus Debug and
Verification
Embedded Software Integration,
Debug and Verification
Tektronix Logic Analyzers
TLA7N4 Logic Analyzer Module
Characteristics
General
Number of Channels (all channels are acquired
including clocks) – TLA7N4: 136 channels (4 are
clock and 4 are qualifier channels).
Channel Grouping – No limit to number of groups or
number of channels per group (all channels can be
reused in multiple groups).
TLA700 Module “Merging” – Three modules can
be “merged” to make up to a 408-Channel module.
Merged modules exhibit the same depth as the
lesser of the three individual modules.
Word/range/setup-and-hold/glitch/transition
recognizers span all three modules. Only one set
of clock connections is required.
Time Stamp – 50-Bit at 500 ps resolution
(6.5 day range).
Clocking/Acquisition Modes – Internal, internal
2X, external. 2 GHz MagniVu
is available simultaneous with all modes.
Number of Mainframe Slots Required per
TLA700 Module – 2.
™
high-speed timing
Input Characteristics
(with P6417, P6418, P6419
or P6434 probes)
Capacitive Loading –
<0.7 pF data and clock (P6419).
1.4 pF typical data; 2 pF typical clock (P6418).
2 pF typical data and clock (P6417 and P6434).
Threshold Selection Range – From +5.0 V to
–2.0 V in 50 mV increments.
Threshold Selection Channel Granularity –
Separate selection for clock (1) and data (16) for
each 17-Channel probe connector.
Threshold Accuracy (including probe) –
±100 mV.
Input Voltage Range – Operating: 6.5 V
centered
p-p
around the programmed threshold.
Non-destructive: ±15 V.
Minimum Input Signal Swing –
250 mV or 25% of signal swing, whichever is
greater (P6417, P6418 and P6419).
300 mV or 25% of signal swing (P6434).
Input Signal Minimum Slew Rate –
200 mV/ns typical.
State Acquisition Characteristics
(with P6417, P6418, P6419
or P6434 probes)
State Clock Rate – 100 MHz standard,
200 MHz optional.
State Data Rate (half/full channels) –
400/200 Mb/s, typical. Requires 200 MHz
state option.
State Memory Depth with Timestamps – 64 Kb,
256 Kb, 1 Mb, or 4 Mb per channel.
Setup-and-Hold Time Selection Range – From
8.5 ns before to 7.0 ns after clock edge.
Setup-and-Hold Window – 2 ns typical.
Minimum Clock Pulse Width – 2 ns.
Active Clock Edge Separation – 5 ns.
Demux Channel Selection – Channels can be
demultiplexed to other channels through user
interface with 8-Channel granularity.
Deep Timing Resolution with Glitch Storage
Enabled – 10 ns to 50 ms.
Deep Timing Memory Depth (half/full channels
with timestamps and with or without transitional storage) – 128/64 Kb, 512/256 Kb, 2/1 Mb,
8/4 Mb per channel.
Deep Timing Memory Depth with Glitch Storage
Enabled – Half of default main memory depth.
Channel-to-Channel Skew – <1 ns typical.
Minimum Recognizable Pulse Width
(single channel) – 2 ns.
Minimum Recognizable Glitch Width
(single channel) – 2 ns.
Minimum Recognizable Multi-channel Trigger
Event – Sample period +2 ns.
Trigger Characteristics
Independent Trigger States – 16.
Maximum Independent If/then Clauses per
State – 16.
Maximum Number of Events per If/then
Clause – 8.
Maximum Number of Actions per If/then
Clause – 8.
Maximum Number of Trigger Events – 18
(2 counter/timers plus any 16 other resources).
Number of Word Recognizers – 16.
Number of Range Recognizers – 4.
Number of Transition Recognizers – 1.
Number of Counter/Timers – 2.
Trigger Event Types – Word, group, channel,
Trigger Sequence Rate – DC to 250 MHz (4 ns).
Counter/Timer Range – 51 Bits each (>100 days
at 4 ns).
Counter Rate – DC to 250 MHz (4 ns).
Timer Clock Rate – 250 MHz (4 ns).
Counter/Timer Latency – None (can be tested or
reset immediately after starting).
Range Recognizers – Double bounded (can be as
wide as any group, must be grouped according to
specified order of significance).
Setup-and-Hold Violation Recognizer Setup Time
Range – From 8 ns before to 7 ns after clock edge
in 0.5 ns increments.
Setup-and-Hold Violation Recognizer Hold Time
Range – From 7 ns before to 8 ns after clock edge
in 0.5 ns increments.
Trigger Position – Any data sample.
MagniVu Trigger Position – MagniVu data is
centered around the module trigger.
Storage Control (data qualification) – Global
(conditional), by state (start/stop), by trigger action or
transitional.
Storage Window Granularity – Single sample or
block-of-31 samples before and after.
Safety – CSA C22.2 No. 1010.1, EN61010-1,
IEC61010-1, UL 3111-1
Physical Characteristics
Dimensionsmmin.
Height26210.3
Width612.4
Depth38115
Weightkglb.
Net (without probes)3.16.7
Shipping (typical)6.313.7
Includes: Probe retainer bracket, probe manual,
certificate of calibration, one-year warranty
(return to Tektronix) and user manual.
Probes must be ordered separately – Order any
combination and quantity of probes by ordering the
P6417, P6418, P6419 or P6434 individually.
TLA7N4 – 136-Channel Logic Analyzer module,
2 GHz timing, 100 MHz state, 64 Kb depth. Options
for up to 4 Mb depth and/or 200 MHz state.
Quantity of Probes to Order
Per Option
ProbeTLA7N4
P6418 Probes8
P6434 Probes4
P6417 Probes8
P6419 Probes8
Logic Analyzer Module Options
(Base configuration is 64 K depth at 100 MHz state.)
Opt. 1S – Increase to 256 K depth at 100 MHz state.
Opt. 2S – Increase to 1 M depth at 100 MHz state.
Opt. 3S – Increase to 4 M depth at 100 MHz state.
Opt. 4S – Increase to 64 K depth at 200 MHz state.
Opt. 5S – Increase to 256 K depth at 200 MHz state.
Opt. 6S – Increase to 1 M depth at 200 MHz state.
Opt. 7S – Increase to 4 M depth at 200 MHz state.
TLA7N4 Service Manual and
Test Fixtures
TLA7N4 Logic Analyzer Performance Verification
and Adjustment Fixture (includes AC adapter;
requires local power cord) – Order 671-3599-00.
TLA7N4 Logic Analyzer Modules Service Manual
(includes Performance Verification and Adjustment
procedures) – Order 071-0864-01.
TLA700 Series Module
Upgrades
You can increase the memory depth and state
speed of most existing TLA700 Series logic
analyzer modules. You can also install a TLA7N4
logic analyzer module into an existing TLA714/
715/720/721/7XM mainframe. Please refer to the
TLA Family Upgrade Guide for further details.
Logic Analyzer Probe
Selection Guidelines
For the TLA7N4 logic analyzer module, you have
the choice of four probe options.
P6418.P6418.
P6418
Part NumberDescription
334-9979-001 sheet of probe labels (not installed)
196-3476-001 each – 8-Channel leadset (barrel connectors
support 0.100" and 2 mm spacing)
Black
196-3479-001 each – 1-Channel leadset (barrel connectors
support 0.100" and 2 mm spacing)
Black
196-3477-00(Optional) 1 each – 8-Channel reduced
bias voltage leadset (barrel connectors
support 0.100" and 2 mm spacing)
White
196-3478-00(Optional) 1 each – 1-Channel reduced
bias voltage leadset (barrel connectors
support 0.100" and 2 mm spacing)
White
SMG5020 each – SMT KlipChip™grabber tips
013-0280-00(Optional) one-to-two adapter
SMK4(Optional) micro KlipChip grabber tip
adapter, 4 each
071-0567-00P6417/P6418 Instruction Manual
Logic Analyzer Module Probes
and Accessories
P6418 – The P6418 is a 17-Channel generalpurpose probe with leadsets and grabber tips for
use with: 1) probing individual test points within
your target system, either directly or with a test
clip, or 2) direct connection to legacy TLA family
processor/bus support probe adapters with
8-Channel probe connectors. The P6418 works
with a wide range of industry-standard probing
accessories for flexible attachment to your target
system. This probe is recommended for most
general-purpose applications.
17-Channel general-purpose probe and
accessories – Order P6418.
P6417 – The P6417 is a 17-Channel generalpurpose probe that is similar to the P6418 with
the additional capability of allowing you to separate
the 8-Channel podlet groups into individual channels for both maximum electrical performance
and maximum distance between adjacent channels.
This probe is recommended for those generalpurpose applications that require maximum flexibility.
17-Channel general-purpose probe and
accessories – Order P6417.
P6417 Probe Cable Length – 1.8 m (6 ft.).
Tektronix Logic Analyzers
TLA7N4 Logic Analyzer Module
P6417
Part NumberDescription
N/A2 each – 8-Channel podlet holders (installed)
N/A1 set of 17 podlet color coding bands (installed)
334-9239-001 sheet of probe labels (not installed)
196-3476-001 each – 8-Channel leadset (barrel connectors
support 0.100" and 2 mm spacing)
Black
196-3479-001 each – 1-Channel leadset (barrel connectors
P6419 – The P6419 is a 17-channel high-density
compression probe, with single-ended clock and
data. This probe utilizes a connector-less probe
attach mechanism for quick and reliable connections
to your system under test. This probe is recommended for those applications that require higher
signal density or a connector-less probe attach.
17 channel High-density Compression Probe,
with Single-ended Clock and Data – Order P6419.
P6419 Probe Cable Length – 1.8 m (6 ft.).
P6434 – The P6434 is a lightweight probe with
quick connect/disconnect and a positive latching
mechanism to ensure a secure, reliable connection.
It is for use with: 1) applications where you have
designed in the AMP Mictor high-density connectors
into your target system or 2) direct connection to
newer TLA family processor/bus support probe
adapters with AMP Mictor 34-Channel probe
connectors. An optional low-profile adapter for lowclearance applications is also available. This probe
is recommended for all high-density applications.
Order UPIK3M (5 each).
Order 671-2508-00 (1 each).
34-Channel Probe Interface Kit with Barrel
Connectors – Order 020-2199-00.
34-Channel Probe Interface Kit with mini-PV
Connectors – Order 020-3000-00.
Differential-to-single-Ended
Converters
Each podlet converts 8 input differential pairs to a
single-ended output for use with the TLA Logic
Analyzer.They draw their power from separate
wires connected to the system under test. The
units are shipped without any input termination
connected and a supply of 100 Ω termination
resistors for use and installation by the user,
if desired. The units are shipped without input
leadsets. Leadsets are also available.
Differential ECL/PECL
to Single-ended ECL
Converter Pod
Each channel is converted via an ON
Semiconductor MC10E416 buffer which will
support speeds as high as 800 MHz. The inputs
have provisions for differential and/or parallel
termination. The input power is provided via two
leads that are connected to a lower voltage and a
higher voltage, each DC-isolated from the output,
allowing operation in both ECL and PECL systems.
Differential LVDS/TTL
to Single-ended TTL
Converter Pod
Each channel is converted via a National
Semiconductor DS90LV032A receiver supporting
data rates in excess of 400 Mbps (200 MHz).
The inputs have provisions for differential terminations and have resistor-diode input protection from
over voltage.
For information or ordering, please contact:
Dragonfly Software Development
4905 SW Griffith Drive, Suite 100
Beaverton, OR 97005-8724
(503) 643-3800 phone
(503) 626-9653 fax
sales@dfsw.com
TLA7N4 Service Options
Opt. C3 – Calibration Service 3 Years.
Opt. C5 – Calibration Service 5 Years.
Opt. D1 – Calibration Data Report.
Opt. D3 – Calibration Data Report 3 Years
(with Opt. C3).
Opt. D5 – Calibration Data Report 5 Years
(with Opt. C5).